1 /* 2 * Copyright (c) 2017 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 */ 10 11 #include "hisi_sas.h" 12 #define DRV_NAME "hisi_sas_v3_hw" 13 14 /* global registers need init*/ 15 #define DLVRY_QUEUE_ENABLE 0x0 16 #define IOST_BASE_ADDR_LO 0x8 17 #define IOST_BASE_ADDR_HI 0xc 18 #define ITCT_BASE_ADDR_LO 0x10 19 #define ITCT_BASE_ADDR_HI 0x14 20 #define IO_BROKEN_MSG_ADDR_LO 0x18 21 #define IO_BROKEN_MSG_ADDR_HI 0x1c 22 #define PHY_CONTEXT 0x20 23 #define PHY_STATE 0x24 24 #define PHY_PORT_NUM_MA 0x28 25 #define PHY_CONN_RATE 0x30 26 #define ITCT_CLR 0x44 27 #define ITCT_CLR_EN_OFF 16 28 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF) 29 #define ITCT_DEV_OFF 0 30 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF) 31 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58 32 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c 33 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60 34 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64 35 #define CFG_MAX_TAG 0x68 36 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84 37 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88 38 #define HGC_GET_ITV_TIME 0x90 39 #define DEVICE_MSG_WORK_MODE 0x94 40 #define OPENA_WT_CONTI_TIME 0x9c 41 #define I_T_NEXUS_LOSS_TIME 0xa0 42 #define MAX_CON_TIME_LIMIT_TIME 0xa4 43 #define BUS_INACTIVE_LIMIT_TIME 0xa8 44 #define REJECT_TO_OPEN_LIMIT_TIME 0xac 45 #define CQ_INT_CONVERGE_EN 0xb0 46 #define CFG_AGING_TIME 0xbc 47 #define HGC_DFX_CFG2 0xc0 48 #define CFG_ABT_SET_QUERY_IPTT 0xd4 49 #define CFG_SET_ABORTED_IPTT_OFF 0 50 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF) 51 #define CFG_SET_ABORTED_EN_OFF 12 52 #define CFG_ABT_SET_IPTT_DONE 0xd8 53 #define CFG_ABT_SET_IPTT_DONE_OFF 0 54 #define HGC_IOMB_PROC1_STATUS 0x104 55 #define CHNL_INT_STATUS 0x148 56 #define HGC_AXI_FIFO_ERR_INFO 0x154 57 #define AXI_ERR_INFO_OFF 0 58 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF) 59 #define FIFO_ERR_INFO_OFF 8 60 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF) 61 #define INT_COAL_EN 0x19c 62 #define OQ_INT_COAL_TIME 0x1a0 63 #define OQ_INT_COAL_CNT 0x1a4 64 #define ENT_INT_COAL_TIME 0x1a8 65 #define ENT_INT_COAL_CNT 0x1ac 66 #define OQ_INT_SRC 0x1b0 67 #define OQ_INT_SRC_MSK 0x1b4 68 #define ENT_INT_SRC1 0x1b8 69 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0 70 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF) 71 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8 72 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF) 73 #define ENT_INT_SRC2 0x1bc 74 #define ENT_INT_SRC3 0x1c0 75 #define ENT_INT_SRC3_WP_DEPTH_OFF 8 76 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9 77 #define ENT_INT_SRC3_RP_DEPTH_OFF 10 78 #define ENT_INT_SRC3_AXI_OFF 11 79 #define ENT_INT_SRC3_FIFO_OFF 12 80 #define ENT_INT_SRC3_LM_OFF 14 81 #define ENT_INT_SRC3_ITC_INT_OFF 15 82 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF) 83 #define ENT_INT_SRC3_ABT_OFF 16 84 #define ENT_INT_SRC_MSK1 0x1c4 85 #define ENT_INT_SRC_MSK2 0x1c8 86 #define ENT_INT_SRC_MSK3 0x1cc 87 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31 88 #define CHNL_PHYUPDOWN_INT_MSK 0x1d0 89 #define CHNL_ENT_INT_MSK 0x1d4 90 #define HGC_COM_INT_MSK 0x1d8 91 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF) 92 #define SAS_ECC_INTR 0x1e8 93 #define SAS_ECC_INTR_MSK 0x1ec 94 #define HGC_ERR_STAT_EN 0x238 95 #define CQE_SEND_CNT 0x248 96 #define DLVRY_Q_0_BASE_ADDR_LO 0x260 97 #define DLVRY_Q_0_BASE_ADDR_HI 0x264 98 #define DLVRY_Q_0_DEPTH 0x268 99 #define DLVRY_Q_0_WR_PTR 0x26c 100 #define DLVRY_Q_0_RD_PTR 0x270 101 #define HYPER_STREAM_ID_EN_CFG 0xc80 102 #define OQ0_INT_SRC_MSK 0xc90 103 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0 104 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4 105 #define COMPL_Q_0_DEPTH 0x4e8 106 #define COMPL_Q_0_WR_PTR 0x4ec 107 #define COMPL_Q_0_RD_PTR 0x4f0 108 #define AWQOS_AWCACHE_CFG 0xc84 109 #define ARQOS_ARCACHE_CFG 0xc88 110 #define HILINK_ERR_DFX 0xe04 111 #define SAS_GPIO_CFG_0 0x1000 112 #define SAS_GPIO_CFG_1 0x1004 113 #define SAS_GPIO_TX_0_1 0x1040 114 #define SAS_CFG_DRIVE_VLD 0x1070 115 116 /* phy registers requiring init */ 117 #define PORT_BASE (0x2000) 118 #define PHY_CFG (PORT_BASE + 0x0) 119 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4) 120 #define PHY_CFG_ENA_OFF 0 121 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF) 122 #define PHY_CFG_DC_OPT_OFF 2 123 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF) 124 #define PHY_CFG_PHY_RST_OFF 3 125 #define PHY_CFG_PHY_RST_MSK (0x1 << PHY_CFG_PHY_RST_OFF) 126 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8) 127 #define PHY_CTRL (PORT_BASE + 0x14) 128 #define PHY_CTRL_RESET_OFF 0 129 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF) 130 #define SL_CFG (PORT_BASE + 0x84) 131 #define AIP_LIMIT (PORT_BASE + 0x90) 132 #define SL_CONTROL (PORT_BASE + 0x94) 133 #define SL_CONTROL_NOTIFY_EN_OFF 0 134 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF) 135 #define SL_CTA_OFF 17 136 #define SL_CTA_MSK (0x1 << SL_CTA_OFF) 137 #define RX_PRIMS_STATUS (PORT_BASE + 0x98) 138 #define RX_BCAST_CHG_OFF 1 139 #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF) 140 #define TX_ID_DWORD0 (PORT_BASE + 0x9c) 141 #define TX_ID_DWORD1 (PORT_BASE + 0xa0) 142 #define TX_ID_DWORD2 (PORT_BASE + 0xa4) 143 #define TX_ID_DWORD3 (PORT_BASE + 0xa8) 144 #define TX_ID_DWORD4 (PORT_BASE + 0xaC) 145 #define TX_ID_DWORD5 (PORT_BASE + 0xb0) 146 #define TX_ID_DWORD6 (PORT_BASE + 0xb4) 147 #define TXID_AUTO (PORT_BASE + 0xb8) 148 #define CT3_OFF 1 149 #define CT3_MSK (0x1 << CT3_OFF) 150 #define TX_HARDRST_OFF 2 151 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF) 152 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4) 153 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) 154 #define STP_LINK_TIMER (PORT_BASE + 0x120) 155 #define STP_LINK_TIMEOUT_STATE (PORT_BASE + 0x124) 156 #define CON_CFG_DRIVER (PORT_BASE + 0x130) 157 #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134) 158 #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138) 159 #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c) 160 #define CHL_INT0 (PORT_BASE + 0x1b4) 161 #define CHL_INT0_HOTPLUG_TOUT_OFF 0 162 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF) 163 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1 164 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF) 165 #define CHL_INT0_SL_PHY_ENABLE_OFF 2 166 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF) 167 #define CHL_INT0_NOT_RDY_OFF 4 168 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF) 169 #define CHL_INT0_PHY_RDY_OFF 5 170 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF) 171 #define CHL_INT1 (PORT_BASE + 0x1b8) 172 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15 173 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF) 174 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17 175 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF) 176 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19 177 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20 178 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21 179 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22 180 #define CHL_INT2 (PORT_BASE + 0x1bc) 181 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0 182 #define CHL_INT2_RX_INVLD_DW_OFF 30 183 #define CHL_INT2_STP_LINK_TIMEOUT_OFF 31 184 #define CHL_INT0_MSK (PORT_BASE + 0x1c0) 185 #define CHL_INT1_MSK (PORT_BASE + 0x1c4) 186 #define CHL_INT2_MSK (PORT_BASE + 0x1c8) 187 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0) 188 #define SAS_RX_TRAIN_TIMER (PORT_BASE + 0x2a4) 189 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0) 190 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4) 191 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8) 192 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc) 193 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0) 194 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4) 195 #define DMA_TX_STATUS (PORT_BASE + 0x2d0) 196 #define DMA_TX_STATUS_BUSY_OFF 0 197 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF) 198 #define DMA_RX_STATUS (PORT_BASE + 0x2e8) 199 #define DMA_RX_STATUS_BUSY_OFF 0 200 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF) 201 202 #define COARSETUNE_TIME (PORT_BASE + 0x304) 203 #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380) 204 #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384) 205 #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390) 206 #define ERR_CNT_DISP_ERR (PORT_BASE + 0x398) 207 208 #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */ 209 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW) 210 #error Max ITCT exceeded 211 #endif 212 213 #define AXI_MASTER_CFG_BASE (0x5000) 214 #define AM_CTRL_GLOBAL (0x0) 215 #define AM_CTRL_SHUTDOWN_REQ_OFF 0 216 #define AM_CTRL_SHUTDOWN_REQ_MSK (0x1 << AM_CTRL_SHUTDOWN_REQ_OFF) 217 #define AM_CURR_TRANS_RETURN (0x150) 218 219 #define AM_CFG_MAX_TRANS (0x5010) 220 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014) 221 #define AXI_CFG (0x5100) 222 #define AM_ROB_ECC_ERR_ADDR (0x510c) 223 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF 0 224 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF) 225 #define AM_ROB_ECC_MULBIT_ERR_ADDR_OFF 8 226 #define AM_ROB_ECC_MULBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_MULBIT_ERR_ADDR_OFF) 227 228 /* RAS registers need init */ 229 #define RAS_BASE (0x6000) 230 #define SAS_RAS_INTR0 (RAS_BASE) 231 #define SAS_RAS_INTR1 (RAS_BASE + 0x04) 232 #define SAS_RAS_INTR0_MASK (RAS_BASE + 0x08) 233 #define SAS_RAS_INTR1_MASK (RAS_BASE + 0x0c) 234 #define CFG_SAS_RAS_INTR_MASK (RAS_BASE + 0x1c) 235 #define SAS_RAS_INTR2 (RAS_BASE + 0x20) 236 #define SAS_RAS_INTR2_MASK (RAS_BASE + 0x24) 237 238 /* HW dma structures */ 239 /* Delivery queue header */ 240 /* dw0 */ 241 #define CMD_HDR_ABORT_FLAG_OFF 0 242 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF) 243 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2 244 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) 245 #define CMD_HDR_RESP_REPORT_OFF 5 246 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF) 247 #define CMD_HDR_TLR_CTRL_OFF 6 248 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF) 249 #define CMD_HDR_PORT_OFF 18 250 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF) 251 #define CMD_HDR_PRIORITY_OFF 27 252 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF) 253 #define CMD_HDR_CMD_OFF 29 254 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF) 255 /* dw1 */ 256 #define CMD_HDR_UNCON_CMD_OFF 3 257 #define CMD_HDR_DIR_OFF 5 258 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF) 259 #define CMD_HDR_RESET_OFF 7 260 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF) 261 #define CMD_HDR_VDTL_OFF 10 262 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF) 263 #define CMD_HDR_FRAME_TYPE_OFF 11 264 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF) 265 #define CMD_HDR_DEV_ID_OFF 16 266 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF) 267 /* dw2 */ 268 #define CMD_HDR_CFL_OFF 0 269 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF) 270 #define CMD_HDR_NCQ_TAG_OFF 10 271 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF) 272 #define CMD_HDR_MRFL_OFF 15 273 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF) 274 #define CMD_HDR_SG_MOD_OFF 24 275 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF) 276 /* dw3 */ 277 #define CMD_HDR_IPTT_OFF 0 278 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF) 279 /* dw6 */ 280 #define CMD_HDR_DIF_SGL_LEN_OFF 0 281 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF) 282 #define CMD_HDR_DATA_SGL_LEN_OFF 16 283 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF) 284 /* dw7 */ 285 #define CMD_HDR_ADDR_MODE_SEL_OFF 15 286 #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF) 287 #define CMD_HDR_ABORT_IPTT_OFF 16 288 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF) 289 290 /* Completion header */ 291 /* dw0 */ 292 #define CMPLT_HDR_CMPLT_OFF 0 293 #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF) 294 #define CMPLT_HDR_ERROR_PHASE_OFF 2 295 #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF) 296 #define CMPLT_HDR_RSPNS_XFRD_OFF 10 297 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF) 298 #define CMPLT_HDR_ERX_OFF 12 299 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF) 300 #define CMPLT_HDR_ABORT_STAT_OFF 13 301 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF) 302 /* abort_stat */ 303 #define STAT_IO_NOT_VALID 0x1 304 #define STAT_IO_NO_DEVICE 0x2 305 #define STAT_IO_COMPLETE 0x3 306 #define STAT_IO_ABORTED 0x4 307 /* dw1 */ 308 #define CMPLT_HDR_IPTT_OFF 0 309 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF) 310 #define CMPLT_HDR_DEV_ID_OFF 16 311 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF) 312 /* dw3 */ 313 #define CMPLT_HDR_IO_IN_TARGET_OFF 17 314 #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF) 315 316 /* ITCT header */ 317 /* qw0 */ 318 #define ITCT_HDR_DEV_TYPE_OFF 0 319 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF) 320 #define ITCT_HDR_VALID_OFF 2 321 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF) 322 #define ITCT_HDR_MCR_OFF 5 323 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF) 324 #define ITCT_HDR_VLN_OFF 9 325 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF) 326 #define ITCT_HDR_SMP_TIMEOUT_OFF 16 327 #define ITCT_HDR_AWT_CONTINUE_OFF 25 328 #define ITCT_HDR_PORT_ID_OFF 28 329 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF) 330 /* qw2 */ 331 #define ITCT_HDR_INLT_OFF 0 332 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF) 333 #define ITCT_HDR_RTOLT_OFF 48 334 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF) 335 336 struct hisi_sas_complete_v3_hdr { 337 __le32 dw0; 338 __le32 dw1; 339 __le32 act; 340 __le32 dw3; 341 }; 342 343 struct hisi_sas_err_record_v3 { 344 /* dw0 */ 345 __le32 trans_tx_fail_type; 346 347 /* dw1 */ 348 __le32 trans_rx_fail_type; 349 350 /* dw2 */ 351 __le16 dma_tx_err_type; 352 __le16 sipc_rx_err_type; 353 354 /* dw3 */ 355 __le32 dma_rx_err_type; 356 }; 357 358 #define RX_DATA_LEN_UNDERFLOW_OFF 6 359 #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF) 360 361 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096 362 #define HISI_SAS_MSI_COUNT_V3_HW 32 363 364 #define DIR_NO_DATA 0 365 #define DIR_TO_INI 1 366 #define DIR_TO_DEVICE 2 367 #define DIR_RESERVED 3 368 369 #define FIS_CMD_IS_UNCONSTRAINED(fis) \ 370 ((fis.command == ATA_CMD_READ_LOG_EXT) || \ 371 (fis.command == ATA_CMD_READ_LOG_DMA_EXT) || \ 372 ((fis.command == ATA_CMD_DEV_RESET) && \ 373 ((fis.control & ATA_SRST) != 0))) 374 375 static bool hisi_sas_intr_conv; 376 MODULE_PARM_DESC(intr_conv, "interrupt converge enable (0-1)"); 377 378 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) 379 { 380 void __iomem *regs = hisi_hba->regs + off; 381 382 return readl(regs); 383 } 384 385 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off) 386 { 387 void __iomem *regs = hisi_hba->regs + off; 388 389 return readl_relaxed(regs); 390 } 391 392 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val) 393 { 394 void __iomem *regs = hisi_hba->regs + off; 395 396 writel(val, regs); 397 } 398 399 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no, 400 u32 off, u32 val) 401 { 402 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 403 404 writel(val, regs); 405 } 406 407 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba, 408 int phy_no, u32 off) 409 { 410 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 411 412 return readl(regs); 413 } 414 415 #define hisi_sas_read32_poll_timeout(off, val, cond, delay_us, \ 416 timeout_us) \ 417 ({ \ 418 void __iomem *regs = hisi_hba->regs + off; \ 419 readl_poll_timeout(regs, val, cond, delay_us, timeout_us); \ 420 }) 421 422 #define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us, \ 423 timeout_us) \ 424 ({ \ 425 void __iomem *regs = hisi_hba->regs + off; \ 426 readl_poll_timeout_atomic(regs, val, cond, delay_us, timeout_us);\ 427 }) 428 429 static void init_reg_v3_hw(struct hisi_hba *hisi_hba) 430 { 431 struct pci_dev *pdev = hisi_hba->pci_dev; 432 int i; 433 434 /* Global registers init */ 435 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 436 (u32)((1ULL << hisi_hba->queue_count) - 1)); 437 hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400); 438 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108); 439 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1); 440 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); 441 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); 442 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); 443 hisi_sas_write32(hisi_hba, CQ_INT_CONVERGE_EN, 444 hisi_sas_intr_conv); 445 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff); 446 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff); 447 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff); 448 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff); 449 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe); 450 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe); 451 if (pdev->revision >= 0x21) 452 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffff7aff); 453 else 454 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xfffe20ff); 455 hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0); 456 hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0); 457 hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0); 458 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x0); 459 hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0); 460 hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0); 461 for (i = 0; i < hisi_hba->queue_count; i++) 462 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0); 463 464 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1); 465 466 for (i = 0; i < hisi_hba->n_phy; i++) { 467 struct hisi_sas_phy *phy = &hisi_hba->phy[i]; 468 struct asd_sas_phy *sas_phy = &phy->sas_phy; 469 u32 prog_phy_link_rate = 0x800; 470 471 if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate < 472 SAS_LINK_RATE_1_5_GBPS)) { 473 prog_phy_link_rate = 0x855; 474 } else { 475 enum sas_linkrate max = sas_phy->phy->maximum_linkrate; 476 477 prog_phy_link_rate = 478 hisi_sas_get_prog_phy_linkrate_mask(max) | 479 0x800; 480 } 481 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 482 prog_phy_link_rate); 483 hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80); 484 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff); 485 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff); 486 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff); 487 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000); 488 if (pdev->revision >= 0x21) 489 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 490 0xffffffff); 491 else 492 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 493 0xff87ffff); 494 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe); 495 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0); 496 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0); 497 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0); 498 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0); 499 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0); 500 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1); 501 hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120); 502 hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x2a0a01); 503 504 /* used for 12G negotiate */ 505 hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e); 506 hisi_sas_phy_write32(hisi_hba, i, AIP_LIMIT, 0x2ffff); 507 } 508 509 for (i = 0; i < hisi_hba->queue_count; i++) { 510 /* Delivery queue */ 511 hisi_sas_write32(hisi_hba, 512 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14), 513 upper_32_bits(hisi_hba->cmd_hdr_dma[i])); 514 515 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14), 516 lower_32_bits(hisi_hba->cmd_hdr_dma[i])); 517 518 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14), 519 HISI_SAS_QUEUE_SLOTS); 520 521 /* Completion queue */ 522 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14), 523 upper_32_bits(hisi_hba->complete_hdr_dma[i])); 524 525 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14), 526 lower_32_bits(hisi_hba->complete_hdr_dma[i])); 527 528 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14), 529 HISI_SAS_QUEUE_SLOTS); 530 } 531 532 /* itct */ 533 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO, 534 lower_32_bits(hisi_hba->itct_dma)); 535 536 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI, 537 upper_32_bits(hisi_hba->itct_dma)); 538 539 /* iost */ 540 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO, 541 lower_32_bits(hisi_hba->iost_dma)); 542 543 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI, 544 upper_32_bits(hisi_hba->iost_dma)); 545 546 /* breakpoint */ 547 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO, 548 lower_32_bits(hisi_hba->breakpoint_dma)); 549 550 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI, 551 upper_32_bits(hisi_hba->breakpoint_dma)); 552 553 /* SATA broken msg */ 554 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO, 555 lower_32_bits(hisi_hba->sata_breakpoint_dma)); 556 557 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI, 558 upper_32_bits(hisi_hba->sata_breakpoint_dma)); 559 560 /* SATA initial fis */ 561 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO, 562 lower_32_bits(hisi_hba->initial_fis_dma)); 563 564 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI, 565 upper_32_bits(hisi_hba->initial_fis_dma)); 566 567 /* RAS registers init */ 568 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0); 569 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0); 570 hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, 0x0); 571 hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, 0x0); 572 573 /* LED registers init */ 574 hisi_sas_write32(hisi_hba, SAS_CFG_DRIVE_VLD, 0x80000ff); 575 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1, 0x80808080); 576 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1 + 0x4, 0x80808080); 577 /* Configure blink generator rate A to 1Hz and B to 4Hz */ 578 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_1, 0x121700); 579 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_0, 0x800000); 580 } 581 582 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 583 { 584 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 585 586 cfg &= ~PHY_CFG_DC_OPT_MSK; 587 cfg |= 1 << PHY_CFG_DC_OPT_OFF; 588 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 589 } 590 591 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 592 { 593 struct sas_identify_frame identify_frame; 594 u32 *identify_buffer; 595 596 memset(&identify_frame, 0, sizeof(identify_frame)); 597 identify_frame.dev_type = SAS_END_DEVICE; 598 identify_frame.frame_type = 0; 599 identify_frame._un1 = 1; 600 identify_frame.initiator_bits = SAS_PROTOCOL_ALL; 601 identify_frame.target_bits = SAS_PROTOCOL_NONE; 602 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 603 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 604 identify_frame.phy_id = phy_no; 605 identify_buffer = (u32 *)(&identify_frame); 606 607 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0, 608 __swab32(identify_buffer[0])); 609 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1, 610 __swab32(identify_buffer[1])); 611 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2, 612 __swab32(identify_buffer[2])); 613 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3, 614 __swab32(identify_buffer[3])); 615 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4, 616 __swab32(identify_buffer[4])); 617 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5, 618 __swab32(identify_buffer[5])); 619 } 620 621 static void setup_itct_v3_hw(struct hisi_hba *hisi_hba, 622 struct hisi_sas_device *sas_dev) 623 { 624 struct domain_device *device = sas_dev->sas_device; 625 struct device *dev = hisi_hba->dev; 626 u64 qw0, device_id = sas_dev->device_id; 627 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id]; 628 struct domain_device *parent_dev = device->parent; 629 struct asd_sas_port *sas_port = device->port; 630 struct hisi_sas_port *port = to_hisi_sas_port(sas_port); 631 632 memset(itct, 0, sizeof(*itct)); 633 634 /* qw0 */ 635 qw0 = 0; 636 switch (sas_dev->dev_type) { 637 case SAS_END_DEVICE: 638 case SAS_EDGE_EXPANDER_DEVICE: 639 case SAS_FANOUT_EXPANDER_DEVICE: 640 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF; 641 break; 642 case SAS_SATA_DEV: 643 case SAS_SATA_PENDING: 644 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) 645 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF; 646 else 647 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF; 648 break; 649 default: 650 dev_warn(dev, "setup itct: unsupported dev type (%d)\n", 651 sas_dev->dev_type); 652 } 653 654 qw0 |= ((1 << ITCT_HDR_VALID_OFF) | 655 (device->linkrate << ITCT_HDR_MCR_OFF) | 656 (1 << ITCT_HDR_VLN_OFF) | 657 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) | 658 (1 << ITCT_HDR_AWT_CONTINUE_OFF) | 659 (port->id << ITCT_HDR_PORT_ID_OFF)); 660 itct->qw0 = cpu_to_le64(qw0); 661 662 /* qw1 */ 663 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE); 664 itct->sas_addr = __swab64(itct->sas_addr); 665 666 /* qw2 */ 667 if (!dev_is_sata(device)) 668 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) | 669 (0x1ULL << ITCT_HDR_RTOLT_OFF)); 670 } 671 672 static void clear_itct_v3_hw(struct hisi_hba *hisi_hba, 673 struct hisi_sas_device *sas_dev) 674 { 675 DECLARE_COMPLETION_ONSTACK(completion); 676 u64 dev_id = sas_dev->device_id; 677 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id]; 678 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); 679 680 sas_dev->completion = &completion; 681 682 /* clear the itct interrupt state */ 683 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) 684 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 685 ENT_INT_SRC3_ITC_INT_MSK); 686 687 /* clear the itct table*/ 688 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK); 689 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val); 690 691 wait_for_completion(sas_dev->completion); 692 memset(itct, 0, sizeof(struct hisi_sas_itct)); 693 } 694 695 static void dereg_device_v3_hw(struct hisi_hba *hisi_hba, 696 struct domain_device *device) 697 { 698 struct hisi_sas_slot *slot, *slot2; 699 struct hisi_sas_device *sas_dev = device->lldd_dev; 700 u32 cfg_abt_set_query_iptt; 701 702 cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba, 703 CFG_ABT_SET_QUERY_IPTT); 704 list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) { 705 cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK; 706 cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) | 707 (slot->idx << CFG_SET_ABORTED_IPTT_OFF); 708 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, 709 cfg_abt_set_query_iptt); 710 } 711 cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF); 712 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, 713 cfg_abt_set_query_iptt); 714 hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE, 715 1 << CFG_ABT_SET_IPTT_DONE_OFF); 716 } 717 718 static int reset_hw_v3_hw(struct hisi_hba *hisi_hba) 719 { 720 struct device *dev = hisi_hba->dev; 721 int ret; 722 u32 val; 723 724 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0); 725 726 /* Disable all of the PHYs */ 727 hisi_sas_stop_phys(hisi_hba); 728 udelay(50); 729 730 /* Ensure axi bus idle */ 731 ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val, 732 20000, 1000000); 733 if (ret) { 734 dev_err(dev, "axi bus is not idle, ret = %d!\n", ret); 735 return -EIO; 736 } 737 738 if (ACPI_HANDLE(dev)) { 739 acpi_status s; 740 741 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL); 742 if (ACPI_FAILURE(s)) { 743 dev_err(dev, "Reset failed\n"); 744 return -EIO; 745 } 746 } else { 747 dev_err(dev, "no reset method!\n"); 748 return -EINVAL; 749 } 750 751 return 0; 752 } 753 754 static int hw_init_v3_hw(struct hisi_hba *hisi_hba) 755 { 756 struct device *dev = hisi_hba->dev; 757 int rc; 758 759 rc = reset_hw_v3_hw(hisi_hba); 760 if (rc) { 761 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc); 762 return rc; 763 } 764 765 msleep(100); 766 init_reg_v3_hw(hisi_hba); 767 768 return 0; 769 } 770 771 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 772 { 773 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 774 775 cfg |= PHY_CFG_ENA_MSK; 776 cfg &= ~PHY_CFG_PHY_RST_MSK; 777 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 778 } 779 780 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 781 { 782 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 783 u32 state; 784 785 cfg &= ~PHY_CFG_ENA_MSK; 786 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 787 788 mdelay(50); 789 790 state = hisi_sas_read32(hisi_hba, PHY_STATE); 791 if (state & BIT(phy_no)) { 792 cfg |= PHY_CFG_PHY_RST_MSK; 793 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 794 } 795 } 796 797 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 798 { 799 config_id_frame_v3_hw(hisi_hba, phy_no); 800 config_phy_opt_mode_v3_hw(hisi_hba, phy_no); 801 enable_phy_v3_hw(hisi_hba, phy_no); 802 } 803 804 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 805 { 806 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 807 u32 txid_auto; 808 809 disable_phy_v3_hw(hisi_hba, phy_no); 810 if (phy->identify.device_type == SAS_END_DEVICE) { 811 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); 812 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, 813 txid_auto | TX_HARDRST_MSK); 814 } 815 msleep(100); 816 start_phy_v3_hw(hisi_hba, phy_no); 817 } 818 819 static enum sas_linkrate phy_get_max_linkrate_v3_hw(void) 820 { 821 return SAS_LINK_RATE_12_0_GBPS; 822 } 823 824 static void phys_init_v3_hw(struct hisi_hba *hisi_hba) 825 { 826 int i; 827 828 for (i = 0; i < hisi_hba->n_phy; i++) { 829 struct hisi_sas_phy *phy = &hisi_hba->phy[i]; 830 struct asd_sas_phy *sas_phy = &phy->sas_phy; 831 832 if (!sas_phy->phy->enabled) 833 continue; 834 835 start_phy_v3_hw(hisi_hba, i); 836 } 837 } 838 839 static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 840 { 841 u32 sl_control; 842 843 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 844 sl_control |= SL_CONTROL_NOTIFY_EN_MSK; 845 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 846 msleep(1); 847 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 848 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK; 849 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 850 } 851 852 static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id) 853 { 854 int i, bitmap = 0; 855 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 856 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 857 858 for (i = 0; i < hisi_hba->n_phy; i++) 859 if (phy_state & BIT(i)) 860 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id) 861 bitmap |= BIT(i); 862 863 return bitmap; 864 } 865 866 /** 867 * The callpath to this function and upto writing the write 868 * queue pointer should be safe from interruption. 869 */ 870 static int 871 get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq) 872 { 873 struct device *dev = hisi_hba->dev; 874 int queue = dq->id; 875 u32 r, w; 876 877 w = dq->wr_point; 878 r = hisi_sas_read32_relaxed(hisi_hba, 879 DLVRY_Q_0_RD_PTR + (queue * 0x14)); 880 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) { 881 dev_warn(dev, "full queue=%d r=%d w=%d\n", 882 queue, r, w); 883 return -EAGAIN; 884 } 885 886 dq->wr_point = (dq->wr_point + 1) % HISI_SAS_QUEUE_SLOTS; 887 888 return w; 889 } 890 891 static void start_delivery_v3_hw(struct hisi_sas_dq *dq) 892 { 893 struct hisi_hba *hisi_hba = dq->hisi_hba; 894 struct hisi_sas_slot *s, *s1, *s2 = NULL; 895 struct list_head *dq_list; 896 int dlvry_queue = dq->id; 897 int wp; 898 899 dq_list = &dq->list; 900 list_for_each_entry_safe(s, s1, &dq->list, delivery) { 901 if (!s->ready) 902 break; 903 s2 = s; 904 list_del(&s->delivery); 905 } 906 907 if (!s2) 908 return; 909 910 /* 911 * Ensure that memories for slots built on other CPUs is observed. 912 */ 913 smp_rmb(); 914 wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS; 915 916 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp); 917 } 918 919 static void prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba, 920 struct hisi_sas_slot *slot, 921 struct hisi_sas_cmd_hdr *hdr, 922 struct scatterlist *scatter, 923 int n_elem) 924 { 925 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot); 926 struct scatterlist *sg; 927 int i; 928 929 for_each_sg(scatter, sg, n_elem, i) { 930 struct hisi_sas_sge *entry = &sge_page->sge[i]; 931 932 entry->addr = cpu_to_le64(sg_dma_address(sg)); 933 entry->page_ctrl_0 = entry->page_ctrl_1 = 0; 934 entry->data_len = cpu_to_le32(sg_dma_len(sg)); 935 entry->data_off = 0; 936 } 937 938 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot)); 939 940 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF); 941 } 942 943 static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba, 944 struct hisi_sas_slot *slot) 945 { 946 struct sas_task *task = slot->task; 947 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 948 struct domain_device *device = task->dev; 949 struct hisi_sas_device *sas_dev = device->lldd_dev; 950 struct hisi_sas_port *port = slot->port; 951 struct sas_ssp_task *ssp_task = &task->ssp_task; 952 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd; 953 struct hisi_sas_tmf_task *tmf = slot->tmf; 954 int has_data = 0, priority = !!tmf; 955 u8 *buf_cmd; 956 u32 dw1 = 0, dw2 = 0; 957 958 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) | 959 (2 << CMD_HDR_TLR_CTRL_OFF) | 960 (port->id << CMD_HDR_PORT_OFF) | 961 (priority << CMD_HDR_PRIORITY_OFF) | 962 (1 << CMD_HDR_CMD_OFF)); /* ssp */ 963 964 dw1 = 1 << CMD_HDR_VDTL_OFF; 965 if (tmf) { 966 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF; 967 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF; 968 } else { 969 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF; 970 switch (scsi_cmnd->sc_data_direction) { 971 case DMA_TO_DEVICE: 972 has_data = 1; 973 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; 974 break; 975 case DMA_FROM_DEVICE: 976 has_data = 1; 977 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; 978 break; 979 default: 980 dw1 &= ~CMD_HDR_DIR_MSK; 981 } 982 } 983 984 /* map itct entry */ 985 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; 986 hdr->dw1 = cpu_to_le32(dw1); 987 988 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr) 989 + 3) / 4) << CMD_HDR_CFL_OFF) | 990 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) | 991 (2 << CMD_HDR_SG_MOD_OFF); 992 hdr->dw2 = cpu_to_le32(dw2); 993 hdr->transfer_tags = cpu_to_le32(slot->idx); 994 995 if (has_data) 996 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, 997 slot->n_elem); 998 999 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); 1000 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); 1001 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1002 1003 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) + 1004 sizeof(struct ssp_frame_hdr); 1005 1006 memcpy(buf_cmd, &task->ssp_task.LUN, 8); 1007 if (!tmf) { 1008 buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3); 1009 memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len); 1010 } else { 1011 buf_cmd[10] = tmf->tmf; 1012 switch (tmf->tmf) { 1013 case TMF_ABORT_TASK: 1014 case TMF_QUERY_TASK: 1015 buf_cmd[12] = 1016 (tmf->tag_of_task_to_be_managed >> 8) & 0xff; 1017 buf_cmd[13] = 1018 tmf->tag_of_task_to_be_managed & 0xff; 1019 break; 1020 default: 1021 break; 1022 } 1023 } 1024 } 1025 1026 static void prep_smp_v3_hw(struct hisi_hba *hisi_hba, 1027 struct hisi_sas_slot *slot) 1028 { 1029 struct sas_task *task = slot->task; 1030 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1031 struct domain_device *device = task->dev; 1032 struct hisi_sas_port *port = slot->port; 1033 struct scatterlist *sg_req; 1034 struct hisi_sas_device *sas_dev = device->lldd_dev; 1035 dma_addr_t req_dma_addr; 1036 unsigned int req_len; 1037 1038 /* req */ 1039 sg_req = &task->smp_task.smp_req; 1040 req_len = sg_dma_len(sg_req); 1041 req_dma_addr = sg_dma_address(sg_req); 1042 1043 /* create header */ 1044 /* dw0 */ 1045 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) | 1046 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */ 1047 (2 << CMD_HDR_CMD_OFF)); /* smp */ 1048 1049 /* map itct entry */ 1050 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) | 1051 (1 << CMD_HDR_FRAME_TYPE_OFF) | 1052 (DIR_NO_DATA << CMD_HDR_DIR_OFF)); 1053 1054 /* dw2 */ 1055 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) | 1056 (HISI_SAS_MAX_SMP_RESP_SZ / 4 << 1057 CMD_HDR_MRFL_OFF)); 1058 1059 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF); 1060 1061 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr); 1062 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1063 1064 } 1065 1066 static void prep_ata_v3_hw(struct hisi_hba *hisi_hba, 1067 struct hisi_sas_slot *slot) 1068 { 1069 struct sas_task *task = slot->task; 1070 struct domain_device *device = task->dev; 1071 struct domain_device *parent_dev = device->parent; 1072 struct hisi_sas_device *sas_dev = device->lldd_dev; 1073 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1074 struct asd_sas_port *sas_port = device->port; 1075 struct hisi_sas_port *port = to_hisi_sas_port(sas_port); 1076 u8 *buf_cmd; 1077 int has_data = 0, hdr_tag = 0; 1078 u32 dw1 = 0, dw2 = 0; 1079 1080 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF); 1081 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) 1082 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF); 1083 else 1084 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF); 1085 1086 switch (task->data_dir) { 1087 case DMA_TO_DEVICE: 1088 has_data = 1; 1089 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; 1090 break; 1091 case DMA_FROM_DEVICE: 1092 has_data = 1; 1093 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; 1094 break; 1095 default: 1096 dw1 &= ~CMD_HDR_DIR_MSK; 1097 } 1098 1099 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) && 1100 (task->ata_task.fis.control & ATA_SRST)) 1101 dw1 |= 1 << CMD_HDR_RESET_OFF; 1102 1103 dw1 |= (hisi_sas_get_ata_protocol( 1104 &task->ata_task.fis, task->data_dir)) 1105 << CMD_HDR_FRAME_TYPE_OFF; 1106 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; 1107 1108 if (FIS_CMD_IS_UNCONSTRAINED(task->ata_task.fis)) 1109 dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF; 1110 1111 hdr->dw1 = cpu_to_le32(dw1); 1112 1113 /* dw2 */ 1114 if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) { 1115 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); 1116 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF; 1117 } 1118 1119 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF | 1120 2 << CMD_HDR_SG_MOD_OFF; 1121 hdr->dw2 = cpu_to_le32(dw2); 1122 1123 /* dw3 */ 1124 hdr->transfer_tags = cpu_to_le32(slot->idx); 1125 1126 if (has_data) 1127 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, 1128 slot->n_elem); 1129 1130 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); 1131 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); 1132 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1133 1134 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot); 1135 1136 if (likely(!task->ata_task.device_control_reg_update)) 1137 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */ 1138 /* fill in command FIS */ 1139 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis)); 1140 } 1141 1142 static void prep_abort_v3_hw(struct hisi_hba *hisi_hba, 1143 struct hisi_sas_slot *slot, 1144 int device_id, int abort_flag, int tag_to_abort) 1145 { 1146 struct sas_task *task = slot->task; 1147 struct domain_device *dev = task->dev; 1148 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1149 struct hisi_sas_port *port = slot->port; 1150 1151 /* dw0 */ 1152 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/ 1153 (port->id << CMD_HDR_PORT_OFF) | 1154 (dev_is_sata(dev) 1155 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) | 1156 (abort_flag 1157 << CMD_HDR_ABORT_FLAG_OFF)); 1158 1159 /* dw1 */ 1160 hdr->dw1 = cpu_to_le32(device_id 1161 << CMD_HDR_DEV_ID_OFF); 1162 1163 /* dw7 */ 1164 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF); 1165 hdr->transfer_tags = cpu_to_le32(slot->idx); 1166 1167 } 1168 1169 static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1170 { 1171 int i, res; 1172 u32 context, port_id, link_rate; 1173 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1174 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1175 struct device *dev = hisi_hba->dev; 1176 unsigned long flags; 1177 1178 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1); 1179 1180 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 1181 port_id = (port_id >> (4 * phy_no)) & 0xf; 1182 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); 1183 link_rate = (link_rate >> (phy_no * 4)) & 0xf; 1184 1185 if (port_id == 0xf) { 1186 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no); 1187 res = IRQ_NONE; 1188 goto end; 1189 } 1190 sas_phy->linkrate = link_rate; 1191 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); 1192 1193 /* Check for SATA dev */ 1194 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT); 1195 if (context & (1 << phy_no)) { 1196 struct hisi_sas_initial_fis *initial_fis; 1197 struct dev_to_host_fis *fis; 1198 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0}; 1199 1200 dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate); 1201 initial_fis = &hisi_hba->initial_fis[phy_no]; 1202 fis = &initial_fis->fis; 1203 1204 /* check ERR bit of Status Register */ 1205 if (fis->status & ATA_ERR) { 1206 dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", 1207 phy_no, fis->status); 1208 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1209 res = IRQ_NONE; 1210 goto end; 1211 } 1212 1213 sas_phy->oob_mode = SATA_OOB_MODE; 1214 attached_sas_addr[0] = 0x50; 1215 attached_sas_addr[7] = phy_no; 1216 memcpy(sas_phy->attached_sas_addr, 1217 attached_sas_addr, 1218 SAS_ADDR_SIZE); 1219 memcpy(sas_phy->frame_rcvd, fis, 1220 sizeof(struct dev_to_host_fis)); 1221 phy->phy_type |= PORT_TYPE_SATA; 1222 phy->identify.device_type = SAS_SATA_DEV; 1223 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 1224 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 1225 } else { 1226 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd; 1227 struct sas_identify_frame *id = 1228 (struct sas_identify_frame *)frame_rcvd; 1229 1230 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate); 1231 for (i = 0; i < 6; i++) { 1232 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no, 1233 RX_IDAF_DWORD0 + (i * 4)); 1234 frame_rcvd[i] = __swab32(idaf); 1235 } 1236 sas_phy->oob_mode = SAS_OOB_MODE; 1237 memcpy(sas_phy->attached_sas_addr, 1238 &id->sas_addr, 1239 SAS_ADDR_SIZE); 1240 phy->phy_type |= PORT_TYPE_SAS; 1241 phy->identify.device_type = id->dev_type; 1242 phy->frame_rcvd_size = sizeof(struct sas_identify_frame); 1243 if (phy->identify.device_type == SAS_END_DEVICE) 1244 phy->identify.target_port_protocols = 1245 SAS_PROTOCOL_SSP; 1246 else if (phy->identify.device_type != SAS_PHY_UNUSED) 1247 phy->identify.target_port_protocols = 1248 SAS_PROTOCOL_SMP; 1249 } 1250 1251 phy->port_id = port_id; 1252 phy->phy_attached = 1; 1253 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP); 1254 res = IRQ_HANDLED; 1255 spin_lock_irqsave(&phy->lock, flags); 1256 if (phy->reset_completion) { 1257 phy->in_reset = 0; 1258 complete(phy->reset_completion); 1259 } 1260 spin_unlock_irqrestore(&phy->lock, flags); 1261 end: 1262 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1263 CHL_INT0_SL_PHY_ENABLE_MSK); 1264 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0); 1265 1266 return res; 1267 } 1268 1269 static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1270 { 1271 u32 phy_state, sl_ctrl, txid_auto; 1272 struct device *dev = hisi_hba->dev; 1273 1274 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1); 1275 1276 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1277 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state); 1278 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0); 1279 1280 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 1281 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, 1282 sl_ctrl&(~SL_CTA_MSK)); 1283 1284 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); 1285 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, 1286 txid_auto | CT3_MSK); 1287 1288 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK); 1289 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0); 1290 1291 return IRQ_HANDLED; 1292 } 1293 1294 static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1295 { 1296 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1297 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1298 struct sas_ha_struct *sas_ha = &hisi_hba->sha; 1299 u32 bcast_status; 1300 1301 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1); 1302 bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS); 1303 if ((bcast_status & RX_BCAST_CHG_MSK) && 1304 !test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)) 1305 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 1306 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1307 CHL_INT0_SL_RX_BCST_ACK_MSK); 1308 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0); 1309 1310 return IRQ_HANDLED; 1311 } 1312 1313 static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p) 1314 { 1315 struct hisi_hba *hisi_hba = p; 1316 u32 irq_msk; 1317 int phy_no = 0; 1318 irqreturn_t res = IRQ_NONE; 1319 1320 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) 1321 & 0x11111111; 1322 while (irq_msk) { 1323 if (irq_msk & 1) { 1324 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, 1325 CHL_INT0); 1326 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1327 int rdy = phy_state & (1 << phy_no); 1328 1329 if (rdy) { 1330 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK) 1331 /* phy up */ 1332 if (phy_up_v3_hw(phy_no, hisi_hba) 1333 == IRQ_HANDLED) 1334 res = IRQ_HANDLED; 1335 if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK) 1336 /* phy bcast */ 1337 if (phy_bcast_v3_hw(phy_no, hisi_hba) 1338 == IRQ_HANDLED) 1339 res = IRQ_HANDLED; 1340 } else { 1341 if (irq_value & CHL_INT0_NOT_RDY_MSK) 1342 /* phy down */ 1343 if (phy_down_v3_hw(phy_no, hisi_hba) 1344 == IRQ_HANDLED) 1345 res = IRQ_HANDLED; 1346 } 1347 } 1348 irq_msk >>= 4; 1349 phy_no++; 1350 } 1351 1352 return res; 1353 } 1354 1355 static const struct hisi_sas_hw_error port_axi_error[] = { 1356 { 1357 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF), 1358 .msg = "dma_tx_axi_wr_err", 1359 }, 1360 { 1361 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF), 1362 .msg = "dma_tx_axi_rd_err", 1363 }, 1364 { 1365 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF), 1366 .msg = "dma_rx_axi_wr_err", 1367 }, 1368 { 1369 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF), 1370 .msg = "dma_rx_axi_rd_err", 1371 }, 1372 }; 1373 1374 static void handle_chl_int1_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 1375 { 1376 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1); 1377 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1_MSK); 1378 struct device *dev = hisi_hba->dev; 1379 int i; 1380 1381 irq_value &= ~irq_msk; 1382 if (!irq_value) 1383 return; 1384 1385 for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) { 1386 const struct hisi_sas_hw_error *error = &port_axi_error[i]; 1387 1388 if (!(irq_value & error->irq_msk)) 1389 continue; 1390 1391 dev_err(dev, "%s error (phy%d 0x%x) found!\n", 1392 error->msg, phy_no, irq_value); 1393 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1394 } 1395 1396 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT1, irq_value); 1397 } 1398 1399 static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 1400 { 1401 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK); 1402 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2); 1403 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1404 struct pci_dev *pci_dev = hisi_hba->pci_dev; 1405 struct device *dev = hisi_hba->dev; 1406 1407 irq_value &= ~irq_msk; 1408 if (!irq_value) 1409 return; 1410 1411 if (irq_value & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) { 1412 dev_warn(dev, "phy%d identify timeout\n", phy_no); 1413 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1414 } 1415 1416 if (irq_value & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) { 1417 u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, 1418 STP_LINK_TIMEOUT_STATE); 1419 1420 dev_warn(dev, "phy%d stp link timeout (0x%x)\n", 1421 phy_no, reg_value); 1422 if (reg_value & BIT(4)) 1423 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1424 } 1425 1426 if ((irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) && 1427 (pci_dev->revision == 0x20)) { 1428 u32 reg_value; 1429 int rc; 1430 1431 rc = hisi_sas_read32_poll_timeout_atomic( 1432 HILINK_ERR_DFX, reg_value, 1433 !((reg_value >> 8) & BIT(phy_no)), 1434 1000, 10000); 1435 if (rc) 1436 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1437 } 1438 1439 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value); 1440 } 1441 1442 static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) 1443 { 1444 struct hisi_hba *hisi_hba = p; 1445 u32 irq_msk; 1446 int phy_no = 0; 1447 1448 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) 1449 & 0xeeeeeeee; 1450 1451 while (irq_msk) { 1452 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, 1453 CHL_INT0); 1454 1455 if (irq_msk & (4 << (phy_no * 4))) 1456 handle_chl_int1_v3_hw(hisi_hba, phy_no); 1457 1458 if (irq_msk & (8 << (phy_no * 4))) 1459 handle_chl_int2_v3_hw(hisi_hba, phy_no); 1460 1461 if (irq_msk & (2 << (phy_no * 4)) && irq_value0) { 1462 hisi_sas_phy_write32(hisi_hba, phy_no, 1463 CHL_INT0, irq_value0 1464 & (~CHL_INT0_SL_RX_BCST_ACK_MSK) 1465 & (~CHL_INT0_SL_PHY_ENABLE_MSK) 1466 & (~CHL_INT0_NOT_RDY_MSK)); 1467 } 1468 irq_msk &= ~(0xe << (phy_no * 4)); 1469 phy_no++; 1470 } 1471 1472 return IRQ_HANDLED; 1473 } 1474 1475 static const struct hisi_sas_hw_error axi_error[] = { 1476 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" }, 1477 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" }, 1478 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" }, 1479 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" }, 1480 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" }, 1481 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" }, 1482 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" }, 1483 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" }, 1484 {}, 1485 }; 1486 1487 static const struct hisi_sas_hw_error fifo_error[] = { 1488 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" }, 1489 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" }, 1490 { .msk = BIT(10), .msg = "GETDQE_FIFO" }, 1491 { .msk = BIT(11), .msg = "CMDP_FIFO" }, 1492 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" }, 1493 {}, 1494 }; 1495 1496 static const struct hisi_sas_hw_error fatal_axi_error[] = { 1497 { 1498 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF), 1499 .msg = "write pointer and depth", 1500 }, 1501 { 1502 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF), 1503 .msg = "iptt no match slot", 1504 }, 1505 { 1506 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF), 1507 .msg = "read pointer and depth", 1508 }, 1509 { 1510 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF), 1511 .reg = HGC_AXI_FIFO_ERR_INFO, 1512 .sub = axi_error, 1513 }, 1514 { 1515 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF), 1516 .reg = HGC_AXI_FIFO_ERR_INFO, 1517 .sub = fifo_error, 1518 }, 1519 { 1520 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF), 1521 .msg = "LM add/fetch list", 1522 }, 1523 { 1524 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF), 1525 .msg = "SAS_HGC_ABT fetch LM list", 1526 }, 1527 }; 1528 1529 static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p) 1530 { 1531 u32 irq_value, irq_msk; 1532 struct hisi_hba *hisi_hba = p; 1533 struct device *dev = hisi_hba->dev; 1534 int i; 1535 1536 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3); 1537 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00); 1538 1539 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); 1540 irq_value &= ~irq_msk; 1541 1542 for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) { 1543 const struct hisi_sas_hw_error *error = &fatal_axi_error[i]; 1544 1545 if (!(irq_value & error->irq_msk)) 1546 continue; 1547 1548 if (error->sub) { 1549 const struct hisi_sas_hw_error *sub = error->sub; 1550 u32 err_value = hisi_sas_read32(hisi_hba, error->reg); 1551 1552 for (; sub->msk || sub->msg; sub++) { 1553 if (!(err_value & sub->msk)) 1554 continue; 1555 1556 dev_err(dev, "%s error (0x%x) found!\n", 1557 sub->msg, irq_value); 1558 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1559 } 1560 } else { 1561 dev_err(dev, "%s error (0x%x) found!\n", 1562 error->msg, irq_value); 1563 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1564 } 1565 } 1566 1567 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) { 1568 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR); 1569 u32 dev_id = reg_val & ITCT_DEV_MSK; 1570 struct hisi_sas_device *sas_dev = 1571 &hisi_hba->devices[dev_id]; 1572 1573 hisi_sas_write32(hisi_hba, ITCT_CLR, 0); 1574 dev_dbg(dev, "clear ITCT ok\n"); 1575 complete(sas_dev->completion); 1576 } 1577 1578 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00); 1579 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk); 1580 1581 return IRQ_HANDLED; 1582 } 1583 1584 static void 1585 slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task, 1586 struct hisi_sas_slot *slot) 1587 { 1588 struct task_status_struct *ts = &task->task_status; 1589 struct hisi_sas_complete_v3_hdr *complete_queue = 1590 hisi_hba->complete_hdr[slot->cmplt_queue]; 1591 struct hisi_sas_complete_v3_hdr *complete_hdr = 1592 &complete_queue[slot->cmplt_queue_slot]; 1593 struct hisi_sas_err_record_v3 *record = 1594 hisi_sas_status_buf_addr_mem(slot); 1595 u32 dma_rx_err_type = record->dma_rx_err_type; 1596 u32 trans_tx_fail_type = record->trans_tx_fail_type; 1597 1598 switch (task->task_proto) { 1599 case SAS_PROTOCOL_SSP: 1600 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) { 1601 ts->residual = trans_tx_fail_type; 1602 ts->stat = SAS_DATA_UNDERRUN; 1603 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { 1604 ts->stat = SAS_QUEUE_FULL; 1605 slot->abort = 1; 1606 } else { 1607 ts->stat = SAS_OPEN_REJECT; 1608 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1609 } 1610 break; 1611 case SAS_PROTOCOL_SATA: 1612 case SAS_PROTOCOL_STP: 1613 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 1614 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) { 1615 ts->residual = trans_tx_fail_type; 1616 ts->stat = SAS_DATA_UNDERRUN; 1617 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { 1618 ts->stat = SAS_PHY_DOWN; 1619 slot->abort = 1; 1620 } else { 1621 ts->stat = SAS_OPEN_REJECT; 1622 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1623 } 1624 hisi_sas_sata_done(task, slot); 1625 break; 1626 case SAS_PROTOCOL_SMP: 1627 ts->stat = SAM_STAT_CHECK_CONDITION; 1628 break; 1629 default: 1630 break; 1631 } 1632 } 1633 1634 static int 1635 slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot) 1636 { 1637 struct sas_task *task = slot->task; 1638 struct hisi_sas_device *sas_dev; 1639 struct device *dev = hisi_hba->dev; 1640 struct task_status_struct *ts; 1641 struct domain_device *device; 1642 struct sas_ha_struct *ha; 1643 enum exec_status sts; 1644 struct hisi_sas_complete_v3_hdr *complete_queue = 1645 hisi_hba->complete_hdr[slot->cmplt_queue]; 1646 struct hisi_sas_complete_v3_hdr *complete_hdr = 1647 &complete_queue[slot->cmplt_queue_slot]; 1648 unsigned long flags; 1649 bool is_internal = slot->is_internal; 1650 1651 if (unlikely(!task || !task->lldd_task || !task->dev)) 1652 return -EINVAL; 1653 1654 ts = &task->task_status; 1655 device = task->dev; 1656 ha = device->port->ha; 1657 sas_dev = device->lldd_dev; 1658 1659 spin_lock_irqsave(&task->task_state_lock, flags); 1660 task->task_state_flags &= 1661 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR); 1662 spin_unlock_irqrestore(&task->task_state_lock, flags); 1663 1664 memset(ts, 0, sizeof(*ts)); 1665 ts->resp = SAS_TASK_COMPLETE; 1666 1667 if (unlikely(!sas_dev)) { 1668 dev_dbg(dev, "slot complete: port has not device\n"); 1669 ts->stat = SAS_PHY_DOWN; 1670 goto out; 1671 } 1672 1673 /* 1674 * Use SAS+TMF status codes 1675 */ 1676 switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK) 1677 >> CMPLT_HDR_ABORT_STAT_OFF) { 1678 case STAT_IO_ABORTED: 1679 /* this IO has been aborted by abort command */ 1680 ts->stat = SAS_ABORTED_TASK; 1681 goto out; 1682 case STAT_IO_COMPLETE: 1683 /* internal abort command complete */ 1684 ts->stat = TMF_RESP_FUNC_SUCC; 1685 goto out; 1686 case STAT_IO_NO_DEVICE: 1687 ts->stat = TMF_RESP_FUNC_COMPLETE; 1688 goto out; 1689 case STAT_IO_NOT_VALID: 1690 /* 1691 * abort single IO, the controller can't find the IO 1692 */ 1693 ts->stat = TMF_RESP_FUNC_FAILED; 1694 goto out; 1695 default: 1696 break; 1697 } 1698 1699 /* check for erroneous completion */ 1700 if ((complete_hdr->dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) { 1701 u32 *error_info = hisi_sas_status_buf_addr_mem(slot); 1702 1703 slot_err_v3_hw(hisi_hba, task, slot); 1704 if (ts->stat != SAS_DATA_UNDERRUN) 1705 dev_info(dev, "erroneous completion iptt=%d task=%p dev id=%d " 1706 "CQ hdr: 0x%x 0x%x 0x%x 0x%x " 1707 "Error info: 0x%x 0x%x 0x%x 0x%x\n", 1708 slot->idx, task, sas_dev->device_id, 1709 complete_hdr->dw0, complete_hdr->dw1, 1710 complete_hdr->act, complete_hdr->dw3, 1711 error_info[0], error_info[1], 1712 error_info[2], error_info[3]); 1713 if (unlikely(slot->abort)) 1714 return ts->stat; 1715 goto out; 1716 } 1717 1718 switch (task->task_proto) { 1719 case SAS_PROTOCOL_SSP: { 1720 struct ssp_response_iu *iu = 1721 hisi_sas_status_buf_addr_mem(slot) + 1722 sizeof(struct hisi_sas_err_record); 1723 1724 sas_ssp_task_response(dev, task, iu); 1725 break; 1726 } 1727 case SAS_PROTOCOL_SMP: { 1728 struct scatterlist *sg_resp = &task->smp_task.smp_resp; 1729 void *to; 1730 1731 ts->stat = SAM_STAT_GOOD; 1732 to = kmap_atomic(sg_page(sg_resp)); 1733 1734 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1, 1735 DMA_FROM_DEVICE); 1736 dma_unmap_sg(dev, &task->smp_task.smp_req, 1, 1737 DMA_TO_DEVICE); 1738 memcpy(to + sg_resp->offset, 1739 hisi_sas_status_buf_addr_mem(slot) + 1740 sizeof(struct hisi_sas_err_record), 1741 sg_dma_len(sg_resp)); 1742 kunmap_atomic(to); 1743 break; 1744 } 1745 case SAS_PROTOCOL_SATA: 1746 case SAS_PROTOCOL_STP: 1747 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 1748 ts->stat = SAM_STAT_GOOD; 1749 hisi_sas_sata_done(task, slot); 1750 break; 1751 default: 1752 ts->stat = SAM_STAT_CHECK_CONDITION; 1753 break; 1754 } 1755 1756 if (!slot->port->port_attached) { 1757 dev_warn(dev, "slot complete: port %d has removed\n", 1758 slot->port->sas_port.id); 1759 ts->stat = SAS_PHY_DOWN; 1760 } 1761 1762 out: 1763 sts = ts->stat; 1764 spin_lock_irqsave(&task->task_state_lock, flags); 1765 if (task->task_state_flags & SAS_TASK_STATE_ABORTED) { 1766 spin_unlock_irqrestore(&task->task_state_lock, flags); 1767 dev_info(dev, "slot complete: task(%p) aborted\n", task); 1768 return SAS_ABORTED_TASK; 1769 } 1770 task->task_state_flags |= SAS_TASK_STATE_DONE; 1771 spin_unlock_irqrestore(&task->task_state_lock, flags); 1772 hisi_sas_slot_task_free(hisi_hba, task, slot); 1773 1774 if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) { 1775 spin_lock_irqsave(&device->done_lock, flags); 1776 if (test_bit(SAS_HA_FROZEN, &ha->state)) { 1777 spin_unlock_irqrestore(&device->done_lock, flags); 1778 dev_info(dev, "slot complete: task(%p) ignored\n ", 1779 task); 1780 return sts; 1781 } 1782 spin_unlock_irqrestore(&device->done_lock, flags); 1783 } 1784 1785 if (task->task_done) 1786 task->task_done(task); 1787 1788 return sts; 1789 } 1790 1791 static void cq_tasklet_v3_hw(unsigned long val) 1792 { 1793 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val; 1794 struct hisi_hba *hisi_hba = cq->hisi_hba; 1795 struct hisi_sas_slot *slot; 1796 struct hisi_sas_complete_v3_hdr *complete_queue; 1797 u32 rd_point = cq->rd_point, wr_point; 1798 int queue = cq->id; 1799 1800 complete_queue = hisi_hba->complete_hdr[queue]; 1801 1802 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR + 1803 (0x14 * queue)); 1804 1805 while (rd_point != wr_point) { 1806 struct hisi_sas_complete_v3_hdr *complete_hdr; 1807 struct device *dev = hisi_hba->dev; 1808 int iptt; 1809 1810 complete_hdr = &complete_queue[rd_point]; 1811 1812 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK; 1813 if (likely(iptt < HISI_SAS_COMMAND_ENTRIES_V3_HW)) { 1814 slot = &hisi_hba->slot_info[iptt]; 1815 slot->cmplt_queue_slot = rd_point; 1816 slot->cmplt_queue = queue; 1817 slot_complete_v3_hw(hisi_hba, slot); 1818 } else 1819 dev_err(dev, "IPTT %d is invalid, discard it.\n", iptt); 1820 1821 if (++rd_point >= HISI_SAS_QUEUE_SLOTS) 1822 rd_point = 0; 1823 } 1824 1825 /* update rd_point */ 1826 cq->rd_point = rd_point; 1827 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point); 1828 } 1829 1830 static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p) 1831 { 1832 struct hisi_sas_cq *cq = p; 1833 struct hisi_hba *hisi_hba = cq->hisi_hba; 1834 int queue = cq->id; 1835 1836 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue); 1837 1838 tasklet_schedule(&cq->tasklet); 1839 1840 return IRQ_HANDLED; 1841 } 1842 1843 static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba) 1844 { 1845 struct device *dev = hisi_hba->dev; 1846 struct pci_dev *pdev = hisi_hba->pci_dev; 1847 int vectors, rc; 1848 int i, k; 1849 int max_msi = HISI_SAS_MSI_COUNT_V3_HW; 1850 1851 vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, 1, 1852 max_msi, PCI_IRQ_MSI); 1853 if (vectors < max_msi) { 1854 dev_err(dev, "could not allocate all msi (%d)\n", vectors); 1855 return -ENOENT; 1856 } 1857 1858 rc = devm_request_irq(dev, pci_irq_vector(pdev, 1), 1859 int_phy_up_down_bcast_v3_hw, 0, 1860 DRV_NAME " phy", hisi_hba); 1861 if (rc) { 1862 dev_err(dev, "could not request phy interrupt, rc=%d\n", rc); 1863 rc = -ENOENT; 1864 goto free_irq_vectors; 1865 } 1866 1867 rc = devm_request_irq(dev, pci_irq_vector(pdev, 2), 1868 int_chnl_int_v3_hw, 0, 1869 DRV_NAME " channel", hisi_hba); 1870 if (rc) { 1871 dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc); 1872 rc = -ENOENT; 1873 goto free_phy_irq; 1874 } 1875 1876 rc = devm_request_irq(dev, pci_irq_vector(pdev, 11), 1877 fatal_axi_int_v3_hw, 0, 1878 DRV_NAME " fatal", hisi_hba); 1879 if (rc) { 1880 dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc); 1881 rc = -ENOENT; 1882 goto free_chnl_interrupt; 1883 } 1884 1885 /* Init tasklets for cq only */ 1886 for (i = 0; i < hisi_hba->queue_count; i++) { 1887 struct hisi_sas_cq *cq = &hisi_hba->cq[i]; 1888 struct tasklet_struct *t = &cq->tasklet; 1889 int nr = hisi_sas_intr_conv ? 16 : 16 + i; 1890 unsigned long irqflags = hisi_sas_intr_conv ? IRQF_SHARED : 0; 1891 1892 rc = devm_request_irq(dev, pci_irq_vector(pdev, nr), 1893 cq_interrupt_v3_hw, irqflags, 1894 DRV_NAME " cq", cq); 1895 if (rc) { 1896 dev_err(dev, 1897 "could not request cq%d interrupt, rc=%d\n", 1898 i, rc); 1899 rc = -ENOENT; 1900 goto free_cq_irqs; 1901 } 1902 1903 tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq); 1904 } 1905 1906 return 0; 1907 1908 free_cq_irqs: 1909 for (k = 0; k < i; k++) { 1910 struct hisi_sas_cq *cq = &hisi_hba->cq[k]; 1911 int nr = hisi_sas_intr_conv ? 16 : 16 + k; 1912 1913 free_irq(pci_irq_vector(pdev, nr), cq); 1914 } 1915 free_irq(pci_irq_vector(pdev, 11), hisi_hba); 1916 free_chnl_interrupt: 1917 free_irq(pci_irq_vector(pdev, 2), hisi_hba); 1918 free_phy_irq: 1919 free_irq(pci_irq_vector(pdev, 1), hisi_hba); 1920 free_irq_vectors: 1921 pci_free_irq_vectors(pdev); 1922 return rc; 1923 } 1924 1925 static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) 1926 { 1927 int rc; 1928 1929 rc = hw_init_v3_hw(hisi_hba); 1930 if (rc) 1931 return rc; 1932 1933 rc = interrupt_init_v3_hw(hisi_hba); 1934 if (rc) 1935 return rc; 1936 1937 return 0; 1938 } 1939 1940 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no, 1941 struct sas_phy_linkrates *r) 1942 { 1943 enum sas_linkrate max = r->maximum_linkrate; 1944 u32 prog_phy_link_rate = 0x800; 1945 1946 prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max); 1947 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, 1948 prog_phy_link_rate); 1949 } 1950 1951 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba) 1952 { 1953 struct pci_dev *pdev = hisi_hba->pci_dev; 1954 int i; 1955 1956 synchronize_irq(pci_irq_vector(pdev, 1)); 1957 synchronize_irq(pci_irq_vector(pdev, 2)); 1958 synchronize_irq(pci_irq_vector(pdev, 11)); 1959 for (i = 0; i < hisi_hba->queue_count; i++) { 1960 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1); 1961 synchronize_irq(pci_irq_vector(pdev, i + 16)); 1962 } 1963 1964 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff); 1965 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff); 1966 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff); 1967 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff); 1968 1969 for (i = 0; i < hisi_hba->n_phy; i++) { 1970 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff); 1971 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff); 1972 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1); 1973 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1); 1974 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1); 1975 } 1976 } 1977 1978 static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba) 1979 { 1980 return hisi_sas_read32(hisi_hba, PHY_STATE); 1981 } 1982 1983 static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 1984 { 1985 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1986 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1987 struct sas_phy *sphy = sas_phy->phy; 1988 u32 reg_value; 1989 1990 /* loss dword sync */ 1991 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST); 1992 sphy->loss_of_dword_sync_count += reg_value; 1993 1994 /* phy reset problem */ 1995 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB); 1996 sphy->phy_reset_problem_count += reg_value; 1997 1998 /* invalid dword */ 1999 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW); 2000 sphy->invalid_dword_count += reg_value; 2001 2002 /* disparity err */ 2003 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR); 2004 sphy->running_disparity_error_count += reg_value; 2005 2006 } 2007 2008 static int disable_host_v3_hw(struct hisi_hba *hisi_hba) 2009 { 2010 struct device *dev = hisi_hba->dev; 2011 u32 status, reg_val; 2012 int rc; 2013 2014 interrupt_disable_v3_hw(hisi_hba); 2015 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0); 2016 hisi_sas_kill_tasklets(hisi_hba); 2017 2018 hisi_sas_stop_phys(hisi_hba); 2019 2020 mdelay(10); 2021 2022 reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE + 2023 AM_CTRL_GLOBAL); 2024 reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK; 2025 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + 2026 AM_CTRL_GLOBAL, reg_val); 2027 2028 /* wait until bus idle */ 2029 rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE + 2030 AM_CURR_TRANS_RETURN, status, 2031 status == 0x3, 10, 100); 2032 if (rc) { 2033 dev_err(dev, "axi bus is not idle, rc=%d\n", rc); 2034 return rc; 2035 } 2036 2037 return 0; 2038 } 2039 2040 static int soft_reset_v3_hw(struct hisi_hba *hisi_hba) 2041 { 2042 struct device *dev = hisi_hba->dev; 2043 int rc; 2044 2045 rc = disable_host_v3_hw(hisi_hba); 2046 if (rc) { 2047 dev_err(dev, "soft reset: disable host failed rc=%d\n", rc); 2048 return rc; 2049 } 2050 2051 hisi_sas_init_mem(hisi_hba); 2052 2053 return hw_init_v3_hw(hisi_hba); 2054 } 2055 2056 static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type, 2057 u8 reg_index, u8 reg_count, u8 *write_data) 2058 { 2059 struct device *dev = hisi_hba->dev; 2060 u32 *data = (u32 *)write_data; 2061 int i; 2062 2063 switch (reg_type) { 2064 case SAS_GPIO_REG_TX: 2065 if ((reg_index + reg_count) > ((hisi_hba->n_phy + 3) / 4)) { 2066 dev_err(dev, "write gpio: invalid reg range[%d, %d]\n", 2067 reg_index, reg_index + reg_count - 1); 2068 return -EINVAL; 2069 } 2070 2071 for (i = 0; i < reg_count; i++) 2072 hisi_sas_write32(hisi_hba, 2073 SAS_GPIO_TX_0_1 + (reg_index + i) * 4, 2074 data[i]); 2075 break; 2076 default: 2077 dev_err(dev, "write gpio: unsupported or bad reg type %d\n", 2078 reg_type); 2079 return -EINVAL; 2080 } 2081 2082 return 0; 2083 } 2084 2085 static void wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba, 2086 int delay_ms, int timeout_ms) 2087 { 2088 struct device *dev = hisi_hba->dev; 2089 int entries, entries_old = 0, time; 2090 2091 for (time = 0; time < timeout_ms; time += delay_ms) { 2092 entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT); 2093 if (entries == entries_old) 2094 break; 2095 2096 entries_old = entries; 2097 msleep(delay_ms); 2098 } 2099 2100 dev_dbg(dev, "wait commands complete %dms\n", time); 2101 } 2102 2103 static ssize_t intr_conv_v3_hw_show(struct device *dev, 2104 struct device_attribute *attr, char *buf) 2105 { 2106 return scnprintf(buf, PAGE_SIZE, "%u\n", hisi_sas_intr_conv); 2107 } 2108 static DEVICE_ATTR_RO(intr_conv_v3_hw); 2109 2110 static void config_intr_coal_v3_hw(struct hisi_hba *hisi_hba) 2111 { 2112 /* config those registers between enable and disable PHYs */ 2113 hisi_sas_stop_phys(hisi_hba); 2114 2115 if (hisi_hba->intr_coal_ticks == 0 || 2116 hisi_hba->intr_coal_count == 0) { 2117 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); 2118 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); 2119 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); 2120 } else { 2121 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x3); 2122 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 2123 hisi_hba->intr_coal_ticks); 2124 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 2125 hisi_hba->intr_coal_count); 2126 } 2127 phys_init_v3_hw(hisi_hba); 2128 } 2129 2130 static ssize_t intr_coal_ticks_v3_hw_show(struct device *dev, 2131 struct device_attribute *attr, 2132 char *buf) 2133 { 2134 struct Scsi_Host *shost = class_to_shost(dev); 2135 struct hisi_hba *hisi_hba = shost_priv(shost); 2136 2137 return scnprintf(buf, PAGE_SIZE, "%u\n", 2138 hisi_hba->intr_coal_ticks); 2139 } 2140 2141 static ssize_t intr_coal_ticks_v3_hw_store(struct device *dev, 2142 struct device_attribute *attr, 2143 const char *buf, size_t count) 2144 { 2145 struct Scsi_Host *shost = class_to_shost(dev); 2146 struct hisi_hba *hisi_hba = shost_priv(shost); 2147 u32 intr_coal_ticks; 2148 int ret; 2149 2150 ret = kstrtou32(buf, 10, &intr_coal_ticks); 2151 if (ret) { 2152 dev_err(dev, "Input data of interrupt coalesce unmatch\n"); 2153 return -EINVAL; 2154 } 2155 2156 if (intr_coal_ticks >= BIT(24)) { 2157 dev_err(dev, "intr_coal_ticks must be less than 2^24!\n"); 2158 return -EINVAL; 2159 } 2160 2161 hisi_hba->intr_coal_ticks = intr_coal_ticks; 2162 2163 config_intr_coal_v3_hw(hisi_hba); 2164 2165 return count; 2166 } 2167 static DEVICE_ATTR_RW(intr_coal_ticks_v3_hw); 2168 2169 static ssize_t intr_coal_count_v3_hw_show(struct device *dev, 2170 struct device_attribute 2171 *attr, char *buf) 2172 { 2173 struct Scsi_Host *shost = class_to_shost(dev); 2174 struct hisi_hba *hisi_hba = shost_priv(shost); 2175 2176 return scnprintf(buf, PAGE_SIZE, "%u\n", 2177 hisi_hba->intr_coal_count); 2178 } 2179 2180 static ssize_t intr_coal_count_v3_hw_store(struct device *dev, 2181 struct device_attribute 2182 *attr, const char *buf, size_t count) 2183 { 2184 struct Scsi_Host *shost = class_to_shost(dev); 2185 struct hisi_hba *hisi_hba = shost_priv(shost); 2186 u32 intr_coal_count; 2187 int ret; 2188 2189 ret = kstrtou32(buf, 10, &intr_coal_count); 2190 if (ret) { 2191 dev_err(dev, "Input data of interrupt coalesce unmatch\n"); 2192 return -EINVAL; 2193 } 2194 2195 if (intr_coal_count >= BIT(8)) { 2196 dev_err(dev, "intr_coal_count must be less than 2^8!\n"); 2197 return -EINVAL; 2198 } 2199 2200 hisi_hba->intr_coal_count = intr_coal_count; 2201 2202 config_intr_coal_v3_hw(hisi_hba); 2203 2204 return count; 2205 } 2206 static DEVICE_ATTR_RW(intr_coal_count_v3_hw); 2207 2208 struct device_attribute *host_attrs_v3_hw[] = { 2209 &dev_attr_phy_event_threshold, 2210 &dev_attr_intr_conv_v3_hw, 2211 &dev_attr_intr_coal_ticks_v3_hw, 2212 &dev_attr_intr_coal_count_v3_hw, 2213 NULL 2214 }; 2215 2216 static struct scsi_host_template sht_v3_hw = { 2217 .name = DRV_NAME, 2218 .module = THIS_MODULE, 2219 .queuecommand = sas_queuecommand, 2220 .target_alloc = sas_target_alloc, 2221 .slave_configure = hisi_sas_slave_configure, 2222 .scan_finished = hisi_sas_scan_finished, 2223 .scan_start = hisi_sas_scan_start, 2224 .change_queue_depth = sas_change_queue_depth, 2225 .bios_param = sas_bios_param, 2226 .this_id = -1, 2227 .sg_tablesize = SG_ALL, 2228 .max_sectors = SCSI_DEFAULT_MAX_SECTORS, 2229 .use_clustering = ENABLE_CLUSTERING, 2230 .eh_device_reset_handler = sas_eh_device_reset_handler, 2231 .eh_target_reset_handler = sas_eh_target_reset_handler, 2232 .target_destroy = sas_target_destroy, 2233 .ioctl = sas_ioctl, 2234 .shost_attrs = host_attrs_v3_hw, 2235 .tag_alloc_policy = BLK_TAG_ALLOC_RR, 2236 }; 2237 2238 static const struct hisi_sas_hw hisi_sas_v3_hw = { 2239 .hw_init = hisi_sas_v3_init, 2240 .setup_itct = setup_itct_v3_hw, 2241 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW, 2242 .get_wideport_bitmap = get_wideport_bitmap_v3_hw, 2243 .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr), 2244 .clear_itct = clear_itct_v3_hw, 2245 .sl_notify = sl_notify_v3_hw, 2246 .prep_ssp = prep_ssp_v3_hw, 2247 .prep_smp = prep_smp_v3_hw, 2248 .prep_stp = prep_ata_v3_hw, 2249 .prep_abort = prep_abort_v3_hw, 2250 .get_free_slot = get_free_slot_v3_hw, 2251 .start_delivery = start_delivery_v3_hw, 2252 .slot_complete = slot_complete_v3_hw, 2253 .phys_init = phys_init_v3_hw, 2254 .phy_start = start_phy_v3_hw, 2255 .phy_disable = disable_phy_v3_hw, 2256 .phy_hard_reset = phy_hard_reset_v3_hw, 2257 .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw, 2258 .phy_set_linkrate = phy_set_linkrate_v3_hw, 2259 .dereg_device = dereg_device_v3_hw, 2260 .soft_reset = soft_reset_v3_hw, 2261 .get_phys_state = get_phys_state_v3_hw, 2262 .get_events = phy_get_events_v3_hw, 2263 .write_gpio = write_gpio_v3_hw, 2264 .wait_cmds_complete_timeout = wait_cmds_complete_timeout_v3_hw, 2265 }; 2266 2267 static struct Scsi_Host * 2268 hisi_sas_shost_alloc_pci(struct pci_dev *pdev) 2269 { 2270 struct Scsi_Host *shost; 2271 struct hisi_hba *hisi_hba; 2272 struct device *dev = &pdev->dev; 2273 2274 shost = scsi_host_alloc(&sht_v3_hw, sizeof(*hisi_hba)); 2275 if (!shost) { 2276 dev_err(dev, "shost alloc failed\n"); 2277 return NULL; 2278 } 2279 hisi_hba = shost_priv(shost); 2280 2281 INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler); 2282 hisi_hba->hw = &hisi_sas_v3_hw; 2283 hisi_hba->pci_dev = pdev; 2284 hisi_hba->dev = dev; 2285 hisi_hba->shost = shost; 2286 SHOST_TO_SAS_HA(shost) = &hisi_hba->sha; 2287 2288 timer_setup(&hisi_hba->timer, NULL, 0); 2289 2290 if (hisi_sas_get_fw_info(hisi_hba) < 0) 2291 goto err_out; 2292 2293 if (hisi_sas_alloc(hisi_hba, shost)) { 2294 hisi_sas_free(hisi_hba); 2295 goto err_out; 2296 } 2297 2298 return shost; 2299 err_out: 2300 scsi_host_put(shost); 2301 dev_err(dev, "shost alloc failed\n"); 2302 return NULL; 2303 } 2304 2305 static int 2306 hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2307 { 2308 struct Scsi_Host *shost; 2309 struct hisi_hba *hisi_hba; 2310 struct device *dev = &pdev->dev; 2311 struct asd_sas_phy **arr_phy; 2312 struct asd_sas_port **arr_port; 2313 struct sas_ha_struct *sha; 2314 int rc, phy_nr, port_nr, i; 2315 2316 rc = pci_enable_device(pdev); 2317 if (rc) 2318 goto err_out; 2319 2320 pci_set_master(pdev); 2321 2322 rc = pci_request_regions(pdev, DRV_NAME); 2323 if (rc) 2324 goto err_out_disable_device; 2325 2326 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) || 2327 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32))) { 2328 dev_err(dev, "No usable DMA addressing method\n"); 2329 rc = -EIO; 2330 goto err_out_regions; 2331 } 2332 2333 shost = hisi_sas_shost_alloc_pci(pdev); 2334 if (!shost) { 2335 rc = -ENOMEM; 2336 goto err_out_regions; 2337 } 2338 2339 sha = SHOST_TO_SAS_HA(shost); 2340 hisi_hba = shost_priv(shost); 2341 dev_set_drvdata(dev, sha); 2342 2343 hisi_hba->regs = pcim_iomap(pdev, 5, 0); 2344 if (!hisi_hba->regs) { 2345 dev_err(dev, "cannot map register.\n"); 2346 rc = -ENOMEM; 2347 goto err_out_ha; 2348 } 2349 2350 phy_nr = port_nr = hisi_hba->n_phy; 2351 2352 arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL); 2353 arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL); 2354 if (!arr_phy || !arr_port) { 2355 rc = -ENOMEM; 2356 goto err_out_ha; 2357 } 2358 2359 sha->sas_phy = arr_phy; 2360 sha->sas_port = arr_port; 2361 sha->core.shost = shost; 2362 sha->lldd_ha = hisi_hba; 2363 2364 shost->transportt = hisi_sas_stt; 2365 shost->max_id = HISI_SAS_MAX_DEVICES; 2366 shost->max_lun = ~0; 2367 shost->max_channel = 1; 2368 shost->max_cmd_len = 16; 2369 shost->sg_tablesize = min_t(u16, SG_ALL, HISI_SAS_SGE_PAGE_CNT); 2370 shost->can_queue = hisi_hba->hw->max_command_entries - 2371 HISI_SAS_RESERVED_IPTT_CNT; 2372 shost->cmd_per_lun = hisi_hba->hw->max_command_entries - 2373 HISI_SAS_RESERVED_IPTT_CNT; 2374 2375 sha->sas_ha_name = DRV_NAME; 2376 sha->dev = dev; 2377 sha->lldd_module = THIS_MODULE; 2378 sha->sas_addr = &hisi_hba->sas_addr[0]; 2379 sha->num_phys = hisi_hba->n_phy; 2380 sha->core.shost = hisi_hba->shost; 2381 2382 for (i = 0; i < hisi_hba->n_phy; i++) { 2383 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy; 2384 sha->sas_port[i] = &hisi_hba->port[i].sas_port; 2385 } 2386 2387 rc = scsi_add_host(shost, dev); 2388 if (rc) 2389 goto err_out_ha; 2390 2391 rc = sas_register_ha(sha); 2392 if (rc) 2393 goto err_out_register_ha; 2394 2395 rc = hisi_hba->hw->hw_init(hisi_hba); 2396 if (rc) 2397 goto err_out_register_ha; 2398 2399 scsi_scan_host(shost); 2400 2401 return 0; 2402 2403 err_out_register_ha: 2404 scsi_remove_host(shost); 2405 err_out_ha: 2406 scsi_host_put(shost); 2407 err_out_regions: 2408 pci_release_regions(pdev); 2409 err_out_disable_device: 2410 pci_disable_device(pdev); 2411 err_out: 2412 return rc; 2413 } 2414 2415 static void 2416 hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba) 2417 { 2418 int i; 2419 2420 free_irq(pci_irq_vector(pdev, 1), hisi_hba); 2421 free_irq(pci_irq_vector(pdev, 2), hisi_hba); 2422 free_irq(pci_irq_vector(pdev, 11), hisi_hba); 2423 for (i = 0; i < hisi_hba->queue_count; i++) { 2424 struct hisi_sas_cq *cq = &hisi_hba->cq[i]; 2425 int nr = hisi_sas_intr_conv ? 16 : 16 + i; 2426 2427 free_irq(pci_irq_vector(pdev, nr), cq); 2428 } 2429 pci_free_irq_vectors(pdev); 2430 } 2431 2432 static void hisi_sas_v3_remove(struct pci_dev *pdev) 2433 { 2434 struct device *dev = &pdev->dev; 2435 struct sas_ha_struct *sha = dev_get_drvdata(dev); 2436 struct hisi_hba *hisi_hba = sha->lldd_ha; 2437 struct Scsi_Host *shost = sha->core.shost; 2438 2439 if (timer_pending(&hisi_hba->timer)) 2440 del_timer(&hisi_hba->timer); 2441 2442 sas_unregister_ha(sha); 2443 sas_remove_host(sha->core.shost); 2444 2445 hisi_sas_v3_destroy_irqs(pdev, hisi_hba); 2446 hisi_sas_kill_tasklets(hisi_hba); 2447 pci_release_regions(pdev); 2448 pci_disable_device(pdev); 2449 hisi_sas_free(hisi_hba); 2450 scsi_host_put(shost); 2451 } 2452 2453 static const struct hisi_sas_hw_error sas_ras_intr0_nfe[] = { 2454 { .irq_msk = BIT(19), .msg = "HILINK_INT" }, 2455 { .irq_msk = BIT(20), .msg = "HILINK_PLL0_OUT_OF_LOCK" }, 2456 { .irq_msk = BIT(21), .msg = "HILINK_PLL1_OUT_OF_LOCK" }, 2457 { .irq_msk = BIT(22), .msg = "HILINK_LOSS_OF_REFCLK0" }, 2458 { .irq_msk = BIT(23), .msg = "HILINK_LOSS_OF_REFCLK1" }, 2459 { .irq_msk = BIT(24), .msg = "DMAC0_TX_POISON" }, 2460 { .irq_msk = BIT(25), .msg = "DMAC1_TX_POISON" }, 2461 { .irq_msk = BIT(26), .msg = "DMAC2_TX_POISON" }, 2462 { .irq_msk = BIT(27), .msg = "DMAC3_TX_POISON" }, 2463 { .irq_msk = BIT(28), .msg = "DMAC4_TX_POISON" }, 2464 { .irq_msk = BIT(29), .msg = "DMAC5_TX_POISON" }, 2465 { .irq_msk = BIT(30), .msg = "DMAC6_TX_POISON" }, 2466 { .irq_msk = BIT(31), .msg = "DMAC7_TX_POISON" }, 2467 }; 2468 2469 static const struct hisi_sas_hw_error sas_ras_intr1_nfe[] = { 2470 { .irq_msk = BIT(0), .msg = "RXM_CFG_MEM3_ECC2B_INTR" }, 2471 { .irq_msk = BIT(1), .msg = "RXM_CFG_MEM2_ECC2B_INTR" }, 2472 { .irq_msk = BIT(2), .msg = "RXM_CFG_MEM1_ECC2B_INTR" }, 2473 { .irq_msk = BIT(3), .msg = "RXM_CFG_MEM0_ECC2B_INTR" }, 2474 { .irq_msk = BIT(4), .msg = "HGC_CQE_ECC2B_INTR" }, 2475 { .irq_msk = BIT(5), .msg = "LM_CFG_IOSTL_ECC2B_INTR" }, 2476 { .irq_msk = BIT(6), .msg = "LM_CFG_ITCTL_ECC2B_INTR" }, 2477 { .irq_msk = BIT(7), .msg = "HGC_ITCT_ECC2B_INTR" }, 2478 { .irq_msk = BIT(8), .msg = "HGC_IOST_ECC2B_INTR" }, 2479 { .irq_msk = BIT(9), .msg = "HGC_DQE_ECC2B_INTR" }, 2480 { .irq_msk = BIT(10), .msg = "DMAC0_RAM_ECC2B_INTR" }, 2481 { .irq_msk = BIT(11), .msg = "DMAC1_RAM_ECC2B_INTR" }, 2482 { .irq_msk = BIT(12), .msg = "DMAC2_RAM_ECC2B_INTR" }, 2483 { .irq_msk = BIT(13), .msg = "DMAC3_RAM_ECC2B_INTR" }, 2484 { .irq_msk = BIT(14), .msg = "DMAC4_RAM_ECC2B_INTR" }, 2485 { .irq_msk = BIT(15), .msg = "DMAC5_RAM_ECC2B_INTR" }, 2486 { .irq_msk = BIT(16), .msg = "DMAC6_RAM_ECC2B_INTR" }, 2487 { .irq_msk = BIT(17), .msg = "DMAC7_RAM_ECC2B_INTR" }, 2488 { .irq_msk = BIT(18), .msg = "OOO_RAM_ECC2B_INTR" }, 2489 { .irq_msk = BIT(20), .msg = "HGC_DQE_POISON_INTR" }, 2490 { .irq_msk = BIT(21), .msg = "HGC_IOST_POISON_INTR" }, 2491 { .irq_msk = BIT(22), .msg = "HGC_ITCT_POISON_INTR" }, 2492 { .irq_msk = BIT(23), .msg = "HGC_ITCT_NCQ_POISON_INTR" }, 2493 { .irq_msk = BIT(24), .msg = "DMAC0_RX_POISON" }, 2494 { .irq_msk = BIT(25), .msg = "DMAC1_RX_POISON" }, 2495 { .irq_msk = BIT(26), .msg = "DMAC2_RX_POISON" }, 2496 { .irq_msk = BIT(27), .msg = "DMAC3_RX_POISON" }, 2497 { .irq_msk = BIT(28), .msg = "DMAC4_RX_POISON" }, 2498 { .irq_msk = BIT(29), .msg = "DMAC5_RX_POISON" }, 2499 { .irq_msk = BIT(30), .msg = "DMAC6_RX_POISON" }, 2500 { .irq_msk = BIT(31), .msg = "DMAC7_RX_POISON" }, 2501 }; 2502 2503 static const struct hisi_sas_hw_error sas_ras_intr2_nfe[] = { 2504 { .irq_msk = BIT(0), .msg = "DMAC0_AXI_BUS_ERR" }, 2505 { .irq_msk = BIT(1), .msg = "DMAC1_AXI_BUS_ERR" }, 2506 { .irq_msk = BIT(2), .msg = "DMAC2_AXI_BUS_ERR" }, 2507 { .irq_msk = BIT(3), .msg = "DMAC3_AXI_BUS_ERR" }, 2508 { .irq_msk = BIT(4), .msg = "DMAC4_AXI_BUS_ERR" }, 2509 { .irq_msk = BIT(5), .msg = "DMAC5_AXI_BUS_ERR" }, 2510 { .irq_msk = BIT(6), .msg = "DMAC6_AXI_BUS_ERR" }, 2511 { .irq_msk = BIT(7), .msg = "DMAC7_AXI_BUS_ERR" }, 2512 { .irq_msk = BIT(8), .msg = "DMAC0_FIFO_OMIT_ERR" }, 2513 { .irq_msk = BIT(9), .msg = "DMAC1_FIFO_OMIT_ERR" }, 2514 { .irq_msk = BIT(10), .msg = "DMAC2_FIFO_OMIT_ERR" }, 2515 { .irq_msk = BIT(11), .msg = "DMAC3_FIFO_OMIT_ERR" }, 2516 { .irq_msk = BIT(12), .msg = "DMAC4_FIFO_OMIT_ERR" }, 2517 { .irq_msk = BIT(13), .msg = "DMAC5_FIFO_OMIT_ERR" }, 2518 { .irq_msk = BIT(14), .msg = "DMAC6_FIFO_OMIT_ERR" }, 2519 { .irq_msk = BIT(15), .msg = "DMAC7_FIFO_OMIT_ERR" }, 2520 { .irq_msk = BIT(16), .msg = "HGC_RLSE_SLOT_UNMATCH" }, 2521 { .irq_msk = BIT(17), .msg = "HGC_LM_ADD_FCH_LIST_ERR" }, 2522 { .irq_msk = BIT(18), .msg = "HGC_AXI_BUS_ERR" }, 2523 { .irq_msk = BIT(19), .msg = "HGC_FIFO_OMIT_ERR" }, 2524 }; 2525 2526 static bool process_non_fatal_error_v3_hw(struct hisi_hba *hisi_hba) 2527 { 2528 struct device *dev = hisi_hba->dev; 2529 const struct hisi_sas_hw_error *ras_error; 2530 bool need_reset = false; 2531 u32 irq_value; 2532 int i; 2533 2534 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR0); 2535 for (i = 0; i < ARRAY_SIZE(sas_ras_intr0_nfe); i++) { 2536 ras_error = &sas_ras_intr0_nfe[i]; 2537 if (ras_error->irq_msk & irq_value) { 2538 dev_warn(dev, "SAS_RAS_INTR0: %s(irq_value=0x%x) found.\n", 2539 ras_error->msg, irq_value); 2540 need_reset = true; 2541 } 2542 } 2543 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0, irq_value); 2544 2545 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR1); 2546 for (i = 0; i < ARRAY_SIZE(sas_ras_intr1_nfe); i++) { 2547 ras_error = &sas_ras_intr1_nfe[i]; 2548 if (ras_error->irq_msk & irq_value) { 2549 dev_warn(dev, "SAS_RAS_INTR1: %s(irq_value=0x%x) found.\n", 2550 ras_error->msg, irq_value); 2551 need_reset = true; 2552 } 2553 } 2554 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1, irq_value); 2555 2556 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR2); 2557 for (i = 0; i < ARRAY_SIZE(sas_ras_intr2_nfe); i++) { 2558 ras_error = &sas_ras_intr2_nfe[i]; 2559 if (ras_error->irq_msk & irq_value) { 2560 dev_warn(dev, "SAS_RAS_INTR2: %s(irq_value=0x%x) found.\n", 2561 ras_error->msg, irq_value); 2562 need_reset = true; 2563 } 2564 } 2565 hisi_sas_write32(hisi_hba, SAS_RAS_INTR2, irq_value); 2566 2567 return need_reset; 2568 } 2569 2570 static pci_ers_result_t hisi_sas_error_detected_v3_hw(struct pci_dev *pdev, 2571 pci_channel_state_t state) 2572 { 2573 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2574 struct hisi_hba *hisi_hba = sha->lldd_ha; 2575 struct device *dev = hisi_hba->dev; 2576 2577 dev_info(dev, "PCI error: detected callback, state(%d)!!\n", state); 2578 if (state == pci_channel_io_perm_failure) 2579 return PCI_ERS_RESULT_DISCONNECT; 2580 2581 if (process_non_fatal_error_v3_hw(hisi_hba)) 2582 return PCI_ERS_RESULT_NEED_RESET; 2583 2584 return PCI_ERS_RESULT_CAN_RECOVER; 2585 } 2586 2587 static pci_ers_result_t hisi_sas_mmio_enabled_v3_hw(struct pci_dev *pdev) 2588 { 2589 return PCI_ERS_RESULT_RECOVERED; 2590 } 2591 2592 static pci_ers_result_t hisi_sas_slot_reset_v3_hw(struct pci_dev *pdev) 2593 { 2594 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2595 struct hisi_hba *hisi_hba = sha->lldd_ha; 2596 struct device *dev = hisi_hba->dev; 2597 HISI_SAS_DECLARE_RST_WORK_ON_STACK(r); 2598 2599 dev_info(dev, "PCI error: slot reset callback!!\n"); 2600 queue_work(hisi_hba->wq, &r.work); 2601 wait_for_completion(r.completion); 2602 if (r.done) 2603 return PCI_ERS_RESULT_RECOVERED; 2604 2605 return PCI_ERS_RESULT_DISCONNECT; 2606 } 2607 2608 static void hisi_sas_reset_prepare_v3_hw(struct pci_dev *pdev) 2609 { 2610 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2611 struct hisi_hba *hisi_hba = sha->lldd_ha; 2612 struct device *dev = hisi_hba->dev; 2613 int rc; 2614 2615 dev_info(dev, "FLR prepare\n"); 2616 set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 2617 hisi_sas_controller_reset_prepare(hisi_hba); 2618 2619 rc = disable_host_v3_hw(hisi_hba); 2620 if (rc) 2621 dev_err(dev, "FLR: disable host failed rc=%d\n", rc); 2622 } 2623 2624 static void hisi_sas_reset_done_v3_hw(struct pci_dev *pdev) 2625 { 2626 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2627 struct hisi_hba *hisi_hba = sha->lldd_ha; 2628 struct device *dev = hisi_hba->dev; 2629 int rc; 2630 2631 hisi_sas_init_mem(hisi_hba); 2632 2633 rc = hw_init_v3_hw(hisi_hba); 2634 if (rc) { 2635 dev_err(dev, "FLR: hw init failed rc=%d\n", rc); 2636 return; 2637 } 2638 2639 hisi_sas_controller_reset_done(hisi_hba); 2640 dev_info(dev, "FLR done\n"); 2641 } 2642 2643 enum { 2644 /* instances of the controller */ 2645 hip08, 2646 }; 2647 2648 static int hisi_sas_v3_suspend(struct pci_dev *pdev, pm_message_t state) 2649 { 2650 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2651 struct hisi_hba *hisi_hba = sha->lldd_ha; 2652 struct device *dev = hisi_hba->dev; 2653 struct Scsi_Host *shost = hisi_hba->shost; 2654 u32 device_state; 2655 int rc; 2656 2657 if (!pdev->pm_cap) { 2658 dev_err(dev, "PCI PM not supported\n"); 2659 return -ENODEV; 2660 } 2661 2662 if (test_and_set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)) 2663 return -1; 2664 2665 scsi_block_requests(shost); 2666 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 2667 flush_workqueue(hisi_hba->wq); 2668 2669 rc = disable_host_v3_hw(hisi_hba); 2670 if (rc) { 2671 dev_err(dev, "PM suspend: disable host failed rc=%d\n", rc); 2672 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 2673 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 2674 scsi_unblock_requests(shost); 2675 return rc; 2676 } 2677 2678 hisi_sas_init_mem(hisi_hba); 2679 2680 device_state = pci_choose_state(pdev, state); 2681 dev_warn(dev, "entering operating state [D%d]\n", 2682 device_state); 2683 pci_save_state(pdev); 2684 pci_disable_device(pdev); 2685 pci_set_power_state(pdev, device_state); 2686 2687 hisi_sas_release_tasks(hisi_hba); 2688 2689 sas_suspend_ha(sha); 2690 return 0; 2691 } 2692 2693 static int hisi_sas_v3_resume(struct pci_dev *pdev) 2694 { 2695 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2696 struct hisi_hba *hisi_hba = sha->lldd_ha; 2697 struct Scsi_Host *shost = hisi_hba->shost; 2698 struct device *dev = hisi_hba->dev; 2699 unsigned int rc; 2700 u32 device_state = pdev->current_state; 2701 2702 dev_warn(dev, "resuming from operating state [D%d]\n", 2703 device_state); 2704 pci_set_power_state(pdev, PCI_D0); 2705 pci_enable_wake(pdev, PCI_D0, 0); 2706 pci_restore_state(pdev); 2707 rc = pci_enable_device(pdev); 2708 if (rc) 2709 dev_err(dev, "enable device failed during resume (%d)\n", rc); 2710 2711 pci_set_master(pdev); 2712 scsi_unblock_requests(shost); 2713 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 2714 2715 sas_prep_resume_ha(sha); 2716 init_reg_v3_hw(hisi_hba); 2717 hisi_hba->hw->phys_init(hisi_hba); 2718 sas_resume_ha(sha); 2719 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 2720 2721 return 0; 2722 } 2723 2724 static const struct pci_device_id sas_v3_pci_table[] = { 2725 { PCI_VDEVICE(HUAWEI, 0xa230), hip08 }, 2726 {} 2727 }; 2728 MODULE_DEVICE_TABLE(pci, sas_v3_pci_table); 2729 2730 static const struct pci_error_handlers hisi_sas_err_handler = { 2731 .error_detected = hisi_sas_error_detected_v3_hw, 2732 .mmio_enabled = hisi_sas_mmio_enabled_v3_hw, 2733 .slot_reset = hisi_sas_slot_reset_v3_hw, 2734 .reset_prepare = hisi_sas_reset_prepare_v3_hw, 2735 .reset_done = hisi_sas_reset_done_v3_hw, 2736 }; 2737 2738 static struct pci_driver sas_v3_pci_driver = { 2739 .name = DRV_NAME, 2740 .id_table = sas_v3_pci_table, 2741 .probe = hisi_sas_v3_probe, 2742 .remove = hisi_sas_v3_remove, 2743 .suspend = hisi_sas_v3_suspend, 2744 .resume = hisi_sas_v3_resume, 2745 .err_handler = &hisi_sas_err_handler, 2746 }; 2747 2748 module_pci_driver(sas_v3_pci_driver); 2749 module_param_named(intr_conv, hisi_sas_intr_conv, bool, 0444); 2750 2751 MODULE_LICENSE("GPL"); 2752 MODULE_AUTHOR("John Garry <john.garry@huawei.com>"); 2753 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device"); 2754 MODULE_ALIAS("pci:" DRV_NAME); 2755