1 /* 2 * Copyright (c) 2017 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 */ 10 11 #include "hisi_sas.h" 12 #define DRV_NAME "hisi_sas_v3_hw" 13 14 /* global registers need init*/ 15 #define DLVRY_QUEUE_ENABLE 0x0 16 #define IOST_BASE_ADDR_LO 0x8 17 #define IOST_BASE_ADDR_HI 0xc 18 #define ITCT_BASE_ADDR_LO 0x10 19 #define ITCT_BASE_ADDR_HI 0x14 20 #define IO_BROKEN_MSG_ADDR_LO 0x18 21 #define IO_BROKEN_MSG_ADDR_HI 0x1c 22 #define PHY_CONTEXT 0x20 23 #define PHY_STATE 0x24 24 #define PHY_PORT_NUM_MA 0x28 25 #define PHY_CONN_RATE 0x30 26 #define ITCT_CLR 0x44 27 #define ITCT_CLR_EN_OFF 16 28 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF) 29 #define ITCT_DEV_OFF 0 30 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF) 31 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58 32 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c 33 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60 34 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64 35 #define CFG_MAX_TAG 0x68 36 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84 37 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88 38 #define HGC_GET_ITV_TIME 0x90 39 #define DEVICE_MSG_WORK_MODE 0x94 40 #define OPENA_WT_CONTI_TIME 0x9c 41 #define I_T_NEXUS_LOSS_TIME 0xa0 42 #define MAX_CON_TIME_LIMIT_TIME 0xa4 43 #define BUS_INACTIVE_LIMIT_TIME 0xa8 44 #define REJECT_TO_OPEN_LIMIT_TIME 0xac 45 #define CFG_AGING_TIME 0xbc 46 #define HGC_DFX_CFG2 0xc0 47 #define CFG_ABT_SET_QUERY_IPTT 0xd4 48 #define CFG_SET_ABORTED_IPTT_OFF 0 49 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF) 50 #define CFG_SET_ABORTED_EN_OFF 12 51 #define CFG_ABT_SET_IPTT_DONE 0xd8 52 #define CFG_ABT_SET_IPTT_DONE_OFF 0 53 #define HGC_IOMB_PROC1_STATUS 0x104 54 #define CFG_1US_TIMER_TRSH 0xcc 55 #define CHNL_INT_STATUS 0x148 56 #define HGC_AXI_FIFO_ERR_INFO 0x154 57 #define AXI_ERR_INFO_OFF 0 58 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF) 59 #define FIFO_ERR_INFO_OFF 8 60 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF) 61 #define INT_COAL_EN 0x19c 62 #define OQ_INT_COAL_TIME 0x1a0 63 #define OQ_INT_COAL_CNT 0x1a4 64 #define ENT_INT_COAL_TIME 0x1a8 65 #define ENT_INT_COAL_CNT 0x1ac 66 #define OQ_INT_SRC 0x1b0 67 #define OQ_INT_SRC_MSK 0x1b4 68 #define ENT_INT_SRC1 0x1b8 69 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0 70 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF) 71 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8 72 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF) 73 #define ENT_INT_SRC2 0x1bc 74 #define ENT_INT_SRC3 0x1c0 75 #define ENT_INT_SRC3_WP_DEPTH_OFF 8 76 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9 77 #define ENT_INT_SRC3_RP_DEPTH_OFF 10 78 #define ENT_INT_SRC3_AXI_OFF 11 79 #define ENT_INT_SRC3_FIFO_OFF 12 80 #define ENT_INT_SRC3_LM_OFF 14 81 #define ENT_INT_SRC3_ITC_INT_OFF 15 82 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF) 83 #define ENT_INT_SRC3_ABT_OFF 16 84 #define ENT_INT_SRC_MSK1 0x1c4 85 #define ENT_INT_SRC_MSK2 0x1c8 86 #define ENT_INT_SRC_MSK3 0x1cc 87 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31 88 #define CHNL_PHYUPDOWN_INT_MSK 0x1d0 89 #define CHNL_ENT_INT_MSK 0x1d4 90 #define HGC_COM_INT_MSK 0x1d8 91 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF) 92 #define SAS_ECC_INTR 0x1e8 93 #define SAS_ECC_INTR_MSK 0x1ec 94 #define HGC_ERR_STAT_EN 0x238 95 #define CQE_SEND_CNT 0x248 96 #define DLVRY_Q_0_BASE_ADDR_LO 0x260 97 #define DLVRY_Q_0_BASE_ADDR_HI 0x264 98 #define DLVRY_Q_0_DEPTH 0x268 99 #define DLVRY_Q_0_WR_PTR 0x26c 100 #define DLVRY_Q_0_RD_PTR 0x270 101 #define HYPER_STREAM_ID_EN_CFG 0xc80 102 #define OQ0_INT_SRC_MSK 0xc90 103 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0 104 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4 105 #define COMPL_Q_0_DEPTH 0x4e8 106 #define COMPL_Q_0_WR_PTR 0x4ec 107 #define COMPL_Q_0_RD_PTR 0x4f0 108 #define AWQOS_AWCACHE_CFG 0xc84 109 #define ARQOS_ARCACHE_CFG 0xc88 110 #define HILINK_ERR_DFX 0xe04 111 #define SAS_GPIO_CFG_0 0x1000 112 #define SAS_GPIO_CFG_1 0x1004 113 #define SAS_GPIO_TX_0_1 0x1040 114 #define SAS_CFG_DRIVE_VLD 0x1070 115 116 /* phy registers requiring init */ 117 #define PORT_BASE (0x2000) 118 #define PHY_CFG (PORT_BASE + 0x0) 119 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4) 120 #define PHY_CFG_ENA_OFF 0 121 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF) 122 #define PHY_CFG_DC_OPT_OFF 2 123 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF) 124 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8) 125 #define PHY_CTRL (PORT_BASE + 0x14) 126 #define PHY_CTRL_RESET_OFF 0 127 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF) 128 #define SL_CFG (PORT_BASE + 0x84) 129 #define SL_CONTROL (PORT_BASE + 0x94) 130 #define SL_CONTROL_NOTIFY_EN_OFF 0 131 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF) 132 #define SL_CTA_OFF 17 133 #define SL_CTA_MSK (0x1 << SL_CTA_OFF) 134 #define RX_PRIMS_STATUS (PORT_BASE + 0x98) 135 #define RX_BCAST_CHG_OFF 1 136 #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF) 137 #define TX_ID_DWORD0 (PORT_BASE + 0x9c) 138 #define TX_ID_DWORD1 (PORT_BASE + 0xa0) 139 #define TX_ID_DWORD2 (PORT_BASE + 0xa4) 140 #define TX_ID_DWORD3 (PORT_BASE + 0xa8) 141 #define TX_ID_DWORD4 (PORT_BASE + 0xaC) 142 #define TX_ID_DWORD5 (PORT_BASE + 0xb0) 143 #define TX_ID_DWORD6 (PORT_BASE + 0xb4) 144 #define TXID_AUTO (PORT_BASE + 0xb8) 145 #define CT3_OFF 1 146 #define CT3_MSK (0x1 << CT3_OFF) 147 #define TX_HARDRST_OFF 2 148 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF) 149 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4) 150 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) 151 #define STP_LINK_TIMER (PORT_BASE + 0x120) 152 #define STP_LINK_TIMEOUT_STATE (PORT_BASE + 0x124) 153 #define CON_CFG_DRIVER (PORT_BASE + 0x130) 154 #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134) 155 #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138) 156 #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c) 157 #define CHL_INT0 (PORT_BASE + 0x1b4) 158 #define CHL_INT0_HOTPLUG_TOUT_OFF 0 159 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF) 160 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1 161 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF) 162 #define CHL_INT0_SL_PHY_ENABLE_OFF 2 163 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF) 164 #define CHL_INT0_NOT_RDY_OFF 4 165 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF) 166 #define CHL_INT0_PHY_RDY_OFF 5 167 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF) 168 #define CHL_INT1 (PORT_BASE + 0x1b8) 169 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15 170 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF) 171 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17 172 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF) 173 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19 174 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20 175 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21 176 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22 177 #define CHL_INT2 (PORT_BASE + 0x1bc) 178 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0 179 #define CHL_INT2_RX_INVLD_DW_OFF 30 180 #define CHL_INT2_STP_LINK_TIMEOUT_OFF 31 181 #define CHL_INT0_MSK (PORT_BASE + 0x1c0) 182 #define CHL_INT1_MSK (PORT_BASE + 0x1c4) 183 #define CHL_INT2_MSK (PORT_BASE + 0x1c8) 184 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0) 185 #define SAS_RX_TRAIN_TIMER (PORT_BASE + 0x2a4) 186 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0) 187 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4) 188 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8) 189 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc) 190 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0) 191 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4) 192 #define DMA_TX_STATUS (PORT_BASE + 0x2d0) 193 #define DMA_TX_STATUS_BUSY_OFF 0 194 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF) 195 #define DMA_RX_STATUS (PORT_BASE + 0x2e8) 196 #define DMA_RX_STATUS_BUSY_OFF 0 197 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF) 198 199 #define COARSETUNE_TIME (PORT_BASE + 0x304) 200 #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380) 201 #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384) 202 #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390) 203 #define ERR_CNT_DISP_ERR (PORT_BASE + 0x398) 204 205 #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */ 206 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW) 207 #error Max ITCT exceeded 208 #endif 209 210 #define AXI_MASTER_CFG_BASE (0x5000) 211 #define AM_CTRL_GLOBAL (0x0) 212 #define AM_CURR_TRANS_RETURN (0x150) 213 214 #define AM_CFG_MAX_TRANS (0x5010) 215 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014) 216 #define AXI_CFG (0x5100) 217 #define AM_ROB_ECC_ERR_ADDR (0x510c) 218 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF 0 219 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF) 220 #define AM_ROB_ECC_MULBIT_ERR_ADDR_OFF 8 221 #define AM_ROB_ECC_MULBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_MULBIT_ERR_ADDR_OFF) 222 223 /* RAS registers need init */ 224 #define RAS_BASE (0x6000) 225 #define SAS_RAS_INTR0 (RAS_BASE) 226 #define SAS_RAS_INTR1 (RAS_BASE + 0x04) 227 #define SAS_RAS_INTR0_MASK (RAS_BASE + 0x08) 228 #define SAS_RAS_INTR1_MASK (RAS_BASE + 0x0c) 229 #define CFG_SAS_RAS_INTR_MASK (RAS_BASE + 0x1c) 230 #define SAS_RAS_INTR2 (RAS_BASE + 0x20) 231 #define SAS_RAS_INTR2_MASK (RAS_BASE + 0x24) 232 233 /* HW dma structures */ 234 /* Delivery queue header */ 235 /* dw0 */ 236 #define CMD_HDR_ABORT_FLAG_OFF 0 237 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF) 238 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2 239 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) 240 #define CMD_HDR_RESP_REPORT_OFF 5 241 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF) 242 #define CMD_HDR_TLR_CTRL_OFF 6 243 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF) 244 #define CMD_HDR_PORT_OFF 18 245 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF) 246 #define CMD_HDR_PRIORITY_OFF 27 247 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF) 248 #define CMD_HDR_CMD_OFF 29 249 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF) 250 /* dw1 */ 251 #define CMD_HDR_UNCON_CMD_OFF 3 252 #define CMD_HDR_DIR_OFF 5 253 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF) 254 #define CMD_HDR_RESET_OFF 7 255 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF) 256 #define CMD_HDR_VDTL_OFF 10 257 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF) 258 #define CMD_HDR_FRAME_TYPE_OFF 11 259 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF) 260 #define CMD_HDR_DEV_ID_OFF 16 261 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF) 262 /* dw2 */ 263 #define CMD_HDR_CFL_OFF 0 264 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF) 265 #define CMD_HDR_NCQ_TAG_OFF 10 266 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF) 267 #define CMD_HDR_MRFL_OFF 15 268 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF) 269 #define CMD_HDR_SG_MOD_OFF 24 270 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF) 271 /* dw3 */ 272 #define CMD_HDR_IPTT_OFF 0 273 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF) 274 /* dw6 */ 275 #define CMD_HDR_DIF_SGL_LEN_OFF 0 276 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF) 277 #define CMD_HDR_DATA_SGL_LEN_OFF 16 278 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF) 279 /* dw7 */ 280 #define CMD_HDR_ADDR_MODE_SEL_OFF 15 281 #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF) 282 #define CMD_HDR_ABORT_IPTT_OFF 16 283 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF) 284 285 /* Completion header */ 286 /* dw0 */ 287 #define CMPLT_HDR_CMPLT_OFF 0 288 #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF) 289 #define CMPLT_HDR_ERROR_PHASE_OFF 2 290 #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF) 291 #define CMPLT_HDR_RSPNS_XFRD_OFF 10 292 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF) 293 #define CMPLT_HDR_ERX_OFF 12 294 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF) 295 #define CMPLT_HDR_ABORT_STAT_OFF 13 296 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF) 297 /* abort_stat */ 298 #define STAT_IO_NOT_VALID 0x1 299 #define STAT_IO_NO_DEVICE 0x2 300 #define STAT_IO_COMPLETE 0x3 301 #define STAT_IO_ABORTED 0x4 302 /* dw1 */ 303 #define CMPLT_HDR_IPTT_OFF 0 304 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF) 305 #define CMPLT_HDR_DEV_ID_OFF 16 306 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF) 307 /* dw3 */ 308 #define CMPLT_HDR_IO_IN_TARGET_OFF 17 309 #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF) 310 311 /* ITCT header */ 312 /* qw0 */ 313 #define ITCT_HDR_DEV_TYPE_OFF 0 314 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF) 315 #define ITCT_HDR_VALID_OFF 2 316 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF) 317 #define ITCT_HDR_MCR_OFF 5 318 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF) 319 #define ITCT_HDR_VLN_OFF 9 320 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF) 321 #define ITCT_HDR_SMP_TIMEOUT_OFF 16 322 #define ITCT_HDR_AWT_CONTINUE_OFF 25 323 #define ITCT_HDR_PORT_ID_OFF 28 324 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF) 325 /* qw2 */ 326 #define ITCT_HDR_INLT_OFF 0 327 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF) 328 #define ITCT_HDR_RTOLT_OFF 48 329 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF) 330 331 struct hisi_sas_complete_v3_hdr { 332 __le32 dw0; 333 __le32 dw1; 334 __le32 act; 335 __le32 dw3; 336 }; 337 338 struct hisi_sas_err_record_v3 { 339 /* dw0 */ 340 __le32 trans_tx_fail_type; 341 342 /* dw1 */ 343 __le32 trans_rx_fail_type; 344 345 /* dw2 */ 346 __le16 dma_tx_err_type; 347 __le16 sipc_rx_err_type; 348 349 /* dw3 */ 350 __le32 dma_rx_err_type; 351 }; 352 353 #define RX_DATA_LEN_UNDERFLOW_OFF 6 354 #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF) 355 356 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096 357 #define HISI_SAS_MSI_COUNT_V3_HW 32 358 359 #define DIR_NO_DATA 0 360 #define DIR_TO_INI 1 361 #define DIR_TO_DEVICE 2 362 #define DIR_RESERVED 3 363 364 #define FIS_CMD_IS_UNCONSTRAINED(fis) \ 365 ((fis.command == ATA_CMD_READ_LOG_EXT) || \ 366 (fis.command == ATA_CMD_READ_LOG_DMA_EXT) || \ 367 ((fis.command == ATA_CMD_DEV_RESET) && \ 368 ((fis.control & ATA_SRST) != 0))) 369 370 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) 371 { 372 void __iomem *regs = hisi_hba->regs + off; 373 374 return readl(regs); 375 } 376 377 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off) 378 { 379 void __iomem *regs = hisi_hba->regs + off; 380 381 return readl_relaxed(regs); 382 } 383 384 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val) 385 { 386 void __iomem *regs = hisi_hba->regs + off; 387 388 writel(val, regs); 389 } 390 391 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no, 392 u32 off, u32 val) 393 { 394 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 395 396 writel(val, regs); 397 } 398 399 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba, 400 int phy_no, u32 off) 401 { 402 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 403 404 return readl(regs); 405 } 406 407 #define hisi_sas_read32_poll_timeout(off, val, cond, delay_us, \ 408 timeout_us) \ 409 ({ \ 410 void __iomem *regs = hisi_hba->regs + off; \ 411 readl_poll_timeout(regs, val, cond, delay_us, timeout_us); \ 412 }) 413 414 #define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us, \ 415 timeout_us) \ 416 ({ \ 417 void __iomem *regs = hisi_hba->regs + off; \ 418 readl_poll_timeout_atomic(regs, val, cond, delay_us, timeout_us);\ 419 }) 420 421 static void init_reg_v3_hw(struct hisi_hba *hisi_hba) 422 { 423 struct pci_dev *pdev = hisi_hba->pci_dev; 424 int i; 425 426 /* Global registers init */ 427 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 428 (u32)((1ULL << hisi_hba->queue_count) - 1)); 429 hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400); 430 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108); 431 hisi_sas_write32(hisi_hba, CFG_1US_TIMER_TRSH, 0xd); 432 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); 433 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); 434 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); 435 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff); 436 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff); 437 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff); 438 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff); 439 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe); 440 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe); 441 if (pdev->revision >= 0x21) 442 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffff7fff); 443 else 444 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xfffe20ff); 445 hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0); 446 hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0); 447 hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0); 448 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x0); 449 hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0); 450 hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0); 451 for (i = 0; i < hisi_hba->queue_count; i++) 452 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0); 453 454 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1); 455 456 for (i = 0; i < hisi_hba->n_phy; i++) { 457 struct hisi_sas_phy *phy = &hisi_hba->phy[i]; 458 struct asd_sas_phy *sas_phy = &phy->sas_phy; 459 u32 prog_phy_link_rate = 0x800; 460 461 if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate < 462 SAS_LINK_RATE_1_5_GBPS)) { 463 prog_phy_link_rate = 0x855; 464 } else { 465 enum sas_linkrate max = sas_phy->phy->maximum_linkrate; 466 467 prog_phy_link_rate = 468 hisi_sas_get_prog_phy_linkrate_mask(max) | 469 0x800; 470 } 471 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 472 prog_phy_link_rate); 473 hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80); 474 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff); 475 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff); 476 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff); 477 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000); 478 if (pdev->revision >= 0x21) 479 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 480 0xffffffff); 481 else 482 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 483 0xff87ffff); 484 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe); 485 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0); 486 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0); 487 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0); 488 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0); 489 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0); 490 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1); 491 hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120); 492 493 /* used for 12G negotiate */ 494 hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e); 495 } 496 497 for (i = 0; i < hisi_hba->queue_count; i++) { 498 /* Delivery queue */ 499 hisi_sas_write32(hisi_hba, 500 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14), 501 upper_32_bits(hisi_hba->cmd_hdr_dma[i])); 502 503 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14), 504 lower_32_bits(hisi_hba->cmd_hdr_dma[i])); 505 506 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14), 507 HISI_SAS_QUEUE_SLOTS); 508 509 /* Completion queue */ 510 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14), 511 upper_32_bits(hisi_hba->complete_hdr_dma[i])); 512 513 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14), 514 lower_32_bits(hisi_hba->complete_hdr_dma[i])); 515 516 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14), 517 HISI_SAS_QUEUE_SLOTS); 518 } 519 520 /* itct */ 521 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO, 522 lower_32_bits(hisi_hba->itct_dma)); 523 524 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI, 525 upper_32_bits(hisi_hba->itct_dma)); 526 527 /* iost */ 528 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO, 529 lower_32_bits(hisi_hba->iost_dma)); 530 531 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI, 532 upper_32_bits(hisi_hba->iost_dma)); 533 534 /* breakpoint */ 535 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO, 536 lower_32_bits(hisi_hba->breakpoint_dma)); 537 538 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI, 539 upper_32_bits(hisi_hba->breakpoint_dma)); 540 541 /* SATA broken msg */ 542 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO, 543 lower_32_bits(hisi_hba->sata_breakpoint_dma)); 544 545 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI, 546 upper_32_bits(hisi_hba->sata_breakpoint_dma)); 547 548 /* SATA initial fis */ 549 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO, 550 lower_32_bits(hisi_hba->initial_fis_dma)); 551 552 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI, 553 upper_32_bits(hisi_hba->initial_fis_dma)); 554 555 /* RAS registers init */ 556 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0); 557 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0); 558 hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, 0x0); 559 hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, 0x0); 560 561 /* LED registers init */ 562 hisi_sas_write32(hisi_hba, SAS_CFG_DRIVE_VLD, 0x80000ff); 563 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1, 0x80808080); 564 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1 + 0x4, 0x80808080); 565 /* Configure blink generator rate A to 1Hz and B to 4Hz */ 566 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_1, 0x121700); 567 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_0, 0x800000); 568 } 569 570 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 571 { 572 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 573 574 cfg &= ~PHY_CFG_DC_OPT_MSK; 575 cfg |= 1 << PHY_CFG_DC_OPT_OFF; 576 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 577 } 578 579 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 580 { 581 struct sas_identify_frame identify_frame; 582 u32 *identify_buffer; 583 584 memset(&identify_frame, 0, sizeof(identify_frame)); 585 identify_frame.dev_type = SAS_END_DEVICE; 586 identify_frame.frame_type = 0; 587 identify_frame._un1 = 1; 588 identify_frame.initiator_bits = SAS_PROTOCOL_ALL; 589 identify_frame.target_bits = SAS_PROTOCOL_NONE; 590 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 591 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 592 identify_frame.phy_id = phy_no; 593 identify_buffer = (u32 *)(&identify_frame); 594 595 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0, 596 __swab32(identify_buffer[0])); 597 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1, 598 __swab32(identify_buffer[1])); 599 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2, 600 __swab32(identify_buffer[2])); 601 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3, 602 __swab32(identify_buffer[3])); 603 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4, 604 __swab32(identify_buffer[4])); 605 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5, 606 __swab32(identify_buffer[5])); 607 } 608 609 static void setup_itct_v3_hw(struct hisi_hba *hisi_hba, 610 struct hisi_sas_device *sas_dev) 611 { 612 struct domain_device *device = sas_dev->sas_device; 613 struct device *dev = hisi_hba->dev; 614 u64 qw0, device_id = sas_dev->device_id; 615 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id]; 616 struct domain_device *parent_dev = device->parent; 617 struct asd_sas_port *sas_port = device->port; 618 struct hisi_sas_port *port = to_hisi_sas_port(sas_port); 619 620 memset(itct, 0, sizeof(*itct)); 621 622 /* qw0 */ 623 qw0 = 0; 624 switch (sas_dev->dev_type) { 625 case SAS_END_DEVICE: 626 case SAS_EDGE_EXPANDER_DEVICE: 627 case SAS_FANOUT_EXPANDER_DEVICE: 628 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF; 629 break; 630 case SAS_SATA_DEV: 631 case SAS_SATA_PENDING: 632 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) 633 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF; 634 else 635 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF; 636 break; 637 default: 638 dev_warn(dev, "setup itct: unsupported dev type (%d)\n", 639 sas_dev->dev_type); 640 } 641 642 qw0 |= ((1 << ITCT_HDR_VALID_OFF) | 643 (device->linkrate << ITCT_HDR_MCR_OFF) | 644 (1 << ITCT_HDR_VLN_OFF) | 645 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) | 646 (1 << ITCT_HDR_AWT_CONTINUE_OFF) | 647 (port->id << ITCT_HDR_PORT_ID_OFF)); 648 itct->qw0 = cpu_to_le64(qw0); 649 650 /* qw1 */ 651 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE); 652 itct->sas_addr = __swab64(itct->sas_addr); 653 654 /* qw2 */ 655 if (!dev_is_sata(device)) 656 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) | 657 (0x1ULL << ITCT_HDR_RTOLT_OFF)); 658 } 659 660 static void clear_itct_v3_hw(struct hisi_hba *hisi_hba, 661 struct hisi_sas_device *sas_dev) 662 { 663 DECLARE_COMPLETION_ONSTACK(completion); 664 u64 dev_id = sas_dev->device_id; 665 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id]; 666 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); 667 668 sas_dev->completion = &completion; 669 670 /* clear the itct interrupt state */ 671 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) 672 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 673 ENT_INT_SRC3_ITC_INT_MSK); 674 675 /* clear the itct table*/ 676 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK); 677 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val); 678 679 wait_for_completion(sas_dev->completion); 680 memset(itct, 0, sizeof(struct hisi_sas_itct)); 681 } 682 683 static void dereg_device_v3_hw(struct hisi_hba *hisi_hba, 684 struct domain_device *device) 685 { 686 struct hisi_sas_slot *slot, *slot2; 687 struct hisi_sas_device *sas_dev = device->lldd_dev; 688 u32 cfg_abt_set_query_iptt; 689 690 cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba, 691 CFG_ABT_SET_QUERY_IPTT); 692 list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) { 693 cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK; 694 cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) | 695 (slot->idx << CFG_SET_ABORTED_IPTT_OFF); 696 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, 697 cfg_abt_set_query_iptt); 698 } 699 cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF); 700 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, 701 cfg_abt_set_query_iptt); 702 hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE, 703 1 << CFG_ABT_SET_IPTT_DONE_OFF); 704 } 705 706 static int reset_hw_v3_hw(struct hisi_hba *hisi_hba) 707 { 708 struct device *dev = hisi_hba->dev; 709 int ret; 710 u32 val; 711 712 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0); 713 714 /* Disable all of the PHYs */ 715 hisi_sas_stop_phys(hisi_hba); 716 udelay(50); 717 718 /* Ensure axi bus idle */ 719 ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val, 720 20000, 1000000); 721 if (ret) { 722 dev_err(dev, "axi bus is not idle, ret = %d!\n", ret); 723 return -EIO; 724 } 725 726 if (ACPI_HANDLE(dev)) { 727 acpi_status s; 728 729 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL); 730 if (ACPI_FAILURE(s)) { 731 dev_err(dev, "Reset failed\n"); 732 return -EIO; 733 } 734 } else { 735 dev_err(dev, "no reset method!\n"); 736 return -EINVAL; 737 } 738 739 return 0; 740 } 741 742 static int hw_init_v3_hw(struct hisi_hba *hisi_hba) 743 { 744 struct device *dev = hisi_hba->dev; 745 int rc; 746 747 rc = reset_hw_v3_hw(hisi_hba); 748 if (rc) { 749 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc); 750 return rc; 751 } 752 753 msleep(100); 754 init_reg_v3_hw(hisi_hba); 755 756 return 0; 757 } 758 759 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 760 { 761 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 762 763 cfg |= PHY_CFG_ENA_MSK; 764 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 765 } 766 767 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 768 { 769 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 770 771 cfg &= ~PHY_CFG_ENA_MSK; 772 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 773 } 774 775 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 776 { 777 config_id_frame_v3_hw(hisi_hba, phy_no); 778 config_phy_opt_mode_v3_hw(hisi_hba, phy_no); 779 enable_phy_v3_hw(hisi_hba, phy_no); 780 } 781 782 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 783 { 784 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 785 u32 txid_auto; 786 787 disable_phy_v3_hw(hisi_hba, phy_no); 788 if (phy->identify.device_type == SAS_END_DEVICE) { 789 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); 790 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, 791 txid_auto | TX_HARDRST_MSK); 792 } 793 msleep(100); 794 start_phy_v3_hw(hisi_hba, phy_no); 795 } 796 797 static enum sas_linkrate phy_get_max_linkrate_v3_hw(void) 798 { 799 return SAS_LINK_RATE_12_0_GBPS; 800 } 801 802 static void phys_init_v3_hw(struct hisi_hba *hisi_hba) 803 { 804 int i; 805 806 for (i = 0; i < hisi_hba->n_phy; i++) { 807 struct hisi_sas_phy *phy = &hisi_hba->phy[i]; 808 struct asd_sas_phy *sas_phy = &phy->sas_phy; 809 810 if (!sas_phy->phy->enabled) 811 continue; 812 813 start_phy_v3_hw(hisi_hba, i); 814 } 815 } 816 817 static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 818 { 819 u32 sl_control; 820 821 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 822 sl_control |= SL_CONTROL_NOTIFY_EN_MSK; 823 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 824 msleep(1); 825 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 826 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK; 827 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 828 } 829 830 static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id) 831 { 832 int i, bitmap = 0; 833 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 834 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 835 836 for (i = 0; i < hisi_hba->n_phy; i++) 837 if (phy_state & BIT(i)) 838 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id) 839 bitmap |= BIT(i); 840 841 return bitmap; 842 } 843 844 /** 845 * The callpath to this function and upto writing the write 846 * queue pointer should be safe from interruption. 847 */ 848 static int 849 get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq) 850 { 851 struct device *dev = hisi_hba->dev; 852 int queue = dq->id; 853 u32 r, w; 854 855 w = dq->wr_point; 856 r = hisi_sas_read32_relaxed(hisi_hba, 857 DLVRY_Q_0_RD_PTR + (queue * 0x14)); 858 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) { 859 dev_warn(dev, "full queue=%d r=%d w=%d\n", 860 queue, r, w); 861 return -EAGAIN; 862 } 863 864 dq->wr_point = (dq->wr_point + 1) % HISI_SAS_QUEUE_SLOTS; 865 866 return w; 867 } 868 869 static void start_delivery_v3_hw(struct hisi_sas_dq *dq) 870 { 871 struct hisi_hba *hisi_hba = dq->hisi_hba; 872 struct hisi_sas_slot *s, *s1; 873 struct list_head *dq_list; 874 int dlvry_queue = dq->id; 875 int wp, count = 0; 876 877 dq_list = &dq->list; 878 list_for_each_entry_safe(s, s1, &dq->list, delivery) { 879 if (!s->ready) 880 break; 881 count++; 882 wp = (s->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS; 883 list_del(&s->delivery); 884 } 885 886 if (!count) 887 return; 888 889 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp); 890 } 891 892 static void prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba, 893 struct hisi_sas_slot *slot, 894 struct hisi_sas_cmd_hdr *hdr, 895 struct scatterlist *scatter, 896 int n_elem) 897 { 898 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot); 899 struct scatterlist *sg; 900 int i; 901 902 for_each_sg(scatter, sg, n_elem, i) { 903 struct hisi_sas_sge *entry = &sge_page->sge[i]; 904 905 entry->addr = cpu_to_le64(sg_dma_address(sg)); 906 entry->page_ctrl_0 = entry->page_ctrl_1 = 0; 907 entry->data_len = cpu_to_le32(sg_dma_len(sg)); 908 entry->data_off = 0; 909 } 910 911 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot)); 912 913 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF); 914 } 915 916 static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba, 917 struct hisi_sas_slot *slot) 918 { 919 struct sas_task *task = slot->task; 920 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 921 struct domain_device *device = task->dev; 922 struct hisi_sas_device *sas_dev = device->lldd_dev; 923 struct hisi_sas_port *port = slot->port; 924 struct sas_ssp_task *ssp_task = &task->ssp_task; 925 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd; 926 struct hisi_sas_tmf_task *tmf = slot->tmf; 927 int has_data = 0, priority = !!tmf; 928 u8 *buf_cmd; 929 u32 dw1 = 0, dw2 = 0; 930 931 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) | 932 (2 << CMD_HDR_TLR_CTRL_OFF) | 933 (port->id << CMD_HDR_PORT_OFF) | 934 (priority << CMD_HDR_PRIORITY_OFF) | 935 (1 << CMD_HDR_CMD_OFF)); /* ssp */ 936 937 dw1 = 1 << CMD_HDR_VDTL_OFF; 938 if (tmf) { 939 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF; 940 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF; 941 } else { 942 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF; 943 switch (scsi_cmnd->sc_data_direction) { 944 case DMA_TO_DEVICE: 945 has_data = 1; 946 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; 947 break; 948 case DMA_FROM_DEVICE: 949 has_data = 1; 950 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; 951 break; 952 default: 953 dw1 &= ~CMD_HDR_DIR_MSK; 954 } 955 } 956 957 /* map itct entry */ 958 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; 959 hdr->dw1 = cpu_to_le32(dw1); 960 961 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr) 962 + 3) / 4) << CMD_HDR_CFL_OFF) | 963 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) | 964 (2 << CMD_HDR_SG_MOD_OFF); 965 hdr->dw2 = cpu_to_le32(dw2); 966 hdr->transfer_tags = cpu_to_le32(slot->idx); 967 968 if (has_data) 969 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, 970 slot->n_elem); 971 972 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); 973 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); 974 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 975 976 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) + 977 sizeof(struct ssp_frame_hdr); 978 979 memcpy(buf_cmd, &task->ssp_task.LUN, 8); 980 if (!tmf) { 981 buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3); 982 memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len); 983 } else { 984 buf_cmd[10] = tmf->tmf; 985 switch (tmf->tmf) { 986 case TMF_ABORT_TASK: 987 case TMF_QUERY_TASK: 988 buf_cmd[12] = 989 (tmf->tag_of_task_to_be_managed >> 8) & 0xff; 990 buf_cmd[13] = 991 tmf->tag_of_task_to_be_managed & 0xff; 992 break; 993 default: 994 break; 995 } 996 } 997 } 998 999 static void prep_smp_v3_hw(struct hisi_hba *hisi_hba, 1000 struct hisi_sas_slot *slot) 1001 { 1002 struct sas_task *task = slot->task; 1003 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1004 struct domain_device *device = task->dev; 1005 struct hisi_sas_port *port = slot->port; 1006 struct scatterlist *sg_req; 1007 struct hisi_sas_device *sas_dev = device->lldd_dev; 1008 dma_addr_t req_dma_addr; 1009 unsigned int req_len; 1010 1011 /* req */ 1012 sg_req = &task->smp_task.smp_req; 1013 req_len = sg_dma_len(sg_req); 1014 req_dma_addr = sg_dma_address(sg_req); 1015 1016 /* create header */ 1017 /* dw0 */ 1018 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) | 1019 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */ 1020 (2 << CMD_HDR_CMD_OFF)); /* smp */ 1021 1022 /* map itct entry */ 1023 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) | 1024 (1 << CMD_HDR_FRAME_TYPE_OFF) | 1025 (DIR_NO_DATA << CMD_HDR_DIR_OFF)); 1026 1027 /* dw2 */ 1028 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) | 1029 (HISI_SAS_MAX_SMP_RESP_SZ / 4 << 1030 CMD_HDR_MRFL_OFF)); 1031 1032 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF); 1033 1034 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr); 1035 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1036 1037 } 1038 1039 static void prep_ata_v3_hw(struct hisi_hba *hisi_hba, 1040 struct hisi_sas_slot *slot) 1041 { 1042 struct sas_task *task = slot->task; 1043 struct domain_device *device = task->dev; 1044 struct domain_device *parent_dev = device->parent; 1045 struct hisi_sas_device *sas_dev = device->lldd_dev; 1046 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1047 struct asd_sas_port *sas_port = device->port; 1048 struct hisi_sas_port *port = to_hisi_sas_port(sas_port); 1049 u8 *buf_cmd; 1050 int has_data = 0, hdr_tag = 0; 1051 u32 dw1 = 0, dw2 = 0; 1052 1053 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF); 1054 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) 1055 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF); 1056 else 1057 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF); 1058 1059 switch (task->data_dir) { 1060 case DMA_TO_DEVICE: 1061 has_data = 1; 1062 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; 1063 break; 1064 case DMA_FROM_DEVICE: 1065 has_data = 1; 1066 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; 1067 break; 1068 default: 1069 dw1 &= ~CMD_HDR_DIR_MSK; 1070 } 1071 1072 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) && 1073 (task->ata_task.fis.control & ATA_SRST)) 1074 dw1 |= 1 << CMD_HDR_RESET_OFF; 1075 1076 dw1 |= (hisi_sas_get_ata_protocol( 1077 &task->ata_task.fis, task->data_dir)) 1078 << CMD_HDR_FRAME_TYPE_OFF; 1079 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; 1080 1081 if (FIS_CMD_IS_UNCONSTRAINED(task->ata_task.fis)) 1082 dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF; 1083 1084 hdr->dw1 = cpu_to_le32(dw1); 1085 1086 /* dw2 */ 1087 if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) { 1088 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); 1089 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF; 1090 } 1091 1092 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF | 1093 2 << CMD_HDR_SG_MOD_OFF; 1094 hdr->dw2 = cpu_to_le32(dw2); 1095 1096 /* dw3 */ 1097 hdr->transfer_tags = cpu_to_le32(slot->idx); 1098 1099 if (has_data) 1100 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, 1101 slot->n_elem); 1102 1103 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); 1104 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); 1105 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1106 1107 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot); 1108 1109 if (likely(!task->ata_task.device_control_reg_update)) 1110 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */ 1111 /* fill in command FIS */ 1112 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis)); 1113 } 1114 1115 static void prep_abort_v3_hw(struct hisi_hba *hisi_hba, 1116 struct hisi_sas_slot *slot, 1117 int device_id, int abort_flag, int tag_to_abort) 1118 { 1119 struct sas_task *task = slot->task; 1120 struct domain_device *dev = task->dev; 1121 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1122 struct hisi_sas_port *port = slot->port; 1123 1124 /* dw0 */ 1125 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/ 1126 (port->id << CMD_HDR_PORT_OFF) | 1127 (dev_is_sata(dev) 1128 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) | 1129 (abort_flag 1130 << CMD_HDR_ABORT_FLAG_OFF)); 1131 1132 /* dw1 */ 1133 hdr->dw1 = cpu_to_le32(device_id 1134 << CMD_HDR_DEV_ID_OFF); 1135 1136 /* dw7 */ 1137 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF); 1138 hdr->transfer_tags = cpu_to_le32(slot->idx); 1139 1140 } 1141 1142 static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1143 { 1144 int i, res; 1145 u32 context, port_id, link_rate; 1146 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1147 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1148 struct device *dev = hisi_hba->dev; 1149 unsigned long flags; 1150 1151 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1); 1152 1153 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 1154 port_id = (port_id >> (4 * phy_no)) & 0xf; 1155 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); 1156 link_rate = (link_rate >> (phy_no * 4)) & 0xf; 1157 1158 if (port_id == 0xf) { 1159 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no); 1160 res = IRQ_NONE; 1161 goto end; 1162 } 1163 sas_phy->linkrate = link_rate; 1164 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); 1165 1166 /* Check for SATA dev */ 1167 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT); 1168 if (context & (1 << phy_no)) { 1169 struct hisi_sas_initial_fis *initial_fis; 1170 struct dev_to_host_fis *fis; 1171 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0}; 1172 1173 dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate); 1174 initial_fis = &hisi_hba->initial_fis[phy_no]; 1175 fis = &initial_fis->fis; 1176 sas_phy->oob_mode = SATA_OOB_MODE; 1177 attached_sas_addr[0] = 0x50; 1178 attached_sas_addr[7] = phy_no; 1179 memcpy(sas_phy->attached_sas_addr, 1180 attached_sas_addr, 1181 SAS_ADDR_SIZE); 1182 memcpy(sas_phy->frame_rcvd, fis, 1183 sizeof(struct dev_to_host_fis)); 1184 phy->phy_type |= PORT_TYPE_SATA; 1185 phy->identify.device_type = SAS_SATA_DEV; 1186 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 1187 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 1188 } else { 1189 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd; 1190 struct sas_identify_frame *id = 1191 (struct sas_identify_frame *)frame_rcvd; 1192 1193 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate); 1194 for (i = 0; i < 6; i++) { 1195 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no, 1196 RX_IDAF_DWORD0 + (i * 4)); 1197 frame_rcvd[i] = __swab32(idaf); 1198 } 1199 sas_phy->oob_mode = SAS_OOB_MODE; 1200 memcpy(sas_phy->attached_sas_addr, 1201 &id->sas_addr, 1202 SAS_ADDR_SIZE); 1203 phy->phy_type |= PORT_TYPE_SAS; 1204 phy->identify.device_type = id->dev_type; 1205 phy->frame_rcvd_size = sizeof(struct sas_identify_frame); 1206 if (phy->identify.device_type == SAS_END_DEVICE) 1207 phy->identify.target_port_protocols = 1208 SAS_PROTOCOL_SSP; 1209 else if (phy->identify.device_type != SAS_PHY_UNUSED) 1210 phy->identify.target_port_protocols = 1211 SAS_PROTOCOL_SMP; 1212 } 1213 1214 phy->port_id = port_id; 1215 phy->phy_attached = 1; 1216 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP); 1217 res = IRQ_HANDLED; 1218 spin_lock_irqsave(&phy->lock, flags); 1219 if (phy->reset_completion) { 1220 phy->in_reset = 0; 1221 complete(phy->reset_completion); 1222 } 1223 spin_unlock_irqrestore(&phy->lock, flags); 1224 end: 1225 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1226 CHL_INT0_SL_PHY_ENABLE_MSK); 1227 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0); 1228 1229 return res; 1230 } 1231 1232 static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1233 { 1234 u32 phy_state, sl_ctrl, txid_auto; 1235 struct device *dev = hisi_hba->dev; 1236 1237 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1); 1238 1239 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1240 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state); 1241 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0); 1242 1243 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 1244 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, 1245 sl_ctrl&(~SL_CTA_MSK)); 1246 1247 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); 1248 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, 1249 txid_auto | CT3_MSK); 1250 1251 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK); 1252 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0); 1253 1254 return IRQ_HANDLED; 1255 } 1256 1257 static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1258 { 1259 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1260 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1261 struct sas_ha_struct *sas_ha = &hisi_hba->sha; 1262 u32 bcast_status; 1263 1264 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1); 1265 bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS); 1266 if (bcast_status & RX_BCAST_CHG_MSK) 1267 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 1268 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1269 CHL_INT0_SL_RX_BCST_ACK_MSK); 1270 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0); 1271 1272 return IRQ_HANDLED; 1273 } 1274 1275 static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p) 1276 { 1277 struct hisi_hba *hisi_hba = p; 1278 u32 irq_msk; 1279 int phy_no = 0; 1280 irqreturn_t res = IRQ_NONE; 1281 1282 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) 1283 & 0x11111111; 1284 while (irq_msk) { 1285 if (irq_msk & 1) { 1286 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, 1287 CHL_INT0); 1288 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1289 int rdy = phy_state & (1 << phy_no); 1290 1291 if (rdy) { 1292 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK) 1293 /* phy up */ 1294 if (phy_up_v3_hw(phy_no, hisi_hba) 1295 == IRQ_HANDLED) 1296 res = IRQ_HANDLED; 1297 if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK) 1298 /* phy bcast */ 1299 if (phy_bcast_v3_hw(phy_no, hisi_hba) 1300 == IRQ_HANDLED) 1301 res = IRQ_HANDLED; 1302 } else { 1303 if (irq_value & CHL_INT0_NOT_RDY_MSK) 1304 /* phy down */ 1305 if (phy_down_v3_hw(phy_no, hisi_hba) 1306 == IRQ_HANDLED) 1307 res = IRQ_HANDLED; 1308 } 1309 } 1310 irq_msk >>= 4; 1311 phy_no++; 1312 } 1313 1314 return res; 1315 } 1316 1317 static const struct hisi_sas_hw_error port_axi_error[] = { 1318 { 1319 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF), 1320 .msg = "dma_tx_axi_wr_err", 1321 }, 1322 { 1323 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF), 1324 .msg = "dma_tx_axi_rd_err", 1325 }, 1326 { 1327 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF), 1328 .msg = "dma_rx_axi_wr_err", 1329 }, 1330 { 1331 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF), 1332 .msg = "dma_rx_axi_rd_err", 1333 }, 1334 }; 1335 1336 static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) 1337 { 1338 struct hisi_hba *hisi_hba = p; 1339 struct device *dev = hisi_hba->dev; 1340 struct pci_dev *pci_dev = hisi_hba->pci_dev; 1341 u32 irq_msk; 1342 int phy_no = 0; 1343 1344 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) 1345 & 0xeeeeeeee; 1346 1347 while (irq_msk) { 1348 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, 1349 CHL_INT0); 1350 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no, 1351 CHL_INT1); 1352 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no, 1353 CHL_INT2); 1354 u32 irq_msk1 = hisi_sas_phy_read32(hisi_hba, phy_no, 1355 CHL_INT1_MSK); 1356 u32 irq_msk2 = hisi_sas_phy_read32(hisi_hba, phy_no, 1357 CHL_INT2_MSK); 1358 1359 irq_value1 &= ~irq_msk1; 1360 irq_value2 &= ~irq_msk2; 1361 1362 if ((irq_msk & (4 << (phy_no * 4))) && 1363 irq_value1) { 1364 int i; 1365 1366 for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) { 1367 const struct hisi_sas_hw_error *error = 1368 &port_axi_error[i]; 1369 1370 if (!(irq_value1 & error->irq_msk)) 1371 continue; 1372 1373 dev_err(dev, "%s error (phy%d 0x%x) found!\n", 1374 error->msg, phy_no, irq_value1); 1375 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1376 } 1377 1378 hisi_sas_phy_write32(hisi_hba, phy_no, 1379 CHL_INT1, irq_value1); 1380 } 1381 1382 if (irq_msk & (8 << (phy_no * 4)) && irq_value2) { 1383 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1384 1385 if (irq_value2 & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) { 1386 dev_warn(dev, "phy%d identify timeout\n", 1387 phy_no); 1388 hisi_sas_notify_phy_event(phy, 1389 HISI_PHYE_LINK_RESET); 1390 1391 } 1392 1393 if (irq_value2 & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) { 1394 u32 reg_value = hisi_sas_phy_read32(hisi_hba, 1395 phy_no, STP_LINK_TIMEOUT_STATE); 1396 1397 dev_warn(dev, "phy%d stp link timeout (0x%x)\n", 1398 phy_no, reg_value); 1399 if (reg_value & BIT(4)) 1400 hisi_sas_notify_phy_event(phy, 1401 HISI_PHYE_LINK_RESET); 1402 } 1403 1404 hisi_sas_phy_write32(hisi_hba, phy_no, 1405 CHL_INT2, irq_value2); 1406 1407 if ((irq_value2 & BIT(CHL_INT2_RX_INVLD_DW_OFF)) && 1408 (pci_dev->revision == 0x20)) { 1409 u32 reg_value; 1410 int rc; 1411 1412 rc = hisi_sas_read32_poll_timeout_atomic( 1413 HILINK_ERR_DFX, reg_value, 1414 !((reg_value >> 8) & BIT(phy_no)), 1415 1000, 10000); 1416 if (rc) { 1417 disable_phy_v3_hw(hisi_hba, phy_no); 1418 hisi_sas_phy_write32(hisi_hba, phy_no, 1419 CHL_INT2, 1420 BIT(CHL_INT2_RX_INVLD_DW_OFF)); 1421 hisi_sas_phy_read32(hisi_hba, phy_no, 1422 ERR_CNT_INVLD_DW); 1423 mdelay(1); 1424 enable_phy_v3_hw(hisi_hba, phy_no); 1425 } 1426 } 1427 } 1428 1429 if (irq_msk & (2 << (phy_no * 4)) && irq_value0) { 1430 hisi_sas_phy_write32(hisi_hba, phy_no, 1431 CHL_INT0, irq_value0 1432 & (~CHL_INT0_SL_RX_BCST_ACK_MSK) 1433 & (~CHL_INT0_SL_PHY_ENABLE_MSK) 1434 & (~CHL_INT0_NOT_RDY_MSK)); 1435 } 1436 irq_msk &= ~(0xe << (phy_no * 4)); 1437 phy_no++; 1438 } 1439 1440 return IRQ_HANDLED; 1441 } 1442 1443 static const struct hisi_sas_hw_error axi_error[] = { 1444 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" }, 1445 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" }, 1446 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" }, 1447 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" }, 1448 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" }, 1449 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" }, 1450 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" }, 1451 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" }, 1452 {}, 1453 }; 1454 1455 static const struct hisi_sas_hw_error fifo_error[] = { 1456 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" }, 1457 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" }, 1458 { .msk = BIT(10), .msg = "GETDQE_FIFO" }, 1459 { .msk = BIT(11), .msg = "CMDP_FIFO" }, 1460 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" }, 1461 {}, 1462 }; 1463 1464 static const struct hisi_sas_hw_error fatal_axi_error[] = { 1465 { 1466 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF), 1467 .msg = "write pointer and depth", 1468 }, 1469 { 1470 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF), 1471 .msg = "iptt no match slot", 1472 }, 1473 { 1474 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF), 1475 .msg = "read pointer and depth", 1476 }, 1477 { 1478 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF), 1479 .reg = HGC_AXI_FIFO_ERR_INFO, 1480 .sub = axi_error, 1481 }, 1482 { 1483 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF), 1484 .reg = HGC_AXI_FIFO_ERR_INFO, 1485 .sub = fifo_error, 1486 }, 1487 { 1488 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF), 1489 .msg = "LM add/fetch list", 1490 }, 1491 { 1492 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF), 1493 .msg = "SAS_HGC_ABT fetch LM list", 1494 }, 1495 }; 1496 1497 static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p) 1498 { 1499 u32 irq_value, irq_msk; 1500 struct hisi_hba *hisi_hba = p; 1501 struct device *dev = hisi_hba->dev; 1502 int i; 1503 1504 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3); 1505 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00); 1506 1507 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); 1508 irq_value &= ~irq_msk; 1509 1510 for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) { 1511 const struct hisi_sas_hw_error *error = &fatal_axi_error[i]; 1512 1513 if (!(irq_value & error->irq_msk)) 1514 continue; 1515 1516 if (error->sub) { 1517 const struct hisi_sas_hw_error *sub = error->sub; 1518 u32 err_value = hisi_sas_read32(hisi_hba, error->reg); 1519 1520 for (; sub->msk || sub->msg; sub++) { 1521 if (!(err_value & sub->msk)) 1522 continue; 1523 1524 dev_err(dev, "%s error (0x%x) found!\n", 1525 sub->msg, irq_value); 1526 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1527 } 1528 } else { 1529 dev_err(dev, "%s error (0x%x) found!\n", 1530 error->msg, irq_value); 1531 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1532 } 1533 } 1534 1535 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) { 1536 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR); 1537 u32 dev_id = reg_val & ITCT_DEV_MSK; 1538 struct hisi_sas_device *sas_dev = 1539 &hisi_hba->devices[dev_id]; 1540 1541 hisi_sas_write32(hisi_hba, ITCT_CLR, 0); 1542 dev_dbg(dev, "clear ITCT ok\n"); 1543 complete(sas_dev->completion); 1544 } 1545 1546 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00); 1547 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk); 1548 1549 return IRQ_HANDLED; 1550 } 1551 1552 static void 1553 slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task, 1554 struct hisi_sas_slot *slot) 1555 { 1556 struct task_status_struct *ts = &task->task_status; 1557 struct hisi_sas_complete_v3_hdr *complete_queue = 1558 hisi_hba->complete_hdr[slot->cmplt_queue]; 1559 struct hisi_sas_complete_v3_hdr *complete_hdr = 1560 &complete_queue[slot->cmplt_queue_slot]; 1561 struct hisi_sas_err_record_v3 *record = 1562 hisi_sas_status_buf_addr_mem(slot); 1563 u32 dma_rx_err_type = record->dma_rx_err_type; 1564 u32 trans_tx_fail_type = record->trans_tx_fail_type; 1565 1566 switch (task->task_proto) { 1567 case SAS_PROTOCOL_SSP: 1568 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) { 1569 ts->residual = trans_tx_fail_type; 1570 ts->stat = SAS_DATA_UNDERRUN; 1571 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { 1572 ts->stat = SAS_QUEUE_FULL; 1573 slot->abort = 1; 1574 } else { 1575 ts->stat = SAS_OPEN_REJECT; 1576 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1577 } 1578 break; 1579 case SAS_PROTOCOL_SATA: 1580 case SAS_PROTOCOL_STP: 1581 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 1582 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) { 1583 ts->residual = trans_tx_fail_type; 1584 ts->stat = SAS_DATA_UNDERRUN; 1585 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { 1586 ts->stat = SAS_PHY_DOWN; 1587 slot->abort = 1; 1588 } else { 1589 ts->stat = SAS_OPEN_REJECT; 1590 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1591 } 1592 hisi_sas_sata_done(task, slot); 1593 break; 1594 case SAS_PROTOCOL_SMP: 1595 ts->stat = SAM_STAT_CHECK_CONDITION; 1596 break; 1597 default: 1598 break; 1599 } 1600 } 1601 1602 static int 1603 slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot) 1604 { 1605 struct sas_task *task = slot->task; 1606 struct hisi_sas_device *sas_dev; 1607 struct device *dev = hisi_hba->dev; 1608 struct task_status_struct *ts; 1609 struct domain_device *device; 1610 struct sas_ha_struct *ha; 1611 enum exec_status sts; 1612 struct hisi_sas_complete_v3_hdr *complete_queue = 1613 hisi_hba->complete_hdr[slot->cmplt_queue]; 1614 struct hisi_sas_complete_v3_hdr *complete_hdr = 1615 &complete_queue[slot->cmplt_queue_slot]; 1616 unsigned long flags; 1617 bool is_internal = slot->is_internal; 1618 1619 if (unlikely(!task || !task->lldd_task || !task->dev)) 1620 return -EINVAL; 1621 1622 ts = &task->task_status; 1623 device = task->dev; 1624 ha = device->port->ha; 1625 sas_dev = device->lldd_dev; 1626 1627 spin_lock_irqsave(&task->task_state_lock, flags); 1628 task->task_state_flags &= 1629 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR); 1630 spin_unlock_irqrestore(&task->task_state_lock, flags); 1631 1632 memset(ts, 0, sizeof(*ts)); 1633 ts->resp = SAS_TASK_COMPLETE; 1634 1635 if (unlikely(!sas_dev)) { 1636 dev_dbg(dev, "slot complete: port has not device\n"); 1637 ts->stat = SAS_PHY_DOWN; 1638 goto out; 1639 } 1640 1641 /* 1642 * Use SAS+TMF status codes 1643 */ 1644 switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK) 1645 >> CMPLT_HDR_ABORT_STAT_OFF) { 1646 case STAT_IO_ABORTED: 1647 /* this IO has been aborted by abort command */ 1648 ts->stat = SAS_ABORTED_TASK; 1649 goto out; 1650 case STAT_IO_COMPLETE: 1651 /* internal abort command complete */ 1652 ts->stat = TMF_RESP_FUNC_SUCC; 1653 goto out; 1654 case STAT_IO_NO_DEVICE: 1655 ts->stat = TMF_RESP_FUNC_COMPLETE; 1656 goto out; 1657 case STAT_IO_NOT_VALID: 1658 /* 1659 * abort single IO, the controller can't find the IO 1660 */ 1661 ts->stat = TMF_RESP_FUNC_FAILED; 1662 goto out; 1663 default: 1664 break; 1665 } 1666 1667 /* check for erroneous completion */ 1668 if ((complete_hdr->dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) { 1669 u32 *error_info = hisi_sas_status_buf_addr_mem(slot); 1670 1671 slot_err_v3_hw(hisi_hba, task, slot); 1672 if (ts->stat != SAS_DATA_UNDERRUN) 1673 dev_info(dev, "erroneous completion iptt=%d task=%p dev id=%d " 1674 "CQ hdr: 0x%x 0x%x 0x%x 0x%x " 1675 "Error info: 0x%x 0x%x 0x%x 0x%x\n", 1676 slot->idx, task, sas_dev->device_id, 1677 complete_hdr->dw0, complete_hdr->dw1, 1678 complete_hdr->act, complete_hdr->dw3, 1679 error_info[0], error_info[1], 1680 error_info[2], error_info[3]); 1681 if (unlikely(slot->abort)) 1682 return ts->stat; 1683 goto out; 1684 } 1685 1686 switch (task->task_proto) { 1687 case SAS_PROTOCOL_SSP: { 1688 struct ssp_response_iu *iu = 1689 hisi_sas_status_buf_addr_mem(slot) + 1690 sizeof(struct hisi_sas_err_record); 1691 1692 sas_ssp_task_response(dev, task, iu); 1693 break; 1694 } 1695 case SAS_PROTOCOL_SMP: { 1696 struct scatterlist *sg_resp = &task->smp_task.smp_resp; 1697 void *to; 1698 1699 ts->stat = SAM_STAT_GOOD; 1700 to = kmap_atomic(sg_page(sg_resp)); 1701 1702 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1, 1703 DMA_FROM_DEVICE); 1704 dma_unmap_sg(dev, &task->smp_task.smp_req, 1, 1705 DMA_TO_DEVICE); 1706 memcpy(to + sg_resp->offset, 1707 hisi_sas_status_buf_addr_mem(slot) + 1708 sizeof(struct hisi_sas_err_record), 1709 sg_dma_len(sg_resp)); 1710 kunmap_atomic(to); 1711 break; 1712 } 1713 case SAS_PROTOCOL_SATA: 1714 case SAS_PROTOCOL_STP: 1715 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 1716 ts->stat = SAM_STAT_GOOD; 1717 hisi_sas_sata_done(task, slot); 1718 break; 1719 default: 1720 ts->stat = SAM_STAT_CHECK_CONDITION; 1721 break; 1722 } 1723 1724 if (!slot->port->port_attached) { 1725 dev_warn(dev, "slot complete: port %d has removed\n", 1726 slot->port->sas_port.id); 1727 ts->stat = SAS_PHY_DOWN; 1728 } 1729 1730 out: 1731 hisi_sas_slot_task_free(hisi_hba, task, slot); 1732 sts = ts->stat; 1733 spin_lock_irqsave(&task->task_state_lock, flags); 1734 if (task->task_state_flags & SAS_TASK_STATE_ABORTED) { 1735 spin_unlock_irqrestore(&task->task_state_lock, flags); 1736 dev_info(dev, "slot complete: task(%p) aborted\n", task); 1737 return SAS_ABORTED_TASK; 1738 } 1739 task->task_state_flags |= SAS_TASK_STATE_DONE; 1740 spin_unlock_irqrestore(&task->task_state_lock, flags); 1741 1742 if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) { 1743 spin_lock_irqsave(&device->done_lock, flags); 1744 if (test_bit(SAS_HA_FROZEN, &ha->state)) { 1745 spin_unlock_irqrestore(&device->done_lock, flags); 1746 dev_info(dev, "slot complete: task(%p) ignored\n ", 1747 task); 1748 return sts; 1749 } 1750 spin_unlock_irqrestore(&device->done_lock, flags); 1751 } 1752 1753 if (task->task_done) 1754 task->task_done(task); 1755 1756 return sts; 1757 } 1758 1759 static void cq_tasklet_v3_hw(unsigned long val) 1760 { 1761 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val; 1762 struct hisi_hba *hisi_hba = cq->hisi_hba; 1763 struct hisi_sas_slot *slot; 1764 struct hisi_sas_complete_v3_hdr *complete_queue; 1765 u32 rd_point = cq->rd_point, wr_point; 1766 int queue = cq->id; 1767 1768 complete_queue = hisi_hba->complete_hdr[queue]; 1769 1770 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR + 1771 (0x14 * queue)); 1772 1773 while (rd_point != wr_point) { 1774 struct hisi_sas_complete_v3_hdr *complete_hdr; 1775 struct device *dev = hisi_hba->dev; 1776 int iptt; 1777 1778 complete_hdr = &complete_queue[rd_point]; 1779 1780 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK; 1781 if (likely(iptt < HISI_SAS_COMMAND_ENTRIES_V3_HW)) { 1782 slot = &hisi_hba->slot_info[iptt]; 1783 slot->cmplt_queue_slot = rd_point; 1784 slot->cmplt_queue = queue; 1785 slot_complete_v3_hw(hisi_hba, slot); 1786 } else 1787 dev_err(dev, "IPTT %d is invalid, discard it.\n", iptt); 1788 1789 if (++rd_point >= HISI_SAS_QUEUE_SLOTS) 1790 rd_point = 0; 1791 } 1792 1793 /* update rd_point */ 1794 cq->rd_point = rd_point; 1795 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point); 1796 } 1797 1798 static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p) 1799 { 1800 struct hisi_sas_cq *cq = p; 1801 struct hisi_hba *hisi_hba = cq->hisi_hba; 1802 int queue = cq->id; 1803 1804 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue); 1805 1806 tasklet_schedule(&cq->tasklet); 1807 1808 return IRQ_HANDLED; 1809 } 1810 1811 static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba) 1812 { 1813 struct device *dev = hisi_hba->dev; 1814 struct pci_dev *pdev = hisi_hba->pci_dev; 1815 int vectors, rc; 1816 int i, k; 1817 int max_msi = HISI_SAS_MSI_COUNT_V3_HW; 1818 1819 vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, 1, 1820 max_msi, PCI_IRQ_MSI); 1821 if (vectors < max_msi) { 1822 dev_err(dev, "could not allocate all msi (%d)\n", vectors); 1823 return -ENOENT; 1824 } 1825 1826 rc = devm_request_irq(dev, pci_irq_vector(pdev, 1), 1827 int_phy_up_down_bcast_v3_hw, 0, 1828 DRV_NAME " phy", hisi_hba); 1829 if (rc) { 1830 dev_err(dev, "could not request phy interrupt, rc=%d\n", rc); 1831 rc = -ENOENT; 1832 goto free_irq_vectors; 1833 } 1834 1835 rc = devm_request_irq(dev, pci_irq_vector(pdev, 2), 1836 int_chnl_int_v3_hw, 0, 1837 DRV_NAME " channel", hisi_hba); 1838 if (rc) { 1839 dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc); 1840 rc = -ENOENT; 1841 goto free_phy_irq; 1842 } 1843 1844 rc = devm_request_irq(dev, pci_irq_vector(pdev, 11), 1845 fatal_axi_int_v3_hw, 0, 1846 DRV_NAME " fatal", hisi_hba); 1847 if (rc) { 1848 dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc); 1849 rc = -ENOENT; 1850 goto free_chnl_interrupt; 1851 } 1852 1853 /* Init tasklets for cq only */ 1854 for (i = 0; i < hisi_hba->queue_count; i++) { 1855 struct hisi_sas_cq *cq = &hisi_hba->cq[i]; 1856 struct tasklet_struct *t = &cq->tasklet; 1857 1858 rc = devm_request_irq(dev, pci_irq_vector(pdev, i+16), 1859 cq_interrupt_v3_hw, 0, 1860 DRV_NAME " cq", cq); 1861 if (rc) { 1862 dev_err(dev, 1863 "could not request cq%d interrupt, rc=%d\n", 1864 i, rc); 1865 rc = -ENOENT; 1866 goto free_cq_irqs; 1867 } 1868 1869 tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq); 1870 } 1871 1872 return 0; 1873 1874 free_cq_irqs: 1875 for (k = 0; k < i; k++) { 1876 struct hisi_sas_cq *cq = &hisi_hba->cq[k]; 1877 1878 free_irq(pci_irq_vector(pdev, k+16), cq); 1879 } 1880 free_irq(pci_irq_vector(pdev, 11), hisi_hba); 1881 free_chnl_interrupt: 1882 free_irq(pci_irq_vector(pdev, 2), hisi_hba); 1883 free_phy_irq: 1884 free_irq(pci_irq_vector(pdev, 1), hisi_hba); 1885 free_irq_vectors: 1886 pci_free_irq_vectors(pdev); 1887 return rc; 1888 } 1889 1890 static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) 1891 { 1892 int rc; 1893 1894 rc = hw_init_v3_hw(hisi_hba); 1895 if (rc) 1896 return rc; 1897 1898 rc = interrupt_init_v3_hw(hisi_hba); 1899 if (rc) 1900 return rc; 1901 1902 return 0; 1903 } 1904 1905 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no, 1906 struct sas_phy_linkrates *r) 1907 { 1908 enum sas_linkrate max = r->maximum_linkrate; 1909 u32 prog_phy_link_rate = 0x800; 1910 1911 prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max); 1912 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, 1913 prog_phy_link_rate); 1914 } 1915 1916 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba) 1917 { 1918 struct pci_dev *pdev = hisi_hba->pci_dev; 1919 int i; 1920 1921 synchronize_irq(pci_irq_vector(pdev, 1)); 1922 synchronize_irq(pci_irq_vector(pdev, 2)); 1923 synchronize_irq(pci_irq_vector(pdev, 11)); 1924 for (i = 0; i < hisi_hba->queue_count; i++) { 1925 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1); 1926 synchronize_irq(pci_irq_vector(pdev, i + 16)); 1927 } 1928 1929 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff); 1930 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff); 1931 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff); 1932 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff); 1933 1934 for (i = 0; i < hisi_hba->n_phy; i++) { 1935 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff); 1936 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff); 1937 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1); 1938 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1); 1939 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1); 1940 } 1941 } 1942 1943 static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba) 1944 { 1945 return hisi_sas_read32(hisi_hba, PHY_STATE); 1946 } 1947 1948 static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 1949 { 1950 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1951 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1952 struct sas_phy *sphy = sas_phy->phy; 1953 u32 reg_value; 1954 1955 /* loss dword sync */ 1956 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST); 1957 sphy->loss_of_dword_sync_count += reg_value; 1958 1959 /* phy reset problem */ 1960 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB); 1961 sphy->phy_reset_problem_count += reg_value; 1962 1963 /* invalid dword */ 1964 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW); 1965 sphy->invalid_dword_count += reg_value; 1966 1967 /* disparity err */ 1968 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR); 1969 sphy->running_disparity_error_count += reg_value; 1970 1971 } 1972 1973 static int soft_reset_v3_hw(struct hisi_hba *hisi_hba) 1974 { 1975 struct device *dev = hisi_hba->dev; 1976 int rc; 1977 u32 status; 1978 1979 interrupt_disable_v3_hw(hisi_hba); 1980 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0); 1981 hisi_sas_kill_tasklets(hisi_hba); 1982 1983 hisi_sas_stop_phys(hisi_hba); 1984 1985 mdelay(10); 1986 1987 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1); 1988 1989 /* wait until bus idle */ 1990 rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE + 1991 AM_CURR_TRANS_RETURN, status, 1992 status == 0x3, 10, 100); 1993 if (rc) { 1994 dev_err(dev, "axi bus is not idle, rc = %d\n", rc); 1995 return rc; 1996 } 1997 1998 hisi_sas_init_mem(hisi_hba); 1999 2000 return hw_init_v3_hw(hisi_hba); 2001 } 2002 2003 static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type, 2004 u8 reg_index, u8 reg_count, u8 *write_data) 2005 { 2006 struct device *dev = hisi_hba->dev; 2007 u32 *data = (u32 *)write_data; 2008 int i; 2009 2010 switch (reg_type) { 2011 case SAS_GPIO_REG_TX: 2012 if ((reg_index + reg_count) > ((hisi_hba->n_phy + 3) / 4)) { 2013 dev_err(dev, "write gpio: invalid reg range[%d, %d]\n", 2014 reg_index, reg_index + reg_count - 1); 2015 return -EINVAL; 2016 } 2017 2018 for (i = 0; i < reg_count; i++) 2019 hisi_sas_write32(hisi_hba, 2020 SAS_GPIO_TX_0_1 + (reg_index + i) * 4, 2021 data[i]); 2022 break; 2023 default: 2024 dev_err(dev, "write gpio: unsupported or bad reg type %d\n", 2025 reg_type); 2026 return -EINVAL; 2027 } 2028 2029 return 0; 2030 } 2031 2032 static void wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba, 2033 int delay_ms, int timeout_ms) 2034 { 2035 struct device *dev = hisi_hba->dev; 2036 int entries, entries_old = 0, time; 2037 2038 for (time = 0; time < timeout_ms; time += delay_ms) { 2039 entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT); 2040 if (entries == entries_old) 2041 break; 2042 2043 entries_old = entries; 2044 msleep(delay_ms); 2045 } 2046 2047 dev_dbg(dev, "wait commands complete %dms\n", time); 2048 } 2049 2050 static struct scsi_host_template sht_v3_hw = { 2051 .name = DRV_NAME, 2052 .module = THIS_MODULE, 2053 .queuecommand = sas_queuecommand, 2054 .target_alloc = sas_target_alloc, 2055 .slave_configure = hisi_sas_slave_configure, 2056 .scan_finished = hisi_sas_scan_finished, 2057 .scan_start = hisi_sas_scan_start, 2058 .change_queue_depth = sas_change_queue_depth, 2059 .bios_param = sas_bios_param, 2060 .can_queue = 1, 2061 .this_id = -1, 2062 .sg_tablesize = SG_ALL, 2063 .max_sectors = SCSI_DEFAULT_MAX_SECTORS, 2064 .use_clustering = ENABLE_CLUSTERING, 2065 .eh_device_reset_handler = sas_eh_device_reset_handler, 2066 .eh_target_reset_handler = sas_eh_target_reset_handler, 2067 .target_destroy = sas_target_destroy, 2068 .ioctl = sas_ioctl, 2069 .shost_attrs = host_attrs, 2070 }; 2071 2072 static const struct hisi_sas_hw hisi_sas_v3_hw = { 2073 .hw_init = hisi_sas_v3_init, 2074 .setup_itct = setup_itct_v3_hw, 2075 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW, 2076 .get_wideport_bitmap = get_wideport_bitmap_v3_hw, 2077 .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr), 2078 .clear_itct = clear_itct_v3_hw, 2079 .sl_notify = sl_notify_v3_hw, 2080 .prep_ssp = prep_ssp_v3_hw, 2081 .prep_smp = prep_smp_v3_hw, 2082 .prep_stp = prep_ata_v3_hw, 2083 .prep_abort = prep_abort_v3_hw, 2084 .get_free_slot = get_free_slot_v3_hw, 2085 .start_delivery = start_delivery_v3_hw, 2086 .slot_complete = slot_complete_v3_hw, 2087 .phys_init = phys_init_v3_hw, 2088 .phy_start = start_phy_v3_hw, 2089 .phy_disable = disable_phy_v3_hw, 2090 .phy_hard_reset = phy_hard_reset_v3_hw, 2091 .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw, 2092 .phy_set_linkrate = phy_set_linkrate_v3_hw, 2093 .dereg_device = dereg_device_v3_hw, 2094 .soft_reset = soft_reset_v3_hw, 2095 .get_phys_state = get_phys_state_v3_hw, 2096 .get_events = phy_get_events_v3_hw, 2097 .write_gpio = write_gpio_v3_hw, 2098 .wait_cmds_complete_timeout = wait_cmds_complete_timeout_v3_hw, 2099 }; 2100 2101 static struct Scsi_Host * 2102 hisi_sas_shost_alloc_pci(struct pci_dev *pdev) 2103 { 2104 struct Scsi_Host *shost; 2105 struct hisi_hba *hisi_hba; 2106 struct device *dev = &pdev->dev; 2107 2108 shost = scsi_host_alloc(&sht_v3_hw, sizeof(*hisi_hba)); 2109 if (!shost) { 2110 dev_err(dev, "shost alloc failed\n"); 2111 return NULL; 2112 } 2113 hisi_hba = shost_priv(shost); 2114 2115 INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler); 2116 hisi_hba->hw = &hisi_sas_v3_hw; 2117 hisi_hba->pci_dev = pdev; 2118 hisi_hba->dev = dev; 2119 hisi_hba->shost = shost; 2120 SHOST_TO_SAS_HA(shost) = &hisi_hba->sha; 2121 2122 timer_setup(&hisi_hba->timer, NULL, 0); 2123 2124 if (hisi_sas_get_fw_info(hisi_hba) < 0) 2125 goto err_out; 2126 2127 if (hisi_sas_alloc(hisi_hba, shost)) { 2128 hisi_sas_free(hisi_hba); 2129 goto err_out; 2130 } 2131 2132 return shost; 2133 err_out: 2134 scsi_host_put(shost); 2135 dev_err(dev, "shost alloc failed\n"); 2136 return NULL; 2137 } 2138 2139 static int 2140 hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2141 { 2142 struct Scsi_Host *shost; 2143 struct hisi_hba *hisi_hba; 2144 struct device *dev = &pdev->dev; 2145 struct asd_sas_phy **arr_phy; 2146 struct asd_sas_port **arr_port; 2147 struct sas_ha_struct *sha; 2148 int rc, phy_nr, port_nr, i; 2149 2150 rc = pci_enable_device(pdev); 2151 if (rc) 2152 goto err_out; 2153 2154 pci_set_master(pdev); 2155 2156 rc = pci_request_regions(pdev, DRV_NAME); 2157 if (rc) 2158 goto err_out_disable_device; 2159 2160 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) || 2161 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) { 2162 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) || 2163 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) { 2164 dev_err(dev, "No usable DMA addressing method\n"); 2165 rc = -EIO; 2166 goto err_out_regions; 2167 } 2168 } 2169 2170 shost = hisi_sas_shost_alloc_pci(pdev); 2171 if (!shost) { 2172 rc = -ENOMEM; 2173 goto err_out_regions; 2174 } 2175 2176 sha = SHOST_TO_SAS_HA(shost); 2177 hisi_hba = shost_priv(shost); 2178 dev_set_drvdata(dev, sha); 2179 2180 hisi_hba->regs = pcim_iomap(pdev, 5, 0); 2181 if (!hisi_hba->regs) { 2182 dev_err(dev, "cannot map register.\n"); 2183 rc = -ENOMEM; 2184 goto err_out_ha; 2185 } 2186 2187 phy_nr = port_nr = hisi_hba->n_phy; 2188 2189 arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL); 2190 arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL); 2191 if (!arr_phy || !arr_port) { 2192 rc = -ENOMEM; 2193 goto err_out_ha; 2194 } 2195 2196 sha->sas_phy = arr_phy; 2197 sha->sas_port = arr_port; 2198 sha->core.shost = shost; 2199 sha->lldd_ha = hisi_hba; 2200 2201 shost->transportt = hisi_sas_stt; 2202 shost->max_id = HISI_SAS_MAX_DEVICES; 2203 shost->max_lun = ~0; 2204 shost->max_channel = 1; 2205 shost->max_cmd_len = 16; 2206 shost->sg_tablesize = min_t(u16, SG_ALL, HISI_SAS_SGE_PAGE_CNT); 2207 shost->can_queue = hisi_hba->hw->max_command_entries; 2208 shost->cmd_per_lun = hisi_hba->hw->max_command_entries; 2209 2210 sha->sas_ha_name = DRV_NAME; 2211 sha->dev = dev; 2212 sha->lldd_module = THIS_MODULE; 2213 sha->sas_addr = &hisi_hba->sas_addr[0]; 2214 sha->num_phys = hisi_hba->n_phy; 2215 sha->core.shost = hisi_hba->shost; 2216 2217 for (i = 0; i < hisi_hba->n_phy; i++) { 2218 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy; 2219 sha->sas_port[i] = &hisi_hba->port[i].sas_port; 2220 } 2221 2222 rc = scsi_add_host(shost, dev); 2223 if (rc) 2224 goto err_out_ha; 2225 2226 rc = sas_register_ha(sha); 2227 if (rc) 2228 goto err_out_register_ha; 2229 2230 rc = hisi_hba->hw->hw_init(hisi_hba); 2231 if (rc) 2232 goto err_out_register_ha; 2233 2234 scsi_scan_host(shost); 2235 2236 return 0; 2237 2238 err_out_register_ha: 2239 scsi_remove_host(shost); 2240 err_out_ha: 2241 scsi_host_put(shost); 2242 err_out_regions: 2243 pci_release_regions(pdev); 2244 err_out_disable_device: 2245 pci_disable_device(pdev); 2246 err_out: 2247 return rc; 2248 } 2249 2250 static void 2251 hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba) 2252 { 2253 int i; 2254 2255 free_irq(pci_irq_vector(pdev, 1), hisi_hba); 2256 free_irq(pci_irq_vector(pdev, 2), hisi_hba); 2257 free_irq(pci_irq_vector(pdev, 11), hisi_hba); 2258 for (i = 0; i < hisi_hba->queue_count; i++) { 2259 struct hisi_sas_cq *cq = &hisi_hba->cq[i]; 2260 2261 free_irq(pci_irq_vector(pdev, i+16), cq); 2262 } 2263 pci_free_irq_vectors(pdev); 2264 } 2265 2266 static void hisi_sas_v3_remove(struct pci_dev *pdev) 2267 { 2268 struct device *dev = &pdev->dev; 2269 struct sas_ha_struct *sha = dev_get_drvdata(dev); 2270 struct hisi_hba *hisi_hba = sha->lldd_ha; 2271 struct Scsi_Host *shost = sha->core.shost; 2272 2273 if (timer_pending(&hisi_hba->timer)) 2274 del_timer(&hisi_hba->timer); 2275 2276 sas_unregister_ha(sha); 2277 sas_remove_host(sha->core.shost); 2278 2279 hisi_sas_v3_destroy_irqs(pdev, hisi_hba); 2280 hisi_sas_kill_tasklets(hisi_hba); 2281 pci_release_regions(pdev); 2282 pci_disable_device(pdev); 2283 hisi_sas_free(hisi_hba); 2284 scsi_host_put(shost); 2285 } 2286 2287 static const struct hisi_sas_hw_error sas_ras_intr0_nfe[] = { 2288 { .irq_msk = BIT(19), .msg = "HILINK_INT" }, 2289 { .irq_msk = BIT(20), .msg = "HILINK_PLL0_OUT_OF_LOCK" }, 2290 { .irq_msk = BIT(21), .msg = "HILINK_PLL1_OUT_OF_LOCK" }, 2291 { .irq_msk = BIT(22), .msg = "HILINK_LOSS_OF_REFCLK0" }, 2292 { .irq_msk = BIT(23), .msg = "HILINK_LOSS_OF_REFCLK1" }, 2293 { .irq_msk = BIT(24), .msg = "DMAC0_TX_POISON" }, 2294 { .irq_msk = BIT(25), .msg = "DMAC1_TX_POISON" }, 2295 { .irq_msk = BIT(26), .msg = "DMAC2_TX_POISON" }, 2296 { .irq_msk = BIT(27), .msg = "DMAC3_TX_POISON" }, 2297 { .irq_msk = BIT(28), .msg = "DMAC4_TX_POISON" }, 2298 { .irq_msk = BIT(29), .msg = "DMAC5_TX_POISON" }, 2299 { .irq_msk = BIT(30), .msg = "DMAC6_TX_POISON" }, 2300 { .irq_msk = BIT(31), .msg = "DMAC7_TX_POISON" }, 2301 }; 2302 2303 static const struct hisi_sas_hw_error sas_ras_intr1_nfe[] = { 2304 { .irq_msk = BIT(0), .msg = "RXM_CFG_MEM3_ECC2B_INTR" }, 2305 { .irq_msk = BIT(1), .msg = "RXM_CFG_MEM2_ECC2B_INTR" }, 2306 { .irq_msk = BIT(2), .msg = "RXM_CFG_MEM1_ECC2B_INTR" }, 2307 { .irq_msk = BIT(3), .msg = "RXM_CFG_MEM0_ECC2B_INTR" }, 2308 { .irq_msk = BIT(4), .msg = "HGC_CQE_ECC2B_INTR" }, 2309 { .irq_msk = BIT(5), .msg = "LM_CFG_IOSTL_ECC2B_INTR" }, 2310 { .irq_msk = BIT(6), .msg = "LM_CFG_ITCTL_ECC2B_INTR" }, 2311 { .irq_msk = BIT(7), .msg = "HGC_ITCT_ECC2B_INTR" }, 2312 { .irq_msk = BIT(8), .msg = "HGC_IOST_ECC2B_INTR" }, 2313 { .irq_msk = BIT(9), .msg = "HGC_DQE_ECC2B_INTR" }, 2314 { .irq_msk = BIT(10), .msg = "DMAC0_RAM_ECC2B_INTR" }, 2315 { .irq_msk = BIT(11), .msg = "DMAC1_RAM_ECC2B_INTR" }, 2316 { .irq_msk = BIT(12), .msg = "DMAC2_RAM_ECC2B_INTR" }, 2317 { .irq_msk = BIT(13), .msg = "DMAC3_RAM_ECC2B_INTR" }, 2318 { .irq_msk = BIT(14), .msg = "DMAC4_RAM_ECC2B_INTR" }, 2319 { .irq_msk = BIT(15), .msg = "DMAC5_RAM_ECC2B_INTR" }, 2320 { .irq_msk = BIT(16), .msg = "DMAC6_RAM_ECC2B_INTR" }, 2321 { .irq_msk = BIT(17), .msg = "DMAC7_RAM_ECC2B_INTR" }, 2322 { .irq_msk = BIT(18), .msg = "OOO_RAM_ECC2B_INTR" }, 2323 { .irq_msk = BIT(20), .msg = "HGC_DQE_POISON_INTR" }, 2324 { .irq_msk = BIT(21), .msg = "HGC_IOST_POISON_INTR" }, 2325 { .irq_msk = BIT(22), .msg = "HGC_ITCT_POISON_INTR" }, 2326 { .irq_msk = BIT(23), .msg = "HGC_ITCT_NCQ_POISON_INTR" }, 2327 { .irq_msk = BIT(24), .msg = "DMAC0_RX_POISON" }, 2328 { .irq_msk = BIT(25), .msg = "DMAC1_RX_POISON" }, 2329 { .irq_msk = BIT(26), .msg = "DMAC2_RX_POISON" }, 2330 { .irq_msk = BIT(27), .msg = "DMAC3_RX_POISON" }, 2331 { .irq_msk = BIT(28), .msg = "DMAC4_RX_POISON" }, 2332 { .irq_msk = BIT(29), .msg = "DMAC5_RX_POISON" }, 2333 { .irq_msk = BIT(30), .msg = "DMAC6_RX_POISON" }, 2334 { .irq_msk = BIT(31), .msg = "DMAC7_RX_POISON" }, 2335 }; 2336 2337 static const struct hisi_sas_hw_error sas_ras_intr2_nfe[] = { 2338 { .irq_msk = BIT(0), .msg = "DMAC0_AXI_BUS_ERR" }, 2339 { .irq_msk = BIT(1), .msg = "DMAC1_AXI_BUS_ERR" }, 2340 { .irq_msk = BIT(2), .msg = "DMAC2_AXI_BUS_ERR" }, 2341 { .irq_msk = BIT(3), .msg = "DMAC3_AXI_BUS_ERR" }, 2342 { .irq_msk = BIT(4), .msg = "DMAC4_AXI_BUS_ERR" }, 2343 { .irq_msk = BIT(5), .msg = "DMAC5_AXI_BUS_ERR" }, 2344 { .irq_msk = BIT(6), .msg = "DMAC6_AXI_BUS_ERR" }, 2345 { .irq_msk = BIT(7), .msg = "DMAC7_AXI_BUS_ERR" }, 2346 { .irq_msk = BIT(8), .msg = "DMAC0_FIFO_OMIT_ERR" }, 2347 { .irq_msk = BIT(9), .msg = "DMAC1_FIFO_OMIT_ERR" }, 2348 { .irq_msk = BIT(10), .msg = "DMAC2_FIFO_OMIT_ERR" }, 2349 { .irq_msk = BIT(11), .msg = "DMAC3_FIFO_OMIT_ERR" }, 2350 { .irq_msk = BIT(12), .msg = "DMAC4_FIFO_OMIT_ERR" }, 2351 { .irq_msk = BIT(13), .msg = "DMAC5_FIFO_OMIT_ERR" }, 2352 { .irq_msk = BIT(14), .msg = "DMAC6_FIFO_OMIT_ERR" }, 2353 { .irq_msk = BIT(15), .msg = "DMAC7_FIFO_OMIT_ERR" }, 2354 { .irq_msk = BIT(16), .msg = "HGC_RLSE_SLOT_UNMATCH" }, 2355 { .irq_msk = BIT(17), .msg = "HGC_LM_ADD_FCH_LIST_ERR" }, 2356 { .irq_msk = BIT(18), .msg = "HGC_AXI_BUS_ERR" }, 2357 { .irq_msk = BIT(19), .msg = "HGC_FIFO_OMIT_ERR" }, 2358 }; 2359 2360 static bool process_non_fatal_error_v3_hw(struct hisi_hba *hisi_hba) 2361 { 2362 struct device *dev = hisi_hba->dev; 2363 const struct hisi_sas_hw_error *ras_error; 2364 bool need_reset = false; 2365 u32 irq_value; 2366 int i; 2367 2368 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR0); 2369 for (i = 0; i < ARRAY_SIZE(sas_ras_intr0_nfe); i++) { 2370 ras_error = &sas_ras_intr0_nfe[i]; 2371 if (ras_error->irq_msk & irq_value) { 2372 dev_warn(dev, "SAS_RAS_INTR0: %s(irq_value=0x%x) found.\n", 2373 ras_error->msg, irq_value); 2374 need_reset = true; 2375 } 2376 } 2377 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0, irq_value); 2378 2379 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR1); 2380 for (i = 0; i < ARRAY_SIZE(sas_ras_intr1_nfe); i++) { 2381 ras_error = &sas_ras_intr1_nfe[i]; 2382 if (ras_error->irq_msk & irq_value) { 2383 dev_warn(dev, "SAS_RAS_INTR1: %s(irq_value=0x%x) found.\n", 2384 ras_error->msg, irq_value); 2385 need_reset = true; 2386 } 2387 } 2388 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1, irq_value); 2389 2390 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR2); 2391 for (i = 0; i < ARRAY_SIZE(sas_ras_intr2_nfe); i++) { 2392 ras_error = &sas_ras_intr2_nfe[i]; 2393 if (ras_error->irq_msk & irq_value) { 2394 dev_warn(dev, "SAS_RAS_INTR2: %s(irq_value=0x%x) found.\n", 2395 ras_error->msg, irq_value); 2396 need_reset = true; 2397 } 2398 } 2399 hisi_sas_write32(hisi_hba, SAS_RAS_INTR2, irq_value); 2400 2401 return need_reset; 2402 } 2403 2404 static pci_ers_result_t hisi_sas_error_detected_v3_hw(struct pci_dev *pdev, 2405 pci_channel_state_t state) 2406 { 2407 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2408 struct hisi_hba *hisi_hba = sha->lldd_ha; 2409 struct device *dev = hisi_hba->dev; 2410 2411 dev_info(dev, "PCI error: detected callback, state(%d)!!\n", state); 2412 if (state == pci_channel_io_perm_failure) 2413 return PCI_ERS_RESULT_DISCONNECT; 2414 2415 if (process_non_fatal_error_v3_hw(hisi_hba)) 2416 return PCI_ERS_RESULT_NEED_RESET; 2417 2418 return PCI_ERS_RESULT_CAN_RECOVER; 2419 } 2420 2421 static pci_ers_result_t hisi_sas_mmio_enabled_v3_hw(struct pci_dev *pdev) 2422 { 2423 return PCI_ERS_RESULT_RECOVERED; 2424 } 2425 2426 static pci_ers_result_t hisi_sas_slot_reset_v3_hw(struct pci_dev *pdev) 2427 { 2428 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2429 struct hisi_hba *hisi_hba = sha->lldd_ha; 2430 struct device *dev = hisi_hba->dev; 2431 HISI_SAS_DECLARE_RST_WORK_ON_STACK(r); 2432 2433 dev_info(dev, "PCI error: slot reset callback!!\n"); 2434 queue_work(hisi_hba->wq, &r.work); 2435 wait_for_completion(r.completion); 2436 if (r.done) 2437 return PCI_ERS_RESULT_RECOVERED; 2438 2439 return PCI_ERS_RESULT_DISCONNECT; 2440 } 2441 2442 enum { 2443 /* instances of the controller */ 2444 hip08, 2445 }; 2446 2447 static int hisi_sas_v3_suspend(struct pci_dev *pdev, pm_message_t state) 2448 { 2449 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2450 struct hisi_hba *hisi_hba = sha->lldd_ha; 2451 struct device *dev = hisi_hba->dev; 2452 struct Scsi_Host *shost = hisi_hba->shost; 2453 u32 device_state, status; 2454 int rc; 2455 u32 reg_val; 2456 2457 if (!pdev->pm_cap) { 2458 dev_err(dev, "PCI PM not supported\n"); 2459 return -ENODEV; 2460 } 2461 2462 if (test_and_set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)) 2463 return -1; 2464 2465 scsi_block_requests(shost); 2466 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 2467 flush_workqueue(hisi_hba->wq); 2468 /* disable DQ/PHY/bus */ 2469 interrupt_disable_v3_hw(hisi_hba); 2470 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0); 2471 hisi_sas_kill_tasklets(hisi_hba); 2472 2473 hisi_sas_stop_phys(hisi_hba); 2474 2475 reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE + 2476 AM_CTRL_GLOBAL); 2477 reg_val |= 0x1; 2478 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + 2479 AM_CTRL_GLOBAL, reg_val); 2480 2481 /* wait until bus idle */ 2482 rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE + 2483 AM_CURR_TRANS_RETURN, status, 2484 status == 0x3, 10, 100); 2485 if (rc) { 2486 dev_err(dev, "axi bus is not idle, rc = %d\n", rc); 2487 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 2488 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 2489 scsi_unblock_requests(shost); 2490 return rc; 2491 } 2492 2493 hisi_sas_init_mem(hisi_hba); 2494 2495 device_state = pci_choose_state(pdev, state); 2496 dev_warn(dev, "entering operating state [D%d]\n", 2497 device_state); 2498 pci_save_state(pdev); 2499 pci_disable_device(pdev); 2500 pci_set_power_state(pdev, device_state); 2501 2502 hisi_sas_release_tasks(hisi_hba); 2503 2504 sas_suspend_ha(sha); 2505 return 0; 2506 } 2507 2508 static int hisi_sas_v3_resume(struct pci_dev *pdev) 2509 { 2510 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2511 struct hisi_hba *hisi_hba = sha->lldd_ha; 2512 struct Scsi_Host *shost = hisi_hba->shost; 2513 struct device *dev = hisi_hba->dev; 2514 unsigned int rc; 2515 u32 device_state = pdev->current_state; 2516 2517 dev_warn(dev, "resuming from operating state [D%d]\n", 2518 device_state); 2519 pci_set_power_state(pdev, PCI_D0); 2520 pci_enable_wake(pdev, PCI_D0, 0); 2521 pci_restore_state(pdev); 2522 rc = pci_enable_device(pdev); 2523 if (rc) 2524 dev_err(dev, "enable device failed during resume (%d)\n", rc); 2525 2526 pci_set_master(pdev); 2527 scsi_unblock_requests(shost); 2528 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 2529 2530 sas_prep_resume_ha(sha); 2531 init_reg_v3_hw(hisi_hba); 2532 hisi_hba->hw->phys_init(hisi_hba); 2533 sas_resume_ha(sha); 2534 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 2535 2536 return 0; 2537 } 2538 2539 static const struct pci_device_id sas_v3_pci_table[] = { 2540 { PCI_VDEVICE(HUAWEI, 0xa230), hip08 }, 2541 {} 2542 }; 2543 MODULE_DEVICE_TABLE(pci, sas_v3_pci_table); 2544 2545 static const struct pci_error_handlers hisi_sas_err_handler = { 2546 .error_detected = hisi_sas_error_detected_v3_hw, 2547 .mmio_enabled = hisi_sas_mmio_enabled_v3_hw, 2548 .slot_reset = hisi_sas_slot_reset_v3_hw, 2549 }; 2550 2551 static struct pci_driver sas_v3_pci_driver = { 2552 .name = DRV_NAME, 2553 .id_table = sas_v3_pci_table, 2554 .probe = hisi_sas_v3_probe, 2555 .remove = hisi_sas_v3_remove, 2556 .suspend = hisi_sas_v3_suspend, 2557 .resume = hisi_sas_v3_resume, 2558 .err_handler = &hisi_sas_err_handler, 2559 }; 2560 2561 module_pci_driver(sas_v3_pci_driver); 2562 2563 MODULE_LICENSE("GPL"); 2564 MODULE_AUTHOR("John Garry <john.garry@huawei.com>"); 2565 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device"); 2566 MODULE_ALIAS("pci:" DRV_NAME); 2567