1 /* 2 * Copyright (c) 2017 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 */ 10 11 #include "hisi_sas.h" 12 #define DRV_NAME "hisi_sas_v3_hw" 13 14 /* global registers need init*/ 15 #define DLVRY_QUEUE_ENABLE 0x0 16 #define IOST_BASE_ADDR_LO 0x8 17 #define IOST_BASE_ADDR_HI 0xc 18 #define ITCT_BASE_ADDR_LO 0x10 19 #define ITCT_BASE_ADDR_HI 0x14 20 #define IO_BROKEN_MSG_ADDR_LO 0x18 21 #define IO_BROKEN_MSG_ADDR_HI 0x1c 22 #define PHY_CONTEXT 0x20 23 #define PHY_STATE 0x24 24 #define PHY_PORT_NUM_MA 0x28 25 #define PHY_CONN_RATE 0x30 26 #define ITCT_CLR 0x44 27 #define ITCT_CLR_EN_OFF 16 28 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF) 29 #define ITCT_DEV_OFF 0 30 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF) 31 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58 32 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c 33 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60 34 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64 35 #define CFG_MAX_TAG 0x68 36 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84 37 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88 38 #define HGC_GET_ITV_TIME 0x90 39 #define DEVICE_MSG_WORK_MODE 0x94 40 #define OPENA_WT_CONTI_TIME 0x9c 41 #define I_T_NEXUS_LOSS_TIME 0xa0 42 #define MAX_CON_TIME_LIMIT_TIME 0xa4 43 #define BUS_INACTIVE_LIMIT_TIME 0xa8 44 #define REJECT_TO_OPEN_LIMIT_TIME 0xac 45 #define CFG_AGING_TIME 0xbc 46 #define HGC_DFX_CFG2 0xc0 47 #define CFG_ABT_SET_QUERY_IPTT 0xd4 48 #define CFG_SET_ABORTED_IPTT_OFF 0 49 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF) 50 #define CFG_SET_ABORTED_EN_OFF 12 51 #define CFG_ABT_SET_IPTT_DONE 0xd8 52 #define CFG_ABT_SET_IPTT_DONE_OFF 0 53 #define HGC_IOMB_PROC1_STATUS 0x104 54 #define CHNL_INT_STATUS 0x148 55 #define HGC_AXI_FIFO_ERR_INFO 0x154 56 #define AXI_ERR_INFO_OFF 0 57 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF) 58 #define FIFO_ERR_INFO_OFF 8 59 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF) 60 #define INT_COAL_EN 0x19c 61 #define OQ_INT_COAL_TIME 0x1a0 62 #define OQ_INT_COAL_CNT 0x1a4 63 #define ENT_INT_COAL_TIME 0x1a8 64 #define ENT_INT_COAL_CNT 0x1ac 65 #define OQ_INT_SRC 0x1b0 66 #define OQ_INT_SRC_MSK 0x1b4 67 #define ENT_INT_SRC1 0x1b8 68 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0 69 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF) 70 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8 71 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF) 72 #define ENT_INT_SRC2 0x1bc 73 #define ENT_INT_SRC3 0x1c0 74 #define ENT_INT_SRC3_WP_DEPTH_OFF 8 75 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9 76 #define ENT_INT_SRC3_RP_DEPTH_OFF 10 77 #define ENT_INT_SRC3_AXI_OFF 11 78 #define ENT_INT_SRC3_FIFO_OFF 12 79 #define ENT_INT_SRC3_LM_OFF 14 80 #define ENT_INT_SRC3_ITC_INT_OFF 15 81 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF) 82 #define ENT_INT_SRC3_ABT_OFF 16 83 #define ENT_INT_SRC_MSK1 0x1c4 84 #define ENT_INT_SRC_MSK2 0x1c8 85 #define ENT_INT_SRC_MSK3 0x1cc 86 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31 87 #define CHNL_PHYUPDOWN_INT_MSK 0x1d0 88 #define CHNL_ENT_INT_MSK 0x1d4 89 #define HGC_COM_INT_MSK 0x1d8 90 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF) 91 #define SAS_ECC_INTR 0x1e8 92 #define SAS_ECC_INTR_MSK 0x1ec 93 #define HGC_ERR_STAT_EN 0x238 94 #define CQE_SEND_CNT 0x248 95 #define DLVRY_Q_0_BASE_ADDR_LO 0x260 96 #define DLVRY_Q_0_BASE_ADDR_HI 0x264 97 #define DLVRY_Q_0_DEPTH 0x268 98 #define DLVRY_Q_0_WR_PTR 0x26c 99 #define DLVRY_Q_0_RD_PTR 0x270 100 #define HYPER_STREAM_ID_EN_CFG 0xc80 101 #define OQ0_INT_SRC_MSK 0xc90 102 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0 103 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4 104 #define COMPL_Q_0_DEPTH 0x4e8 105 #define COMPL_Q_0_WR_PTR 0x4ec 106 #define COMPL_Q_0_RD_PTR 0x4f0 107 #define AWQOS_AWCACHE_CFG 0xc84 108 #define ARQOS_ARCACHE_CFG 0xc88 109 #define HILINK_ERR_DFX 0xe04 110 #define SAS_GPIO_CFG_0 0x1000 111 #define SAS_GPIO_CFG_1 0x1004 112 #define SAS_GPIO_TX_0_1 0x1040 113 #define SAS_CFG_DRIVE_VLD 0x1070 114 115 /* phy registers requiring init */ 116 #define PORT_BASE (0x2000) 117 #define PHY_CFG (PORT_BASE + 0x0) 118 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4) 119 #define PHY_CFG_ENA_OFF 0 120 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF) 121 #define PHY_CFG_DC_OPT_OFF 2 122 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF) 123 #define PHY_CFG_PHY_RST_OFF 3 124 #define PHY_CFG_PHY_RST_MSK (0x1 << PHY_CFG_PHY_RST_OFF) 125 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8) 126 #define PHY_CTRL (PORT_BASE + 0x14) 127 #define PHY_CTRL_RESET_OFF 0 128 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF) 129 #define SL_CFG (PORT_BASE + 0x84) 130 #define SL_CONTROL (PORT_BASE + 0x94) 131 #define SL_CONTROL_NOTIFY_EN_OFF 0 132 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF) 133 #define SL_CTA_OFF 17 134 #define SL_CTA_MSK (0x1 << SL_CTA_OFF) 135 #define RX_PRIMS_STATUS (PORT_BASE + 0x98) 136 #define RX_BCAST_CHG_OFF 1 137 #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF) 138 #define TX_ID_DWORD0 (PORT_BASE + 0x9c) 139 #define TX_ID_DWORD1 (PORT_BASE + 0xa0) 140 #define TX_ID_DWORD2 (PORT_BASE + 0xa4) 141 #define TX_ID_DWORD3 (PORT_BASE + 0xa8) 142 #define TX_ID_DWORD4 (PORT_BASE + 0xaC) 143 #define TX_ID_DWORD5 (PORT_BASE + 0xb0) 144 #define TX_ID_DWORD6 (PORT_BASE + 0xb4) 145 #define TXID_AUTO (PORT_BASE + 0xb8) 146 #define CT3_OFF 1 147 #define CT3_MSK (0x1 << CT3_OFF) 148 #define TX_HARDRST_OFF 2 149 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF) 150 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4) 151 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) 152 #define STP_LINK_TIMER (PORT_BASE + 0x120) 153 #define STP_LINK_TIMEOUT_STATE (PORT_BASE + 0x124) 154 #define CON_CFG_DRIVER (PORT_BASE + 0x130) 155 #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134) 156 #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138) 157 #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c) 158 #define CHL_INT0 (PORT_BASE + 0x1b4) 159 #define CHL_INT0_HOTPLUG_TOUT_OFF 0 160 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF) 161 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1 162 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF) 163 #define CHL_INT0_SL_PHY_ENABLE_OFF 2 164 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF) 165 #define CHL_INT0_NOT_RDY_OFF 4 166 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF) 167 #define CHL_INT0_PHY_RDY_OFF 5 168 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF) 169 #define CHL_INT1 (PORT_BASE + 0x1b8) 170 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15 171 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF) 172 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17 173 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF) 174 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19 175 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20 176 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21 177 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22 178 #define CHL_INT2 (PORT_BASE + 0x1bc) 179 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0 180 #define CHL_INT2_RX_INVLD_DW_OFF 30 181 #define CHL_INT2_STP_LINK_TIMEOUT_OFF 31 182 #define CHL_INT0_MSK (PORT_BASE + 0x1c0) 183 #define CHL_INT1_MSK (PORT_BASE + 0x1c4) 184 #define CHL_INT2_MSK (PORT_BASE + 0x1c8) 185 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0) 186 #define SAS_RX_TRAIN_TIMER (PORT_BASE + 0x2a4) 187 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0) 188 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4) 189 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8) 190 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc) 191 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0) 192 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4) 193 #define DMA_TX_STATUS (PORT_BASE + 0x2d0) 194 #define DMA_TX_STATUS_BUSY_OFF 0 195 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF) 196 #define DMA_RX_STATUS (PORT_BASE + 0x2e8) 197 #define DMA_RX_STATUS_BUSY_OFF 0 198 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF) 199 200 #define COARSETUNE_TIME (PORT_BASE + 0x304) 201 #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380) 202 #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384) 203 #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390) 204 #define ERR_CNT_DISP_ERR (PORT_BASE + 0x398) 205 206 #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */ 207 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW) 208 #error Max ITCT exceeded 209 #endif 210 211 #define AXI_MASTER_CFG_BASE (0x5000) 212 #define AM_CTRL_GLOBAL (0x0) 213 #define AM_CTRL_SHUTDOWN_REQ_OFF 0 214 #define AM_CTRL_SHUTDOWN_REQ_MSK (0x1 << AM_CTRL_SHUTDOWN_REQ_OFF) 215 #define AM_CURR_TRANS_RETURN (0x150) 216 217 #define AM_CFG_MAX_TRANS (0x5010) 218 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014) 219 #define AXI_CFG (0x5100) 220 #define AM_ROB_ECC_ERR_ADDR (0x510c) 221 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF 0 222 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF) 223 #define AM_ROB_ECC_MULBIT_ERR_ADDR_OFF 8 224 #define AM_ROB_ECC_MULBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_MULBIT_ERR_ADDR_OFF) 225 226 /* RAS registers need init */ 227 #define RAS_BASE (0x6000) 228 #define SAS_RAS_INTR0 (RAS_BASE) 229 #define SAS_RAS_INTR1 (RAS_BASE + 0x04) 230 #define SAS_RAS_INTR0_MASK (RAS_BASE + 0x08) 231 #define SAS_RAS_INTR1_MASK (RAS_BASE + 0x0c) 232 #define CFG_SAS_RAS_INTR_MASK (RAS_BASE + 0x1c) 233 #define SAS_RAS_INTR2 (RAS_BASE + 0x20) 234 #define SAS_RAS_INTR2_MASK (RAS_BASE + 0x24) 235 236 /* HW dma structures */ 237 /* Delivery queue header */ 238 /* dw0 */ 239 #define CMD_HDR_ABORT_FLAG_OFF 0 240 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF) 241 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2 242 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) 243 #define CMD_HDR_RESP_REPORT_OFF 5 244 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF) 245 #define CMD_HDR_TLR_CTRL_OFF 6 246 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF) 247 #define CMD_HDR_PORT_OFF 18 248 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF) 249 #define CMD_HDR_PRIORITY_OFF 27 250 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF) 251 #define CMD_HDR_CMD_OFF 29 252 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF) 253 /* dw1 */ 254 #define CMD_HDR_UNCON_CMD_OFF 3 255 #define CMD_HDR_DIR_OFF 5 256 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF) 257 #define CMD_HDR_RESET_OFF 7 258 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF) 259 #define CMD_HDR_VDTL_OFF 10 260 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF) 261 #define CMD_HDR_FRAME_TYPE_OFF 11 262 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF) 263 #define CMD_HDR_DEV_ID_OFF 16 264 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF) 265 /* dw2 */ 266 #define CMD_HDR_CFL_OFF 0 267 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF) 268 #define CMD_HDR_NCQ_TAG_OFF 10 269 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF) 270 #define CMD_HDR_MRFL_OFF 15 271 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF) 272 #define CMD_HDR_SG_MOD_OFF 24 273 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF) 274 /* dw3 */ 275 #define CMD_HDR_IPTT_OFF 0 276 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF) 277 /* dw6 */ 278 #define CMD_HDR_DIF_SGL_LEN_OFF 0 279 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF) 280 #define CMD_HDR_DATA_SGL_LEN_OFF 16 281 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF) 282 /* dw7 */ 283 #define CMD_HDR_ADDR_MODE_SEL_OFF 15 284 #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF) 285 #define CMD_HDR_ABORT_IPTT_OFF 16 286 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF) 287 288 /* Completion header */ 289 /* dw0 */ 290 #define CMPLT_HDR_CMPLT_OFF 0 291 #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF) 292 #define CMPLT_HDR_ERROR_PHASE_OFF 2 293 #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF) 294 #define CMPLT_HDR_RSPNS_XFRD_OFF 10 295 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF) 296 #define CMPLT_HDR_ERX_OFF 12 297 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF) 298 #define CMPLT_HDR_ABORT_STAT_OFF 13 299 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF) 300 /* abort_stat */ 301 #define STAT_IO_NOT_VALID 0x1 302 #define STAT_IO_NO_DEVICE 0x2 303 #define STAT_IO_COMPLETE 0x3 304 #define STAT_IO_ABORTED 0x4 305 /* dw1 */ 306 #define CMPLT_HDR_IPTT_OFF 0 307 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF) 308 #define CMPLT_HDR_DEV_ID_OFF 16 309 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF) 310 /* dw3 */ 311 #define CMPLT_HDR_IO_IN_TARGET_OFF 17 312 #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF) 313 314 /* ITCT header */ 315 /* qw0 */ 316 #define ITCT_HDR_DEV_TYPE_OFF 0 317 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF) 318 #define ITCT_HDR_VALID_OFF 2 319 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF) 320 #define ITCT_HDR_MCR_OFF 5 321 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF) 322 #define ITCT_HDR_VLN_OFF 9 323 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF) 324 #define ITCT_HDR_SMP_TIMEOUT_OFF 16 325 #define ITCT_HDR_AWT_CONTINUE_OFF 25 326 #define ITCT_HDR_PORT_ID_OFF 28 327 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF) 328 /* qw2 */ 329 #define ITCT_HDR_INLT_OFF 0 330 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF) 331 #define ITCT_HDR_RTOLT_OFF 48 332 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF) 333 334 struct hisi_sas_complete_v3_hdr { 335 __le32 dw0; 336 __le32 dw1; 337 __le32 act; 338 __le32 dw3; 339 }; 340 341 struct hisi_sas_err_record_v3 { 342 /* dw0 */ 343 __le32 trans_tx_fail_type; 344 345 /* dw1 */ 346 __le32 trans_rx_fail_type; 347 348 /* dw2 */ 349 __le16 dma_tx_err_type; 350 __le16 sipc_rx_err_type; 351 352 /* dw3 */ 353 __le32 dma_rx_err_type; 354 }; 355 356 #define RX_DATA_LEN_UNDERFLOW_OFF 6 357 #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF) 358 359 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096 360 #define HISI_SAS_MSI_COUNT_V3_HW 32 361 362 #define DIR_NO_DATA 0 363 #define DIR_TO_INI 1 364 #define DIR_TO_DEVICE 2 365 #define DIR_RESERVED 3 366 367 #define FIS_CMD_IS_UNCONSTRAINED(fis) \ 368 ((fis.command == ATA_CMD_READ_LOG_EXT) || \ 369 (fis.command == ATA_CMD_READ_LOG_DMA_EXT) || \ 370 ((fis.command == ATA_CMD_DEV_RESET) && \ 371 ((fis.control & ATA_SRST) != 0))) 372 373 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) 374 { 375 void __iomem *regs = hisi_hba->regs + off; 376 377 return readl(regs); 378 } 379 380 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off) 381 { 382 void __iomem *regs = hisi_hba->regs + off; 383 384 return readl_relaxed(regs); 385 } 386 387 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val) 388 { 389 void __iomem *regs = hisi_hba->regs + off; 390 391 writel(val, regs); 392 } 393 394 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no, 395 u32 off, u32 val) 396 { 397 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 398 399 writel(val, regs); 400 } 401 402 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba, 403 int phy_no, u32 off) 404 { 405 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 406 407 return readl(regs); 408 } 409 410 #define hisi_sas_read32_poll_timeout(off, val, cond, delay_us, \ 411 timeout_us) \ 412 ({ \ 413 void __iomem *regs = hisi_hba->regs + off; \ 414 readl_poll_timeout(regs, val, cond, delay_us, timeout_us); \ 415 }) 416 417 #define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us, \ 418 timeout_us) \ 419 ({ \ 420 void __iomem *regs = hisi_hba->regs + off; \ 421 readl_poll_timeout_atomic(regs, val, cond, delay_us, timeout_us);\ 422 }) 423 424 static void init_reg_v3_hw(struct hisi_hba *hisi_hba) 425 { 426 struct pci_dev *pdev = hisi_hba->pci_dev; 427 int i; 428 429 /* Global registers init */ 430 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 431 (u32)((1ULL << hisi_hba->queue_count) - 1)); 432 hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400); 433 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108); 434 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); 435 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); 436 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); 437 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff); 438 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff); 439 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff); 440 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff); 441 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe); 442 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe); 443 if (pdev->revision >= 0x21) 444 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffff7fff); 445 else 446 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xfffe20ff); 447 hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0); 448 hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0); 449 hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0); 450 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x0); 451 hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0); 452 hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0); 453 for (i = 0; i < hisi_hba->queue_count; i++) 454 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0); 455 456 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1); 457 458 for (i = 0; i < hisi_hba->n_phy; i++) { 459 struct hisi_sas_phy *phy = &hisi_hba->phy[i]; 460 struct asd_sas_phy *sas_phy = &phy->sas_phy; 461 u32 prog_phy_link_rate = 0x800; 462 463 if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate < 464 SAS_LINK_RATE_1_5_GBPS)) { 465 prog_phy_link_rate = 0x855; 466 } else { 467 enum sas_linkrate max = sas_phy->phy->maximum_linkrate; 468 469 prog_phy_link_rate = 470 hisi_sas_get_prog_phy_linkrate_mask(max) | 471 0x800; 472 } 473 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 474 prog_phy_link_rate); 475 hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80); 476 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff); 477 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff); 478 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff); 479 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000); 480 if (pdev->revision >= 0x21) 481 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 482 0xffffffff); 483 else 484 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 485 0xff87ffff); 486 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe); 487 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0); 488 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0); 489 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0); 490 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0); 491 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0); 492 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1); 493 hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120); 494 hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x2a0a01); 495 496 /* used for 12G negotiate */ 497 hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e); 498 } 499 500 for (i = 0; i < hisi_hba->queue_count; i++) { 501 /* Delivery queue */ 502 hisi_sas_write32(hisi_hba, 503 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14), 504 upper_32_bits(hisi_hba->cmd_hdr_dma[i])); 505 506 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14), 507 lower_32_bits(hisi_hba->cmd_hdr_dma[i])); 508 509 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14), 510 HISI_SAS_QUEUE_SLOTS); 511 512 /* Completion queue */ 513 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14), 514 upper_32_bits(hisi_hba->complete_hdr_dma[i])); 515 516 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14), 517 lower_32_bits(hisi_hba->complete_hdr_dma[i])); 518 519 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14), 520 HISI_SAS_QUEUE_SLOTS); 521 } 522 523 /* itct */ 524 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO, 525 lower_32_bits(hisi_hba->itct_dma)); 526 527 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI, 528 upper_32_bits(hisi_hba->itct_dma)); 529 530 /* iost */ 531 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO, 532 lower_32_bits(hisi_hba->iost_dma)); 533 534 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI, 535 upper_32_bits(hisi_hba->iost_dma)); 536 537 /* breakpoint */ 538 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO, 539 lower_32_bits(hisi_hba->breakpoint_dma)); 540 541 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI, 542 upper_32_bits(hisi_hba->breakpoint_dma)); 543 544 /* SATA broken msg */ 545 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO, 546 lower_32_bits(hisi_hba->sata_breakpoint_dma)); 547 548 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI, 549 upper_32_bits(hisi_hba->sata_breakpoint_dma)); 550 551 /* SATA initial fis */ 552 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO, 553 lower_32_bits(hisi_hba->initial_fis_dma)); 554 555 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI, 556 upper_32_bits(hisi_hba->initial_fis_dma)); 557 558 /* RAS registers init */ 559 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0); 560 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0); 561 hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, 0x0); 562 hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, 0x0); 563 564 /* LED registers init */ 565 hisi_sas_write32(hisi_hba, SAS_CFG_DRIVE_VLD, 0x80000ff); 566 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1, 0x80808080); 567 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1 + 0x4, 0x80808080); 568 /* Configure blink generator rate A to 1Hz and B to 4Hz */ 569 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_1, 0x121700); 570 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_0, 0x800000); 571 } 572 573 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 574 { 575 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 576 577 cfg &= ~PHY_CFG_DC_OPT_MSK; 578 cfg |= 1 << PHY_CFG_DC_OPT_OFF; 579 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 580 } 581 582 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 583 { 584 struct sas_identify_frame identify_frame; 585 u32 *identify_buffer; 586 587 memset(&identify_frame, 0, sizeof(identify_frame)); 588 identify_frame.dev_type = SAS_END_DEVICE; 589 identify_frame.frame_type = 0; 590 identify_frame._un1 = 1; 591 identify_frame.initiator_bits = SAS_PROTOCOL_ALL; 592 identify_frame.target_bits = SAS_PROTOCOL_NONE; 593 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 594 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 595 identify_frame.phy_id = phy_no; 596 identify_buffer = (u32 *)(&identify_frame); 597 598 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0, 599 __swab32(identify_buffer[0])); 600 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1, 601 __swab32(identify_buffer[1])); 602 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2, 603 __swab32(identify_buffer[2])); 604 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3, 605 __swab32(identify_buffer[3])); 606 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4, 607 __swab32(identify_buffer[4])); 608 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5, 609 __swab32(identify_buffer[5])); 610 } 611 612 static void setup_itct_v3_hw(struct hisi_hba *hisi_hba, 613 struct hisi_sas_device *sas_dev) 614 { 615 struct domain_device *device = sas_dev->sas_device; 616 struct device *dev = hisi_hba->dev; 617 u64 qw0, device_id = sas_dev->device_id; 618 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id]; 619 struct domain_device *parent_dev = device->parent; 620 struct asd_sas_port *sas_port = device->port; 621 struct hisi_sas_port *port = to_hisi_sas_port(sas_port); 622 623 memset(itct, 0, sizeof(*itct)); 624 625 /* qw0 */ 626 qw0 = 0; 627 switch (sas_dev->dev_type) { 628 case SAS_END_DEVICE: 629 case SAS_EDGE_EXPANDER_DEVICE: 630 case SAS_FANOUT_EXPANDER_DEVICE: 631 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF; 632 break; 633 case SAS_SATA_DEV: 634 case SAS_SATA_PENDING: 635 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) 636 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF; 637 else 638 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF; 639 break; 640 default: 641 dev_warn(dev, "setup itct: unsupported dev type (%d)\n", 642 sas_dev->dev_type); 643 } 644 645 qw0 |= ((1 << ITCT_HDR_VALID_OFF) | 646 (device->linkrate << ITCT_HDR_MCR_OFF) | 647 (1 << ITCT_HDR_VLN_OFF) | 648 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) | 649 (1 << ITCT_HDR_AWT_CONTINUE_OFF) | 650 (port->id << ITCT_HDR_PORT_ID_OFF)); 651 itct->qw0 = cpu_to_le64(qw0); 652 653 /* qw1 */ 654 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE); 655 itct->sas_addr = __swab64(itct->sas_addr); 656 657 /* qw2 */ 658 if (!dev_is_sata(device)) 659 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) | 660 (0x1ULL << ITCT_HDR_RTOLT_OFF)); 661 } 662 663 static void clear_itct_v3_hw(struct hisi_hba *hisi_hba, 664 struct hisi_sas_device *sas_dev) 665 { 666 DECLARE_COMPLETION_ONSTACK(completion); 667 u64 dev_id = sas_dev->device_id; 668 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id]; 669 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); 670 671 sas_dev->completion = &completion; 672 673 /* clear the itct interrupt state */ 674 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) 675 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 676 ENT_INT_SRC3_ITC_INT_MSK); 677 678 /* clear the itct table*/ 679 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK); 680 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val); 681 682 wait_for_completion(sas_dev->completion); 683 memset(itct, 0, sizeof(struct hisi_sas_itct)); 684 } 685 686 static void dereg_device_v3_hw(struct hisi_hba *hisi_hba, 687 struct domain_device *device) 688 { 689 struct hisi_sas_slot *slot, *slot2; 690 struct hisi_sas_device *sas_dev = device->lldd_dev; 691 u32 cfg_abt_set_query_iptt; 692 693 cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba, 694 CFG_ABT_SET_QUERY_IPTT); 695 list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) { 696 cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK; 697 cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) | 698 (slot->idx << CFG_SET_ABORTED_IPTT_OFF); 699 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, 700 cfg_abt_set_query_iptt); 701 } 702 cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF); 703 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, 704 cfg_abt_set_query_iptt); 705 hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE, 706 1 << CFG_ABT_SET_IPTT_DONE_OFF); 707 } 708 709 static int reset_hw_v3_hw(struct hisi_hba *hisi_hba) 710 { 711 struct device *dev = hisi_hba->dev; 712 int ret; 713 u32 val; 714 715 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0); 716 717 /* Disable all of the PHYs */ 718 hisi_sas_stop_phys(hisi_hba); 719 udelay(50); 720 721 /* Ensure axi bus idle */ 722 ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val, 723 20000, 1000000); 724 if (ret) { 725 dev_err(dev, "axi bus is not idle, ret = %d!\n", ret); 726 return -EIO; 727 } 728 729 if (ACPI_HANDLE(dev)) { 730 acpi_status s; 731 732 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL); 733 if (ACPI_FAILURE(s)) { 734 dev_err(dev, "Reset failed\n"); 735 return -EIO; 736 } 737 } else { 738 dev_err(dev, "no reset method!\n"); 739 return -EINVAL; 740 } 741 742 return 0; 743 } 744 745 static int hw_init_v3_hw(struct hisi_hba *hisi_hba) 746 { 747 struct device *dev = hisi_hba->dev; 748 int rc; 749 750 rc = reset_hw_v3_hw(hisi_hba); 751 if (rc) { 752 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc); 753 return rc; 754 } 755 756 msleep(100); 757 init_reg_v3_hw(hisi_hba); 758 759 return 0; 760 } 761 762 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 763 { 764 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 765 766 cfg |= PHY_CFG_ENA_MSK; 767 cfg &= ~PHY_CFG_PHY_RST_MSK; 768 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 769 } 770 771 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 772 { 773 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 774 u32 state; 775 776 cfg &= ~PHY_CFG_ENA_MSK; 777 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 778 779 mdelay(50); 780 781 state = hisi_sas_read32(hisi_hba, PHY_STATE); 782 if (state & BIT(phy_no)) { 783 cfg |= PHY_CFG_PHY_RST_MSK; 784 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 785 } 786 } 787 788 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 789 { 790 config_id_frame_v3_hw(hisi_hba, phy_no); 791 config_phy_opt_mode_v3_hw(hisi_hba, phy_no); 792 enable_phy_v3_hw(hisi_hba, phy_no); 793 } 794 795 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 796 { 797 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 798 u32 txid_auto; 799 800 disable_phy_v3_hw(hisi_hba, phy_no); 801 if (phy->identify.device_type == SAS_END_DEVICE) { 802 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); 803 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, 804 txid_auto | TX_HARDRST_MSK); 805 } 806 msleep(100); 807 start_phy_v3_hw(hisi_hba, phy_no); 808 } 809 810 static enum sas_linkrate phy_get_max_linkrate_v3_hw(void) 811 { 812 return SAS_LINK_RATE_12_0_GBPS; 813 } 814 815 static void phys_init_v3_hw(struct hisi_hba *hisi_hba) 816 { 817 int i; 818 819 for (i = 0; i < hisi_hba->n_phy; i++) { 820 struct hisi_sas_phy *phy = &hisi_hba->phy[i]; 821 struct asd_sas_phy *sas_phy = &phy->sas_phy; 822 823 if (!sas_phy->phy->enabled) 824 continue; 825 826 start_phy_v3_hw(hisi_hba, i); 827 } 828 } 829 830 static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 831 { 832 u32 sl_control; 833 834 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 835 sl_control |= SL_CONTROL_NOTIFY_EN_MSK; 836 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 837 msleep(1); 838 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 839 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK; 840 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 841 } 842 843 static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id) 844 { 845 int i, bitmap = 0; 846 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 847 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 848 849 for (i = 0; i < hisi_hba->n_phy; i++) 850 if (phy_state & BIT(i)) 851 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id) 852 bitmap |= BIT(i); 853 854 return bitmap; 855 } 856 857 /** 858 * The callpath to this function and upto writing the write 859 * queue pointer should be safe from interruption. 860 */ 861 static int 862 get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq) 863 { 864 struct device *dev = hisi_hba->dev; 865 int queue = dq->id; 866 u32 r, w; 867 868 w = dq->wr_point; 869 r = hisi_sas_read32_relaxed(hisi_hba, 870 DLVRY_Q_0_RD_PTR + (queue * 0x14)); 871 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) { 872 dev_warn(dev, "full queue=%d r=%d w=%d\n", 873 queue, r, w); 874 return -EAGAIN; 875 } 876 877 dq->wr_point = (dq->wr_point + 1) % HISI_SAS_QUEUE_SLOTS; 878 879 return w; 880 } 881 882 static void start_delivery_v3_hw(struct hisi_sas_dq *dq) 883 { 884 struct hisi_hba *hisi_hba = dq->hisi_hba; 885 struct hisi_sas_slot *s, *s1, *s2 = NULL; 886 struct list_head *dq_list; 887 int dlvry_queue = dq->id; 888 int wp; 889 890 dq_list = &dq->list; 891 list_for_each_entry_safe(s, s1, &dq->list, delivery) { 892 if (!s->ready) 893 break; 894 s2 = s; 895 list_del(&s->delivery); 896 } 897 898 if (!s2) 899 return; 900 901 /* 902 * Ensure that memories for slots built on other CPUs is observed. 903 */ 904 smp_rmb(); 905 wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS; 906 907 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp); 908 } 909 910 static void prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba, 911 struct hisi_sas_slot *slot, 912 struct hisi_sas_cmd_hdr *hdr, 913 struct scatterlist *scatter, 914 int n_elem) 915 { 916 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot); 917 struct scatterlist *sg; 918 int i; 919 920 for_each_sg(scatter, sg, n_elem, i) { 921 struct hisi_sas_sge *entry = &sge_page->sge[i]; 922 923 entry->addr = cpu_to_le64(sg_dma_address(sg)); 924 entry->page_ctrl_0 = entry->page_ctrl_1 = 0; 925 entry->data_len = cpu_to_le32(sg_dma_len(sg)); 926 entry->data_off = 0; 927 } 928 929 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot)); 930 931 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF); 932 } 933 934 static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba, 935 struct hisi_sas_slot *slot) 936 { 937 struct sas_task *task = slot->task; 938 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 939 struct domain_device *device = task->dev; 940 struct hisi_sas_device *sas_dev = device->lldd_dev; 941 struct hisi_sas_port *port = slot->port; 942 struct sas_ssp_task *ssp_task = &task->ssp_task; 943 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd; 944 struct hisi_sas_tmf_task *tmf = slot->tmf; 945 int has_data = 0, priority = !!tmf; 946 u8 *buf_cmd; 947 u32 dw1 = 0, dw2 = 0; 948 949 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) | 950 (2 << CMD_HDR_TLR_CTRL_OFF) | 951 (port->id << CMD_HDR_PORT_OFF) | 952 (priority << CMD_HDR_PRIORITY_OFF) | 953 (1 << CMD_HDR_CMD_OFF)); /* ssp */ 954 955 dw1 = 1 << CMD_HDR_VDTL_OFF; 956 if (tmf) { 957 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF; 958 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF; 959 } else { 960 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF; 961 switch (scsi_cmnd->sc_data_direction) { 962 case DMA_TO_DEVICE: 963 has_data = 1; 964 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; 965 break; 966 case DMA_FROM_DEVICE: 967 has_data = 1; 968 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; 969 break; 970 default: 971 dw1 &= ~CMD_HDR_DIR_MSK; 972 } 973 } 974 975 /* map itct entry */ 976 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; 977 hdr->dw1 = cpu_to_le32(dw1); 978 979 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr) 980 + 3) / 4) << CMD_HDR_CFL_OFF) | 981 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) | 982 (2 << CMD_HDR_SG_MOD_OFF); 983 hdr->dw2 = cpu_to_le32(dw2); 984 hdr->transfer_tags = cpu_to_le32(slot->idx); 985 986 if (has_data) 987 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, 988 slot->n_elem); 989 990 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); 991 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); 992 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 993 994 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) + 995 sizeof(struct ssp_frame_hdr); 996 997 memcpy(buf_cmd, &task->ssp_task.LUN, 8); 998 if (!tmf) { 999 buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3); 1000 memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len); 1001 } else { 1002 buf_cmd[10] = tmf->tmf; 1003 switch (tmf->tmf) { 1004 case TMF_ABORT_TASK: 1005 case TMF_QUERY_TASK: 1006 buf_cmd[12] = 1007 (tmf->tag_of_task_to_be_managed >> 8) & 0xff; 1008 buf_cmd[13] = 1009 tmf->tag_of_task_to_be_managed & 0xff; 1010 break; 1011 default: 1012 break; 1013 } 1014 } 1015 } 1016 1017 static void prep_smp_v3_hw(struct hisi_hba *hisi_hba, 1018 struct hisi_sas_slot *slot) 1019 { 1020 struct sas_task *task = slot->task; 1021 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1022 struct domain_device *device = task->dev; 1023 struct hisi_sas_port *port = slot->port; 1024 struct scatterlist *sg_req; 1025 struct hisi_sas_device *sas_dev = device->lldd_dev; 1026 dma_addr_t req_dma_addr; 1027 unsigned int req_len; 1028 1029 /* req */ 1030 sg_req = &task->smp_task.smp_req; 1031 req_len = sg_dma_len(sg_req); 1032 req_dma_addr = sg_dma_address(sg_req); 1033 1034 /* create header */ 1035 /* dw0 */ 1036 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) | 1037 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */ 1038 (2 << CMD_HDR_CMD_OFF)); /* smp */ 1039 1040 /* map itct entry */ 1041 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) | 1042 (1 << CMD_HDR_FRAME_TYPE_OFF) | 1043 (DIR_NO_DATA << CMD_HDR_DIR_OFF)); 1044 1045 /* dw2 */ 1046 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) | 1047 (HISI_SAS_MAX_SMP_RESP_SZ / 4 << 1048 CMD_HDR_MRFL_OFF)); 1049 1050 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF); 1051 1052 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr); 1053 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1054 1055 } 1056 1057 static void prep_ata_v3_hw(struct hisi_hba *hisi_hba, 1058 struct hisi_sas_slot *slot) 1059 { 1060 struct sas_task *task = slot->task; 1061 struct domain_device *device = task->dev; 1062 struct domain_device *parent_dev = device->parent; 1063 struct hisi_sas_device *sas_dev = device->lldd_dev; 1064 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1065 struct asd_sas_port *sas_port = device->port; 1066 struct hisi_sas_port *port = to_hisi_sas_port(sas_port); 1067 u8 *buf_cmd; 1068 int has_data = 0, hdr_tag = 0; 1069 u32 dw1 = 0, dw2 = 0; 1070 1071 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF); 1072 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) 1073 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF); 1074 else 1075 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF); 1076 1077 switch (task->data_dir) { 1078 case DMA_TO_DEVICE: 1079 has_data = 1; 1080 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; 1081 break; 1082 case DMA_FROM_DEVICE: 1083 has_data = 1; 1084 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; 1085 break; 1086 default: 1087 dw1 &= ~CMD_HDR_DIR_MSK; 1088 } 1089 1090 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) && 1091 (task->ata_task.fis.control & ATA_SRST)) 1092 dw1 |= 1 << CMD_HDR_RESET_OFF; 1093 1094 dw1 |= (hisi_sas_get_ata_protocol( 1095 &task->ata_task.fis, task->data_dir)) 1096 << CMD_HDR_FRAME_TYPE_OFF; 1097 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; 1098 1099 if (FIS_CMD_IS_UNCONSTRAINED(task->ata_task.fis)) 1100 dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF; 1101 1102 hdr->dw1 = cpu_to_le32(dw1); 1103 1104 /* dw2 */ 1105 if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) { 1106 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); 1107 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF; 1108 } 1109 1110 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF | 1111 2 << CMD_HDR_SG_MOD_OFF; 1112 hdr->dw2 = cpu_to_le32(dw2); 1113 1114 /* dw3 */ 1115 hdr->transfer_tags = cpu_to_le32(slot->idx); 1116 1117 if (has_data) 1118 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, 1119 slot->n_elem); 1120 1121 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); 1122 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); 1123 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1124 1125 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot); 1126 1127 if (likely(!task->ata_task.device_control_reg_update)) 1128 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */ 1129 /* fill in command FIS */ 1130 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis)); 1131 } 1132 1133 static void prep_abort_v3_hw(struct hisi_hba *hisi_hba, 1134 struct hisi_sas_slot *slot, 1135 int device_id, int abort_flag, int tag_to_abort) 1136 { 1137 struct sas_task *task = slot->task; 1138 struct domain_device *dev = task->dev; 1139 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1140 struct hisi_sas_port *port = slot->port; 1141 1142 /* dw0 */ 1143 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/ 1144 (port->id << CMD_HDR_PORT_OFF) | 1145 (dev_is_sata(dev) 1146 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) | 1147 (abort_flag 1148 << CMD_HDR_ABORT_FLAG_OFF)); 1149 1150 /* dw1 */ 1151 hdr->dw1 = cpu_to_le32(device_id 1152 << CMD_HDR_DEV_ID_OFF); 1153 1154 /* dw7 */ 1155 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF); 1156 hdr->transfer_tags = cpu_to_le32(slot->idx); 1157 1158 } 1159 1160 static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1161 { 1162 int i, res; 1163 u32 context, port_id, link_rate; 1164 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1165 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1166 struct device *dev = hisi_hba->dev; 1167 unsigned long flags; 1168 1169 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1); 1170 1171 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 1172 port_id = (port_id >> (4 * phy_no)) & 0xf; 1173 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); 1174 link_rate = (link_rate >> (phy_no * 4)) & 0xf; 1175 1176 if (port_id == 0xf) { 1177 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no); 1178 res = IRQ_NONE; 1179 goto end; 1180 } 1181 sas_phy->linkrate = link_rate; 1182 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); 1183 1184 /* Check for SATA dev */ 1185 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT); 1186 if (context & (1 << phy_no)) { 1187 struct hisi_sas_initial_fis *initial_fis; 1188 struct dev_to_host_fis *fis; 1189 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0}; 1190 1191 dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate); 1192 initial_fis = &hisi_hba->initial_fis[phy_no]; 1193 fis = &initial_fis->fis; 1194 sas_phy->oob_mode = SATA_OOB_MODE; 1195 attached_sas_addr[0] = 0x50; 1196 attached_sas_addr[7] = phy_no; 1197 memcpy(sas_phy->attached_sas_addr, 1198 attached_sas_addr, 1199 SAS_ADDR_SIZE); 1200 memcpy(sas_phy->frame_rcvd, fis, 1201 sizeof(struct dev_to_host_fis)); 1202 phy->phy_type |= PORT_TYPE_SATA; 1203 phy->identify.device_type = SAS_SATA_DEV; 1204 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 1205 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 1206 } else { 1207 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd; 1208 struct sas_identify_frame *id = 1209 (struct sas_identify_frame *)frame_rcvd; 1210 1211 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate); 1212 for (i = 0; i < 6; i++) { 1213 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no, 1214 RX_IDAF_DWORD0 + (i * 4)); 1215 frame_rcvd[i] = __swab32(idaf); 1216 } 1217 sas_phy->oob_mode = SAS_OOB_MODE; 1218 memcpy(sas_phy->attached_sas_addr, 1219 &id->sas_addr, 1220 SAS_ADDR_SIZE); 1221 phy->phy_type |= PORT_TYPE_SAS; 1222 phy->identify.device_type = id->dev_type; 1223 phy->frame_rcvd_size = sizeof(struct sas_identify_frame); 1224 if (phy->identify.device_type == SAS_END_DEVICE) 1225 phy->identify.target_port_protocols = 1226 SAS_PROTOCOL_SSP; 1227 else if (phy->identify.device_type != SAS_PHY_UNUSED) 1228 phy->identify.target_port_protocols = 1229 SAS_PROTOCOL_SMP; 1230 } 1231 1232 phy->port_id = port_id; 1233 phy->phy_attached = 1; 1234 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP); 1235 res = IRQ_HANDLED; 1236 spin_lock_irqsave(&phy->lock, flags); 1237 if (phy->reset_completion) { 1238 phy->in_reset = 0; 1239 complete(phy->reset_completion); 1240 } 1241 spin_unlock_irqrestore(&phy->lock, flags); 1242 end: 1243 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1244 CHL_INT0_SL_PHY_ENABLE_MSK); 1245 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0); 1246 1247 return res; 1248 } 1249 1250 static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1251 { 1252 u32 phy_state, sl_ctrl, txid_auto; 1253 struct device *dev = hisi_hba->dev; 1254 1255 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1); 1256 1257 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1258 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state); 1259 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0); 1260 1261 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 1262 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, 1263 sl_ctrl&(~SL_CTA_MSK)); 1264 1265 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); 1266 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, 1267 txid_auto | CT3_MSK); 1268 1269 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK); 1270 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0); 1271 1272 return IRQ_HANDLED; 1273 } 1274 1275 static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1276 { 1277 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1278 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1279 struct sas_ha_struct *sas_ha = &hisi_hba->sha; 1280 u32 bcast_status; 1281 1282 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1); 1283 bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS); 1284 if ((bcast_status & RX_BCAST_CHG_MSK) && 1285 !test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)) 1286 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 1287 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1288 CHL_INT0_SL_RX_BCST_ACK_MSK); 1289 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0); 1290 1291 return IRQ_HANDLED; 1292 } 1293 1294 static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p) 1295 { 1296 struct hisi_hba *hisi_hba = p; 1297 u32 irq_msk; 1298 int phy_no = 0; 1299 irqreturn_t res = IRQ_NONE; 1300 1301 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) 1302 & 0x11111111; 1303 while (irq_msk) { 1304 if (irq_msk & 1) { 1305 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, 1306 CHL_INT0); 1307 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1308 int rdy = phy_state & (1 << phy_no); 1309 1310 if (rdy) { 1311 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK) 1312 /* phy up */ 1313 if (phy_up_v3_hw(phy_no, hisi_hba) 1314 == IRQ_HANDLED) 1315 res = IRQ_HANDLED; 1316 if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK) 1317 /* phy bcast */ 1318 if (phy_bcast_v3_hw(phy_no, hisi_hba) 1319 == IRQ_HANDLED) 1320 res = IRQ_HANDLED; 1321 } else { 1322 if (irq_value & CHL_INT0_NOT_RDY_MSK) 1323 /* phy down */ 1324 if (phy_down_v3_hw(phy_no, hisi_hba) 1325 == IRQ_HANDLED) 1326 res = IRQ_HANDLED; 1327 } 1328 } 1329 irq_msk >>= 4; 1330 phy_no++; 1331 } 1332 1333 return res; 1334 } 1335 1336 static const struct hisi_sas_hw_error port_axi_error[] = { 1337 { 1338 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF), 1339 .msg = "dma_tx_axi_wr_err", 1340 }, 1341 { 1342 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF), 1343 .msg = "dma_tx_axi_rd_err", 1344 }, 1345 { 1346 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF), 1347 .msg = "dma_rx_axi_wr_err", 1348 }, 1349 { 1350 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF), 1351 .msg = "dma_rx_axi_rd_err", 1352 }, 1353 }; 1354 1355 static void handle_chl_int1_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 1356 { 1357 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1); 1358 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1_MSK); 1359 struct device *dev = hisi_hba->dev; 1360 int i; 1361 1362 irq_value &= ~irq_msk; 1363 if (!irq_value) 1364 return; 1365 1366 for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) { 1367 const struct hisi_sas_hw_error *error = &port_axi_error[i]; 1368 1369 if (!(irq_value & error->irq_msk)) 1370 continue; 1371 1372 dev_err(dev, "%s error (phy%d 0x%x) found!\n", 1373 error->msg, phy_no, irq_value); 1374 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1375 } 1376 1377 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT1, irq_value); 1378 } 1379 1380 static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 1381 { 1382 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK); 1383 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2); 1384 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1385 struct pci_dev *pci_dev = hisi_hba->pci_dev; 1386 struct device *dev = hisi_hba->dev; 1387 1388 irq_value &= ~irq_msk; 1389 if (!irq_value) 1390 return; 1391 1392 if (irq_value & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) { 1393 dev_warn(dev, "phy%d identify timeout\n", phy_no); 1394 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1395 } 1396 1397 if (irq_value & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) { 1398 u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, 1399 STP_LINK_TIMEOUT_STATE); 1400 1401 dev_warn(dev, "phy%d stp link timeout (0x%x)\n", 1402 phy_no, reg_value); 1403 if (reg_value & BIT(4)) 1404 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1405 } 1406 1407 if ((irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) && 1408 (pci_dev->revision == 0x20)) { 1409 u32 reg_value; 1410 int rc; 1411 1412 rc = hisi_sas_read32_poll_timeout_atomic( 1413 HILINK_ERR_DFX, reg_value, 1414 !((reg_value >> 8) & BIT(phy_no)), 1415 1000, 10000); 1416 if (rc) 1417 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1418 } 1419 1420 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value); 1421 } 1422 1423 static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) 1424 { 1425 struct hisi_hba *hisi_hba = p; 1426 u32 irq_msk; 1427 int phy_no = 0; 1428 1429 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) 1430 & 0xeeeeeeee; 1431 1432 while (irq_msk) { 1433 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, 1434 CHL_INT0); 1435 1436 if (irq_msk & (4 << (phy_no * 4))) 1437 handle_chl_int1_v3_hw(hisi_hba, phy_no); 1438 1439 if (irq_msk & (8 << (phy_no * 4))) 1440 handle_chl_int2_v3_hw(hisi_hba, phy_no); 1441 1442 if (irq_msk & (2 << (phy_no * 4)) && irq_value0) { 1443 hisi_sas_phy_write32(hisi_hba, phy_no, 1444 CHL_INT0, irq_value0 1445 & (~CHL_INT0_SL_RX_BCST_ACK_MSK) 1446 & (~CHL_INT0_SL_PHY_ENABLE_MSK) 1447 & (~CHL_INT0_NOT_RDY_MSK)); 1448 } 1449 irq_msk &= ~(0xe << (phy_no * 4)); 1450 phy_no++; 1451 } 1452 1453 return IRQ_HANDLED; 1454 } 1455 1456 static const struct hisi_sas_hw_error axi_error[] = { 1457 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" }, 1458 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" }, 1459 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" }, 1460 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" }, 1461 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" }, 1462 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" }, 1463 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" }, 1464 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" }, 1465 {}, 1466 }; 1467 1468 static const struct hisi_sas_hw_error fifo_error[] = { 1469 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" }, 1470 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" }, 1471 { .msk = BIT(10), .msg = "GETDQE_FIFO" }, 1472 { .msk = BIT(11), .msg = "CMDP_FIFO" }, 1473 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" }, 1474 {}, 1475 }; 1476 1477 static const struct hisi_sas_hw_error fatal_axi_error[] = { 1478 { 1479 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF), 1480 .msg = "write pointer and depth", 1481 }, 1482 { 1483 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF), 1484 .msg = "iptt no match slot", 1485 }, 1486 { 1487 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF), 1488 .msg = "read pointer and depth", 1489 }, 1490 { 1491 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF), 1492 .reg = HGC_AXI_FIFO_ERR_INFO, 1493 .sub = axi_error, 1494 }, 1495 { 1496 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF), 1497 .reg = HGC_AXI_FIFO_ERR_INFO, 1498 .sub = fifo_error, 1499 }, 1500 { 1501 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF), 1502 .msg = "LM add/fetch list", 1503 }, 1504 { 1505 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF), 1506 .msg = "SAS_HGC_ABT fetch LM list", 1507 }, 1508 }; 1509 1510 static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p) 1511 { 1512 u32 irq_value, irq_msk; 1513 struct hisi_hba *hisi_hba = p; 1514 struct device *dev = hisi_hba->dev; 1515 int i; 1516 1517 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3); 1518 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00); 1519 1520 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); 1521 irq_value &= ~irq_msk; 1522 1523 for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) { 1524 const struct hisi_sas_hw_error *error = &fatal_axi_error[i]; 1525 1526 if (!(irq_value & error->irq_msk)) 1527 continue; 1528 1529 if (error->sub) { 1530 const struct hisi_sas_hw_error *sub = error->sub; 1531 u32 err_value = hisi_sas_read32(hisi_hba, error->reg); 1532 1533 for (; sub->msk || sub->msg; sub++) { 1534 if (!(err_value & sub->msk)) 1535 continue; 1536 1537 dev_err(dev, "%s error (0x%x) found!\n", 1538 sub->msg, irq_value); 1539 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1540 } 1541 } else { 1542 dev_err(dev, "%s error (0x%x) found!\n", 1543 error->msg, irq_value); 1544 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1545 } 1546 } 1547 1548 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) { 1549 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR); 1550 u32 dev_id = reg_val & ITCT_DEV_MSK; 1551 struct hisi_sas_device *sas_dev = 1552 &hisi_hba->devices[dev_id]; 1553 1554 hisi_sas_write32(hisi_hba, ITCT_CLR, 0); 1555 dev_dbg(dev, "clear ITCT ok\n"); 1556 complete(sas_dev->completion); 1557 } 1558 1559 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00); 1560 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk); 1561 1562 return IRQ_HANDLED; 1563 } 1564 1565 static void 1566 slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task, 1567 struct hisi_sas_slot *slot) 1568 { 1569 struct task_status_struct *ts = &task->task_status; 1570 struct hisi_sas_complete_v3_hdr *complete_queue = 1571 hisi_hba->complete_hdr[slot->cmplt_queue]; 1572 struct hisi_sas_complete_v3_hdr *complete_hdr = 1573 &complete_queue[slot->cmplt_queue_slot]; 1574 struct hisi_sas_err_record_v3 *record = 1575 hisi_sas_status_buf_addr_mem(slot); 1576 u32 dma_rx_err_type = record->dma_rx_err_type; 1577 u32 trans_tx_fail_type = record->trans_tx_fail_type; 1578 1579 switch (task->task_proto) { 1580 case SAS_PROTOCOL_SSP: 1581 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) { 1582 ts->residual = trans_tx_fail_type; 1583 ts->stat = SAS_DATA_UNDERRUN; 1584 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { 1585 ts->stat = SAS_QUEUE_FULL; 1586 slot->abort = 1; 1587 } else { 1588 ts->stat = SAS_OPEN_REJECT; 1589 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1590 } 1591 break; 1592 case SAS_PROTOCOL_SATA: 1593 case SAS_PROTOCOL_STP: 1594 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 1595 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) { 1596 ts->residual = trans_tx_fail_type; 1597 ts->stat = SAS_DATA_UNDERRUN; 1598 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { 1599 ts->stat = SAS_PHY_DOWN; 1600 slot->abort = 1; 1601 } else { 1602 ts->stat = SAS_OPEN_REJECT; 1603 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1604 } 1605 hisi_sas_sata_done(task, slot); 1606 break; 1607 case SAS_PROTOCOL_SMP: 1608 ts->stat = SAM_STAT_CHECK_CONDITION; 1609 break; 1610 default: 1611 break; 1612 } 1613 } 1614 1615 static int 1616 slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot) 1617 { 1618 struct sas_task *task = slot->task; 1619 struct hisi_sas_device *sas_dev; 1620 struct device *dev = hisi_hba->dev; 1621 struct task_status_struct *ts; 1622 struct domain_device *device; 1623 struct sas_ha_struct *ha; 1624 enum exec_status sts; 1625 struct hisi_sas_complete_v3_hdr *complete_queue = 1626 hisi_hba->complete_hdr[slot->cmplt_queue]; 1627 struct hisi_sas_complete_v3_hdr *complete_hdr = 1628 &complete_queue[slot->cmplt_queue_slot]; 1629 unsigned long flags; 1630 bool is_internal = slot->is_internal; 1631 1632 if (unlikely(!task || !task->lldd_task || !task->dev)) 1633 return -EINVAL; 1634 1635 ts = &task->task_status; 1636 device = task->dev; 1637 ha = device->port->ha; 1638 sas_dev = device->lldd_dev; 1639 1640 spin_lock_irqsave(&task->task_state_lock, flags); 1641 task->task_state_flags &= 1642 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR); 1643 spin_unlock_irqrestore(&task->task_state_lock, flags); 1644 1645 memset(ts, 0, sizeof(*ts)); 1646 ts->resp = SAS_TASK_COMPLETE; 1647 1648 if (unlikely(!sas_dev)) { 1649 dev_dbg(dev, "slot complete: port has not device\n"); 1650 ts->stat = SAS_PHY_DOWN; 1651 goto out; 1652 } 1653 1654 /* 1655 * Use SAS+TMF status codes 1656 */ 1657 switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK) 1658 >> CMPLT_HDR_ABORT_STAT_OFF) { 1659 case STAT_IO_ABORTED: 1660 /* this IO has been aborted by abort command */ 1661 ts->stat = SAS_ABORTED_TASK; 1662 goto out; 1663 case STAT_IO_COMPLETE: 1664 /* internal abort command complete */ 1665 ts->stat = TMF_RESP_FUNC_SUCC; 1666 goto out; 1667 case STAT_IO_NO_DEVICE: 1668 ts->stat = TMF_RESP_FUNC_COMPLETE; 1669 goto out; 1670 case STAT_IO_NOT_VALID: 1671 /* 1672 * abort single IO, the controller can't find the IO 1673 */ 1674 ts->stat = TMF_RESP_FUNC_FAILED; 1675 goto out; 1676 default: 1677 break; 1678 } 1679 1680 /* check for erroneous completion */ 1681 if ((complete_hdr->dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) { 1682 u32 *error_info = hisi_sas_status_buf_addr_mem(slot); 1683 1684 slot_err_v3_hw(hisi_hba, task, slot); 1685 if (ts->stat != SAS_DATA_UNDERRUN) 1686 dev_info(dev, "erroneous completion iptt=%d task=%p dev id=%d " 1687 "CQ hdr: 0x%x 0x%x 0x%x 0x%x " 1688 "Error info: 0x%x 0x%x 0x%x 0x%x\n", 1689 slot->idx, task, sas_dev->device_id, 1690 complete_hdr->dw0, complete_hdr->dw1, 1691 complete_hdr->act, complete_hdr->dw3, 1692 error_info[0], error_info[1], 1693 error_info[2], error_info[3]); 1694 if (unlikely(slot->abort)) 1695 return ts->stat; 1696 goto out; 1697 } 1698 1699 switch (task->task_proto) { 1700 case SAS_PROTOCOL_SSP: { 1701 struct ssp_response_iu *iu = 1702 hisi_sas_status_buf_addr_mem(slot) + 1703 sizeof(struct hisi_sas_err_record); 1704 1705 sas_ssp_task_response(dev, task, iu); 1706 break; 1707 } 1708 case SAS_PROTOCOL_SMP: { 1709 struct scatterlist *sg_resp = &task->smp_task.smp_resp; 1710 void *to; 1711 1712 ts->stat = SAM_STAT_GOOD; 1713 to = kmap_atomic(sg_page(sg_resp)); 1714 1715 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1, 1716 DMA_FROM_DEVICE); 1717 dma_unmap_sg(dev, &task->smp_task.smp_req, 1, 1718 DMA_TO_DEVICE); 1719 memcpy(to + sg_resp->offset, 1720 hisi_sas_status_buf_addr_mem(slot) + 1721 sizeof(struct hisi_sas_err_record), 1722 sg_dma_len(sg_resp)); 1723 kunmap_atomic(to); 1724 break; 1725 } 1726 case SAS_PROTOCOL_SATA: 1727 case SAS_PROTOCOL_STP: 1728 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 1729 ts->stat = SAM_STAT_GOOD; 1730 hisi_sas_sata_done(task, slot); 1731 break; 1732 default: 1733 ts->stat = SAM_STAT_CHECK_CONDITION; 1734 break; 1735 } 1736 1737 if (!slot->port->port_attached) { 1738 dev_warn(dev, "slot complete: port %d has removed\n", 1739 slot->port->sas_port.id); 1740 ts->stat = SAS_PHY_DOWN; 1741 } 1742 1743 out: 1744 hisi_sas_slot_task_free(hisi_hba, task, slot); 1745 sts = ts->stat; 1746 spin_lock_irqsave(&task->task_state_lock, flags); 1747 if (task->task_state_flags & SAS_TASK_STATE_ABORTED) { 1748 spin_unlock_irqrestore(&task->task_state_lock, flags); 1749 dev_info(dev, "slot complete: task(%p) aborted\n", task); 1750 return SAS_ABORTED_TASK; 1751 } 1752 task->task_state_flags |= SAS_TASK_STATE_DONE; 1753 spin_unlock_irqrestore(&task->task_state_lock, flags); 1754 1755 if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) { 1756 spin_lock_irqsave(&device->done_lock, flags); 1757 if (test_bit(SAS_HA_FROZEN, &ha->state)) { 1758 spin_unlock_irqrestore(&device->done_lock, flags); 1759 dev_info(dev, "slot complete: task(%p) ignored\n ", 1760 task); 1761 return sts; 1762 } 1763 spin_unlock_irqrestore(&device->done_lock, flags); 1764 } 1765 1766 if (task->task_done) 1767 task->task_done(task); 1768 1769 return sts; 1770 } 1771 1772 static void cq_tasklet_v3_hw(unsigned long val) 1773 { 1774 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val; 1775 struct hisi_hba *hisi_hba = cq->hisi_hba; 1776 struct hisi_sas_slot *slot; 1777 struct hisi_sas_complete_v3_hdr *complete_queue; 1778 u32 rd_point = cq->rd_point, wr_point; 1779 int queue = cq->id; 1780 1781 complete_queue = hisi_hba->complete_hdr[queue]; 1782 1783 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR + 1784 (0x14 * queue)); 1785 1786 while (rd_point != wr_point) { 1787 struct hisi_sas_complete_v3_hdr *complete_hdr; 1788 struct device *dev = hisi_hba->dev; 1789 int iptt; 1790 1791 complete_hdr = &complete_queue[rd_point]; 1792 1793 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK; 1794 if (likely(iptt < HISI_SAS_COMMAND_ENTRIES_V3_HW)) { 1795 slot = &hisi_hba->slot_info[iptt]; 1796 slot->cmplt_queue_slot = rd_point; 1797 slot->cmplt_queue = queue; 1798 slot_complete_v3_hw(hisi_hba, slot); 1799 } else 1800 dev_err(dev, "IPTT %d is invalid, discard it.\n", iptt); 1801 1802 if (++rd_point >= HISI_SAS_QUEUE_SLOTS) 1803 rd_point = 0; 1804 } 1805 1806 /* update rd_point */ 1807 cq->rd_point = rd_point; 1808 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point); 1809 } 1810 1811 static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p) 1812 { 1813 struct hisi_sas_cq *cq = p; 1814 struct hisi_hba *hisi_hba = cq->hisi_hba; 1815 int queue = cq->id; 1816 1817 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue); 1818 1819 tasklet_schedule(&cq->tasklet); 1820 1821 return IRQ_HANDLED; 1822 } 1823 1824 static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba) 1825 { 1826 struct device *dev = hisi_hba->dev; 1827 struct pci_dev *pdev = hisi_hba->pci_dev; 1828 int vectors, rc; 1829 int i, k; 1830 int max_msi = HISI_SAS_MSI_COUNT_V3_HW; 1831 1832 vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, 1, 1833 max_msi, PCI_IRQ_MSI); 1834 if (vectors < max_msi) { 1835 dev_err(dev, "could not allocate all msi (%d)\n", vectors); 1836 return -ENOENT; 1837 } 1838 1839 rc = devm_request_irq(dev, pci_irq_vector(pdev, 1), 1840 int_phy_up_down_bcast_v3_hw, 0, 1841 DRV_NAME " phy", hisi_hba); 1842 if (rc) { 1843 dev_err(dev, "could not request phy interrupt, rc=%d\n", rc); 1844 rc = -ENOENT; 1845 goto free_irq_vectors; 1846 } 1847 1848 rc = devm_request_irq(dev, pci_irq_vector(pdev, 2), 1849 int_chnl_int_v3_hw, 0, 1850 DRV_NAME " channel", hisi_hba); 1851 if (rc) { 1852 dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc); 1853 rc = -ENOENT; 1854 goto free_phy_irq; 1855 } 1856 1857 rc = devm_request_irq(dev, pci_irq_vector(pdev, 11), 1858 fatal_axi_int_v3_hw, 0, 1859 DRV_NAME " fatal", hisi_hba); 1860 if (rc) { 1861 dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc); 1862 rc = -ENOENT; 1863 goto free_chnl_interrupt; 1864 } 1865 1866 /* Init tasklets for cq only */ 1867 for (i = 0; i < hisi_hba->queue_count; i++) { 1868 struct hisi_sas_cq *cq = &hisi_hba->cq[i]; 1869 struct tasklet_struct *t = &cq->tasklet; 1870 1871 rc = devm_request_irq(dev, pci_irq_vector(pdev, i+16), 1872 cq_interrupt_v3_hw, 0, 1873 DRV_NAME " cq", cq); 1874 if (rc) { 1875 dev_err(dev, 1876 "could not request cq%d interrupt, rc=%d\n", 1877 i, rc); 1878 rc = -ENOENT; 1879 goto free_cq_irqs; 1880 } 1881 1882 tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq); 1883 } 1884 1885 return 0; 1886 1887 free_cq_irqs: 1888 for (k = 0; k < i; k++) { 1889 struct hisi_sas_cq *cq = &hisi_hba->cq[k]; 1890 1891 free_irq(pci_irq_vector(pdev, k+16), cq); 1892 } 1893 free_irq(pci_irq_vector(pdev, 11), hisi_hba); 1894 free_chnl_interrupt: 1895 free_irq(pci_irq_vector(pdev, 2), hisi_hba); 1896 free_phy_irq: 1897 free_irq(pci_irq_vector(pdev, 1), hisi_hba); 1898 free_irq_vectors: 1899 pci_free_irq_vectors(pdev); 1900 return rc; 1901 } 1902 1903 static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) 1904 { 1905 int rc; 1906 1907 rc = hw_init_v3_hw(hisi_hba); 1908 if (rc) 1909 return rc; 1910 1911 rc = interrupt_init_v3_hw(hisi_hba); 1912 if (rc) 1913 return rc; 1914 1915 return 0; 1916 } 1917 1918 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no, 1919 struct sas_phy_linkrates *r) 1920 { 1921 enum sas_linkrate max = r->maximum_linkrate; 1922 u32 prog_phy_link_rate = 0x800; 1923 1924 prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max); 1925 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, 1926 prog_phy_link_rate); 1927 } 1928 1929 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba) 1930 { 1931 struct pci_dev *pdev = hisi_hba->pci_dev; 1932 int i; 1933 1934 synchronize_irq(pci_irq_vector(pdev, 1)); 1935 synchronize_irq(pci_irq_vector(pdev, 2)); 1936 synchronize_irq(pci_irq_vector(pdev, 11)); 1937 for (i = 0; i < hisi_hba->queue_count; i++) { 1938 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1); 1939 synchronize_irq(pci_irq_vector(pdev, i + 16)); 1940 } 1941 1942 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff); 1943 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff); 1944 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff); 1945 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff); 1946 1947 for (i = 0; i < hisi_hba->n_phy; i++) { 1948 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff); 1949 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff); 1950 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1); 1951 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1); 1952 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1); 1953 } 1954 } 1955 1956 static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba) 1957 { 1958 return hisi_sas_read32(hisi_hba, PHY_STATE); 1959 } 1960 1961 static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 1962 { 1963 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1964 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1965 struct sas_phy *sphy = sas_phy->phy; 1966 u32 reg_value; 1967 1968 /* loss dword sync */ 1969 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST); 1970 sphy->loss_of_dword_sync_count += reg_value; 1971 1972 /* phy reset problem */ 1973 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB); 1974 sphy->phy_reset_problem_count += reg_value; 1975 1976 /* invalid dword */ 1977 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW); 1978 sphy->invalid_dword_count += reg_value; 1979 1980 /* disparity err */ 1981 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR); 1982 sphy->running_disparity_error_count += reg_value; 1983 1984 } 1985 1986 static int disable_host_v3_hw(struct hisi_hba *hisi_hba) 1987 { 1988 struct device *dev = hisi_hba->dev; 1989 u32 status, reg_val; 1990 int rc; 1991 1992 interrupt_disable_v3_hw(hisi_hba); 1993 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0); 1994 hisi_sas_kill_tasklets(hisi_hba); 1995 1996 hisi_sas_stop_phys(hisi_hba); 1997 1998 mdelay(10); 1999 2000 reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE + 2001 AM_CTRL_GLOBAL); 2002 reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK; 2003 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + 2004 AM_CTRL_GLOBAL, reg_val); 2005 2006 /* wait until bus idle */ 2007 rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE + 2008 AM_CURR_TRANS_RETURN, status, 2009 status == 0x3, 10, 100); 2010 if (rc) { 2011 dev_err(dev, "axi bus is not idle, rc=%d\n", rc); 2012 return rc; 2013 } 2014 2015 return 0; 2016 } 2017 2018 static int soft_reset_v3_hw(struct hisi_hba *hisi_hba) 2019 { 2020 struct device *dev = hisi_hba->dev; 2021 int rc; 2022 2023 rc = disable_host_v3_hw(hisi_hba); 2024 if (rc) { 2025 dev_err(dev, "soft reset: disable host failed rc=%d\n", rc); 2026 return rc; 2027 } 2028 2029 hisi_sas_init_mem(hisi_hba); 2030 2031 return hw_init_v3_hw(hisi_hba); 2032 } 2033 2034 static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type, 2035 u8 reg_index, u8 reg_count, u8 *write_data) 2036 { 2037 struct device *dev = hisi_hba->dev; 2038 u32 *data = (u32 *)write_data; 2039 int i; 2040 2041 switch (reg_type) { 2042 case SAS_GPIO_REG_TX: 2043 if ((reg_index + reg_count) > ((hisi_hba->n_phy + 3) / 4)) { 2044 dev_err(dev, "write gpio: invalid reg range[%d, %d]\n", 2045 reg_index, reg_index + reg_count - 1); 2046 return -EINVAL; 2047 } 2048 2049 for (i = 0; i < reg_count; i++) 2050 hisi_sas_write32(hisi_hba, 2051 SAS_GPIO_TX_0_1 + (reg_index + i) * 4, 2052 data[i]); 2053 break; 2054 default: 2055 dev_err(dev, "write gpio: unsupported or bad reg type %d\n", 2056 reg_type); 2057 return -EINVAL; 2058 } 2059 2060 return 0; 2061 } 2062 2063 static void wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba, 2064 int delay_ms, int timeout_ms) 2065 { 2066 struct device *dev = hisi_hba->dev; 2067 int entries, entries_old = 0, time; 2068 2069 for (time = 0; time < timeout_ms; time += delay_ms) { 2070 entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT); 2071 if (entries == entries_old) 2072 break; 2073 2074 entries_old = entries; 2075 msleep(delay_ms); 2076 } 2077 2078 dev_dbg(dev, "wait commands complete %dms\n", time); 2079 } 2080 2081 static struct scsi_host_template sht_v3_hw = { 2082 .name = DRV_NAME, 2083 .module = THIS_MODULE, 2084 .queuecommand = sas_queuecommand, 2085 .target_alloc = sas_target_alloc, 2086 .slave_configure = hisi_sas_slave_configure, 2087 .scan_finished = hisi_sas_scan_finished, 2088 .scan_start = hisi_sas_scan_start, 2089 .change_queue_depth = sas_change_queue_depth, 2090 .bios_param = sas_bios_param, 2091 .can_queue = 1, 2092 .this_id = -1, 2093 .sg_tablesize = SG_ALL, 2094 .max_sectors = SCSI_DEFAULT_MAX_SECTORS, 2095 .use_clustering = ENABLE_CLUSTERING, 2096 .eh_device_reset_handler = sas_eh_device_reset_handler, 2097 .eh_target_reset_handler = sas_eh_target_reset_handler, 2098 .target_destroy = sas_target_destroy, 2099 .ioctl = sas_ioctl, 2100 .shost_attrs = host_attrs, 2101 }; 2102 2103 static const struct hisi_sas_hw hisi_sas_v3_hw = { 2104 .hw_init = hisi_sas_v3_init, 2105 .setup_itct = setup_itct_v3_hw, 2106 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW, 2107 .get_wideport_bitmap = get_wideport_bitmap_v3_hw, 2108 .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr), 2109 .clear_itct = clear_itct_v3_hw, 2110 .sl_notify = sl_notify_v3_hw, 2111 .prep_ssp = prep_ssp_v3_hw, 2112 .prep_smp = prep_smp_v3_hw, 2113 .prep_stp = prep_ata_v3_hw, 2114 .prep_abort = prep_abort_v3_hw, 2115 .get_free_slot = get_free_slot_v3_hw, 2116 .start_delivery = start_delivery_v3_hw, 2117 .slot_complete = slot_complete_v3_hw, 2118 .phys_init = phys_init_v3_hw, 2119 .phy_start = start_phy_v3_hw, 2120 .phy_disable = disable_phy_v3_hw, 2121 .phy_hard_reset = phy_hard_reset_v3_hw, 2122 .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw, 2123 .phy_set_linkrate = phy_set_linkrate_v3_hw, 2124 .dereg_device = dereg_device_v3_hw, 2125 .soft_reset = soft_reset_v3_hw, 2126 .get_phys_state = get_phys_state_v3_hw, 2127 .get_events = phy_get_events_v3_hw, 2128 .write_gpio = write_gpio_v3_hw, 2129 .wait_cmds_complete_timeout = wait_cmds_complete_timeout_v3_hw, 2130 }; 2131 2132 static struct Scsi_Host * 2133 hisi_sas_shost_alloc_pci(struct pci_dev *pdev) 2134 { 2135 struct Scsi_Host *shost; 2136 struct hisi_hba *hisi_hba; 2137 struct device *dev = &pdev->dev; 2138 2139 shost = scsi_host_alloc(&sht_v3_hw, sizeof(*hisi_hba)); 2140 if (!shost) { 2141 dev_err(dev, "shost alloc failed\n"); 2142 return NULL; 2143 } 2144 hisi_hba = shost_priv(shost); 2145 2146 INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler); 2147 hisi_hba->hw = &hisi_sas_v3_hw; 2148 hisi_hba->pci_dev = pdev; 2149 hisi_hba->dev = dev; 2150 hisi_hba->shost = shost; 2151 SHOST_TO_SAS_HA(shost) = &hisi_hba->sha; 2152 2153 timer_setup(&hisi_hba->timer, NULL, 0); 2154 2155 if (hisi_sas_get_fw_info(hisi_hba) < 0) 2156 goto err_out; 2157 2158 if (hisi_sas_alloc(hisi_hba, shost)) { 2159 hisi_sas_free(hisi_hba); 2160 goto err_out; 2161 } 2162 2163 return shost; 2164 err_out: 2165 scsi_host_put(shost); 2166 dev_err(dev, "shost alloc failed\n"); 2167 return NULL; 2168 } 2169 2170 static int 2171 hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2172 { 2173 struct Scsi_Host *shost; 2174 struct hisi_hba *hisi_hba; 2175 struct device *dev = &pdev->dev; 2176 struct asd_sas_phy **arr_phy; 2177 struct asd_sas_port **arr_port; 2178 struct sas_ha_struct *sha; 2179 int rc, phy_nr, port_nr, i; 2180 2181 rc = pci_enable_device(pdev); 2182 if (rc) 2183 goto err_out; 2184 2185 pci_set_master(pdev); 2186 2187 rc = pci_request_regions(pdev, DRV_NAME); 2188 if (rc) 2189 goto err_out_disable_device; 2190 2191 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) || 2192 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) { 2193 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) || 2194 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) { 2195 dev_err(dev, "No usable DMA addressing method\n"); 2196 rc = -EIO; 2197 goto err_out_regions; 2198 } 2199 } 2200 2201 shost = hisi_sas_shost_alloc_pci(pdev); 2202 if (!shost) { 2203 rc = -ENOMEM; 2204 goto err_out_regions; 2205 } 2206 2207 sha = SHOST_TO_SAS_HA(shost); 2208 hisi_hba = shost_priv(shost); 2209 dev_set_drvdata(dev, sha); 2210 2211 hisi_hba->regs = pcim_iomap(pdev, 5, 0); 2212 if (!hisi_hba->regs) { 2213 dev_err(dev, "cannot map register.\n"); 2214 rc = -ENOMEM; 2215 goto err_out_ha; 2216 } 2217 2218 phy_nr = port_nr = hisi_hba->n_phy; 2219 2220 arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL); 2221 arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL); 2222 if (!arr_phy || !arr_port) { 2223 rc = -ENOMEM; 2224 goto err_out_ha; 2225 } 2226 2227 sha->sas_phy = arr_phy; 2228 sha->sas_port = arr_port; 2229 sha->core.shost = shost; 2230 sha->lldd_ha = hisi_hba; 2231 2232 shost->transportt = hisi_sas_stt; 2233 shost->max_id = HISI_SAS_MAX_DEVICES; 2234 shost->max_lun = ~0; 2235 shost->max_channel = 1; 2236 shost->max_cmd_len = 16; 2237 shost->sg_tablesize = min_t(u16, SG_ALL, HISI_SAS_SGE_PAGE_CNT); 2238 shost->can_queue = hisi_hba->hw->max_command_entries; 2239 shost->cmd_per_lun = hisi_hba->hw->max_command_entries; 2240 2241 sha->sas_ha_name = DRV_NAME; 2242 sha->dev = dev; 2243 sha->lldd_module = THIS_MODULE; 2244 sha->sas_addr = &hisi_hba->sas_addr[0]; 2245 sha->num_phys = hisi_hba->n_phy; 2246 sha->core.shost = hisi_hba->shost; 2247 2248 for (i = 0; i < hisi_hba->n_phy; i++) { 2249 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy; 2250 sha->sas_port[i] = &hisi_hba->port[i].sas_port; 2251 } 2252 2253 rc = scsi_add_host(shost, dev); 2254 if (rc) 2255 goto err_out_ha; 2256 2257 rc = sas_register_ha(sha); 2258 if (rc) 2259 goto err_out_register_ha; 2260 2261 rc = hisi_hba->hw->hw_init(hisi_hba); 2262 if (rc) 2263 goto err_out_register_ha; 2264 2265 scsi_scan_host(shost); 2266 2267 return 0; 2268 2269 err_out_register_ha: 2270 scsi_remove_host(shost); 2271 err_out_ha: 2272 scsi_host_put(shost); 2273 err_out_regions: 2274 pci_release_regions(pdev); 2275 err_out_disable_device: 2276 pci_disable_device(pdev); 2277 err_out: 2278 return rc; 2279 } 2280 2281 static void 2282 hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba) 2283 { 2284 int i; 2285 2286 free_irq(pci_irq_vector(pdev, 1), hisi_hba); 2287 free_irq(pci_irq_vector(pdev, 2), hisi_hba); 2288 free_irq(pci_irq_vector(pdev, 11), hisi_hba); 2289 for (i = 0; i < hisi_hba->queue_count; i++) { 2290 struct hisi_sas_cq *cq = &hisi_hba->cq[i]; 2291 2292 free_irq(pci_irq_vector(pdev, i+16), cq); 2293 } 2294 pci_free_irq_vectors(pdev); 2295 } 2296 2297 static void hisi_sas_v3_remove(struct pci_dev *pdev) 2298 { 2299 struct device *dev = &pdev->dev; 2300 struct sas_ha_struct *sha = dev_get_drvdata(dev); 2301 struct hisi_hba *hisi_hba = sha->lldd_ha; 2302 struct Scsi_Host *shost = sha->core.shost; 2303 2304 if (timer_pending(&hisi_hba->timer)) 2305 del_timer(&hisi_hba->timer); 2306 2307 sas_unregister_ha(sha); 2308 sas_remove_host(sha->core.shost); 2309 2310 hisi_sas_v3_destroy_irqs(pdev, hisi_hba); 2311 hisi_sas_kill_tasklets(hisi_hba); 2312 pci_release_regions(pdev); 2313 pci_disable_device(pdev); 2314 hisi_sas_free(hisi_hba); 2315 scsi_host_put(shost); 2316 } 2317 2318 static const struct hisi_sas_hw_error sas_ras_intr0_nfe[] = { 2319 { .irq_msk = BIT(19), .msg = "HILINK_INT" }, 2320 { .irq_msk = BIT(20), .msg = "HILINK_PLL0_OUT_OF_LOCK" }, 2321 { .irq_msk = BIT(21), .msg = "HILINK_PLL1_OUT_OF_LOCK" }, 2322 { .irq_msk = BIT(22), .msg = "HILINK_LOSS_OF_REFCLK0" }, 2323 { .irq_msk = BIT(23), .msg = "HILINK_LOSS_OF_REFCLK1" }, 2324 { .irq_msk = BIT(24), .msg = "DMAC0_TX_POISON" }, 2325 { .irq_msk = BIT(25), .msg = "DMAC1_TX_POISON" }, 2326 { .irq_msk = BIT(26), .msg = "DMAC2_TX_POISON" }, 2327 { .irq_msk = BIT(27), .msg = "DMAC3_TX_POISON" }, 2328 { .irq_msk = BIT(28), .msg = "DMAC4_TX_POISON" }, 2329 { .irq_msk = BIT(29), .msg = "DMAC5_TX_POISON" }, 2330 { .irq_msk = BIT(30), .msg = "DMAC6_TX_POISON" }, 2331 { .irq_msk = BIT(31), .msg = "DMAC7_TX_POISON" }, 2332 }; 2333 2334 static const struct hisi_sas_hw_error sas_ras_intr1_nfe[] = { 2335 { .irq_msk = BIT(0), .msg = "RXM_CFG_MEM3_ECC2B_INTR" }, 2336 { .irq_msk = BIT(1), .msg = "RXM_CFG_MEM2_ECC2B_INTR" }, 2337 { .irq_msk = BIT(2), .msg = "RXM_CFG_MEM1_ECC2B_INTR" }, 2338 { .irq_msk = BIT(3), .msg = "RXM_CFG_MEM0_ECC2B_INTR" }, 2339 { .irq_msk = BIT(4), .msg = "HGC_CQE_ECC2B_INTR" }, 2340 { .irq_msk = BIT(5), .msg = "LM_CFG_IOSTL_ECC2B_INTR" }, 2341 { .irq_msk = BIT(6), .msg = "LM_CFG_ITCTL_ECC2B_INTR" }, 2342 { .irq_msk = BIT(7), .msg = "HGC_ITCT_ECC2B_INTR" }, 2343 { .irq_msk = BIT(8), .msg = "HGC_IOST_ECC2B_INTR" }, 2344 { .irq_msk = BIT(9), .msg = "HGC_DQE_ECC2B_INTR" }, 2345 { .irq_msk = BIT(10), .msg = "DMAC0_RAM_ECC2B_INTR" }, 2346 { .irq_msk = BIT(11), .msg = "DMAC1_RAM_ECC2B_INTR" }, 2347 { .irq_msk = BIT(12), .msg = "DMAC2_RAM_ECC2B_INTR" }, 2348 { .irq_msk = BIT(13), .msg = "DMAC3_RAM_ECC2B_INTR" }, 2349 { .irq_msk = BIT(14), .msg = "DMAC4_RAM_ECC2B_INTR" }, 2350 { .irq_msk = BIT(15), .msg = "DMAC5_RAM_ECC2B_INTR" }, 2351 { .irq_msk = BIT(16), .msg = "DMAC6_RAM_ECC2B_INTR" }, 2352 { .irq_msk = BIT(17), .msg = "DMAC7_RAM_ECC2B_INTR" }, 2353 { .irq_msk = BIT(18), .msg = "OOO_RAM_ECC2B_INTR" }, 2354 { .irq_msk = BIT(20), .msg = "HGC_DQE_POISON_INTR" }, 2355 { .irq_msk = BIT(21), .msg = "HGC_IOST_POISON_INTR" }, 2356 { .irq_msk = BIT(22), .msg = "HGC_ITCT_POISON_INTR" }, 2357 { .irq_msk = BIT(23), .msg = "HGC_ITCT_NCQ_POISON_INTR" }, 2358 { .irq_msk = BIT(24), .msg = "DMAC0_RX_POISON" }, 2359 { .irq_msk = BIT(25), .msg = "DMAC1_RX_POISON" }, 2360 { .irq_msk = BIT(26), .msg = "DMAC2_RX_POISON" }, 2361 { .irq_msk = BIT(27), .msg = "DMAC3_RX_POISON" }, 2362 { .irq_msk = BIT(28), .msg = "DMAC4_RX_POISON" }, 2363 { .irq_msk = BIT(29), .msg = "DMAC5_RX_POISON" }, 2364 { .irq_msk = BIT(30), .msg = "DMAC6_RX_POISON" }, 2365 { .irq_msk = BIT(31), .msg = "DMAC7_RX_POISON" }, 2366 }; 2367 2368 static const struct hisi_sas_hw_error sas_ras_intr2_nfe[] = { 2369 { .irq_msk = BIT(0), .msg = "DMAC0_AXI_BUS_ERR" }, 2370 { .irq_msk = BIT(1), .msg = "DMAC1_AXI_BUS_ERR" }, 2371 { .irq_msk = BIT(2), .msg = "DMAC2_AXI_BUS_ERR" }, 2372 { .irq_msk = BIT(3), .msg = "DMAC3_AXI_BUS_ERR" }, 2373 { .irq_msk = BIT(4), .msg = "DMAC4_AXI_BUS_ERR" }, 2374 { .irq_msk = BIT(5), .msg = "DMAC5_AXI_BUS_ERR" }, 2375 { .irq_msk = BIT(6), .msg = "DMAC6_AXI_BUS_ERR" }, 2376 { .irq_msk = BIT(7), .msg = "DMAC7_AXI_BUS_ERR" }, 2377 { .irq_msk = BIT(8), .msg = "DMAC0_FIFO_OMIT_ERR" }, 2378 { .irq_msk = BIT(9), .msg = "DMAC1_FIFO_OMIT_ERR" }, 2379 { .irq_msk = BIT(10), .msg = "DMAC2_FIFO_OMIT_ERR" }, 2380 { .irq_msk = BIT(11), .msg = "DMAC3_FIFO_OMIT_ERR" }, 2381 { .irq_msk = BIT(12), .msg = "DMAC4_FIFO_OMIT_ERR" }, 2382 { .irq_msk = BIT(13), .msg = "DMAC5_FIFO_OMIT_ERR" }, 2383 { .irq_msk = BIT(14), .msg = "DMAC6_FIFO_OMIT_ERR" }, 2384 { .irq_msk = BIT(15), .msg = "DMAC7_FIFO_OMIT_ERR" }, 2385 { .irq_msk = BIT(16), .msg = "HGC_RLSE_SLOT_UNMATCH" }, 2386 { .irq_msk = BIT(17), .msg = "HGC_LM_ADD_FCH_LIST_ERR" }, 2387 { .irq_msk = BIT(18), .msg = "HGC_AXI_BUS_ERR" }, 2388 { .irq_msk = BIT(19), .msg = "HGC_FIFO_OMIT_ERR" }, 2389 }; 2390 2391 static bool process_non_fatal_error_v3_hw(struct hisi_hba *hisi_hba) 2392 { 2393 struct device *dev = hisi_hba->dev; 2394 const struct hisi_sas_hw_error *ras_error; 2395 bool need_reset = false; 2396 u32 irq_value; 2397 int i; 2398 2399 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR0); 2400 for (i = 0; i < ARRAY_SIZE(sas_ras_intr0_nfe); i++) { 2401 ras_error = &sas_ras_intr0_nfe[i]; 2402 if (ras_error->irq_msk & irq_value) { 2403 dev_warn(dev, "SAS_RAS_INTR0: %s(irq_value=0x%x) found.\n", 2404 ras_error->msg, irq_value); 2405 need_reset = true; 2406 } 2407 } 2408 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0, irq_value); 2409 2410 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR1); 2411 for (i = 0; i < ARRAY_SIZE(sas_ras_intr1_nfe); i++) { 2412 ras_error = &sas_ras_intr1_nfe[i]; 2413 if (ras_error->irq_msk & irq_value) { 2414 dev_warn(dev, "SAS_RAS_INTR1: %s(irq_value=0x%x) found.\n", 2415 ras_error->msg, irq_value); 2416 need_reset = true; 2417 } 2418 } 2419 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1, irq_value); 2420 2421 irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR2); 2422 for (i = 0; i < ARRAY_SIZE(sas_ras_intr2_nfe); i++) { 2423 ras_error = &sas_ras_intr2_nfe[i]; 2424 if (ras_error->irq_msk & irq_value) { 2425 dev_warn(dev, "SAS_RAS_INTR2: %s(irq_value=0x%x) found.\n", 2426 ras_error->msg, irq_value); 2427 need_reset = true; 2428 } 2429 } 2430 hisi_sas_write32(hisi_hba, SAS_RAS_INTR2, irq_value); 2431 2432 return need_reset; 2433 } 2434 2435 static pci_ers_result_t hisi_sas_error_detected_v3_hw(struct pci_dev *pdev, 2436 pci_channel_state_t state) 2437 { 2438 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2439 struct hisi_hba *hisi_hba = sha->lldd_ha; 2440 struct device *dev = hisi_hba->dev; 2441 2442 dev_info(dev, "PCI error: detected callback, state(%d)!!\n", state); 2443 if (state == pci_channel_io_perm_failure) 2444 return PCI_ERS_RESULT_DISCONNECT; 2445 2446 if (process_non_fatal_error_v3_hw(hisi_hba)) 2447 return PCI_ERS_RESULT_NEED_RESET; 2448 2449 return PCI_ERS_RESULT_CAN_RECOVER; 2450 } 2451 2452 static pci_ers_result_t hisi_sas_mmio_enabled_v3_hw(struct pci_dev *pdev) 2453 { 2454 return PCI_ERS_RESULT_RECOVERED; 2455 } 2456 2457 static pci_ers_result_t hisi_sas_slot_reset_v3_hw(struct pci_dev *pdev) 2458 { 2459 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2460 struct hisi_hba *hisi_hba = sha->lldd_ha; 2461 struct device *dev = hisi_hba->dev; 2462 HISI_SAS_DECLARE_RST_WORK_ON_STACK(r); 2463 2464 dev_info(dev, "PCI error: slot reset callback!!\n"); 2465 queue_work(hisi_hba->wq, &r.work); 2466 wait_for_completion(r.completion); 2467 if (r.done) 2468 return PCI_ERS_RESULT_RECOVERED; 2469 2470 return PCI_ERS_RESULT_DISCONNECT; 2471 } 2472 2473 static void hisi_sas_reset_prepare_v3_hw(struct pci_dev *pdev) 2474 { 2475 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2476 struct hisi_hba *hisi_hba = sha->lldd_ha; 2477 struct device *dev = hisi_hba->dev; 2478 int rc; 2479 2480 dev_info(dev, "FLR prepare\n"); 2481 set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 2482 hisi_sas_controller_reset_prepare(hisi_hba); 2483 2484 rc = disable_host_v3_hw(hisi_hba); 2485 if (rc) 2486 dev_err(dev, "FLR: disable host failed rc=%d\n", rc); 2487 } 2488 2489 static void hisi_sas_reset_done_v3_hw(struct pci_dev *pdev) 2490 { 2491 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2492 struct hisi_hba *hisi_hba = sha->lldd_ha; 2493 struct device *dev = hisi_hba->dev; 2494 int rc; 2495 2496 hisi_sas_init_mem(hisi_hba); 2497 2498 rc = hw_init_v3_hw(hisi_hba); 2499 if (rc) { 2500 dev_err(dev, "FLR: hw init failed rc=%d\n", rc); 2501 return; 2502 } 2503 2504 hisi_sas_controller_reset_done(hisi_hba); 2505 dev_info(dev, "FLR done\n"); 2506 } 2507 2508 enum { 2509 /* instances of the controller */ 2510 hip08, 2511 }; 2512 2513 static int hisi_sas_v3_suspend(struct pci_dev *pdev, pm_message_t state) 2514 { 2515 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2516 struct hisi_hba *hisi_hba = sha->lldd_ha; 2517 struct device *dev = hisi_hba->dev; 2518 struct Scsi_Host *shost = hisi_hba->shost; 2519 u32 device_state; 2520 int rc; 2521 2522 if (!pdev->pm_cap) { 2523 dev_err(dev, "PCI PM not supported\n"); 2524 return -ENODEV; 2525 } 2526 2527 if (test_and_set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)) 2528 return -1; 2529 2530 scsi_block_requests(shost); 2531 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 2532 flush_workqueue(hisi_hba->wq); 2533 2534 rc = disable_host_v3_hw(hisi_hba); 2535 if (rc) { 2536 dev_err(dev, "PM suspend: disable host failed rc=%d\n", rc); 2537 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 2538 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 2539 scsi_unblock_requests(shost); 2540 return rc; 2541 } 2542 2543 hisi_sas_init_mem(hisi_hba); 2544 2545 device_state = pci_choose_state(pdev, state); 2546 dev_warn(dev, "entering operating state [D%d]\n", 2547 device_state); 2548 pci_save_state(pdev); 2549 pci_disable_device(pdev); 2550 pci_set_power_state(pdev, device_state); 2551 2552 hisi_sas_release_tasks(hisi_hba); 2553 2554 sas_suspend_ha(sha); 2555 return 0; 2556 } 2557 2558 static int hisi_sas_v3_resume(struct pci_dev *pdev) 2559 { 2560 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 2561 struct hisi_hba *hisi_hba = sha->lldd_ha; 2562 struct Scsi_Host *shost = hisi_hba->shost; 2563 struct device *dev = hisi_hba->dev; 2564 unsigned int rc; 2565 u32 device_state = pdev->current_state; 2566 2567 dev_warn(dev, "resuming from operating state [D%d]\n", 2568 device_state); 2569 pci_set_power_state(pdev, PCI_D0); 2570 pci_enable_wake(pdev, PCI_D0, 0); 2571 pci_restore_state(pdev); 2572 rc = pci_enable_device(pdev); 2573 if (rc) 2574 dev_err(dev, "enable device failed during resume (%d)\n", rc); 2575 2576 pci_set_master(pdev); 2577 scsi_unblock_requests(shost); 2578 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 2579 2580 sas_prep_resume_ha(sha); 2581 init_reg_v3_hw(hisi_hba); 2582 hisi_hba->hw->phys_init(hisi_hba); 2583 sas_resume_ha(sha); 2584 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 2585 2586 return 0; 2587 } 2588 2589 static const struct pci_device_id sas_v3_pci_table[] = { 2590 { PCI_VDEVICE(HUAWEI, 0xa230), hip08 }, 2591 {} 2592 }; 2593 MODULE_DEVICE_TABLE(pci, sas_v3_pci_table); 2594 2595 static const struct pci_error_handlers hisi_sas_err_handler = { 2596 .error_detected = hisi_sas_error_detected_v3_hw, 2597 .mmio_enabled = hisi_sas_mmio_enabled_v3_hw, 2598 .slot_reset = hisi_sas_slot_reset_v3_hw, 2599 .reset_prepare = hisi_sas_reset_prepare_v3_hw, 2600 .reset_done = hisi_sas_reset_done_v3_hw, 2601 }; 2602 2603 static struct pci_driver sas_v3_pci_driver = { 2604 .name = DRV_NAME, 2605 .id_table = sas_v3_pci_table, 2606 .probe = hisi_sas_v3_probe, 2607 .remove = hisi_sas_v3_remove, 2608 .suspend = hisi_sas_v3_suspend, 2609 .resume = hisi_sas_v3_resume, 2610 .err_handler = &hisi_sas_err_handler, 2611 }; 2612 2613 module_pci_driver(sas_v3_pci_driver); 2614 2615 MODULE_LICENSE("GPL"); 2616 MODULE_AUTHOR("John Garry <john.garry@huawei.com>"); 2617 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device"); 2618 MODULE_ALIAS("pci:" DRV_NAME); 2619