1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright (c) 2017 Hisilicon Limited.
4  */
5 
6 #include <linux/sched/clock.h>
7 #include "hisi_sas.h"
8 #define DRV_NAME "hisi_sas_v3_hw"
9 
10 /* global registers need init */
11 #define DLVRY_QUEUE_ENABLE		0x0
12 #define IOST_BASE_ADDR_LO		0x8
13 #define IOST_BASE_ADDR_HI		0xc
14 #define ITCT_BASE_ADDR_LO		0x10
15 #define ITCT_BASE_ADDR_HI		0x14
16 #define IO_BROKEN_MSG_ADDR_LO		0x18
17 #define IO_BROKEN_MSG_ADDR_HI		0x1c
18 #define PHY_CONTEXT			0x20
19 #define PHY_STATE			0x24
20 #define PHY_PORT_NUM_MA			0x28
21 #define PHY_CONN_RATE			0x30
22 #define ITCT_CLR			0x44
23 #define ITCT_CLR_EN_OFF			16
24 #define ITCT_CLR_EN_MSK			(0x1 << ITCT_CLR_EN_OFF)
25 #define ITCT_DEV_OFF			0
26 #define ITCT_DEV_MSK			(0x7ff << ITCT_DEV_OFF)
27 #define SAS_AXI_USER3			0x50
28 #define IO_SATA_BROKEN_MSG_ADDR_LO	0x58
29 #define IO_SATA_BROKEN_MSG_ADDR_HI	0x5c
30 #define SATA_INITI_D2H_STORE_ADDR_LO	0x60
31 #define SATA_INITI_D2H_STORE_ADDR_HI	0x64
32 #define CFG_MAX_TAG			0x68
33 #define TRANS_LOCK_ICT_TIME		0X70
34 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL	0x84
35 #define HGC_SAS_TXFAIL_RETRY_CTRL	0x88
36 #define HGC_GET_ITV_TIME		0x90
37 #define DEVICE_MSG_WORK_MODE		0x94
38 #define OPENA_WT_CONTI_TIME		0x9c
39 #define I_T_NEXUS_LOSS_TIME		0xa0
40 #define MAX_CON_TIME_LIMIT_TIME		0xa4
41 #define BUS_INACTIVE_LIMIT_TIME		0xa8
42 #define REJECT_TO_OPEN_LIMIT_TIME	0xac
43 #define CQ_INT_CONVERGE_EN		0xb0
44 #define CFG_AGING_TIME			0xbc
45 #define HGC_DFX_CFG2			0xc0
46 #define CFG_ABT_SET_QUERY_IPTT	0xd4
47 #define CFG_SET_ABORTED_IPTT_OFF	0
48 #define CFG_SET_ABORTED_IPTT_MSK	(0xfff << CFG_SET_ABORTED_IPTT_OFF)
49 #define CFG_SET_ABORTED_EN_OFF	12
50 #define CFG_ABT_SET_IPTT_DONE	0xd8
51 #define CFG_ABT_SET_IPTT_DONE_OFF	0
52 #define HGC_IOMB_PROC1_STATUS	0x104
53 #define HGC_LM_DFX_STATUS2		0x128
54 #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF		0
55 #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK	(0xfff << \
56 					 HGC_LM_DFX_STATUS2_IOSTLIST_OFF)
57 #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF		12
58 #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK	(0x7ff << \
59 					 HGC_LM_DFX_STATUS2_ITCTLIST_OFF)
60 #define HGC_CQE_ECC_ADDR		0x13c
61 #define HGC_CQE_ECC_1B_ADDR_OFF	0
62 #define HGC_CQE_ECC_1B_ADDR_MSK	(0x3f << HGC_CQE_ECC_1B_ADDR_OFF)
63 #define HGC_CQE_ECC_MB_ADDR_OFF	8
64 #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF)
65 #define HGC_IOST_ECC_ADDR		0x140
66 #define HGC_IOST_ECC_1B_ADDR_OFF	0
67 #define HGC_IOST_ECC_1B_ADDR_MSK	(0x3ff << HGC_IOST_ECC_1B_ADDR_OFF)
68 #define HGC_IOST_ECC_MB_ADDR_OFF	16
69 #define HGC_IOST_ECC_MB_ADDR_MSK	(0x3ff << HGC_IOST_ECC_MB_ADDR_OFF)
70 #define HGC_DQE_ECC_ADDR		0x144
71 #define HGC_DQE_ECC_1B_ADDR_OFF	0
72 #define HGC_DQE_ECC_1B_ADDR_MSK	(0xfff << HGC_DQE_ECC_1B_ADDR_OFF)
73 #define HGC_DQE_ECC_MB_ADDR_OFF	16
74 #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF)
75 #define CHNL_INT_STATUS			0x148
76 #define TAB_DFX				0x14c
77 #define HGC_ITCT_ECC_ADDR		0x150
78 #define HGC_ITCT_ECC_1B_ADDR_OFF		0
79 #define HGC_ITCT_ECC_1B_ADDR_MSK		(0x3ff << \
80 						 HGC_ITCT_ECC_1B_ADDR_OFF)
81 #define HGC_ITCT_ECC_MB_ADDR_OFF		16
82 #define HGC_ITCT_ECC_MB_ADDR_MSK		(0x3ff << \
83 						 HGC_ITCT_ECC_MB_ADDR_OFF)
84 #define HGC_AXI_FIFO_ERR_INFO  0x154
85 #define AXI_ERR_INFO_OFF               0
86 #define AXI_ERR_INFO_MSK               (0xff << AXI_ERR_INFO_OFF)
87 #define FIFO_ERR_INFO_OFF              8
88 #define FIFO_ERR_INFO_MSK              (0xff << FIFO_ERR_INFO_OFF)
89 #define TAB_RD_TYPE			0x15c
90 #define INT_COAL_EN			0x19c
91 #define OQ_INT_COAL_TIME		0x1a0
92 #define OQ_INT_COAL_CNT			0x1a4
93 #define ENT_INT_COAL_TIME		0x1a8
94 #define ENT_INT_COAL_CNT		0x1ac
95 #define OQ_INT_SRC			0x1b0
96 #define OQ_INT_SRC_MSK			0x1b4
97 #define ENT_INT_SRC1			0x1b8
98 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF	0
99 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK	(0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
100 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF	8
101 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK	(0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
102 #define ENT_INT_SRC2			0x1bc
103 #define ENT_INT_SRC3			0x1c0
104 #define ENT_INT_SRC3_WP_DEPTH_OFF		8
105 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF	9
106 #define ENT_INT_SRC3_RP_DEPTH_OFF		10
107 #define ENT_INT_SRC3_AXI_OFF			11
108 #define ENT_INT_SRC3_FIFO_OFF			12
109 #define ENT_INT_SRC3_LM_OFF				14
110 #define ENT_INT_SRC3_ITC_INT_OFF	15
111 #define ENT_INT_SRC3_ITC_INT_MSK	(0x1 << ENT_INT_SRC3_ITC_INT_OFF)
112 #define ENT_INT_SRC3_ABT_OFF		16
113 #define ENT_INT_SRC3_DQE_POISON_OFF	18
114 #define ENT_INT_SRC3_IOST_POISON_OFF	19
115 #define ENT_INT_SRC3_ITCT_POISON_OFF	20
116 #define ENT_INT_SRC3_ITCT_NCQ_POISON_OFF	21
117 #define ENT_INT_SRC_MSK1		0x1c4
118 #define ENT_INT_SRC_MSK2		0x1c8
119 #define ENT_INT_SRC_MSK3		0x1cc
120 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF	31
121 #define CHNL_PHYUPDOWN_INT_MSK		0x1d0
122 #define CHNL_ENT_INT_MSK			0x1d4
123 #define HGC_COM_INT_MSK				0x1d8
124 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK	(0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
125 #define SAS_ECC_INTR			0x1e8
126 #define SAS_ECC_INTR_DQE_ECC_1B_OFF		0
127 #define SAS_ECC_INTR_DQE_ECC_MB_OFF		1
128 #define SAS_ECC_INTR_IOST_ECC_1B_OFF	2
129 #define SAS_ECC_INTR_IOST_ECC_MB_OFF	3
130 #define SAS_ECC_INTR_ITCT_ECC_1B_OFF	4
131 #define SAS_ECC_INTR_ITCT_ECC_MB_OFF	5
132 #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF	6
133 #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF	7
134 #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF	8
135 #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF	9
136 #define SAS_ECC_INTR_CQE_ECC_1B_OFF		10
137 #define SAS_ECC_INTR_CQE_ECC_MB_OFF		11
138 #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF	12
139 #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF	13
140 #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF	14
141 #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF	15
142 #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF	16
143 #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF	17
144 #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF	18
145 #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF	19
146 #define SAS_ECC_INTR_OOO_RAM_ECC_1B_OFF		20
147 #define SAS_ECC_INTR_OOO_RAM_ECC_MB_OFF		21
148 #define SAS_ECC_INTR_MSK		0x1ec
149 #define HGC_ERR_STAT_EN			0x238
150 #define CQE_SEND_CNT			0x248
151 #define DLVRY_Q_0_BASE_ADDR_LO		0x260
152 #define DLVRY_Q_0_BASE_ADDR_HI		0x264
153 #define DLVRY_Q_0_DEPTH			0x268
154 #define DLVRY_Q_0_WR_PTR		0x26c
155 #define DLVRY_Q_0_RD_PTR		0x270
156 #define HYPER_STREAM_ID_EN_CFG		0xc80
157 #define OQ0_INT_SRC_MSK			0xc90
158 #define COMPL_Q_0_BASE_ADDR_LO		0x4e0
159 #define COMPL_Q_0_BASE_ADDR_HI		0x4e4
160 #define COMPL_Q_0_DEPTH			0x4e8
161 #define COMPL_Q_0_WR_PTR		0x4ec
162 #define COMPL_Q_0_RD_PTR		0x4f0
163 #define HGC_RXM_DFX_STATUS14		0xae8
164 #define HGC_RXM_DFX_STATUS14_MEM0_OFF	0
165 #define HGC_RXM_DFX_STATUS14_MEM0_MSK	(0x1ff << \
166 					 HGC_RXM_DFX_STATUS14_MEM0_OFF)
167 #define HGC_RXM_DFX_STATUS14_MEM1_OFF	9
168 #define HGC_RXM_DFX_STATUS14_MEM1_MSK	(0x1ff << \
169 					 HGC_RXM_DFX_STATUS14_MEM1_OFF)
170 #define HGC_RXM_DFX_STATUS14_MEM2_OFF	18
171 #define HGC_RXM_DFX_STATUS14_MEM2_MSK	(0x1ff << \
172 					 HGC_RXM_DFX_STATUS14_MEM2_OFF)
173 #define HGC_RXM_DFX_STATUS15		0xaec
174 #define HGC_RXM_DFX_STATUS15_MEM3_OFF	0
175 #define HGC_RXM_DFX_STATUS15_MEM3_MSK	(0x1ff << \
176 					 HGC_RXM_DFX_STATUS15_MEM3_OFF)
177 #define AWQOS_AWCACHE_CFG	0xc84
178 #define ARQOS_ARCACHE_CFG	0xc88
179 #define HILINK_ERR_DFX		0xe04
180 #define SAS_GPIO_CFG_0		0x1000
181 #define SAS_GPIO_CFG_1		0x1004
182 #define SAS_GPIO_TX_0_1	0x1040
183 #define SAS_CFG_DRIVE_VLD	0x1070
184 
185 /* phy registers requiring init */
186 #define PORT_BASE			(0x2000)
187 #define PHY_CFG				(PORT_BASE + 0x0)
188 #define HARD_PHY_LINKRATE		(PORT_BASE + 0x4)
189 #define PHY_CFG_ENA_OFF			0
190 #define PHY_CFG_ENA_MSK			(0x1 << PHY_CFG_ENA_OFF)
191 #define PHY_CFG_DC_OPT_OFF		2
192 #define PHY_CFG_DC_OPT_MSK		(0x1 << PHY_CFG_DC_OPT_OFF)
193 #define PHY_CFG_PHY_RST_OFF		3
194 #define PHY_CFG_PHY_RST_MSK		(0x1 << PHY_CFG_PHY_RST_OFF)
195 #define PROG_PHY_LINK_RATE		(PORT_BASE + 0x8)
196 #define CFG_PROG_PHY_LINK_RATE_OFF	0
197 #define CFG_PROG_PHY_LINK_RATE_MSK	(0xff << CFG_PROG_PHY_LINK_RATE_OFF)
198 #define CFG_PROG_OOB_PHY_LINK_RATE_OFF	8
199 #define CFG_PROG_OOB_PHY_LINK_RATE_MSK	(0xf << CFG_PROG_OOB_PHY_LINK_RATE_OFF)
200 #define PHY_CTRL			(PORT_BASE + 0x14)
201 #define PHY_CTRL_RESET_OFF		0
202 #define PHY_CTRL_RESET_MSK		(0x1 << PHY_CTRL_RESET_OFF)
203 #define CMD_HDR_PIR_OFF			8
204 #define CMD_HDR_PIR_MSK			(0x1 << CMD_HDR_PIR_OFF)
205 #define SERDES_CFG			(PORT_BASE + 0x1c)
206 #define CFG_ALOS_CHK_DISABLE_OFF	9
207 #define CFG_ALOS_CHK_DISABLE_MSK	(0x1 << CFG_ALOS_CHK_DISABLE_OFF)
208 #define SAS_PHY_BIST_CTRL		(PORT_BASE + 0x2c)
209 #define CFG_BIST_MODE_SEL_OFF		0
210 #define CFG_BIST_MODE_SEL_MSK		(0xf << CFG_BIST_MODE_SEL_OFF)
211 #define CFG_LOOP_TEST_MODE_OFF		14
212 #define CFG_LOOP_TEST_MODE_MSK		(0x3 << CFG_LOOP_TEST_MODE_OFF)
213 #define CFG_RX_BIST_EN_OFF		16
214 #define CFG_RX_BIST_EN_MSK		(0x1 << CFG_RX_BIST_EN_OFF)
215 #define CFG_TX_BIST_EN_OFF		17
216 #define CFG_TX_BIST_EN_MSK		(0x1 << CFG_TX_BIST_EN_OFF)
217 #define CFG_BIST_TEST_OFF		18
218 #define CFG_BIST_TEST_MSK		(0x1 << CFG_BIST_TEST_OFF)
219 #define SAS_PHY_BIST_CODE		(PORT_BASE + 0x30)
220 #define SAS_PHY_BIST_CODE1		(PORT_BASE + 0x34)
221 #define SAS_BIST_ERR_CNT		(PORT_BASE + 0x38)
222 #define SL_CFG				(PORT_BASE + 0x84)
223 #define AIP_LIMIT			(PORT_BASE + 0x90)
224 #define SL_CONTROL			(PORT_BASE + 0x94)
225 #define SL_CONTROL_NOTIFY_EN_OFF	0
226 #define SL_CONTROL_NOTIFY_EN_MSK	(0x1 << SL_CONTROL_NOTIFY_EN_OFF)
227 #define SL_CTA_OFF		17
228 #define SL_CTA_MSK		(0x1 << SL_CTA_OFF)
229 #define RX_PRIMS_STATUS			(PORT_BASE + 0x98)
230 #define RX_BCAST_CHG_OFF		1
231 #define RX_BCAST_CHG_MSK		(0x1 << RX_BCAST_CHG_OFF)
232 #define TX_ID_DWORD0			(PORT_BASE + 0x9c)
233 #define TX_ID_DWORD1			(PORT_BASE + 0xa0)
234 #define TX_ID_DWORD2			(PORT_BASE + 0xa4)
235 #define TX_ID_DWORD3			(PORT_BASE + 0xa8)
236 #define TX_ID_DWORD4			(PORT_BASE + 0xaC)
237 #define TX_ID_DWORD5			(PORT_BASE + 0xb0)
238 #define TX_ID_DWORD6			(PORT_BASE + 0xb4)
239 #define TXID_AUTO				(PORT_BASE + 0xb8)
240 #define CT3_OFF		1
241 #define CT3_MSK		(0x1 << CT3_OFF)
242 #define TX_HARDRST_OFF          2
243 #define TX_HARDRST_MSK          (0x1 << TX_HARDRST_OFF)
244 #define RX_IDAF_DWORD0			(PORT_BASE + 0xc4)
245 #define RXOP_CHECK_CFG_H		(PORT_BASE + 0xfc)
246 #define STP_LINK_TIMER			(PORT_BASE + 0x120)
247 #define STP_LINK_TIMEOUT_STATE		(PORT_BASE + 0x124)
248 #define CON_CFG_DRIVER			(PORT_BASE + 0x130)
249 #define SAS_SSP_CON_TIMER_CFG		(PORT_BASE + 0x134)
250 #define SAS_SMP_CON_TIMER_CFG		(PORT_BASE + 0x138)
251 #define SAS_STP_CON_TIMER_CFG		(PORT_BASE + 0x13c)
252 #define CHL_INT0			(PORT_BASE + 0x1b4)
253 #define CHL_INT0_HOTPLUG_TOUT_OFF	0
254 #define CHL_INT0_HOTPLUG_TOUT_MSK	(0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
255 #define CHL_INT0_SL_RX_BCST_ACK_OFF	1
256 #define CHL_INT0_SL_RX_BCST_ACK_MSK	(0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
257 #define CHL_INT0_SL_PHY_ENABLE_OFF	2
258 #define CHL_INT0_SL_PHY_ENABLE_MSK	(0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
259 #define CHL_INT0_NOT_RDY_OFF		4
260 #define CHL_INT0_NOT_RDY_MSK		(0x1 << CHL_INT0_NOT_RDY_OFF)
261 #define CHL_INT0_PHY_RDY_OFF		5
262 #define CHL_INT0_PHY_RDY_MSK		(0x1 << CHL_INT0_PHY_RDY_OFF)
263 #define CHL_INT1			(PORT_BASE + 0x1b8)
264 #define CHL_INT1_DMAC_TX_ECC_MB_ERR_OFF	15
265 #define CHL_INT1_DMAC_TX_ECC_1B_ERR_OFF	16
266 #define CHL_INT1_DMAC_RX_ECC_MB_ERR_OFF	17
267 #define CHL_INT1_DMAC_RX_ECC_1B_ERR_OFF	18
268 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF	19
269 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF	20
270 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF	21
271 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF	22
272 #define CHL_INT1_DMAC_TX_FIFO_ERR_OFF	23
273 #define CHL_INT1_DMAC_RX_FIFO_ERR_OFF	24
274 #define CHL_INT1_DMAC_TX_AXI_RUSER_ERR_OFF	26
275 #define CHL_INT1_DMAC_RX_AXI_RUSER_ERR_OFF	27
276 #define CHL_INT2			(PORT_BASE + 0x1bc)
277 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF	0
278 #define CHL_INT2_RX_DISP_ERR_OFF	28
279 #define CHL_INT2_RX_CODE_ERR_OFF	29
280 #define CHL_INT2_RX_INVLD_DW_OFF	30
281 #define CHL_INT2_STP_LINK_TIMEOUT_OFF	31
282 #define CHL_INT0_MSK			(PORT_BASE + 0x1c0)
283 #define CHL_INT1_MSK			(PORT_BASE + 0x1c4)
284 #define CHL_INT2_MSK			(PORT_BASE + 0x1c8)
285 #define SAS_EC_INT_COAL_TIME		(PORT_BASE + 0x1cc)
286 #define CHL_INT_COAL_EN			(PORT_BASE + 0x1d0)
287 #define SAS_RX_TRAIN_TIMER		(PORT_BASE + 0x2a4)
288 #define PHY_CTRL_RDY_MSK		(PORT_BASE + 0x2b0)
289 #define PHYCTRL_NOT_RDY_MSK		(PORT_BASE + 0x2b4)
290 #define PHYCTRL_DWS_RESET_MSK		(PORT_BASE + 0x2b8)
291 #define PHYCTRL_PHY_ENA_MSK		(PORT_BASE + 0x2bc)
292 #define SL_RX_BCAST_CHK_MSK		(PORT_BASE + 0x2c0)
293 #define PHYCTRL_OOB_RESTART_MSK		(PORT_BASE + 0x2c4)
294 #define DMA_TX_STATUS			(PORT_BASE + 0x2d0)
295 #define DMA_TX_STATUS_BUSY_OFF		0
296 #define DMA_TX_STATUS_BUSY_MSK		(0x1 << DMA_TX_STATUS_BUSY_OFF)
297 #define DMA_RX_STATUS			(PORT_BASE + 0x2e8)
298 #define DMA_RX_STATUS_BUSY_OFF		0
299 #define DMA_RX_STATUS_BUSY_MSK		(0x1 << DMA_RX_STATUS_BUSY_OFF)
300 
301 #define COARSETUNE_TIME			(PORT_BASE + 0x304)
302 #define TXDEEMPH_G1			(PORT_BASE + 0x350)
303 #define ERR_CNT_DWS_LOST		(PORT_BASE + 0x380)
304 #define ERR_CNT_RESET_PROB		(PORT_BASE + 0x384)
305 #define ERR_CNT_INVLD_DW		(PORT_BASE + 0x390)
306 #define ERR_CNT_CODE_ERR		(PORT_BASE + 0x394)
307 #define ERR_CNT_DISP_ERR		(PORT_BASE + 0x398)
308 #define DFX_FIFO_CTRL			(PORT_BASE + 0x3a0)
309 #define DFX_FIFO_CTRL_TRIGGER_MODE_OFF	0
310 #define DFX_FIFO_CTRL_TRIGGER_MODE_MSK	(0x7 << DFX_FIFO_CTRL_TRIGGER_MODE_OFF)
311 #define DFX_FIFO_CTRL_DUMP_MODE_OFF	3
312 #define DFX_FIFO_CTRL_DUMP_MODE_MSK	(0x7 << DFX_FIFO_CTRL_DUMP_MODE_OFF)
313 #define DFX_FIFO_CTRL_SIGNAL_SEL_OFF	6
314 #define DFX_FIFO_CTRL_SIGNAL_SEL_MSK	(0xF << DFX_FIFO_CTRL_SIGNAL_SEL_OFF)
315 #define DFX_FIFO_CTRL_DUMP_DISABLE_OFF	10
316 #define DFX_FIFO_CTRL_DUMP_DISABLE_MSK	(0x1 << DFX_FIFO_CTRL_DUMP_DISABLE_OFF)
317 #define DFX_FIFO_TRIGGER		(PORT_BASE + 0x3a4)
318 #define DFX_FIFO_TRIGGER_MSK		(PORT_BASE + 0x3a8)
319 #define DFX_FIFO_DUMP_MSK		(PORT_BASE + 0x3aC)
320 #define DFX_FIFO_RD_DATA		(PORT_BASE + 0x3b0)
321 
322 #define DEFAULT_ITCT_HW		2048 /* reset value, not reprogrammed */
323 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW)
324 #error Max ITCT exceeded
325 #endif
326 
327 #define AXI_MASTER_CFG_BASE		(0x5000)
328 #define AM_CTRL_GLOBAL			(0x0)
329 #define AM_CTRL_SHUTDOWN_REQ_OFF	0
330 #define AM_CTRL_SHUTDOWN_REQ_MSK	(0x1 << AM_CTRL_SHUTDOWN_REQ_OFF)
331 #define AM_CURR_TRANS_RETURN	(0x150)
332 
333 #define AM_CFG_MAX_TRANS		(0x5010)
334 #define AM_CFG_SINGLE_PORT_MAX_TRANS	(0x5014)
335 #define AXI_CFG					(0x5100)
336 #define AM_ROB_ECC_ERR_ADDR		(0x510c)
337 #define AM_ROB_ECC_ERR_ADDR_OFF	0
338 #define AM_ROB_ECC_ERR_ADDR_MSK	0xffffffff
339 
340 /* RAS registers need init */
341 #define RAS_BASE		(0x6000)
342 #define SAS_RAS_INTR0			(RAS_BASE)
343 #define SAS_RAS_INTR1			(RAS_BASE + 0x04)
344 #define SAS_RAS_INTR0_MASK		(RAS_BASE + 0x08)
345 #define SAS_RAS_INTR1_MASK		(RAS_BASE + 0x0c)
346 #define CFG_SAS_RAS_INTR_MASK		(RAS_BASE + 0x1c)
347 #define SAS_RAS_INTR2			(RAS_BASE + 0x20)
348 #define SAS_RAS_INTR2_MASK		(RAS_BASE + 0x24)
349 
350 /* HW dma structures */
351 /* Delivery queue header */
352 /* dw0 */
353 #define CMD_HDR_ABORT_FLAG_OFF		0
354 #define CMD_HDR_ABORT_FLAG_MSK		(0x3 << CMD_HDR_ABORT_FLAG_OFF)
355 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF	2
356 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK	(0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
357 #define CMD_HDR_RESP_REPORT_OFF		5
358 #define CMD_HDR_RESP_REPORT_MSK		(0x1 << CMD_HDR_RESP_REPORT_OFF)
359 #define CMD_HDR_TLR_CTRL_OFF		6
360 #define CMD_HDR_TLR_CTRL_MSK		(0x3 << CMD_HDR_TLR_CTRL_OFF)
361 #define CMD_HDR_PORT_OFF		18
362 #define CMD_HDR_PORT_MSK		(0xf << CMD_HDR_PORT_OFF)
363 #define CMD_HDR_PRIORITY_OFF		27
364 #define CMD_HDR_PRIORITY_MSK		(0x1 << CMD_HDR_PRIORITY_OFF)
365 #define CMD_HDR_CMD_OFF			29
366 #define CMD_HDR_CMD_MSK			(0x7 << CMD_HDR_CMD_OFF)
367 /* dw1 */
368 #define CMD_HDR_UNCON_CMD_OFF	3
369 #define CMD_HDR_DIR_OFF			5
370 #define CMD_HDR_DIR_MSK			(0x3 << CMD_HDR_DIR_OFF)
371 #define CMD_HDR_RESET_OFF		7
372 #define CMD_HDR_RESET_MSK		(0x1 << CMD_HDR_RESET_OFF)
373 #define CMD_HDR_VDTL_OFF		10
374 #define CMD_HDR_VDTL_MSK		(0x1 << CMD_HDR_VDTL_OFF)
375 #define CMD_HDR_FRAME_TYPE_OFF		11
376 #define CMD_HDR_FRAME_TYPE_MSK		(0x1f << CMD_HDR_FRAME_TYPE_OFF)
377 #define CMD_HDR_DEV_ID_OFF		16
378 #define CMD_HDR_DEV_ID_MSK		(0xffff << CMD_HDR_DEV_ID_OFF)
379 /* dw2 */
380 #define CMD_HDR_CFL_OFF			0
381 #define CMD_HDR_CFL_MSK			(0x1ff << CMD_HDR_CFL_OFF)
382 #define CMD_HDR_NCQ_TAG_OFF		10
383 #define CMD_HDR_NCQ_TAG_MSK		(0x1f << CMD_HDR_NCQ_TAG_OFF)
384 #define CMD_HDR_MRFL_OFF		15
385 #define CMD_HDR_MRFL_MSK		(0x1ff << CMD_HDR_MRFL_OFF)
386 #define CMD_HDR_SG_MOD_OFF		24
387 #define CMD_HDR_SG_MOD_MSK		(0x3 << CMD_HDR_SG_MOD_OFF)
388 /* dw3 */
389 #define CMD_HDR_IPTT_OFF		0
390 #define CMD_HDR_IPTT_MSK		(0xffff << CMD_HDR_IPTT_OFF)
391 /* dw6 */
392 #define CMD_HDR_DIF_SGL_LEN_OFF		0
393 #define CMD_HDR_DIF_SGL_LEN_MSK		(0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
394 #define CMD_HDR_DATA_SGL_LEN_OFF	16
395 #define CMD_HDR_DATA_SGL_LEN_MSK	(0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
396 /* dw7 */
397 #define CMD_HDR_ADDR_MODE_SEL_OFF		15
398 #define CMD_HDR_ADDR_MODE_SEL_MSK		(1 << CMD_HDR_ADDR_MODE_SEL_OFF)
399 #define CMD_HDR_ABORT_IPTT_OFF		16
400 #define CMD_HDR_ABORT_IPTT_MSK		(0xffff << CMD_HDR_ABORT_IPTT_OFF)
401 
402 /* Completion header */
403 /* dw0 */
404 #define CMPLT_HDR_CMPLT_OFF		0
405 #define CMPLT_HDR_CMPLT_MSK		(0x3 << CMPLT_HDR_CMPLT_OFF)
406 #define CMPLT_HDR_ERROR_PHASE_OFF   2
407 #define CMPLT_HDR_ERROR_PHASE_MSK   (0xff << CMPLT_HDR_ERROR_PHASE_OFF)
408 /* bit[9:2] Error Phase */
409 #define ERR_PHASE_RESPONSE_FRAME_REV_STAGE_OFF	\
410 					8
411 #define ERR_PHASE_RESPONSE_FRAME_REV_STAGE_MSK	\
412 	(0x1 << ERR_PHASE_RESPONSE_FRAME_REV_STAGE_OFF)
413 #define CMPLT_HDR_RSPNS_XFRD_OFF	10
414 #define CMPLT_HDR_RSPNS_XFRD_MSK	(0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
415 #define CMPLT_HDR_RSPNS_GOOD_OFF	11
416 #define CMPLT_HDR_RSPNS_GOOD_MSK	(0x1 << CMPLT_HDR_RSPNS_GOOD_OFF)
417 #define CMPLT_HDR_ERX_OFF		12
418 #define CMPLT_HDR_ERX_MSK		(0x1 << CMPLT_HDR_ERX_OFF)
419 #define CMPLT_HDR_ABORT_STAT_OFF	13
420 #define CMPLT_HDR_ABORT_STAT_MSK	(0x7 << CMPLT_HDR_ABORT_STAT_OFF)
421 /* abort_stat */
422 #define STAT_IO_NOT_VALID		0x1
423 #define STAT_IO_NO_DEVICE		0x2
424 #define STAT_IO_COMPLETE		0x3
425 #define STAT_IO_ABORTED			0x4
426 /* dw1 */
427 #define CMPLT_HDR_IPTT_OFF		0
428 #define CMPLT_HDR_IPTT_MSK		(0xffff << CMPLT_HDR_IPTT_OFF)
429 #define CMPLT_HDR_DEV_ID_OFF		16
430 #define CMPLT_HDR_DEV_ID_MSK		(0xffff << CMPLT_HDR_DEV_ID_OFF)
431 /* dw3 */
432 #define SATA_DISK_IN_ERROR_STATUS_OFF	8
433 #define SATA_DISK_IN_ERROR_STATUS_MSK	(0x1 << SATA_DISK_IN_ERROR_STATUS_OFF)
434 #define CMPLT_HDR_SATA_DISK_ERR_OFF	16
435 #define CMPLT_HDR_SATA_DISK_ERR_MSK	(0x1 << CMPLT_HDR_SATA_DISK_ERR_OFF)
436 #define CMPLT_HDR_IO_IN_TARGET_OFF	17
437 #define CMPLT_HDR_IO_IN_TARGET_MSK	(0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
438 /* bit[23:18] ERR_FIS_ATA_STATUS */
439 #define FIS_ATA_STATUS_ERR_OFF		18
440 #define FIS_ATA_STATUS_ERR_MSK		(0x1 << FIS_ATA_STATUS_ERR_OFF)
441 #define FIS_TYPE_SDB_OFF		31
442 #define FIS_TYPE_SDB_MSK		(0x1 << FIS_TYPE_SDB_OFF)
443 
444 /* ITCT header */
445 /* qw0 */
446 #define ITCT_HDR_DEV_TYPE_OFF		0
447 #define ITCT_HDR_DEV_TYPE_MSK		(0x3 << ITCT_HDR_DEV_TYPE_OFF)
448 #define ITCT_HDR_VALID_OFF		2
449 #define ITCT_HDR_VALID_MSK		(0x1 << ITCT_HDR_VALID_OFF)
450 #define ITCT_HDR_MCR_OFF		5
451 #define ITCT_HDR_MCR_MSK		(0xf << ITCT_HDR_MCR_OFF)
452 #define ITCT_HDR_VLN_OFF		9
453 #define ITCT_HDR_VLN_MSK		(0xf << ITCT_HDR_VLN_OFF)
454 #define ITCT_HDR_SMP_TIMEOUT_OFF	16
455 #define ITCT_HDR_AWT_CONTINUE_OFF	25
456 #define ITCT_HDR_PORT_ID_OFF		28
457 #define ITCT_HDR_PORT_ID_MSK		(0xf << ITCT_HDR_PORT_ID_OFF)
458 /* qw2 */
459 #define ITCT_HDR_INLT_OFF		0
460 #define ITCT_HDR_INLT_MSK		(0xffffULL << ITCT_HDR_INLT_OFF)
461 #define ITCT_HDR_RTOLT_OFF		48
462 #define ITCT_HDR_RTOLT_MSK		(0xffffULL << ITCT_HDR_RTOLT_OFF)
463 
464 struct hisi_sas_protect_iu_v3_hw {
465 	u32 dw0;
466 	u32 lbrtcv;
467 	u32 lbrtgv;
468 	u32 dw3;
469 	u32 dw4;
470 	u32 dw5;
471 	u32 rsv;
472 };
473 
474 struct hisi_sas_complete_v3_hdr {
475 	__le32 dw0;
476 	__le32 dw1;
477 	__le32 act;
478 	__le32 dw3;
479 };
480 
481 struct hisi_sas_err_record_v3 {
482 	/* dw0 */
483 	__le32 trans_tx_fail_type;
484 
485 	/* dw1 */
486 	__le32 trans_rx_fail_type;
487 
488 	/* dw2 */
489 	__le16 dma_tx_err_type;
490 	__le16 sipc_rx_err_type;
491 
492 	/* dw3 */
493 	__le32 dma_rx_err_type;
494 };
495 
496 #define RX_DATA_LEN_UNDERFLOW_OFF	6
497 #define RX_DATA_LEN_UNDERFLOW_MSK	(1 << RX_DATA_LEN_UNDERFLOW_OFF)
498 
499 #define RX_FIS_STATUS_ERR_OFF		0
500 #define RX_FIS_STATUS_ERR_MSK		(1 << RX_FIS_STATUS_ERR_OFF)
501 
502 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
503 #define HISI_SAS_MSI_COUNT_V3_HW 32
504 
505 #define DIR_NO_DATA 0
506 #define DIR_TO_INI 1
507 #define DIR_TO_DEVICE 2
508 #define DIR_RESERVED 3
509 
510 #define FIS_CMD_IS_UNCONSTRAINED(fis) \
511 	((fis.command == ATA_CMD_READ_LOG_EXT) || \
512 	(fis.command == ATA_CMD_READ_LOG_DMA_EXT) || \
513 	((fis.command == ATA_CMD_DEV_RESET) && \
514 	((fis.control & ATA_SRST) != 0)))
515 
516 #define T10_INSRT_EN_OFF    0
517 #define T10_INSRT_EN_MSK    (1 << T10_INSRT_EN_OFF)
518 #define T10_RMV_EN_OFF	    1
519 #define T10_RMV_EN_MSK	    (1 << T10_RMV_EN_OFF)
520 #define T10_RPLC_EN_OFF	    2
521 #define T10_RPLC_EN_MSK	    (1 << T10_RPLC_EN_OFF)
522 #define T10_CHK_EN_OFF	    3
523 #define T10_CHK_EN_MSK	    (1 << T10_CHK_EN_OFF)
524 #define INCR_LBRT_OFF	    5
525 #define INCR_LBRT_MSK	    (1 << INCR_LBRT_OFF)
526 #define USR_DATA_BLOCK_SZ_OFF	20
527 #define USR_DATA_BLOCK_SZ_MSK	(0x3 << USR_DATA_BLOCK_SZ_OFF)
528 #define T10_CHK_MSK_OFF	    16
529 #define T10_CHK_REF_TAG_MSK (0xf0 << T10_CHK_MSK_OFF)
530 #define T10_CHK_APP_TAG_MSK (0xc << T10_CHK_MSK_OFF)
531 
532 #define BASE_VECTORS_V3_HW  16
533 #define MIN_AFFINE_VECTORS_V3_HW  (BASE_VECTORS_V3_HW + 1)
534 
535 #define CHNL_INT_STS_MSK	0xeeeeeeee
536 #define CHNL_INT_STS_PHY_MSK	0xe
537 #define CHNL_INT_STS_INT0_MSK BIT(1)
538 #define CHNL_INT_STS_INT1_MSK BIT(2)
539 #define CHNL_INT_STS_INT2_MSK BIT(3)
540 #define CHNL_WIDTH 4
541 
542 #define BAR_NO_V3_HW	5
543 
544 enum {
545 	DSM_FUNC_ERR_HANDLE_MSI = 0,
546 };
547 
548 static bool hisi_sas_intr_conv;
549 MODULE_PARM_DESC(intr_conv, "interrupt converge enable (0-1)");
550 
551 /* permit overriding the host protection capabilities mask (EEDP/T10 PI) */
552 static int prot_mask;
553 module_param(prot_mask, int, 0444);
554 MODULE_PARM_DESC(prot_mask, " host protection capabilities mask, def=0x0 ");
555 
556 /* the index of iopoll queues are bigger than interrupt queues' */
557 static int experimental_iopoll_q_cnt;
558 module_param(experimental_iopoll_q_cnt, int, 0444);
559 MODULE_PARM_DESC(experimental_iopoll_q_cnt, "number of queues to be used as poll mode, def=0");
560 
561 static void debugfs_work_handler_v3_hw(struct work_struct *work);
562 static void debugfs_snapshot_regs_v3_hw(struct hisi_hba *hisi_hba);
563 
564 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
565 {
566 	void __iomem *regs = hisi_hba->regs + off;
567 
568 	return readl(regs);
569 }
570 
571 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
572 {
573 	void __iomem *regs = hisi_hba->regs + off;
574 
575 	writel(val, regs);
576 }
577 
578 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
579 				 u32 off, u32 val)
580 {
581 	void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
582 
583 	writel(val, regs);
584 }
585 
586 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
587 				      int phy_no, u32 off)
588 {
589 	void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
590 
591 	return readl(regs);
592 }
593 
594 #define hisi_sas_read32_poll_timeout(off, val, cond, delay_us,		\
595 				     timeout_us)			\
596 ({									\
597 	void __iomem *regs = hisi_hba->regs + off;			\
598 	readl_poll_timeout(regs, val, cond, delay_us, timeout_us);	\
599 })
600 
601 #define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us,	\
602 					    timeout_us)			\
603 ({									\
604 	void __iomem *regs = hisi_hba->regs + off;			\
605 	readl_poll_timeout_atomic(regs, val, cond, delay_us, timeout_us);\
606 })
607 
608 static void interrupt_enable_v3_hw(struct hisi_hba *hisi_hba)
609 {
610 	int i;
611 
612 	for (i = 0; i < hisi_hba->queue_count; i++)
613 		hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0);
614 
615 	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe);
616 	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe);
617 	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffc220ff);
618 	hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x155555);
619 
620 	for (i = 0; i < hisi_hba->n_phy; i++) {
621 		hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xf2057fff);
622 		hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe);
623 		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
624 		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
625 		hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
626 	}
627 }
628 
629 static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
630 {
631 	struct pci_dev *pdev = hisi_hba->pci_dev;
632 	int i, j;
633 
634 	/* Global registers init */
635 	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
636 			 (u32)((1ULL << hisi_hba->queue_count) - 1));
637 	hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400);
638 	/* time / CLK_AHB = 2.5s / 2ns = 0x4A817C80 */
639 	hisi_sas_write32(hisi_hba, TRANS_LOCK_ICT_TIME, 0x4A817C80);
640 	hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
641 	hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
642 	hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
643 	hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
644 	hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
645 	hisi_sas_write32(hisi_hba, CQ_INT_CONVERGE_EN,
646 			 hisi_sas_intr_conv);
647 	hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff);
648 	hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
649 	hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
650 	hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
651 	hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0);
652 	hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0);
653 	hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0);
654 	hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0);
655 	hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0);
656 	hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
657 
658 	if (pdev->revision < 0x30)
659 		hisi_sas_write32(hisi_hba, SAS_AXI_USER3, 0);
660 
661 	interrupt_enable_v3_hw(hisi_hba);
662 	for (i = 0; i < hisi_hba->n_phy; i++) {
663 		enum sas_linkrate max;
664 		struct hisi_sas_phy *phy = &hisi_hba->phy[i];
665 		struct asd_sas_phy *sas_phy = &phy->sas_phy;
666 		u32 prog_phy_link_rate = hisi_sas_phy_read32(hisi_hba, i,
667 							   PROG_PHY_LINK_RATE);
668 
669 		prog_phy_link_rate &= ~CFG_PROG_PHY_LINK_RATE_MSK;
670 		if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate <
671 				SAS_LINK_RATE_1_5_GBPS))
672 			max = SAS_LINK_RATE_12_0_GBPS;
673 		else
674 			max = sas_phy->phy->maximum_linkrate;
675 		prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
676 		hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE,
677 			prog_phy_link_rate);
678 		hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80);
679 		hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
680 		hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
681 		hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
682 		hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
683 		hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
684 		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
685 		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1);
686 		hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120);
687 		hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x2a0a01);
688 		hisi_sas_phy_write32(hisi_hba, i, SAS_EC_INT_COAL_TIME,
689 				     0x30f4240);
690 		hisi_sas_phy_write32(hisi_hba, i, AIP_LIMIT, 0x2ffff);
691 
692 		/* set value through firmware for 920B and later version */
693 		if (pdev->revision < 0x30) {
694 			hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG, 0x32);
695 			hisi_sas_phy_write32(hisi_hba, i, SERDES_CFG, 0xffc00);
696 			/* used for 12G negotiate */
697 			hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e);
698 		}
699 
700 		/* get default FFE configuration for BIST */
701 		for (j = 0; j < FFE_CFG_MAX; j++) {
702 			u32 val = hisi_sas_phy_read32(hisi_hba, i,
703 						      TXDEEMPH_G1 + (j * 0x4));
704 			hisi_hba->debugfs_bist_ffe[i][j] = val;
705 		}
706 	}
707 
708 	for (i = 0; i < hisi_hba->queue_count; i++) {
709 		/* Delivery queue */
710 		hisi_sas_write32(hisi_hba,
711 				 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
712 				 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
713 
714 		hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
715 				 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
716 
717 		hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
718 				 HISI_SAS_QUEUE_SLOTS);
719 
720 		/* Completion queue */
721 		hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
722 				 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
723 
724 		hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
725 				 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
726 
727 		hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
728 				 HISI_SAS_QUEUE_SLOTS);
729 	}
730 
731 	/* itct */
732 	hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
733 			 lower_32_bits(hisi_hba->itct_dma));
734 
735 	hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
736 			 upper_32_bits(hisi_hba->itct_dma));
737 
738 	/* iost */
739 	hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
740 			 lower_32_bits(hisi_hba->iost_dma));
741 
742 	hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
743 			 upper_32_bits(hisi_hba->iost_dma));
744 
745 	/* breakpoint */
746 	hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
747 			 lower_32_bits(hisi_hba->breakpoint_dma));
748 
749 	hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
750 			 upper_32_bits(hisi_hba->breakpoint_dma));
751 
752 	/* SATA broken msg */
753 	hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
754 			 lower_32_bits(hisi_hba->sata_breakpoint_dma));
755 
756 	hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
757 			 upper_32_bits(hisi_hba->sata_breakpoint_dma));
758 
759 	/* SATA initial fis */
760 	hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
761 			 lower_32_bits(hisi_hba->initial_fis_dma));
762 
763 	hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
764 			 upper_32_bits(hisi_hba->initial_fis_dma));
765 
766 	/* RAS registers init */
767 	hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0);
768 	hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0);
769 	hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, 0x0);
770 	hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, 0x0);
771 
772 	/* LED registers init */
773 	hisi_sas_write32(hisi_hba, SAS_CFG_DRIVE_VLD, 0x80000ff);
774 	hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1, 0x80808080);
775 	hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1 + 0x4, 0x80808080);
776 	/* Configure blink generator rate A to 1Hz and B to 4Hz */
777 	hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_1, 0x121700);
778 	hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_0, 0x800000);
779 }
780 
781 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
782 {
783 	u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
784 
785 	cfg &= ~PHY_CFG_DC_OPT_MSK;
786 	cfg |= 1 << PHY_CFG_DC_OPT_OFF;
787 	hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
788 }
789 
790 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
791 {
792 	struct sas_identify_frame identify_frame;
793 	u32 *identify_buffer;
794 
795 	memset(&identify_frame, 0, sizeof(identify_frame));
796 	identify_frame.dev_type = SAS_END_DEVICE;
797 	identify_frame.frame_type = 0;
798 	identify_frame._un1 = 1;
799 	identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
800 	identify_frame.target_bits = SAS_PROTOCOL_NONE;
801 	memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
802 	memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr,	SAS_ADDR_SIZE);
803 	identify_frame.phy_id = phy_no;
804 	identify_buffer = (u32 *)(&identify_frame);
805 
806 	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
807 			__swab32(identify_buffer[0]));
808 	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
809 			__swab32(identify_buffer[1]));
810 	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
811 			__swab32(identify_buffer[2]));
812 	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
813 			__swab32(identify_buffer[3]));
814 	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
815 			__swab32(identify_buffer[4]));
816 	hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
817 			__swab32(identify_buffer[5]));
818 }
819 
820 static void setup_itct_v3_hw(struct hisi_hba *hisi_hba,
821 			     struct hisi_sas_device *sas_dev)
822 {
823 	struct domain_device *device = sas_dev->sas_device;
824 	struct device *dev = hisi_hba->dev;
825 	u64 qw0, device_id = sas_dev->device_id;
826 	struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
827 	struct domain_device *parent_dev = device->parent;
828 	struct asd_sas_port *sas_port = device->port;
829 	struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
830 	u64 sas_addr;
831 
832 	memset(itct, 0, sizeof(*itct));
833 
834 	/* qw0 */
835 	qw0 = 0;
836 	switch (sas_dev->dev_type) {
837 	case SAS_END_DEVICE:
838 	case SAS_EDGE_EXPANDER_DEVICE:
839 	case SAS_FANOUT_EXPANDER_DEVICE:
840 		qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
841 		break;
842 	case SAS_SATA_DEV:
843 	case SAS_SATA_PENDING:
844 		if (parent_dev && dev_is_expander(parent_dev->dev_type))
845 			qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
846 		else
847 			qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
848 		break;
849 	default:
850 		dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
851 			 sas_dev->dev_type);
852 	}
853 
854 	qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
855 		(device->linkrate << ITCT_HDR_MCR_OFF) |
856 		(1 << ITCT_HDR_VLN_OFF) |
857 		(0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) |
858 		(1 << ITCT_HDR_AWT_CONTINUE_OFF) |
859 		(port->id << ITCT_HDR_PORT_ID_OFF));
860 	itct->qw0 = cpu_to_le64(qw0);
861 
862 	/* qw1 */
863 	memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE);
864 	itct->sas_addr = cpu_to_le64(__swab64(sas_addr));
865 
866 	/* qw2 */
867 	if (!dev_is_sata(device))
868 		itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
869 					(0x1ULL << ITCT_HDR_RTOLT_OFF));
870 }
871 
872 static int clear_itct_v3_hw(struct hisi_hba *hisi_hba,
873 			    struct hisi_sas_device *sas_dev)
874 {
875 	DECLARE_COMPLETION_ONSTACK(completion);
876 	u64 dev_id = sas_dev->device_id;
877 	struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
878 	u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
879 	struct device *dev = hisi_hba->dev;
880 
881 	sas_dev->completion = &completion;
882 
883 	/* clear the itct interrupt state */
884 	if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
885 		hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
886 				 ENT_INT_SRC3_ITC_INT_MSK);
887 
888 	/* clear the itct table */
889 	reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
890 	hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
891 
892 	if (!wait_for_completion_timeout(sas_dev->completion,
893 					 HISI_SAS_CLEAR_ITCT_TIMEOUT)) {
894 		dev_warn(dev, "failed to clear ITCT\n");
895 		return -ETIMEDOUT;
896 	}
897 
898 	memset(itct, 0, sizeof(struct hisi_sas_itct));
899 	return 0;
900 }
901 
902 static void dereg_device_v3_hw(struct hisi_hba *hisi_hba,
903 				struct domain_device *device)
904 {
905 	struct hisi_sas_slot *slot, *slot2;
906 	struct hisi_sas_device *sas_dev = device->lldd_dev;
907 	u32 cfg_abt_set_query_iptt;
908 
909 	cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba,
910 		CFG_ABT_SET_QUERY_IPTT);
911 	spin_lock(&sas_dev->lock);
912 	list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) {
913 		cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK;
914 		cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) |
915 			(slot->idx << CFG_SET_ABORTED_IPTT_OFF);
916 		hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
917 			cfg_abt_set_query_iptt);
918 	}
919 	spin_unlock(&sas_dev->lock);
920 	cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF);
921 	hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
922 		cfg_abt_set_query_iptt);
923 	hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE,
924 					1 << CFG_ABT_SET_IPTT_DONE_OFF);
925 }
926 
927 static int reset_hw_v3_hw(struct hisi_hba *hisi_hba)
928 {
929 	struct device *dev = hisi_hba->dev;
930 	int ret;
931 	u32 val;
932 
933 	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
934 
935 	/* Disable all of the PHYs */
936 	hisi_sas_stop_phys(hisi_hba);
937 	udelay(50);
938 
939 	/* Ensure axi bus idle */
940 	ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val,
941 					   20000, 1000000);
942 	if (ret) {
943 		dev_err(dev, "axi bus is not idle, ret = %d!\n", ret);
944 		return -EIO;
945 	}
946 
947 	if (ACPI_HANDLE(dev)) {
948 		acpi_status s;
949 
950 		s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
951 		if (ACPI_FAILURE(s)) {
952 			dev_err(dev, "Reset failed\n");
953 			return -EIO;
954 		}
955 	} else {
956 		dev_err(dev, "no reset method!\n");
957 		return -EINVAL;
958 	}
959 
960 	return 0;
961 }
962 
963 static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
964 {
965 	struct device *dev = hisi_hba->dev;
966 	struct acpi_device *acpi_dev;
967 	union acpi_object *obj;
968 	guid_t guid;
969 	int rc;
970 
971 	rc = reset_hw_v3_hw(hisi_hba);
972 	if (rc) {
973 		dev_err(dev, "hisi_sas_reset_hw failed, rc=%d\n", rc);
974 		return rc;
975 	}
976 
977 	msleep(100);
978 	init_reg_v3_hw(hisi_hba);
979 
980 	if (guid_parse("D5918B4B-37AE-4E10-A99F-E5E8A6EF4C1F", &guid)) {
981 		dev_err(dev, "Parse GUID failed\n");
982 		return -EINVAL;
983 	}
984 
985 	/*
986 	 * This DSM handles some hardware-related configurations:
987 	 * 1. Switch over to MSI error handling in kernel
988 	 * 2. BIOS *may* reset some register values through this method
989 	 */
990 	obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &guid, 0,
991 				DSM_FUNC_ERR_HANDLE_MSI, NULL);
992 	if (!obj)
993 		dev_warn(dev, "can not find DSM method, ignore\n");
994 	else
995 		ACPI_FREE(obj);
996 
997 	acpi_dev = ACPI_COMPANION(dev);
998 	if (!acpi_device_power_manageable(acpi_dev))
999 		dev_notice(dev, "neither _PS0 nor _PR0 is defined\n");
1000 	return 0;
1001 }
1002 
1003 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1004 {
1005 	u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1006 
1007 	cfg |= PHY_CFG_ENA_MSK;
1008 	cfg &= ~PHY_CFG_PHY_RST_MSK;
1009 	hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1010 }
1011 
1012 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1013 {
1014 	u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1015 	u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK);
1016 	static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) |
1017 			       BIT(CHL_INT2_RX_CODE_ERR_OFF) |
1018 			       BIT(CHL_INT2_RX_INVLD_DW_OFF);
1019 	u32 state;
1020 
1021 	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, msk | irq_msk);
1022 
1023 	cfg &= ~PHY_CFG_ENA_MSK;
1024 	hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1025 
1026 	mdelay(50);
1027 
1028 	state = hisi_sas_read32(hisi_hba, PHY_STATE);
1029 	if (state & BIT(phy_no)) {
1030 		cfg |= PHY_CFG_PHY_RST_MSK;
1031 		hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
1032 	}
1033 
1034 	udelay(1);
1035 
1036 	hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
1037 	hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
1038 	hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR);
1039 
1040 	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, msk);
1041 	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, irq_msk);
1042 }
1043 
1044 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1045 {
1046 	config_id_frame_v3_hw(hisi_hba, phy_no);
1047 	config_phy_opt_mode_v3_hw(hisi_hba, phy_no);
1048 	enable_phy_v3_hw(hisi_hba, phy_no);
1049 }
1050 
1051 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1052 {
1053 	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1054 	u32 txid_auto;
1055 
1056 	hisi_sas_phy_enable(hisi_hba, phy_no, 0);
1057 	if (phy->identify.device_type == SAS_END_DEVICE) {
1058 		txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1059 		hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1060 					txid_auto | TX_HARDRST_MSK);
1061 	}
1062 	msleep(100);
1063 	hisi_sas_phy_enable(hisi_hba, phy_no, 1);
1064 }
1065 
1066 static enum sas_linkrate phy_get_max_linkrate_v3_hw(void)
1067 {
1068 	return SAS_LINK_RATE_12_0_GBPS;
1069 }
1070 
1071 static void phys_init_v3_hw(struct hisi_hba *hisi_hba)
1072 {
1073 	int i;
1074 
1075 	for (i = 0; i < hisi_hba->n_phy; i++) {
1076 		struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1077 		struct asd_sas_phy *sas_phy = &phy->sas_phy;
1078 
1079 		if (!sas_phy->phy->enabled)
1080 			continue;
1081 
1082 		hisi_sas_phy_enable(hisi_hba, i, 1);
1083 	}
1084 }
1085 
1086 static void sl_notify_ssp_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1087 {
1088 	u32 sl_control;
1089 
1090 	sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1091 	sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
1092 	hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1093 	msleep(1);
1094 	sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1095 	sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
1096 	hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
1097 }
1098 
1099 static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id)
1100 {
1101 	int i, bitmap = 0;
1102 	u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1103 	u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1104 
1105 	for (i = 0; i < hisi_hba->n_phy; i++)
1106 		if (phy_state & BIT(i))
1107 			if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
1108 				bitmap |= BIT(i);
1109 
1110 	return bitmap;
1111 }
1112 
1113 static void start_delivery_v3_hw(struct hisi_sas_dq *dq)
1114 {
1115 	struct hisi_hba *hisi_hba = dq->hisi_hba;
1116 	struct hisi_sas_slot *s, *s1, *s2 = NULL;
1117 	int dlvry_queue = dq->id;
1118 	int wp;
1119 
1120 	list_for_each_entry_safe(s, s1, &dq->list, delivery) {
1121 		if (!s->ready)
1122 			break;
1123 		s2 = s;
1124 		list_del(&s->delivery);
1125 	}
1126 
1127 	if (!s2)
1128 		return;
1129 
1130 	/*
1131 	 * Ensure that memories for slots built on other CPUs is observed.
1132 	 */
1133 	smp_rmb();
1134 	wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS;
1135 
1136 	hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp);
1137 }
1138 
1139 static void prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba,
1140 			      struct hisi_sas_slot *slot,
1141 			      struct hisi_sas_cmd_hdr *hdr,
1142 			      struct scatterlist *scatter,
1143 			      int n_elem)
1144 {
1145 	struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
1146 	struct scatterlist *sg;
1147 	int i;
1148 
1149 	for_each_sg(scatter, sg, n_elem, i) {
1150 		struct hisi_sas_sge *entry = &sge_page->sge[i];
1151 
1152 		entry->addr = cpu_to_le64(sg_dma_address(sg));
1153 		entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
1154 		entry->data_len = cpu_to_le32(sg_dma_len(sg));
1155 		entry->data_off = 0;
1156 	}
1157 
1158 	hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
1159 
1160 	hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
1161 }
1162 
1163 static void prep_prd_sge_dif_v3_hw(struct hisi_hba *hisi_hba,
1164 				   struct hisi_sas_slot *slot,
1165 				   struct hisi_sas_cmd_hdr *hdr,
1166 				   struct scatterlist *scatter,
1167 				   int n_elem)
1168 {
1169 	struct hisi_sas_sge_dif_page *sge_dif_page;
1170 	struct scatterlist *sg;
1171 	int i;
1172 
1173 	sge_dif_page = hisi_sas_sge_dif_addr_mem(slot);
1174 
1175 	for_each_sg(scatter, sg, n_elem, i) {
1176 		struct hisi_sas_sge *entry = &sge_dif_page->sge[i];
1177 
1178 		entry->addr = cpu_to_le64(sg_dma_address(sg));
1179 		entry->page_ctrl_0 = 0;
1180 		entry->page_ctrl_1 = 0;
1181 		entry->data_len = cpu_to_le32(sg_dma_len(sg));
1182 		entry->data_off = 0;
1183 	}
1184 
1185 	hdr->dif_prd_table_addr =
1186 		cpu_to_le64(hisi_sas_sge_dif_addr_dma(slot));
1187 
1188 	hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DIF_SGL_LEN_OFF);
1189 }
1190 
1191 static u32 get_prot_chk_msk_v3_hw(struct scsi_cmnd *scsi_cmnd)
1192 {
1193 	unsigned char prot_flags = scsi_cmnd->prot_flags;
1194 
1195 	if (prot_flags & SCSI_PROT_REF_CHECK)
1196 		return T10_CHK_APP_TAG_MSK;
1197 	return T10_CHK_REF_TAG_MSK | T10_CHK_APP_TAG_MSK;
1198 }
1199 
1200 static void fill_prot_v3_hw(struct scsi_cmnd *scsi_cmnd,
1201 			    struct hisi_sas_protect_iu_v3_hw *prot)
1202 {
1203 	unsigned char prot_op = scsi_get_prot_op(scsi_cmnd);
1204 	unsigned int interval = scsi_prot_interval(scsi_cmnd);
1205 	u32 lbrt_chk_val = t10_pi_ref_tag(scsi_cmd_to_rq(scsi_cmnd));
1206 
1207 	switch (prot_op) {
1208 	case SCSI_PROT_READ_INSERT:
1209 		prot->dw0 |= T10_INSRT_EN_MSK;
1210 		prot->lbrtgv = lbrt_chk_val;
1211 		break;
1212 	case SCSI_PROT_READ_STRIP:
1213 		prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK);
1214 		prot->lbrtcv = lbrt_chk_val;
1215 		prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
1216 		break;
1217 	case SCSI_PROT_READ_PASS:
1218 		prot->dw0 |= T10_CHK_EN_MSK;
1219 		prot->lbrtcv = lbrt_chk_val;
1220 		prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
1221 		break;
1222 	case SCSI_PROT_WRITE_INSERT:
1223 		prot->dw0 |= T10_INSRT_EN_MSK;
1224 		prot->lbrtgv = lbrt_chk_val;
1225 		break;
1226 	case SCSI_PROT_WRITE_STRIP:
1227 		prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK);
1228 		prot->lbrtcv = lbrt_chk_val;
1229 		break;
1230 	case SCSI_PROT_WRITE_PASS:
1231 		prot->dw0 |= T10_CHK_EN_MSK;
1232 		prot->lbrtcv = lbrt_chk_val;
1233 		prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd);
1234 		break;
1235 	default:
1236 		WARN(1, "prot_op(0x%x) is not valid\n", prot_op);
1237 		break;
1238 	}
1239 
1240 	switch (interval) {
1241 	case 512:
1242 		break;
1243 	case 4096:
1244 		prot->dw0 |= (0x1 << USR_DATA_BLOCK_SZ_OFF);
1245 		break;
1246 	case 520:
1247 		prot->dw0 |= (0x2 << USR_DATA_BLOCK_SZ_OFF);
1248 		break;
1249 	default:
1250 		WARN(1, "protection interval (0x%x) invalid\n",
1251 		     interval);
1252 		break;
1253 	}
1254 
1255 	prot->dw0 |= INCR_LBRT_MSK;
1256 }
1257 
1258 static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
1259 			  struct hisi_sas_slot *slot)
1260 {
1261 	struct sas_task *task = slot->task;
1262 	struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1263 	struct domain_device *device = task->dev;
1264 	struct hisi_sas_device *sas_dev = device->lldd_dev;
1265 	struct hisi_sas_port *port = slot->port;
1266 	struct sas_ssp_task *ssp_task = &task->ssp_task;
1267 	struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
1268 	struct sas_tmf_task *tmf = slot->tmf;
1269 	int has_data = 0, priority = !!tmf;
1270 	unsigned char prot_op;
1271 	u8 *buf_cmd;
1272 	u32 dw1 = 0, dw2 = 0, len = 0;
1273 
1274 	hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
1275 			       (2 << CMD_HDR_TLR_CTRL_OFF) |
1276 			       (port->id << CMD_HDR_PORT_OFF) |
1277 			       (priority << CMD_HDR_PRIORITY_OFF) |
1278 			       (1 << CMD_HDR_CMD_OFF)); /* ssp */
1279 
1280 	dw1 = 1 << CMD_HDR_VDTL_OFF;
1281 	if (tmf) {
1282 		dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
1283 		dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
1284 	} else {
1285 		prot_op = scsi_get_prot_op(scsi_cmnd);
1286 		dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
1287 		switch (scsi_cmnd->sc_data_direction) {
1288 		case DMA_TO_DEVICE:
1289 			has_data = 1;
1290 			dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1291 			break;
1292 		case DMA_FROM_DEVICE:
1293 			has_data = 1;
1294 			dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1295 			break;
1296 		default:
1297 			dw1 &= ~CMD_HDR_DIR_MSK;
1298 		}
1299 	}
1300 
1301 	/* map itct entry */
1302 	dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1303 
1304 	dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
1305 	      + 3) / 4) << CMD_HDR_CFL_OFF) |
1306 	      ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
1307 	      (2 << CMD_HDR_SG_MOD_OFF);
1308 	hdr->dw2 = cpu_to_le32(dw2);
1309 	hdr->transfer_tags = cpu_to_le32(slot->idx);
1310 
1311 	if (has_data) {
1312 		prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
1313 				   slot->n_elem);
1314 
1315 		if (scsi_prot_sg_count(scsi_cmnd))
1316 			prep_prd_sge_dif_v3_hw(hisi_hba, slot, hdr,
1317 					       scsi_prot_sglist(scsi_cmnd),
1318 					       slot->n_elem_dif);
1319 	}
1320 
1321 	hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1322 	hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1323 
1324 	buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
1325 		sizeof(struct ssp_frame_hdr);
1326 
1327 	memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1328 	if (!tmf) {
1329 		buf_cmd[9] = ssp_task->task_attr;
1330 		memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len);
1331 	} else {
1332 		buf_cmd[10] = tmf->tmf;
1333 		switch (tmf->tmf) {
1334 		case TMF_ABORT_TASK:
1335 		case TMF_QUERY_TASK:
1336 			buf_cmd[12] =
1337 				(tmf->tag_of_task_to_be_managed >> 8) & 0xff;
1338 			buf_cmd[13] =
1339 				tmf->tag_of_task_to_be_managed & 0xff;
1340 			break;
1341 		default:
1342 			break;
1343 		}
1344 	}
1345 
1346 	if (has_data && (prot_op != SCSI_PROT_NORMAL)) {
1347 		struct hisi_sas_protect_iu_v3_hw prot;
1348 		u8 *buf_cmd_prot;
1349 
1350 		hdr->dw7 |= cpu_to_le32(1 << CMD_HDR_ADDR_MODE_SEL_OFF);
1351 		dw1 |= CMD_HDR_PIR_MSK;
1352 		buf_cmd_prot = hisi_sas_cmd_hdr_addr_mem(slot) +
1353 			       sizeof(struct ssp_frame_hdr) +
1354 			       sizeof(struct ssp_command_iu);
1355 
1356 		memset(&prot, 0, sizeof(struct hisi_sas_protect_iu_v3_hw));
1357 		fill_prot_v3_hw(scsi_cmnd, &prot);
1358 		memcpy(buf_cmd_prot, &prot,
1359 		       sizeof(struct hisi_sas_protect_iu_v3_hw));
1360 		/*
1361 		 * For READ, we need length of info read to memory, while for
1362 		 * WRITE we need length of data written to the disk.
1363 		 */
1364 		if (prot_op == SCSI_PROT_WRITE_INSERT ||
1365 		    prot_op == SCSI_PROT_READ_INSERT ||
1366 		    prot_op == SCSI_PROT_WRITE_PASS ||
1367 		    prot_op == SCSI_PROT_READ_PASS) {
1368 			unsigned int interval = scsi_prot_interval(scsi_cmnd);
1369 			unsigned int ilog2_interval = ilog2(interval);
1370 
1371 			len = (task->total_xfer_len >> ilog2_interval) * 8;
1372 		}
1373 	}
1374 
1375 	hdr->dw1 = cpu_to_le32(dw1);
1376 
1377 	hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len + len);
1378 }
1379 
1380 static void prep_smp_v3_hw(struct hisi_hba *hisi_hba,
1381 			  struct hisi_sas_slot *slot)
1382 {
1383 	struct sas_task *task = slot->task;
1384 	struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1385 	struct domain_device *device = task->dev;
1386 	struct hisi_sas_port *port = slot->port;
1387 	struct scatterlist *sg_req;
1388 	struct hisi_sas_device *sas_dev = device->lldd_dev;
1389 	dma_addr_t req_dma_addr;
1390 	unsigned int req_len;
1391 
1392 	/* req */
1393 	sg_req = &task->smp_task.smp_req;
1394 	req_len = sg_dma_len(sg_req);
1395 	req_dma_addr = sg_dma_address(sg_req);
1396 
1397 	/* create header */
1398 	/* dw0 */
1399 	hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
1400 			       (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
1401 			       (2 << CMD_HDR_CMD_OFF)); /* smp */
1402 
1403 	/* map itct entry */
1404 	hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
1405 			       (1 << CMD_HDR_FRAME_TYPE_OFF) |
1406 			       (DIR_NO_DATA << CMD_HDR_DIR_OFF));
1407 
1408 	/* dw2 */
1409 	hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
1410 			       (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
1411 			       CMD_HDR_MRFL_OFF));
1412 
1413 	hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
1414 
1415 	hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
1416 	hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1417 }
1418 
1419 static void prep_ata_v3_hw(struct hisi_hba *hisi_hba,
1420 			  struct hisi_sas_slot *slot)
1421 {
1422 	struct sas_task *task = slot->task;
1423 	struct domain_device *device = task->dev;
1424 	struct domain_device *parent_dev = device->parent;
1425 	struct hisi_sas_device *sas_dev = device->lldd_dev;
1426 	struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1427 	struct asd_sas_port *sas_port = device->port;
1428 	struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
1429 	u8 *buf_cmd;
1430 	int has_data = 0, hdr_tag = 0;
1431 	u32 dw1 = 0, dw2 = 0;
1432 
1433 	hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
1434 	if (parent_dev && dev_is_expander(parent_dev->dev_type))
1435 		hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
1436 	else
1437 		hdr->dw0 |= cpu_to_le32(4U << CMD_HDR_CMD_OFF);
1438 
1439 	switch (task->data_dir) {
1440 	case DMA_TO_DEVICE:
1441 		has_data = 1;
1442 		dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1443 		break;
1444 	case DMA_FROM_DEVICE:
1445 		has_data = 1;
1446 		dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1447 		break;
1448 	default:
1449 		dw1 &= ~CMD_HDR_DIR_MSK;
1450 	}
1451 
1452 	if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
1453 			(task->ata_task.fis.control & ATA_SRST))
1454 		dw1 |= 1 << CMD_HDR_RESET_OFF;
1455 
1456 	dw1 |= (hisi_sas_get_ata_protocol(
1457 		&task->ata_task.fis, task->data_dir))
1458 		<< CMD_HDR_FRAME_TYPE_OFF;
1459 	dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1460 
1461 	if (FIS_CMD_IS_UNCONSTRAINED(task->ata_task.fis))
1462 		dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF;
1463 
1464 	hdr->dw1 = cpu_to_le32(dw1);
1465 
1466 	/* dw2 */
1467 	if (task->ata_task.use_ncq) {
1468 		struct ata_queued_cmd *qc = task->uldd_task;
1469 
1470 		hdr_tag = qc->tag;
1471 		task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
1472 		dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
1473 	}
1474 
1475 	dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
1476 			2 << CMD_HDR_SG_MOD_OFF;
1477 	hdr->dw2 = cpu_to_le32(dw2);
1478 
1479 	/* dw3 */
1480 	hdr->transfer_tags = cpu_to_le32(slot->idx);
1481 
1482 	if (has_data)
1483 		prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
1484 					slot->n_elem);
1485 
1486 	hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1487 	hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1488 	hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1489 
1490 	buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
1491 
1492 	if (likely(!task->ata_task.device_control_reg_update))
1493 		task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
1494 	/* fill in command FIS */
1495 	memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
1496 }
1497 
1498 static void prep_abort_v3_hw(struct hisi_hba *hisi_hba,
1499 			     struct hisi_sas_slot *slot)
1500 {
1501 	struct sas_task *task = slot->task;
1502 	struct sas_internal_abort_task *abort = &task->abort_task;
1503 	struct domain_device *dev = task->dev;
1504 	struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1505 	struct hisi_sas_port *port = slot->port;
1506 	struct hisi_sas_device *sas_dev = dev->lldd_dev;
1507 	bool sata = dev_is_sata(dev);
1508 
1509 	/* dw0 */
1510 	hdr->dw0 = cpu_to_le32((5U << CMD_HDR_CMD_OFF) | /* abort */
1511 			       (port->id << CMD_HDR_PORT_OFF) |
1512 				(sata << CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
1513 				(abort->type << CMD_HDR_ABORT_FLAG_OFF));
1514 
1515 	/* dw1 */
1516 	hdr->dw1 = cpu_to_le32(sas_dev->device_id
1517 			<< CMD_HDR_DEV_ID_OFF);
1518 
1519 	/* dw7 */
1520 	hdr->dw7 = cpu_to_le32(abort->tag << CMD_HDR_ABORT_IPTT_OFF);
1521 	hdr->transfer_tags = cpu_to_le32(slot->idx);
1522 }
1523 
1524 static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1525 {
1526 	int i;
1527 	irqreturn_t res;
1528 	u32 context, port_id, link_rate;
1529 	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1530 	struct asd_sas_phy *sas_phy = &phy->sas_phy;
1531 	struct device *dev = hisi_hba->dev;
1532 
1533 	hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
1534 
1535 	port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1536 	port_id = (port_id >> (4 * phy_no)) & 0xf;
1537 	link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1538 	link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1539 
1540 	if (port_id == 0xf) {
1541 		dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1542 		res = IRQ_NONE;
1543 		goto end;
1544 	}
1545 	sas_phy->linkrate = link_rate;
1546 	phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1547 
1548 	/* Check for SATA dev */
1549 	context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1550 	if (context & (1 << phy_no)) {
1551 		struct hisi_sas_initial_fis *initial_fis;
1552 		struct dev_to_host_fis *fis;
1553 		u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
1554 		struct Scsi_Host *shost = hisi_hba->shost;
1555 
1556 		dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate);
1557 		initial_fis = &hisi_hba->initial_fis[phy_no];
1558 		fis = &initial_fis->fis;
1559 
1560 		/* check ERR bit of Status Register */
1561 		if (fis->status & ATA_ERR) {
1562 			dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n",
1563 				 phy_no, fis->status);
1564 			hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1565 			res = IRQ_NONE;
1566 			goto end;
1567 		}
1568 
1569 		sas_phy->oob_mode = SATA_OOB_MODE;
1570 		attached_sas_addr[0] = 0x50;
1571 		attached_sas_addr[6] = shost->host_no;
1572 		attached_sas_addr[7] = phy_no;
1573 		memcpy(sas_phy->attached_sas_addr,
1574 		       attached_sas_addr,
1575 		       SAS_ADDR_SIZE);
1576 		memcpy(sas_phy->frame_rcvd, fis,
1577 		       sizeof(struct dev_to_host_fis));
1578 		phy->phy_type |= PORT_TYPE_SATA;
1579 		phy->identify.device_type = SAS_SATA_DEV;
1580 		phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
1581 		phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
1582 	} else {
1583 		u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1584 		struct sas_identify_frame *id =
1585 			(struct sas_identify_frame *)frame_rcvd;
1586 
1587 		dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1588 		for (i = 0; i < 6; i++) {
1589 			u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1590 					       RX_IDAF_DWORD0 + (i * 4));
1591 			frame_rcvd[i] = __swab32(idaf);
1592 		}
1593 		sas_phy->oob_mode = SAS_OOB_MODE;
1594 		memcpy(sas_phy->attached_sas_addr,
1595 		       &id->sas_addr,
1596 		       SAS_ADDR_SIZE);
1597 		phy->phy_type |= PORT_TYPE_SAS;
1598 		phy->identify.device_type = id->dev_type;
1599 		phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
1600 		if (phy->identify.device_type == SAS_END_DEVICE)
1601 			phy->identify.target_port_protocols =
1602 				SAS_PROTOCOL_SSP;
1603 		else if (phy->identify.device_type != SAS_PHY_UNUSED)
1604 			phy->identify.target_port_protocols =
1605 				SAS_PROTOCOL_SMP;
1606 	}
1607 
1608 	phy->port_id = port_id;
1609 	spin_lock(&phy->lock);
1610 	/* Delete timer and set phy_attached atomically */
1611 	del_timer(&phy->timer);
1612 	phy->phy_attached = 1;
1613 	spin_unlock(&phy->lock);
1614 
1615 	/*
1616 	 * Call pm_runtime_get_noresume() which pairs with
1617 	 * hisi_sas_phyup_pm_work() -> pm_runtime_put_sync().
1618 	 * For failure call pm_runtime_put() as we are in a hardirq context.
1619 	 */
1620 	pm_runtime_get_noresume(dev);
1621 	res = hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP_PM);
1622 	if (!res)
1623 		pm_runtime_put(dev);
1624 
1625 	res = IRQ_HANDLED;
1626 
1627 end:
1628 	if (phy->reset_completion)
1629 		complete(phy->reset_completion);
1630 	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1631 			     CHL_INT0_SL_PHY_ENABLE_MSK);
1632 	hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
1633 
1634 	return res;
1635 }
1636 
1637 static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1638 {
1639 	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1640 	u32 phy_state, sl_ctrl, txid_auto;
1641 	struct device *dev = hisi_hba->dev;
1642 
1643 	atomic_inc(&phy->down_cnt);
1644 
1645 	del_timer(&phy->timer);
1646 	hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
1647 
1648 	phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1649 	dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
1650 	hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0,
1651 			  GFP_ATOMIC);
1652 
1653 	sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1654 	hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
1655 						sl_ctrl&(~SL_CTA_MSK));
1656 
1657 	txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1658 	hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1659 						txid_auto | CT3_MSK);
1660 
1661 	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
1662 	hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
1663 
1664 	return IRQ_HANDLED;
1665 }
1666 
1667 static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1668 {
1669 	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1670 	u32 bcast_status;
1671 
1672 	hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
1673 	bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS);
1674 	if (bcast_status & RX_BCAST_CHG_MSK)
1675 		hisi_sas_phy_bcast(phy);
1676 	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1677 			     CHL_INT0_SL_RX_BCST_ACK_MSK);
1678 	hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
1679 
1680 	return IRQ_HANDLED;
1681 }
1682 
1683 static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p)
1684 {
1685 	struct hisi_hba *hisi_hba = p;
1686 	u32 irq_msk;
1687 	int phy_no = 0;
1688 	irqreturn_t res = IRQ_NONE;
1689 
1690 	irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1691 				& 0x11111111;
1692 	while (irq_msk) {
1693 		if (irq_msk  & 1) {
1694 			u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1695 							    CHL_INT0);
1696 			u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1697 			int rdy = phy_state & (1 << phy_no);
1698 
1699 			if (rdy) {
1700 				if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
1701 					/* phy up */
1702 					if (phy_up_v3_hw(phy_no, hisi_hba)
1703 							== IRQ_HANDLED)
1704 						res = IRQ_HANDLED;
1705 				if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK)
1706 					/* phy bcast */
1707 					if (phy_bcast_v3_hw(phy_no, hisi_hba)
1708 							== IRQ_HANDLED)
1709 						res = IRQ_HANDLED;
1710 			} else {
1711 				if (irq_value & CHL_INT0_NOT_RDY_MSK)
1712 					/* phy down */
1713 					if (phy_down_v3_hw(phy_no, hisi_hba)
1714 							== IRQ_HANDLED)
1715 						res = IRQ_HANDLED;
1716 			}
1717 		}
1718 		irq_msk >>= 4;
1719 		phy_no++;
1720 	}
1721 
1722 	return res;
1723 }
1724 
1725 static const struct hisi_sas_hw_error port_axi_error[] = {
1726 	{
1727 		.irq_msk = BIT(CHL_INT1_DMAC_TX_ECC_MB_ERR_OFF),
1728 		.msg = "dmac_tx_ecc_bad_err",
1729 	},
1730 	{
1731 		.irq_msk = BIT(CHL_INT1_DMAC_RX_ECC_MB_ERR_OFF),
1732 		.msg = "dmac_rx_ecc_bad_err",
1733 	},
1734 	{
1735 		.irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF),
1736 		.msg = "dma_tx_axi_wr_err",
1737 	},
1738 	{
1739 		.irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF),
1740 		.msg = "dma_tx_axi_rd_err",
1741 	},
1742 	{
1743 		.irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF),
1744 		.msg = "dma_rx_axi_wr_err",
1745 	},
1746 	{
1747 		.irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF),
1748 		.msg = "dma_rx_axi_rd_err",
1749 	},
1750 	{
1751 		.irq_msk = BIT(CHL_INT1_DMAC_TX_FIFO_ERR_OFF),
1752 		.msg = "dma_tx_fifo_err",
1753 	},
1754 	{
1755 		.irq_msk = BIT(CHL_INT1_DMAC_RX_FIFO_ERR_OFF),
1756 		.msg = "dma_rx_fifo_err",
1757 	},
1758 	{
1759 		.irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RUSER_ERR_OFF),
1760 		.msg = "dma_tx_axi_ruser_err",
1761 	},
1762 	{
1763 		.irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RUSER_ERR_OFF),
1764 		.msg = "dma_rx_axi_ruser_err",
1765 	},
1766 };
1767 
1768 static void handle_chl_int1_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1769 {
1770 	u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1);
1771 	u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1_MSK);
1772 	struct device *dev = hisi_hba->dev;
1773 	int i;
1774 
1775 	irq_value &= ~irq_msk;
1776 	if (!irq_value) {
1777 		dev_warn(dev, "phy%d channel int 1 received with status bits cleared\n",
1778 			 phy_no);
1779 		return;
1780 	}
1781 
1782 	for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) {
1783 		const struct hisi_sas_hw_error *error = &port_axi_error[i];
1784 
1785 		if (!(irq_value & error->irq_msk))
1786 			continue;
1787 
1788 		dev_err(dev, "%s error (phy%d 0x%x) found!\n",
1789 			error->msg, phy_no, irq_value);
1790 		queue_work(hisi_hba->wq, &hisi_hba->rst_work);
1791 	}
1792 
1793 	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT1, irq_value);
1794 }
1795 
1796 static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1797 {
1798 	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1799 	struct asd_sas_phy *sas_phy = &phy->sas_phy;
1800 	struct sas_phy *sphy = sas_phy->phy;
1801 	unsigned long flags;
1802 	u32 reg_value;
1803 
1804 	spin_lock_irqsave(&phy->lock, flags);
1805 
1806 	/* loss dword sync */
1807 	reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST);
1808 	sphy->loss_of_dword_sync_count += reg_value;
1809 
1810 	/* phy reset problem */
1811 	reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB);
1812 	sphy->phy_reset_problem_count += reg_value;
1813 
1814 	/* invalid dword */
1815 	reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW);
1816 	sphy->invalid_dword_count += reg_value;
1817 
1818 	/* disparity err */
1819 	reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR);
1820 	sphy->running_disparity_error_count += reg_value;
1821 
1822 	/* code violation error */
1823 	reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR);
1824 	phy->code_violation_err_count += reg_value;
1825 
1826 	spin_unlock_irqrestore(&phy->lock, flags);
1827 }
1828 
1829 static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1830 {
1831 	u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK);
1832 	u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2);
1833 	struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1834 	struct pci_dev *pci_dev = hisi_hba->pci_dev;
1835 	struct device *dev = hisi_hba->dev;
1836 	static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) |
1837 			BIT(CHL_INT2_RX_CODE_ERR_OFF) |
1838 			BIT(CHL_INT2_RX_INVLD_DW_OFF);
1839 
1840 	irq_value &= ~irq_msk;
1841 	if (!irq_value) {
1842 		dev_warn(dev, "phy%d channel int 2 received with status bits cleared\n",
1843 			 phy_no);
1844 		return;
1845 	}
1846 
1847 	if (irq_value & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) {
1848 		dev_warn(dev, "phy%d identify timeout\n", phy_no);
1849 		hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1850 	}
1851 
1852 	if (irq_value & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) {
1853 		u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1854 				STP_LINK_TIMEOUT_STATE);
1855 
1856 		dev_warn(dev, "phy%d stp link timeout (0x%x)\n",
1857 			 phy_no, reg_value);
1858 		if (reg_value & BIT(4))
1859 			hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1860 	}
1861 
1862 	if (pci_dev->revision > 0x20 && (irq_value & msk)) {
1863 		struct asd_sas_phy *sas_phy = &phy->sas_phy;
1864 		struct sas_phy *sphy = sas_phy->phy;
1865 
1866 		phy_get_events_v3_hw(hisi_hba, phy_no);
1867 
1868 		if (irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF))
1869 			dev_info(dev, "phy%d invalid dword cnt:   %u\n", phy_no,
1870 				 sphy->invalid_dword_count);
1871 
1872 		if (irq_value & BIT(CHL_INT2_RX_CODE_ERR_OFF))
1873 			dev_info(dev, "phy%d code violation cnt:  %u\n", phy_no,
1874 				 phy->code_violation_err_count);
1875 
1876 		if (irq_value & BIT(CHL_INT2_RX_DISP_ERR_OFF))
1877 			dev_info(dev, "phy%d disparity error cnt: %u\n", phy_no,
1878 				 sphy->running_disparity_error_count);
1879 	}
1880 
1881 	if ((irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) &&
1882 	    (pci_dev->revision == 0x20)) {
1883 		u32 reg_value;
1884 		int rc;
1885 
1886 		rc = hisi_sas_read32_poll_timeout_atomic(
1887 				HILINK_ERR_DFX, reg_value,
1888 				!((reg_value >> 8) & BIT(phy_no)),
1889 				1000, 10000);
1890 		if (rc)
1891 			hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1892 	}
1893 
1894 	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value);
1895 }
1896 
1897 static void handle_chl_int0_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
1898 {
1899 	u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0);
1900 
1901 	if (irq_value0 & CHL_INT0_PHY_RDY_MSK)
1902 		hisi_sas_phy_oob_ready(hisi_hba, phy_no);
1903 
1904 	hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1905 			     irq_value0 & (~CHL_INT0_SL_RX_BCST_ACK_MSK)
1906 			     & (~CHL_INT0_SL_PHY_ENABLE_MSK)
1907 			     & (~CHL_INT0_NOT_RDY_MSK));
1908 }
1909 
1910 static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
1911 {
1912 	struct hisi_hba *hisi_hba = p;
1913 	u32 irq_msk;
1914 	int phy_no = 0;
1915 
1916 	irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1917 		  & CHNL_INT_STS_MSK;
1918 
1919 	while (irq_msk) {
1920 		if (irq_msk & (CHNL_INT_STS_INT0_MSK << (phy_no * CHNL_WIDTH)))
1921 			handle_chl_int0_v3_hw(hisi_hba, phy_no);
1922 
1923 		if (irq_msk & (CHNL_INT_STS_INT1_MSK << (phy_no * CHNL_WIDTH)))
1924 			handle_chl_int1_v3_hw(hisi_hba, phy_no);
1925 
1926 		if (irq_msk & (CHNL_INT_STS_INT2_MSK << (phy_no * CHNL_WIDTH)))
1927 			handle_chl_int2_v3_hw(hisi_hba, phy_no);
1928 
1929 		irq_msk &= ~(CHNL_INT_STS_PHY_MSK << (phy_no * CHNL_WIDTH));
1930 		phy_no++;
1931 	}
1932 
1933 	return IRQ_HANDLED;
1934 }
1935 
1936 static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = {
1937 	{
1938 		.irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF),
1939 		.msk = HGC_DQE_ECC_MB_ADDR_MSK,
1940 		.shift = HGC_DQE_ECC_MB_ADDR_OFF,
1941 		.msg = "hgc_dqe_eccbad_intr",
1942 		.reg = HGC_DQE_ECC_ADDR,
1943 	},
1944 	{
1945 		.irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF),
1946 		.msk = HGC_IOST_ECC_MB_ADDR_MSK,
1947 		.shift = HGC_IOST_ECC_MB_ADDR_OFF,
1948 		.msg = "hgc_iost_eccbad_intr",
1949 		.reg = HGC_IOST_ECC_ADDR,
1950 	},
1951 	{
1952 		.irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF),
1953 		.msk = HGC_ITCT_ECC_MB_ADDR_MSK,
1954 		.shift = HGC_ITCT_ECC_MB_ADDR_OFF,
1955 		.msg = "hgc_itct_eccbad_intr",
1956 		.reg = HGC_ITCT_ECC_ADDR,
1957 	},
1958 	{
1959 		.irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF),
1960 		.msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK,
1961 		.shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF,
1962 		.msg = "hgc_iostl_eccbad_intr",
1963 		.reg = HGC_LM_DFX_STATUS2,
1964 	},
1965 	{
1966 		.irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF),
1967 		.msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK,
1968 		.shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF,
1969 		.msg = "hgc_itctl_eccbad_intr",
1970 		.reg = HGC_LM_DFX_STATUS2,
1971 	},
1972 	{
1973 		.irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF),
1974 		.msk = HGC_CQE_ECC_MB_ADDR_MSK,
1975 		.shift = HGC_CQE_ECC_MB_ADDR_OFF,
1976 		.msg = "hgc_cqe_eccbad_intr",
1977 		.reg = HGC_CQE_ECC_ADDR,
1978 	},
1979 	{
1980 		.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF),
1981 		.msk = HGC_RXM_DFX_STATUS14_MEM0_MSK,
1982 		.shift = HGC_RXM_DFX_STATUS14_MEM0_OFF,
1983 		.msg = "rxm_mem0_eccbad_intr",
1984 		.reg = HGC_RXM_DFX_STATUS14,
1985 	},
1986 	{
1987 		.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF),
1988 		.msk = HGC_RXM_DFX_STATUS14_MEM1_MSK,
1989 		.shift = HGC_RXM_DFX_STATUS14_MEM1_OFF,
1990 		.msg = "rxm_mem1_eccbad_intr",
1991 		.reg = HGC_RXM_DFX_STATUS14,
1992 	},
1993 	{
1994 		.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF),
1995 		.msk = HGC_RXM_DFX_STATUS14_MEM2_MSK,
1996 		.shift = HGC_RXM_DFX_STATUS14_MEM2_OFF,
1997 		.msg = "rxm_mem2_eccbad_intr",
1998 		.reg = HGC_RXM_DFX_STATUS14,
1999 	},
2000 	{
2001 		.irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF),
2002 		.msk = HGC_RXM_DFX_STATUS15_MEM3_MSK,
2003 		.shift = HGC_RXM_DFX_STATUS15_MEM3_OFF,
2004 		.msg = "rxm_mem3_eccbad_intr",
2005 		.reg = HGC_RXM_DFX_STATUS15,
2006 	},
2007 	{
2008 		.irq_msk = BIT(SAS_ECC_INTR_OOO_RAM_ECC_MB_OFF),
2009 		.msk = AM_ROB_ECC_ERR_ADDR_MSK,
2010 		.shift = AM_ROB_ECC_ERR_ADDR_OFF,
2011 		.msg = "ooo_ram_eccbad_intr",
2012 		.reg = AM_ROB_ECC_ERR_ADDR,
2013 	},
2014 };
2015 
2016 static void multi_bit_ecc_error_process_v3_hw(struct hisi_hba *hisi_hba,
2017 					      u32 irq_value)
2018 {
2019 	struct device *dev = hisi_hba->dev;
2020 	const struct hisi_sas_hw_error *ecc_error;
2021 	u32 val;
2022 	int i;
2023 
2024 	for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) {
2025 		ecc_error = &multi_bit_ecc_errors[i];
2026 		if (irq_value & ecc_error->irq_msk) {
2027 			val = hisi_sas_read32(hisi_hba, ecc_error->reg);
2028 			val &= ecc_error->msk;
2029 			val >>= ecc_error->shift;
2030 			dev_err(dev, "%s (0x%x) found: mem addr is 0x%08X\n",
2031 				ecc_error->msg, irq_value, val);
2032 			queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2033 		}
2034 	}
2035 }
2036 
2037 static void fatal_ecc_int_v3_hw(struct hisi_hba *hisi_hba)
2038 {
2039 	u32 irq_value, irq_msk;
2040 
2041 	irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK);
2042 	hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
2043 
2044 	irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
2045 	if (irq_value)
2046 		multi_bit_ecc_error_process_v3_hw(hisi_hba, irq_value);
2047 
2048 	hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value);
2049 	hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk);
2050 }
2051 
2052 static const struct hisi_sas_hw_error axi_error[] = {
2053 	{ .msk = BIT(0), .msg = "IOST_AXI_W_ERR" },
2054 	{ .msk = BIT(1), .msg = "IOST_AXI_R_ERR" },
2055 	{ .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" },
2056 	{ .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" },
2057 	{ .msk = BIT(4), .msg = "SATA_AXI_W_ERR" },
2058 	{ .msk = BIT(5), .msg = "SATA_AXI_R_ERR" },
2059 	{ .msk = BIT(6), .msg = "DQE_AXI_R_ERR" },
2060 	{ .msk = BIT(7), .msg = "CQE_AXI_W_ERR" },
2061 	{}
2062 };
2063 
2064 static const struct hisi_sas_hw_error fifo_error[] = {
2065 	{ .msk = BIT(8),  .msg = "CQE_WINFO_FIFO" },
2066 	{ .msk = BIT(9),  .msg = "CQE_MSG_FIFIO" },
2067 	{ .msk = BIT(10), .msg = "GETDQE_FIFO" },
2068 	{ .msk = BIT(11), .msg = "CMDP_FIFO" },
2069 	{ .msk = BIT(12), .msg = "AWTCTRL_FIFO" },
2070 	{}
2071 };
2072 
2073 static const struct hisi_sas_hw_error fatal_axi_error[] = {
2074 	{
2075 		.irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF),
2076 		.msg = "write pointer and depth",
2077 	},
2078 	{
2079 		.irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF),
2080 		.msg = "iptt no match slot",
2081 	},
2082 	{
2083 		.irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF),
2084 		.msg = "read pointer and depth",
2085 	},
2086 	{
2087 		.irq_msk = BIT(ENT_INT_SRC3_AXI_OFF),
2088 		.reg = HGC_AXI_FIFO_ERR_INFO,
2089 		.sub = axi_error,
2090 	},
2091 	{
2092 		.irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF),
2093 		.reg = HGC_AXI_FIFO_ERR_INFO,
2094 		.sub = fifo_error,
2095 	},
2096 	{
2097 		.irq_msk = BIT(ENT_INT_SRC3_LM_OFF),
2098 		.msg = "LM add/fetch list",
2099 	},
2100 	{
2101 		.irq_msk = BIT(ENT_INT_SRC3_ABT_OFF),
2102 		.msg = "SAS_HGC_ABT fetch LM list",
2103 	},
2104 	{
2105 		.irq_msk = BIT(ENT_INT_SRC3_DQE_POISON_OFF),
2106 		.msg = "read dqe poison",
2107 	},
2108 	{
2109 		.irq_msk = BIT(ENT_INT_SRC3_IOST_POISON_OFF),
2110 		.msg = "read iost poison",
2111 	},
2112 	{
2113 		.irq_msk = BIT(ENT_INT_SRC3_ITCT_POISON_OFF),
2114 		.msg = "read itct poison",
2115 	},
2116 	{
2117 		.irq_msk = BIT(ENT_INT_SRC3_ITCT_NCQ_POISON_OFF),
2118 		.msg = "read itct ncq poison",
2119 	},
2120 
2121 };
2122 
2123 static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p)
2124 {
2125 	u32 irq_value, irq_msk;
2126 	struct hisi_hba *hisi_hba = p;
2127 	struct device *dev = hisi_hba->dev;
2128 	struct pci_dev *pdev = hisi_hba->pci_dev;
2129 	int i;
2130 
2131 	irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
2132 	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00);
2133 
2134 	irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
2135 	irq_value &= ~irq_msk;
2136 
2137 	for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) {
2138 		const struct hisi_sas_hw_error *error = &fatal_axi_error[i];
2139 
2140 		if (!(irq_value & error->irq_msk))
2141 			continue;
2142 
2143 		if (error->sub) {
2144 			const struct hisi_sas_hw_error *sub = error->sub;
2145 			u32 err_value = hisi_sas_read32(hisi_hba, error->reg);
2146 
2147 			for (; sub->msk || sub->msg; sub++) {
2148 				if (!(err_value & sub->msk))
2149 					continue;
2150 
2151 				dev_err(dev, "%s error (0x%x) found!\n",
2152 					sub->msg, irq_value);
2153 				queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2154 			}
2155 		} else {
2156 			dev_err(dev, "%s error (0x%x) found!\n",
2157 				error->msg, irq_value);
2158 			queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2159 		}
2160 
2161 		if (pdev->revision < 0x21) {
2162 			u32 reg_val;
2163 
2164 			reg_val = hisi_sas_read32(hisi_hba,
2165 						  AXI_MASTER_CFG_BASE +
2166 						  AM_CTRL_GLOBAL);
2167 			reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK;
2168 			hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
2169 					 AM_CTRL_GLOBAL, reg_val);
2170 		}
2171 	}
2172 
2173 	fatal_ecc_int_v3_hw(hisi_hba);
2174 
2175 	if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) {
2176 		u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
2177 		u32 dev_id = reg_val & ITCT_DEV_MSK;
2178 		struct hisi_sas_device *sas_dev =
2179 				&hisi_hba->devices[dev_id];
2180 
2181 		hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
2182 		dev_dbg(dev, "clear ITCT ok\n");
2183 		complete(sas_dev->completion);
2184 	}
2185 
2186 	hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00);
2187 	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk);
2188 
2189 	return IRQ_HANDLED;
2190 }
2191 
2192 static bool is_ncq_err_v3_hw(struct hisi_sas_complete_v3_hdr *complete_hdr)
2193 {
2194 	u32 dw0, dw3;
2195 
2196 	dw0 = le32_to_cpu(complete_hdr->dw0);
2197 	dw3 = le32_to_cpu(complete_hdr->dw3);
2198 
2199 	return (dw0 & ERR_PHASE_RESPONSE_FRAME_REV_STAGE_MSK) &&
2200 	       (dw3 & FIS_TYPE_SDB_MSK) &&
2201 	       (dw3 & FIS_ATA_STATUS_ERR_MSK);
2202 }
2203 
2204 static bool
2205 slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
2206 	       struct hisi_sas_slot *slot)
2207 {
2208 	struct task_status_struct *ts = &task->task_status;
2209 	struct hisi_sas_complete_v3_hdr *complete_queue =
2210 			hisi_hba->complete_hdr[slot->cmplt_queue];
2211 	struct hisi_sas_complete_v3_hdr *complete_hdr =
2212 			&complete_queue[slot->cmplt_queue_slot];
2213 	struct hisi_sas_err_record_v3 *record =
2214 			hisi_sas_status_buf_addr_mem(slot);
2215 	u32 dma_rx_err_type = le32_to_cpu(record->dma_rx_err_type);
2216 	u32 trans_tx_fail_type = le32_to_cpu(record->trans_tx_fail_type);
2217 	u16 sipc_rx_err_type = le16_to_cpu(record->sipc_rx_err_type);
2218 	u32 dw3 = le32_to_cpu(complete_hdr->dw3);
2219 	u32 dw0 = le32_to_cpu(complete_hdr->dw0);
2220 
2221 	switch (task->task_proto) {
2222 	case SAS_PROTOCOL_SSP:
2223 		if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
2224 			/*
2225 			 * If returned response frame is incorrect because of data underflow,
2226 			 * but I/O information has been written to the host memory, we examine
2227 			 * response IU.
2228 			 */
2229 			if (!(dw0 & CMPLT_HDR_RSPNS_GOOD_MSK) &&
2230 			    (dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))
2231 				return false;
2232 
2233 			ts->residual = trans_tx_fail_type;
2234 			ts->stat = SAS_DATA_UNDERRUN;
2235 		} else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
2236 			ts->stat = SAS_QUEUE_FULL;
2237 			slot->abort = 1;
2238 		} else {
2239 			ts->stat = SAS_OPEN_REJECT;
2240 			ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2241 		}
2242 		break;
2243 	case SAS_PROTOCOL_SATA:
2244 	case SAS_PROTOCOL_STP:
2245 	case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2246 		if ((dw0 & CMPLT_HDR_RSPNS_XFRD_MSK) &&
2247 		    (sipc_rx_err_type & RX_FIS_STATUS_ERR_MSK)) {
2248 			if (task->ata_task.use_ncq) {
2249 				struct domain_device *device = task->dev;
2250 				struct hisi_sas_device *sas_dev = device->lldd_dev;
2251 
2252 				sas_dev->dev_status = HISI_SAS_DEV_NCQ_ERR;
2253 				slot->abort = 1;
2254 			} else {
2255 				ts->stat = SAS_PROTO_RESPONSE;
2256 			}
2257 		} else if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
2258 			ts->residual = trans_tx_fail_type;
2259 			ts->stat = SAS_DATA_UNDERRUN;
2260 		} else if ((dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) ||
2261 			   (dw3 & SATA_DISK_IN_ERROR_STATUS_MSK)) {
2262 			ts->stat = SAS_PHY_DOWN;
2263 			slot->abort = 1;
2264 		} else {
2265 			ts->stat = SAS_OPEN_REJECT;
2266 			ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2267 		}
2268 		if (dw0 & CMPLT_HDR_RSPNS_XFRD_MSK)
2269 			hisi_sas_sata_done(task, slot);
2270 		break;
2271 	case SAS_PROTOCOL_SMP:
2272 		ts->stat = SAS_SAM_STAT_CHECK_CONDITION;
2273 		break;
2274 	default:
2275 		break;
2276 	}
2277 	return true;
2278 }
2279 
2280 static void slot_complete_v3_hw(struct hisi_hba *hisi_hba,
2281 				struct hisi_sas_slot *slot)
2282 {
2283 	struct sas_task *task = slot->task;
2284 	struct hisi_sas_device *sas_dev;
2285 	struct device *dev = hisi_hba->dev;
2286 	struct task_status_struct *ts;
2287 	struct domain_device *device;
2288 	struct sas_ha_struct *ha;
2289 	struct hisi_sas_complete_v3_hdr *complete_queue =
2290 			hisi_hba->complete_hdr[slot->cmplt_queue];
2291 	struct hisi_sas_complete_v3_hdr *complete_hdr =
2292 			&complete_queue[slot->cmplt_queue_slot];
2293 	unsigned long flags;
2294 	bool is_internal = slot->is_internal;
2295 	u32 dw0, dw1, dw3;
2296 
2297 	if (unlikely(!task || !task->lldd_task || !task->dev))
2298 		return;
2299 
2300 	ts = &task->task_status;
2301 	device = task->dev;
2302 	ha = device->port->ha;
2303 	sas_dev = device->lldd_dev;
2304 
2305 	spin_lock_irqsave(&task->task_state_lock, flags);
2306 	task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2307 	spin_unlock_irqrestore(&task->task_state_lock, flags);
2308 
2309 	memset(ts, 0, sizeof(*ts));
2310 	ts->resp = SAS_TASK_COMPLETE;
2311 
2312 	if (unlikely(!sas_dev)) {
2313 		dev_dbg(dev, "slot complete: port has not device\n");
2314 		ts->stat = SAS_PHY_DOWN;
2315 		goto out;
2316 	}
2317 
2318 	dw0 = le32_to_cpu(complete_hdr->dw0);
2319 	dw1 = le32_to_cpu(complete_hdr->dw1);
2320 	dw3 = le32_to_cpu(complete_hdr->dw3);
2321 
2322 	/*
2323 	 * Use SAS+TMF status codes
2324 	 */
2325 	switch ((dw0 & CMPLT_HDR_ABORT_STAT_MSK) >> CMPLT_HDR_ABORT_STAT_OFF) {
2326 	case STAT_IO_ABORTED:
2327 		/* this IO has been aborted by abort command */
2328 		ts->stat = SAS_ABORTED_TASK;
2329 		goto out;
2330 	case STAT_IO_COMPLETE:
2331 		/* internal abort command complete */
2332 		ts->stat = TMF_RESP_FUNC_SUCC;
2333 		goto out;
2334 	case STAT_IO_NO_DEVICE:
2335 		ts->stat = TMF_RESP_FUNC_COMPLETE;
2336 		goto out;
2337 	case STAT_IO_NOT_VALID:
2338 		/*
2339 		 * abort single IO, the controller can't find the IO
2340 		 */
2341 		ts->stat = TMF_RESP_FUNC_FAILED;
2342 		goto out;
2343 	default:
2344 		break;
2345 	}
2346 
2347 	/* check for erroneous completion */
2348 	if ((dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) {
2349 		u32 *error_info = hisi_sas_status_buf_addr_mem(slot);
2350 
2351 		if (slot_err_v3_hw(hisi_hba, task, slot)) {
2352 			if (ts->stat != SAS_DATA_UNDERRUN)
2353 				dev_info(dev, "erroneous completion iptt=%d task=%pK dev id=%d addr=%016llx CQ hdr: 0x%x 0x%x 0x%x 0x%x Error info: 0x%x 0x%x 0x%x 0x%x\n",
2354 					slot->idx, task, sas_dev->device_id,
2355 					SAS_ADDR(device->sas_addr),
2356 					dw0, dw1, complete_hdr->act, dw3,
2357 					error_info[0], error_info[1],
2358 					error_info[2], error_info[3]);
2359 			if (unlikely(slot->abort)) {
2360 				if (dev_is_sata(device) && task->ata_task.use_ncq)
2361 					sas_ata_device_link_abort(device, true);
2362 				else
2363 					sas_task_abort(task);
2364 
2365 				return;
2366 			}
2367 			goto out;
2368 		}
2369 	}
2370 
2371 	switch (task->task_proto) {
2372 	case SAS_PROTOCOL_SSP: {
2373 		struct ssp_response_iu *iu =
2374 			hisi_sas_status_buf_addr_mem(slot) +
2375 			sizeof(struct hisi_sas_err_record);
2376 
2377 		sas_ssp_task_response(dev, task, iu);
2378 		break;
2379 	}
2380 	case SAS_PROTOCOL_SMP: {
2381 		struct scatterlist *sg_resp = &task->smp_task.smp_resp;
2382 		void *to = page_address(sg_page(sg_resp));
2383 
2384 		ts->stat = SAS_SAM_STAT_GOOD;
2385 
2386 		memcpy(to + sg_resp->offset,
2387 			hisi_sas_status_buf_addr_mem(slot) +
2388 		       sizeof(struct hisi_sas_err_record),
2389 		       sg_resp->length);
2390 		break;
2391 	}
2392 	case SAS_PROTOCOL_SATA:
2393 	case SAS_PROTOCOL_STP:
2394 	case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
2395 		ts->stat = SAS_SAM_STAT_GOOD;
2396 		if (dw0 & CMPLT_HDR_RSPNS_XFRD_MSK)
2397 			hisi_sas_sata_done(task, slot);
2398 		break;
2399 	default:
2400 		ts->stat = SAS_SAM_STAT_CHECK_CONDITION;
2401 		break;
2402 	}
2403 
2404 	if (!slot->port->port_attached) {
2405 		dev_warn(dev, "slot complete: port %d has removed\n",
2406 			slot->port->sas_port.id);
2407 		ts->stat = SAS_PHY_DOWN;
2408 	}
2409 
2410 out:
2411 	spin_lock_irqsave(&task->task_state_lock, flags);
2412 	if (task->task_state_flags & SAS_TASK_STATE_ABORTED) {
2413 		spin_unlock_irqrestore(&task->task_state_lock, flags);
2414 		dev_info(dev, "slot complete: task(%pK) aborted\n", task);
2415 		return;
2416 	}
2417 	task->task_state_flags |= SAS_TASK_STATE_DONE;
2418 	spin_unlock_irqrestore(&task->task_state_lock, flags);
2419 	hisi_sas_slot_task_free(hisi_hba, task, slot, true);
2420 
2421 	if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) {
2422 		spin_lock_irqsave(&device->done_lock, flags);
2423 		if (test_bit(SAS_HA_FROZEN, &ha->state)) {
2424 			spin_unlock_irqrestore(&device->done_lock, flags);
2425 			dev_info(dev, "slot complete: task(%pK) ignored\n ",
2426 				 task);
2427 			return;
2428 		}
2429 		spin_unlock_irqrestore(&device->done_lock, flags);
2430 	}
2431 
2432 	if (task->task_done)
2433 		task->task_done(task);
2434 }
2435 
2436 static int complete_v3_hw(struct hisi_sas_cq *cq)
2437 {
2438 	struct hisi_sas_complete_v3_hdr *complete_queue;
2439 	struct hisi_hba *hisi_hba = cq->hisi_hba;
2440 	u32 rd_point, wr_point;
2441 	int queue = cq->id;
2442 	int completed;
2443 
2444 	rd_point = cq->rd_point;
2445 	complete_queue = hisi_hba->complete_hdr[queue];
2446 
2447 	wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
2448 				   (0x14 * queue));
2449 	completed = (wr_point + HISI_SAS_QUEUE_SLOTS - rd_point) % HISI_SAS_QUEUE_SLOTS;
2450 
2451 	while (rd_point != wr_point) {
2452 		struct hisi_sas_complete_v3_hdr *complete_hdr;
2453 		struct device *dev = hisi_hba->dev;
2454 		struct hisi_sas_slot *slot;
2455 		u32 dw0, dw1, dw3;
2456 		int iptt;
2457 
2458 		complete_hdr = &complete_queue[rd_point];
2459 		dw0 = le32_to_cpu(complete_hdr->dw0);
2460 		dw1 = le32_to_cpu(complete_hdr->dw1);
2461 		dw3 = le32_to_cpu(complete_hdr->dw3);
2462 
2463 		iptt = dw1 & CMPLT_HDR_IPTT_MSK;
2464 		if (unlikely((dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) &&
2465 			     (dw3 & CMPLT_HDR_SATA_DISK_ERR_MSK)) {
2466 			int device_id = (dw1 & CMPLT_HDR_DEV_ID_MSK) >>
2467 					CMPLT_HDR_DEV_ID_OFF;
2468 			struct hisi_sas_itct *itct =
2469 				&hisi_hba->itct[device_id];
2470 			struct hisi_sas_device *sas_dev =
2471 				&hisi_hba->devices[device_id];
2472 			struct domain_device *device = sas_dev->sas_device;
2473 
2474 			dev_err(dev, "erroneous completion disk err dev id=%d sas_addr=0x%llx CQ hdr: 0x%x 0x%x 0x%x 0x%x\n",
2475 				device_id, itct->sas_addr, dw0, dw1,
2476 				complete_hdr->act, dw3);
2477 
2478 			if (is_ncq_err_v3_hw(complete_hdr))
2479 				sas_dev->dev_status = HISI_SAS_DEV_NCQ_ERR;
2480 
2481 			sas_ata_device_link_abort(device, true);
2482 		} else if (likely(iptt < HISI_SAS_COMMAND_ENTRIES_V3_HW)) {
2483 			slot = &hisi_hba->slot_info[iptt];
2484 			slot->cmplt_queue_slot = rd_point;
2485 			slot->cmplt_queue = queue;
2486 			slot_complete_v3_hw(hisi_hba, slot);
2487 		} else
2488 			dev_err(dev, "IPTT %d is invalid, discard it.\n", iptt);
2489 
2490 		if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
2491 			rd_point = 0;
2492 	}
2493 
2494 	/* update rd_point */
2495 	cq->rd_point = rd_point;
2496 	hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
2497 
2498 	return completed;
2499 }
2500 
2501 static int queue_complete_v3_hw(struct Scsi_Host *shost, unsigned int queue)
2502 {
2503 	struct hisi_hba *hisi_hba = shost_priv(shost);
2504 	struct hisi_sas_cq *cq = &hisi_hba->cq[queue];
2505 	int completed;
2506 
2507 	spin_lock(&cq->poll_lock);
2508 	completed = complete_v3_hw(cq);
2509 	spin_unlock(&cq->poll_lock);
2510 
2511 	return completed;
2512 }
2513 
2514 static irqreturn_t cq_thread_v3_hw(int irq_no, void *p)
2515 {
2516 	struct hisi_sas_cq *cq = p;
2517 
2518 	complete_v3_hw(cq);
2519 
2520 	return IRQ_HANDLED;
2521 }
2522 
2523 static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p)
2524 {
2525 	struct hisi_sas_cq *cq = p;
2526 	struct hisi_hba *hisi_hba = cq->hisi_hba;
2527 	int queue = cq->id;
2528 
2529 	hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
2530 
2531 	return IRQ_WAKE_THREAD;
2532 }
2533 
2534 static void hisi_sas_v3_free_vectors(void *data)
2535 {
2536 	struct pci_dev *pdev = data;
2537 
2538 	pci_free_irq_vectors(pdev);
2539 }
2540 
2541 static int interrupt_preinit_v3_hw(struct hisi_hba *hisi_hba)
2542 {
2543 	/* Allocate all MSI vectors to avoid re-insertion issue */
2544 	int max_msi = HISI_SAS_MSI_COUNT_V3_HW;
2545 	int vectors, min_msi;
2546 	struct Scsi_Host *shost = hisi_hba->shost;
2547 	struct pci_dev *pdev = hisi_hba->pci_dev;
2548 	struct irq_affinity desc = {
2549 		.pre_vectors = BASE_VECTORS_V3_HW,
2550 	};
2551 
2552 	min_msi = MIN_AFFINE_VECTORS_V3_HW;
2553 	vectors = pci_alloc_irq_vectors_affinity(pdev,
2554 						 min_msi, max_msi,
2555 						 PCI_IRQ_MSI |
2556 						 PCI_IRQ_AFFINITY,
2557 						 &desc);
2558 	if (vectors < 0)
2559 		return -ENOENT;
2560 
2561 
2562 	hisi_hba->cq_nvecs = vectors - BASE_VECTORS_V3_HW - hisi_hba->iopoll_q_cnt;
2563 	shost->nr_hw_queues = hisi_hba->cq_nvecs + hisi_hba->iopoll_q_cnt;
2564 
2565 	return devm_add_action(&pdev->dev, hisi_sas_v3_free_vectors, pdev);
2566 }
2567 
2568 static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
2569 {
2570 	struct device *dev = hisi_hba->dev;
2571 	struct pci_dev *pdev = hisi_hba->pci_dev;
2572 	int rc, i;
2573 
2574 	rc = devm_request_irq(dev, pci_irq_vector(pdev, 1),
2575 			      int_phy_up_down_bcast_v3_hw, 0,
2576 			      DRV_NAME " phy", hisi_hba);
2577 	if (rc) {
2578 		dev_err(dev, "could not request phy interrupt, rc=%d\n", rc);
2579 		return -ENOENT;
2580 	}
2581 
2582 	rc = devm_request_irq(dev, pci_irq_vector(pdev, 2),
2583 			      int_chnl_int_v3_hw, 0,
2584 			      DRV_NAME " channel", hisi_hba);
2585 	if (rc) {
2586 		dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc);
2587 		return -ENOENT;
2588 	}
2589 
2590 	rc = devm_request_irq(dev, pci_irq_vector(pdev, 11),
2591 			      fatal_axi_int_v3_hw, 0,
2592 			      DRV_NAME " fatal", hisi_hba);
2593 	if (rc) {
2594 		dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc);
2595 		return -ENOENT;
2596 	}
2597 
2598 	if (hisi_sas_intr_conv)
2599 		dev_info(dev, "Enable interrupt converge\n");
2600 
2601 	for (i = 0; i < hisi_hba->cq_nvecs; i++) {
2602 		struct hisi_sas_cq *cq = &hisi_hba->cq[i];
2603 		int nr = hisi_sas_intr_conv ? 16 : 16 + i;
2604 		unsigned long irqflags = hisi_sas_intr_conv ? IRQF_SHARED :
2605 							      IRQF_ONESHOT;
2606 
2607 		cq->irq_no = pci_irq_vector(pdev, nr);
2608 		rc = devm_request_threaded_irq(dev, cq->irq_no,
2609 				      cq_interrupt_v3_hw,
2610 				      cq_thread_v3_hw,
2611 				      irqflags,
2612 				      DRV_NAME " cq", cq);
2613 		if (rc) {
2614 			dev_err(dev, "could not request cq%d interrupt, rc=%d\n",
2615 				i, rc);
2616 			return -ENOENT;
2617 		}
2618 		cq->irq_mask = pci_irq_get_affinity(pdev, i + BASE_VECTORS_V3_HW);
2619 		if (!cq->irq_mask) {
2620 			dev_err(dev, "could not get cq%d irq affinity!\n", i);
2621 			return -ENOENT;
2622 		}
2623 	}
2624 
2625 	return 0;
2626 }
2627 
2628 static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
2629 {
2630 	int rc;
2631 
2632 	rc = hw_init_v3_hw(hisi_hba);
2633 	if (rc)
2634 		return rc;
2635 
2636 	rc = interrupt_init_v3_hw(hisi_hba);
2637 	if (rc)
2638 		return rc;
2639 
2640 	return 0;
2641 }
2642 
2643 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no,
2644 		struct sas_phy_linkrates *r)
2645 {
2646 	enum sas_linkrate max = r->maximum_linkrate;
2647 	u32 prog_phy_link_rate = hisi_sas_phy_read32(hisi_hba, phy_no,
2648 						     PROG_PHY_LINK_RATE);
2649 
2650 	prog_phy_link_rate &= ~CFG_PROG_PHY_LINK_RATE_MSK;
2651 	prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max);
2652 	hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
2653 			     prog_phy_link_rate);
2654 }
2655 
2656 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba)
2657 {
2658 	struct pci_dev *pdev = hisi_hba->pci_dev;
2659 	int i;
2660 
2661 	synchronize_irq(pci_irq_vector(pdev, 1));
2662 	synchronize_irq(pci_irq_vector(pdev, 2));
2663 	synchronize_irq(pci_irq_vector(pdev, 11));
2664 	for (i = 0; i < hisi_hba->queue_count; i++)
2665 		hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
2666 
2667 	for (i = 0; i < hisi_hba->cq_nvecs; i++)
2668 		synchronize_irq(pci_irq_vector(pdev, i + 16));
2669 
2670 	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
2671 	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
2672 	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
2673 	hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
2674 
2675 	for (i = 0; i < hisi_hba->n_phy; i++) {
2676 		hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
2677 		hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
2678 		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1);
2679 		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1);
2680 		hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1);
2681 	}
2682 }
2683 
2684 static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba)
2685 {
2686 	return hisi_sas_read32(hisi_hba, PHY_STATE);
2687 }
2688 
2689 static int disable_host_v3_hw(struct hisi_hba *hisi_hba)
2690 {
2691 	struct device *dev = hisi_hba->dev;
2692 	u32 status, reg_val;
2693 	int rc;
2694 
2695 	hisi_sas_sync_poll_cqs(hisi_hba);
2696 	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
2697 
2698 	hisi_sas_stop_phys(hisi_hba);
2699 
2700 	mdelay(10);
2701 
2702 	reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
2703 				  AM_CTRL_GLOBAL);
2704 	reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK;
2705 	hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
2706 			 AM_CTRL_GLOBAL, reg_val);
2707 
2708 	/* wait until bus idle */
2709 	rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE +
2710 					  AM_CURR_TRANS_RETURN, status,
2711 					  status == 0x3, 10, 100);
2712 	if (rc) {
2713 		dev_err(dev, "axi bus is not idle, rc=%d\n", rc);
2714 		return rc;
2715 	}
2716 
2717 	return 0;
2718 }
2719 
2720 static int soft_reset_v3_hw(struct hisi_hba *hisi_hba)
2721 {
2722 	struct device *dev = hisi_hba->dev;
2723 	int rc;
2724 
2725 	interrupt_disable_v3_hw(hisi_hba);
2726 	rc = disable_host_v3_hw(hisi_hba);
2727 	if (rc) {
2728 		dev_err(dev, "soft reset: disable host failed rc=%d\n", rc);
2729 		return rc;
2730 	}
2731 
2732 	hisi_sas_init_mem(hisi_hba);
2733 
2734 	return hw_init_v3_hw(hisi_hba);
2735 }
2736 
2737 static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type,
2738 			u8 reg_index, u8 reg_count, u8 *write_data)
2739 {
2740 	struct device *dev = hisi_hba->dev;
2741 	u32 *data = (u32 *)write_data;
2742 	int i;
2743 
2744 	switch (reg_type) {
2745 	case SAS_GPIO_REG_TX:
2746 		if ((reg_index + reg_count) > ((hisi_hba->n_phy + 3) / 4)) {
2747 			dev_err(dev, "write gpio: invalid reg range[%d, %d]\n",
2748 				reg_index, reg_index + reg_count - 1);
2749 			return -EINVAL;
2750 		}
2751 
2752 		for (i = 0; i < reg_count; i++)
2753 			hisi_sas_write32(hisi_hba,
2754 					 SAS_GPIO_TX_0_1 + (reg_index + i) * 4,
2755 					 data[i]);
2756 		break;
2757 	default:
2758 		dev_err(dev, "write gpio: unsupported or bad reg type %d\n",
2759 			reg_type);
2760 		return -EINVAL;
2761 	}
2762 
2763 	return 0;
2764 }
2765 
2766 static void wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba,
2767 					     int delay_ms, int timeout_ms)
2768 {
2769 	struct device *dev = hisi_hba->dev;
2770 	int entries, entries_old = 0, time;
2771 
2772 	for (time = 0; time < timeout_ms; time += delay_ms) {
2773 		entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT);
2774 		if (entries == entries_old)
2775 			break;
2776 
2777 		entries_old = entries;
2778 		msleep(delay_ms);
2779 	}
2780 
2781 	if (time >= timeout_ms) {
2782 		dev_dbg(dev, "Wait commands complete timeout!\n");
2783 		return;
2784 	}
2785 
2786 	dev_dbg(dev, "wait commands complete %dms\n", time);
2787 }
2788 
2789 static ssize_t intr_conv_v3_hw_show(struct device *dev,
2790 				    struct device_attribute *attr, char *buf)
2791 {
2792 	return scnprintf(buf, PAGE_SIZE, "%u\n", hisi_sas_intr_conv);
2793 }
2794 static DEVICE_ATTR_RO(intr_conv_v3_hw);
2795 
2796 static void config_intr_coal_v3_hw(struct hisi_hba *hisi_hba)
2797 {
2798 	/* config those registers between enable and disable PHYs */
2799 	hisi_sas_stop_phys(hisi_hba);
2800 
2801 	if (hisi_hba->intr_coal_ticks == 0 ||
2802 	    hisi_hba->intr_coal_count == 0) {
2803 		hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
2804 		hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
2805 		hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
2806 	} else {
2807 		hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x3);
2808 		hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME,
2809 				 hisi_hba->intr_coal_ticks);
2810 		hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT,
2811 				 hisi_hba->intr_coal_count);
2812 	}
2813 	phys_init_v3_hw(hisi_hba);
2814 }
2815 
2816 static ssize_t intr_coal_ticks_v3_hw_show(struct device *dev,
2817 					  struct device_attribute *attr,
2818 					  char *buf)
2819 {
2820 	struct Scsi_Host *shost = class_to_shost(dev);
2821 	struct hisi_hba *hisi_hba = shost_priv(shost);
2822 
2823 	return scnprintf(buf, PAGE_SIZE, "%u\n",
2824 			 hisi_hba->intr_coal_ticks);
2825 }
2826 
2827 static ssize_t intr_coal_ticks_v3_hw_store(struct device *dev,
2828 					   struct device_attribute *attr,
2829 					   const char *buf, size_t count)
2830 {
2831 	struct Scsi_Host *shost = class_to_shost(dev);
2832 	struct hisi_hba *hisi_hba = shost_priv(shost);
2833 	u32 intr_coal_ticks;
2834 	int ret;
2835 
2836 	ret = kstrtou32(buf, 10, &intr_coal_ticks);
2837 	if (ret) {
2838 		dev_err(dev, "Input data of interrupt coalesce unmatch\n");
2839 		return -EINVAL;
2840 	}
2841 
2842 	if (intr_coal_ticks >= BIT(24)) {
2843 		dev_err(dev, "intr_coal_ticks must be less than 2^24!\n");
2844 		return -EINVAL;
2845 	}
2846 
2847 	hisi_hba->intr_coal_ticks = intr_coal_ticks;
2848 
2849 	config_intr_coal_v3_hw(hisi_hba);
2850 
2851 	return count;
2852 }
2853 static DEVICE_ATTR_RW(intr_coal_ticks_v3_hw);
2854 
2855 static ssize_t intr_coal_count_v3_hw_show(struct device *dev,
2856 					  struct device_attribute
2857 					  *attr, char *buf)
2858 {
2859 	struct Scsi_Host *shost = class_to_shost(dev);
2860 	struct hisi_hba *hisi_hba = shost_priv(shost);
2861 
2862 	return scnprintf(buf, PAGE_SIZE, "%u\n",
2863 			 hisi_hba->intr_coal_count);
2864 }
2865 
2866 static ssize_t intr_coal_count_v3_hw_store(struct device *dev,
2867 		struct device_attribute
2868 		*attr, const char *buf, size_t count)
2869 {
2870 	struct Scsi_Host *shost = class_to_shost(dev);
2871 	struct hisi_hba *hisi_hba = shost_priv(shost);
2872 	u32 intr_coal_count;
2873 	int ret;
2874 
2875 	ret = kstrtou32(buf, 10, &intr_coal_count);
2876 	if (ret) {
2877 		dev_err(dev, "Input data of interrupt coalesce unmatch\n");
2878 		return -EINVAL;
2879 	}
2880 
2881 	if (intr_coal_count >= BIT(8)) {
2882 		dev_err(dev, "intr_coal_count must be less than 2^8!\n");
2883 		return -EINVAL;
2884 	}
2885 
2886 	hisi_hba->intr_coal_count = intr_coal_count;
2887 
2888 	config_intr_coal_v3_hw(hisi_hba);
2889 
2890 	return count;
2891 }
2892 static DEVICE_ATTR_RW(intr_coal_count_v3_hw);
2893 
2894 static ssize_t iopoll_q_cnt_v3_hw_show(struct device *dev,
2895 					  struct device_attribute
2896 					  *attr, char *buf)
2897 {
2898 	struct Scsi_Host *shost = class_to_shost(dev);
2899 	struct hisi_hba *hisi_hba = shost_priv(shost);
2900 
2901 	return scnprintf(buf, PAGE_SIZE, "%u\n",
2902 			 hisi_hba->iopoll_q_cnt);
2903 }
2904 static DEVICE_ATTR_RO(iopoll_q_cnt_v3_hw);
2905 
2906 static int slave_configure_v3_hw(struct scsi_device *sdev)
2907 {
2908 	struct Scsi_Host *shost = dev_to_shost(&sdev->sdev_gendev);
2909 	struct hisi_hba *hisi_hba = shost_priv(shost);
2910 	int ret = hisi_sas_slave_configure(sdev);
2911 	struct device *dev = hisi_hba->dev;
2912 
2913 	if (ret)
2914 		return ret;
2915 
2916 	if (sdev->type == TYPE_ENCLOSURE)
2917 		return 0;
2918 
2919 	if (!device_link_add(&sdev->sdev_gendev, dev,
2920 			     DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE)) {
2921 		if (pm_runtime_enabled(dev)) {
2922 			dev_info(dev, "add device link failed, disable runtime PM for the host\n");
2923 			pm_runtime_disable(dev);
2924 		}
2925 	}
2926 
2927 	return 0;
2928 }
2929 
2930 static struct attribute *host_v3_hw_attrs[] = {
2931 	&dev_attr_phy_event_threshold.attr,
2932 	&dev_attr_intr_conv_v3_hw.attr,
2933 	&dev_attr_intr_coal_ticks_v3_hw.attr,
2934 	&dev_attr_intr_coal_count_v3_hw.attr,
2935 	&dev_attr_iopoll_q_cnt_v3_hw.attr,
2936 	NULL
2937 };
2938 
2939 ATTRIBUTE_GROUPS(host_v3_hw);
2940 
2941 #define HISI_SAS_DEBUGFS_REG(x) {#x, x}
2942 
2943 struct hisi_sas_debugfs_reg_lu {
2944 	char *name;
2945 	int off;
2946 };
2947 
2948 struct hisi_sas_debugfs_reg {
2949 	const struct hisi_sas_debugfs_reg_lu *lu;
2950 	int count;
2951 	int base_off;
2952 };
2953 
2954 static const struct hisi_sas_debugfs_reg_lu debugfs_port_reg_lu[] = {
2955 	HISI_SAS_DEBUGFS_REG(PHY_CFG),
2956 	HISI_SAS_DEBUGFS_REG(HARD_PHY_LINKRATE),
2957 	HISI_SAS_DEBUGFS_REG(PROG_PHY_LINK_RATE),
2958 	HISI_SAS_DEBUGFS_REG(PHY_CTRL),
2959 	HISI_SAS_DEBUGFS_REG(SL_CFG),
2960 	HISI_SAS_DEBUGFS_REG(AIP_LIMIT),
2961 	HISI_SAS_DEBUGFS_REG(SL_CONTROL),
2962 	HISI_SAS_DEBUGFS_REG(RX_PRIMS_STATUS),
2963 	HISI_SAS_DEBUGFS_REG(TX_ID_DWORD0),
2964 	HISI_SAS_DEBUGFS_REG(TX_ID_DWORD1),
2965 	HISI_SAS_DEBUGFS_REG(TX_ID_DWORD2),
2966 	HISI_SAS_DEBUGFS_REG(TX_ID_DWORD3),
2967 	HISI_SAS_DEBUGFS_REG(TX_ID_DWORD4),
2968 	HISI_SAS_DEBUGFS_REG(TX_ID_DWORD5),
2969 	HISI_SAS_DEBUGFS_REG(TX_ID_DWORD6),
2970 	HISI_SAS_DEBUGFS_REG(TXID_AUTO),
2971 	HISI_SAS_DEBUGFS_REG(RX_IDAF_DWORD0),
2972 	HISI_SAS_DEBUGFS_REG(RXOP_CHECK_CFG_H),
2973 	HISI_SAS_DEBUGFS_REG(STP_LINK_TIMER),
2974 	HISI_SAS_DEBUGFS_REG(STP_LINK_TIMEOUT_STATE),
2975 	HISI_SAS_DEBUGFS_REG(CON_CFG_DRIVER),
2976 	HISI_SAS_DEBUGFS_REG(SAS_SSP_CON_TIMER_CFG),
2977 	HISI_SAS_DEBUGFS_REG(SAS_SMP_CON_TIMER_CFG),
2978 	HISI_SAS_DEBUGFS_REG(SAS_STP_CON_TIMER_CFG),
2979 	HISI_SAS_DEBUGFS_REG(CHL_INT0),
2980 	HISI_SAS_DEBUGFS_REG(CHL_INT1),
2981 	HISI_SAS_DEBUGFS_REG(CHL_INT2),
2982 	HISI_SAS_DEBUGFS_REG(CHL_INT0_MSK),
2983 	HISI_SAS_DEBUGFS_REG(CHL_INT1_MSK),
2984 	HISI_SAS_DEBUGFS_REG(CHL_INT2_MSK),
2985 	HISI_SAS_DEBUGFS_REG(SAS_EC_INT_COAL_TIME),
2986 	HISI_SAS_DEBUGFS_REG(CHL_INT_COAL_EN),
2987 	HISI_SAS_DEBUGFS_REG(SAS_RX_TRAIN_TIMER),
2988 	HISI_SAS_DEBUGFS_REG(PHY_CTRL_RDY_MSK),
2989 	HISI_SAS_DEBUGFS_REG(PHYCTRL_NOT_RDY_MSK),
2990 	HISI_SAS_DEBUGFS_REG(PHYCTRL_DWS_RESET_MSK),
2991 	HISI_SAS_DEBUGFS_REG(PHYCTRL_PHY_ENA_MSK),
2992 	HISI_SAS_DEBUGFS_REG(SL_RX_BCAST_CHK_MSK),
2993 	HISI_SAS_DEBUGFS_REG(PHYCTRL_OOB_RESTART_MSK),
2994 	HISI_SAS_DEBUGFS_REG(DMA_TX_STATUS),
2995 	HISI_SAS_DEBUGFS_REG(DMA_RX_STATUS),
2996 	HISI_SAS_DEBUGFS_REG(COARSETUNE_TIME),
2997 	HISI_SAS_DEBUGFS_REG(ERR_CNT_DWS_LOST),
2998 	HISI_SAS_DEBUGFS_REG(ERR_CNT_RESET_PROB),
2999 	HISI_SAS_DEBUGFS_REG(ERR_CNT_INVLD_DW),
3000 	HISI_SAS_DEBUGFS_REG(ERR_CNT_CODE_ERR),
3001 	HISI_SAS_DEBUGFS_REG(ERR_CNT_DISP_ERR),
3002 	{}
3003 };
3004 
3005 static const struct hisi_sas_debugfs_reg debugfs_port_reg = {
3006 	.lu = debugfs_port_reg_lu,
3007 	.count = 0x100,
3008 	.base_off = PORT_BASE,
3009 };
3010 
3011 static const struct hisi_sas_debugfs_reg_lu debugfs_global_reg_lu[] = {
3012 	HISI_SAS_DEBUGFS_REG(DLVRY_QUEUE_ENABLE),
3013 	HISI_SAS_DEBUGFS_REG(PHY_CONTEXT),
3014 	HISI_SAS_DEBUGFS_REG(PHY_STATE),
3015 	HISI_SAS_DEBUGFS_REG(PHY_PORT_NUM_MA),
3016 	HISI_SAS_DEBUGFS_REG(PHY_CONN_RATE),
3017 	HISI_SAS_DEBUGFS_REG(ITCT_CLR),
3018 	HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_LO),
3019 	HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_HI),
3020 	HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_LO),
3021 	HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_HI),
3022 	HISI_SAS_DEBUGFS_REG(CFG_MAX_TAG),
3023 	HISI_SAS_DEBUGFS_REG(TRANS_LOCK_ICT_TIME),
3024 	HISI_SAS_DEBUGFS_REG(HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL),
3025 	HISI_SAS_DEBUGFS_REG(HGC_SAS_TXFAIL_RETRY_CTRL),
3026 	HISI_SAS_DEBUGFS_REG(HGC_GET_ITV_TIME),
3027 	HISI_SAS_DEBUGFS_REG(DEVICE_MSG_WORK_MODE),
3028 	HISI_SAS_DEBUGFS_REG(OPENA_WT_CONTI_TIME),
3029 	HISI_SAS_DEBUGFS_REG(I_T_NEXUS_LOSS_TIME),
3030 	HISI_SAS_DEBUGFS_REG(MAX_CON_TIME_LIMIT_TIME),
3031 	HISI_SAS_DEBUGFS_REG(BUS_INACTIVE_LIMIT_TIME),
3032 	HISI_SAS_DEBUGFS_REG(REJECT_TO_OPEN_LIMIT_TIME),
3033 	HISI_SAS_DEBUGFS_REG(CQ_INT_CONVERGE_EN),
3034 	HISI_SAS_DEBUGFS_REG(CFG_AGING_TIME),
3035 	HISI_SAS_DEBUGFS_REG(HGC_DFX_CFG2),
3036 	HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_QUERY_IPTT),
3037 	HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_IPTT_DONE),
3038 	HISI_SAS_DEBUGFS_REG(HGC_IOMB_PROC1_STATUS),
3039 	HISI_SAS_DEBUGFS_REG(CHNL_INT_STATUS),
3040 	HISI_SAS_DEBUGFS_REG(HGC_AXI_FIFO_ERR_INFO),
3041 	HISI_SAS_DEBUGFS_REG(INT_COAL_EN),
3042 	HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_TIME),
3043 	HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_CNT),
3044 	HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_TIME),
3045 	HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_CNT),
3046 	HISI_SAS_DEBUGFS_REG(OQ_INT_SRC),
3047 	HISI_SAS_DEBUGFS_REG(OQ_INT_SRC_MSK),
3048 	HISI_SAS_DEBUGFS_REG(ENT_INT_SRC1),
3049 	HISI_SAS_DEBUGFS_REG(ENT_INT_SRC2),
3050 	HISI_SAS_DEBUGFS_REG(ENT_INT_SRC3),
3051 	HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK1),
3052 	HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK2),
3053 	HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK3),
3054 	HISI_SAS_DEBUGFS_REG(CHNL_PHYUPDOWN_INT_MSK),
3055 	HISI_SAS_DEBUGFS_REG(CHNL_ENT_INT_MSK),
3056 	HISI_SAS_DEBUGFS_REG(HGC_COM_INT_MSK),
3057 	HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR),
3058 	HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR_MSK),
3059 	HISI_SAS_DEBUGFS_REG(HGC_ERR_STAT_EN),
3060 	HISI_SAS_DEBUGFS_REG(CQE_SEND_CNT),
3061 	HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_DEPTH),
3062 	HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_WR_PTR),
3063 	HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_RD_PTR),
3064 	HISI_SAS_DEBUGFS_REG(HYPER_STREAM_ID_EN_CFG),
3065 	HISI_SAS_DEBUGFS_REG(OQ0_INT_SRC_MSK),
3066 	HISI_SAS_DEBUGFS_REG(COMPL_Q_0_DEPTH),
3067 	HISI_SAS_DEBUGFS_REG(COMPL_Q_0_WR_PTR),
3068 	HISI_SAS_DEBUGFS_REG(COMPL_Q_0_RD_PTR),
3069 	HISI_SAS_DEBUGFS_REG(AWQOS_AWCACHE_CFG),
3070 	HISI_SAS_DEBUGFS_REG(ARQOS_ARCACHE_CFG),
3071 	HISI_SAS_DEBUGFS_REG(HILINK_ERR_DFX),
3072 	HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_0),
3073 	HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_1),
3074 	HISI_SAS_DEBUGFS_REG(SAS_GPIO_TX_0_1),
3075 	HISI_SAS_DEBUGFS_REG(SAS_CFG_DRIVE_VLD),
3076 	{}
3077 };
3078 
3079 static const struct hisi_sas_debugfs_reg debugfs_global_reg = {
3080 	.lu = debugfs_global_reg_lu,
3081 	.count = 0x800,
3082 };
3083 
3084 static const struct hisi_sas_debugfs_reg_lu debugfs_axi_reg_lu[] = {
3085 	HISI_SAS_DEBUGFS_REG(AM_CFG_MAX_TRANS),
3086 	HISI_SAS_DEBUGFS_REG(AM_CFG_SINGLE_PORT_MAX_TRANS),
3087 	HISI_SAS_DEBUGFS_REG(AXI_CFG),
3088 	HISI_SAS_DEBUGFS_REG(AM_ROB_ECC_ERR_ADDR),
3089 	{}
3090 };
3091 
3092 static const struct hisi_sas_debugfs_reg debugfs_axi_reg = {
3093 	.lu = debugfs_axi_reg_lu,
3094 	.count = 0x61,
3095 	.base_off = AXI_MASTER_CFG_BASE,
3096 };
3097 
3098 static const struct hisi_sas_debugfs_reg_lu debugfs_ras_reg_lu[] = {
3099 	HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR0),
3100 	HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR1),
3101 	HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR0_MASK),
3102 	HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR1_MASK),
3103 	HISI_SAS_DEBUGFS_REG(CFG_SAS_RAS_INTR_MASK),
3104 	HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR2),
3105 	HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR2_MASK),
3106 	{}
3107 };
3108 
3109 static const struct hisi_sas_debugfs_reg debugfs_ras_reg = {
3110 	.lu = debugfs_ras_reg_lu,
3111 	.count = 0x10,
3112 	.base_off = RAS_BASE,
3113 };
3114 
3115 static void debugfs_snapshot_prepare_v3_hw(struct hisi_hba *hisi_hba)
3116 {
3117 	struct Scsi_Host *shost = hisi_hba->shost;
3118 
3119 	scsi_block_requests(shost);
3120 	wait_cmds_complete_timeout_v3_hw(hisi_hba, 100, 5000);
3121 
3122 	set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
3123 	hisi_sas_sync_cqs(hisi_hba);
3124 	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
3125 }
3126 
3127 static void debugfs_snapshot_restore_v3_hw(struct hisi_hba *hisi_hba)
3128 {
3129 	struct Scsi_Host *shost = hisi_hba->shost;
3130 
3131 	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
3132 			 (u32)((1ULL << hisi_hba->queue_count) - 1));
3133 
3134 	clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
3135 	scsi_unblock_requests(shost);
3136 }
3137 
3138 static void read_iost_itct_cache_v3_hw(struct hisi_hba *hisi_hba,
3139 				       enum hisi_sas_debugfs_cache_type type,
3140 				       u32 *cache)
3141 {
3142 	u32 cache_dw_size = HISI_SAS_IOST_ITCT_CACHE_DW_SZ *
3143 			    HISI_SAS_IOST_ITCT_CACHE_NUM;
3144 	struct device *dev = hisi_hba->dev;
3145 	u32 *buf = cache;
3146 	u32 i, val;
3147 
3148 	hisi_sas_write32(hisi_hba, TAB_RD_TYPE, type);
3149 
3150 	for (i = 0; i < HISI_SAS_IOST_ITCT_CACHE_DW_SZ; i++) {
3151 		val = hisi_sas_read32(hisi_hba, TAB_DFX);
3152 		if (val == 0xffffffff)
3153 			break;
3154 	}
3155 
3156 	if (val != 0xffffffff) {
3157 		dev_err(dev, "Issue occurred in reading IOST/ITCT cache!\n");
3158 		return;
3159 	}
3160 
3161 	memset(buf, 0, cache_dw_size * 4);
3162 	buf[0] = val;
3163 
3164 	for (i = 1; i < cache_dw_size; i++)
3165 		buf[i] = hisi_sas_read32(hisi_hba, TAB_DFX);
3166 }
3167 
3168 static void hisi_sas_bist_test_prep_v3_hw(struct hisi_hba *hisi_hba)
3169 {
3170 	u32 reg_val;
3171 	int phy_no = hisi_hba->debugfs_bist_phy_no;
3172 	int i;
3173 
3174 	/* disable PHY */
3175 	hisi_sas_phy_enable(hisi_hba, phy_no, 0);
3176 
3177 	/* update FFE */
3178 	for (i = 0; i < FFE_CFG_MAX; i++)
3179 		hisi_sas_phy_write32(hisi_hba, phy_no, TXDEEMPH_G1 + (i * 0x4),
3180 				     hisi_hba->debugfs_bist_ffe[phy_no][i]);
3181 
3182 	/* disable ALOS */
3183 	reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SERDES_CFG);
3184 	reg_val |= CFG_ALOS_CHK_DISABLE_MSK;
3185 	hisi_sas_phy_write32(hisi_hba, phy_no, SERDES_CFG, reg_val);
3186 }
3187 
3188 static void hisi_sas_bist_test_restore_v3_hw(struct hisi_hba *hisi_hba)
3189 {
3190 	u32 reg_val;
3191 	int phy_no = hisi_hba->debugfs_bist_phy_no;
3192 
3193 	/* disable loopback */
3194 	reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL);
3195 	reg_val &= ~(CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK |
3196 		     CFG_BIST_TEST_MSK);
3197 	hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL, reg_val);
3198 
3199 	/* enable ALOS */
3200 	reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, SERDES_CFG);
3201 	reg_val &= ~CFG_ALOS_CHK_DISABLE_MSK;
3202 	hisi_sas_phy_write32(hisi_hba, phy_no, SERDES_CFG, reg_val);
3203 
3204 	/* restore the linkrate */
3205 	reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);
3206 	/* init OOB link rate as 1.5 Gbits */
3207 	reg_val &= ~CFG_PROG_OOB_PHY_LINK_RATE_MSK;
3208 	reg_val |= (0x8 << CFG_PROG_OOB_PHY_LINK_RATE_OFF);
3209 	hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, reg_val);
3210 
3211 	/* enable PHY */
3212 	hisi_sas_phy_enable(hisi_hba, phy_no, 1);
3213 }
3214 
3215 #define SAS_PHY_BIST_CODE_INIT	0x1
3216 #define SAS_PHY_BIST_CODE1_INIT	0X80
3217 static int debugfs_set_bist_v3_hw(struct hisi_hba *hisi_hba, bool enable)
3218 {
3219 	u32 reg_val, mode_tmp;
3220 	u32 linkrate = hisi_hba->debugfs_bist_linkrate;
3221 	u32 phy_no = hisi_hba->debugfs_bist_phy_no;
3222 	u32 *ffe = hisi_hba->debugfs_bist_ffe[phy_no];
3223 	u32 code_mode = hisi_hba->debugfs_bist_code_mode;
3224 	u32 path_mode = hisi_hba->debugfs_bist_mode;
3225 	u32 *fix_code = &hisi_hba->debugfs_bist_fixed_code[0];
3226 	struct device *dev = hisi_hba->dev;
3227 
3228 	dev_info(dev, "BIST info:phy%d link_rate=%d code_mode=%d path_mode=%d ffe={0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x} fixed_code={0x%x, 0x%x}\n",
3229 		 phy_no, linkrate, code_mode, path_mode,
3230 		 ffe[FFE_SAS_1_5_GBPS], ffe[FFE_SAS_3_0_GBPS],
3231 		 ffe[FFE_SAS_6_0_GBPS], ffe[FFE_SAS_12_0_GBPS],
3232 		 ffe[FFE_SATA_1_5_GBPS], ffe[FFE_SATA_3_0_GBPS],
3233 		 ffe[FFE_SATA_6_0_GBPS], fix_code[FIXED_CODE],
3234 		 fix_code[FIXED_CODE_1]);
3235 	mode_tmp = path_mode ? 2 : 1;
3236 	if (enable) {
3237 		/* some preparations before bist test */
3238 		hisi_sas_bist_test_prep_v3_hw(hisi_hba);
3239 
3240 		/* set linkrate of bit test*/
3241 		reg_val = hisi_sas_phy_read32(hisi_hba, phy_no,
3242 					      PROG_PHY_LINK_RATE);
3243 		reg_val &= ~CFG_PROG_OOB_PHY_LINK_RATE_MSK;
3244 		reg_val |= (linkrate << CFG_PROG_OOB_PHY_LINK_RATE_OFF);
3245 		hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
3246 				     reg_val);
3247 
3248 		/* set code mode of bit test */
3249 		reg_val = hisi_sas_phy_read32(hisi_hba, phy_no,
3250 					      SAS_PHY_BIST_CTRL);
3251 		reg_val &= ~(CFG_BIST_MODE_SEL_MSK | CFG_LOOP_TEST_MODE_MSK |
3252 			     CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK |
3253 			     CFG_BIST_TEST_MSK);
3254 		reg_val |= ((code_mode << CFG_BIST_MODE_SEL_OFF) |
3255 			    (mode_tmp << CFG_LOOP_TEST_MODE_OFF) |
3256 			    CFG_BIST_TEST_MSK);
3257 		hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL,
3258 				     reg_val);
3259 
3260 		/* set the bist init value */
3261 		if (code_mode == HISI_SAS_BIST_CODE_MODE_FIXED_DATA) {
3262 			reg_val = hisi_hba->debugfs_bist_fixed_code[0];
3263 			hisi_sas_phy_write32(hisi_hba, phy_no,
3264 					     SAS_PHY_BIST_CODE, reg_val);
3265 
3266 			reg_val = hisi_hba->debugfs_bist_fixed_code[1];
3267 			hisi_sas_phy_write32(hisi_hba, phy_no,
3268 					     SAS_PHY_BIST_CODE1, reg_val);
3269 		} else {
3270 			hisi_sas_phy_write32(hisi_hba, phy_no,
3271 					     SAS_PHY_BIST_CODE,
3272 					     SAS_PHY_BIST_CODE_INIT);
3273 			hisi_sas_phy_write32(hisi_hba, phy_no,
3274 					     SAS_PHY_BIST_CODE1,
3275 					     SAS_PHY_BIST_CODE1_INIT);
3276 		}
3277 
3278 		mdelay(100);
3279 		reg_val |= (CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK);
3280 		hisi_sas_phy_write32(hisi_hba, phy_no, SAS_PHY_BIST_CTRL,
3281 				     reg_val);
3282 
3283 		/* clear error bit */
3284 		mdelay(100);
3285 		hisi_sas_phy_read32(hisi_hba, phy_no, SAS_BIST_ERR_CNT);
3286 	} else {
3287 		/* disable bist test and recover it */
3288 		hisi_hba->debugfs_bist_cnt += hisi_sas_phy_read32(hisi_hba,
3289 				phy_no, SAS_BIST_ERR_CNT);
3290 		hisi_sas_bist_test_restore_v3_hw(hisi_hba);
3291 	}
3292 
3293 	return 0;
3294 }
3295 
3296 static void hisi_sas_map_queues(struct Scsi_Host *shost)
3297 {
3298 	struct hisi_hba *hisi_hba = shost_priv(shost);
3299 	struct blk_mq_queue_map *qmap;
3300 	int i, qoff;
3301 
3302 	for (i = 0, qoff = 0; i < shost->nr_maps; i++) {
3303 		qmap = &shost->tag_set.map[i];
3304 		if (i == HCTX_TYPE_DEFAULT) {
3305 			qmap->nr_queues = hisi_hba->cq_nvecs;
3306 		} else if (i == HCTX_TYPE_POLL) {
3307 			qmap->nr_queues = hisi_hba->iopoll_q_cnt;
3308 		} else {
3309 			qmap->nr_queues = 0;
3310 			continue;
3311 		}
3312 
3313 		/* At least one interrupt hardware queue */
3314 		if (!qmap->nr_queues)
3315 			WARN_ON(i == HCTX_TYPE_DEFAULT);
3316 		qmap->queue_offset = qoff;
3317 		if (i == HCTX_TYPE_POLL)
3318 			blk_mq_map_queues(qmap);
3319 		else
3320 			blk_mq_pci_map_queues(qmap, hisi_hba->pci_dev,
3321 					      BASE_VECTORS_V3_HW);
3322 		qoff += qmap->nr_queues;
3323 	}
3324 }
3325 
3326 static const struct scsi_host_template sht_v3_hw = {
3327 	.name			= DRV_NAME,
3328 	.proc_name		= DRV_NAME,
3329 	.module			= THIS_MODULE,
3330 	.queuecommand		= sas_queuecommand,
3331 	.dma_need_drain		= ata_scsi_dma_need_drain,
3332 	.target_alloc		= sas_target_alloc,
3333 	.slave_configure	= slave_configure_v3_hw,
3334 	.scan_finished		= hisi_sas_scan_finished,
3335 	.scan_start		= hisi_sas_scan_start,
3336 	.map_queues		= hisi_sas_map_queues,
3337 	.change_queue_depth	= sas_change_queue_depth,
3338 	.bios_param		= sas_bios_param,
3339 	.this_id		= -1,
3340 	.sg_tablesize		= HISI_SAS_SGE_PAGE_CNT,
3341 	.sg_prot_tablesize	= HISI_SAS_SGE_PAGE_CNT,
3342 	.max_sectors		= SCSI_DEFAULT_MAX_SECTORS,
3343 	.eh_device_reset_handler = sas_eh_device_reset_handler,
3344 	.eh_target_reset_handler = sas_eh_target_reset_handler,
3345 	.slave_alloc		= hisi_sas_slave_alloc,
3346 	.target_destroy		= sas_target_destroy,
3347 	.ioctl			= sas_ioctl,
3348 #ifdef CONFIG_COMPAT
3349 	.compat_ioctl		= sas_ioctl,
3350 #endif
3351 	.shost_groups		= host_v3_hw_groups,
3352 	.tag_alloc_policy	= BLK_TAG_ALLOC_RR,
3353 	.host_reset             = hisi_sas_host_reset,
3354 	.host_tagset		= 1,
3355 	.mq_poll		= queue_complete_v3_hw,
3356 };
3357 
3358 static const struct hisi_sas_hw hisi_sas_v3_hw = {
3359 	.setup_itct = setup_itct_v3_hw,
3360 	.get_wideport_bitmap = get_wideport_bitmap_v3_hw,
3361 	.complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
3362 	.clear_itct = clear_itct_v3_hw,
3363 	.sl_notify_ssp = sl_notify_ssp_v3_hw,
3364 	.prep_ssp = prep_ssp_v3_hw,
3365 	.prep_smp = prep_smp_v3_hw,
3366 	.prep_stp = prep_ata_v3_hw,
3367 	.prep_abort = prep_abort_v3_hw,
3368 	.start_delivery = start_delivery_v3_hw,
3369 	.phys_init = phys_init_v3_hw,
3370 	.phy_start = start_phy_v3_hw,
3371 	.phy_disable = disable_phy_v3_hw,
3372 	.phy_hard_reset = phy_hard_reset_v3_hw,
3373 	.phy_get_max_linkrate = phy_get_max_linkrate_v3_hw,
3374 	.phy_set_linkrate = phy_set_linkrate_v3_hw,
3375 	.dereg_device = dereg_device_v3_hw,
3376 	.soft_reset = soft_reset_v3_hw,
3377 	.get_phys_state = get_phys_state_v3_hw,
3378 	.get_events = phy_get_events_v3_hw,
3379 	.write_gpio = write_gpio_v3_hw,
3380 	.wait_cmds_complete_timeout = wait_cmds_complete_timeout_v3_hw,
3381 	.debugfs_snapshot_regs = debugfs_snapshot_regs_v3_hw,
3382 };
3383 
3384 static struct Scsi_Host *
3385 hisi_sas_shost_alloc_pci(struct pci_dev *pdev)
3386 {
3387 	struct Scsi_Host *shost;
3388 	struct hisi_hba *hisi_hba;
3389 	struct device *dev = &pdev->dev;
3390 
3391 	shost = scsi_host_alloc(&sht_v3_hw, sizeof(*hisi_hba));
3392 	if (!shost) {
3393 		dev_err(dev, "shost alloc failed\n");
3394 		return NULL;
3395 	}
3396 	hisi_hba = shost_priv(shost);
3397 
3398 	INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler);
3399 	INIT_WORK(&hisi_hba->debugfs_work, debugfs_work_handler_v3_hw);
3400 	hisi_hba->hw = &hisi_sas_v3_hw;
3401 	hisi_hba->pci_dev = pdev;
3402 	hisi_hba->dev = dev;
3403 	hisi_hba->shost = shost;
3404 	SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
3405 
3406 	if (prot_mask & ~HISI_SAS_PROT_MASK)
3407 		dev_err(dev, "unsupported protection mask 0x%x, using default (0x0)\n",
3408 			prot_mask);
3409 	else
3410 		hisi_hba->prot_mask = prot_mask;
3411 
3412 	if (hisi_sas_get_fw_info(hisi_hba) < 0)
3413 		goto err_out;
3414 
3415 	if (experimental_iopoll_q_cnt < 0 ||
3416 		experimental_iopoll_q_cnt >= hisi_hba->queue_count)
3417 		dev_err(dev, "iopoll queue count %d cannot exceed or equal 16, using default 0\n",
3418 			experimental_iopoll_q_cnt);
3419 	else
3420 		hisi_hba->iopoll_q_cnt = experimental_iopoll_q_cnt;
3421 
3422 	if (hisi_sas_alloc(hisi_hba)) {
3423 		hisi_sas_free(hisi_hba);
3424 		goto err_out;
3425 	}
3426 
3427 	return shost;
3428 err_out:
3429 	scsi_host_put(shost);
3430 	dev_err(dev, "shost alloc failed\n");
3431 	return NULL;
3432 }
3433 
3434 static void debugfs_snapshot_cq_reg_v3_hw(struct hisi_hba *hisi_hba)
3435 {
3436 	int queue_entry_size = hisi_hba->hw->complete_hdr_size;
3437 	int dump_index = hisi_hba->debugfs_dump_index;
3438 	int i;
3439 
3440 	for (i = 0; i < hisi_hba->queue_count; i++)
3441 		memcpy(hisi_hba->debugfs_cq[dump_index][i].complete_hdr,
3442 		       hisi_hba->complete_hdr[i],
3443 		       HISI_SAS_QUEUE_SLOTS * queue_entry_size);
3444 }
3445 
3446 static void debugfs_snapshot_dq_reg_v3_hw(struct hisi_hba *hisi_hba)
3447 {
3448 	int queue_entry_size = sizeof(struct hisi_sas_cmd_hdr);
3449 	int dump_index = hisi_hba->debugfs_dump_index;
3450 	int i;
3451 
3452 	for (i = 0; i < hisi_hba->queue_count; i++) {
3453 		struct hisi_sas_cmd_hdr *debugfs_cmd_hdr, *cmd_hdr;
3454 		int j;
3455 
3456 		debugfs_cmd_hdr = hisi_hba->debugfs_dq[dump_index][i].hdr;
3457 		cmd_hdr = hisi_hba->cmd_hdr[i];
3458 
3459 		for (j = 0; j < HISI_SAS_QUEUE_SLOTS; j++)
3460 			memcpy(&debugfs_cmd_hdr[j], &cmd_hdr[j],
3461 			       queue_entry_size);
3462 	}
3463 }
3464 
3465 static void debugfs_snapshot_port_reg_v3_hw(struct hisi_hba *hisi_hba)
3466 {
3467 	int dump_index = hisi_hba->debugfs_dump_index;
3468 	const struct hisi_sas_debugfs_reg *port = &debugfs_port_reg;
3469 	int i, phy_cnt;
3470 	u32 offset;
3471 	u32 *databuf;
3472 
3473 	for (phy_cnt = 0; phy_cnt < hisi_hba->n_phy; phy_cnt++) {
3474 		databuf = hisi_hba->debugfs_port_reg[dump_index][phy_cnt].data;
3475 		for (i = 0; i < port->count; i++, databuf++) {
3476 			offset = port->base_off + 4 * i;
3477 			*databuf = hisi_sas_phy_read32(hisi_hba, phy_cnt,
3478 						       offset);
3479 		}
3480 	}
3481 }
3482 
3483 static void debugfs_snapshot_global_reg_v3_hw(struct hisi_hba *hisi_hba)
3484 {
3485 	int dump_index = hisi_hba->debugfs_dump_index;
3486 	u32 *databuf = hisi_hba->debugfs_regs[dump_index][DEBUGFS_GLOBAL].data;
3487 	int i;
3488 
3489 	for (i = 0; i < debugfs_global_reg.count; i++, databuf++)
3490 		*databuf = hisi_sas_read32(hisi_hba, 4 * i);
3491 }
3492 
3493 static void debugfs_snapshot_axi_reg_v3_hw(struct hisi_hba *hisi_hba)
3494 {
3495 	int dump_index = hisi_hba->debugfs_dump_index;
3496 	u32 *databuf = hisi_hba->debugfs_regs[dump_index][DEBUGFS_AXI].data;
3497 	const struct hisi_sas_debugfs_reg *axi = &debugfs_axi_reg;
3498 	int i;
3499 
3500 	for (i = 0; i < axi->count; i++, databuf++)
3501 		*databuf = hisi_sas_read32(hisi_hba, 4 * i + axi->base_off);
3502 }
3503 
3504 static void debugfs_snapshot_ras_reg_v3_hw(struct hisi_hba *hisi_hba)
3505 {
3506 	int dump_index = hisi_hba->debugfs_dump_index;
3507 	u32 *databuf = hisi_hba->debugfs_regs[dump_index][DEBUGFS_RAS].data;
3508 	const struct hisi_sas_debugfs_reg *ras = &debugfs_ras_reg;
3509 	int i;
3510 
3511 	for (i = 0; i < ras->count; i++, databuf++)
3512 		*databuf = hisi_sas_read32(hisi_hba, 4 * i + ras->base_off);
3513 }
3514 
3515 static void debugfs_snapshot_itct_reg_v3_hw(struct hisi_hba *hisi_hba)
3516 {
3517 	int dump_index = hisi_hba->debugfs_dump_index;
3518 	void *cachebuf = hisi_hba->debugfs_itct_cache[dump_index].cache;
3519 	void *databuf = hisi_hba->debugfs_itct[dump_index].itct;
3520 	struct hisi_sas_itct *itct;
3521 	int i;
3522 
3523 	read_iost_itct_cache_v3_hw(hisi_hba, HISI_SAS_ITCT_CACHE, cachebuf);
3524 
3525 	itct = hisi_hba->itct;
3526 
3527 	for (i = 0; i < HISI_SAS_MAX_ITCT_ENTRIES; i++, itct++) {
3528 		memcpy(databuf, itct, sizeof(struct hisi_sas_itct));
3529 		databuf += sizeof(struct hisi_sas_itct);
3530 	}
3531 }
3532 
3533 static void debugfs_snapshot_iost_reg_v3_hw(struct hisi_hba *hisi_hba)
3534 {
3535 	int dump_index = hisi_hba->debugfs_dump_index;
3536 	int max_command_entries = HISI_SAS_MAX_COMMANDS;
3537 	void *cachebuf = hisi_hba->debugfs_iost_cache[dump_index].cache;
3538 	void *databuf = hisi_hba->debugfs_iost[dump_index].iost;
3539 	struct hisi_sas_iost *iost;
3540 	int i;
3541 
3542 	read_iost_itct_cache_v3_hw(hisi_hba, HISI_SAS_IOST_CACHE, cachebuf);
3543 
3544 	iost = hisi_hba->iost;
3545 
3546 	for (i = 0; i < max_command_entries; i++, iost++) {
3547 		memcpy(databuf, iost, sizeof(struct hisi_sas_iost));
3548 		databuf += sizeof(struct hisi_sas_iost);
3549 	}
3550 }
3551 
3552 static const char *
3553 debugfs_to_reg_name_v3_hw(int off, int base_off,
3554 			  const struct hisi_sas_debugfs_reg_lu *lu)
3555 {
3556 	for (; lu->name; lu++) {
3557 		if (off == lu->off - base_off)
3558 			return lu->name;
3559 	}
3560 
3561 	return NULL;
3562 }
3563 
3564 static void debugfs_print_reg_v3_hw(u32 *regs_val, struct seq_file *s,
3565 				    const struct hisi_sas_debugfs_reg *reg)
3566 {
3567 	int i;
3568 
3569 	for (i = 0; i < reg->count; i++) {
3570 		int off = i * 4;
3571 		const char *name;
3572 
3573 		name = debugfs_to_reg_name_v3_hw(off, reg->base_off,
3574 						 reg->lu);
3575 
3576 		if (name)
3577 			seq_printf(s, "0x%08x 0x%08x %s\n", off,
3578 				   regs_val[i], name);
3579 		else
3580 			seq_printf(s, "0x%08x 0x%08x\n", off,
3581 				   regs_val[i]);
3582 	}
3583 }
3584 
3585 static int debugfs_global_v3_hw_show(struct seq_file *s, void *p)
3586 {
3587 	struct hisi_sas_debugfs_regs *global = s->private;
3588 
3589 	debugfs_print_reg_v3_hw(global->data, s,
3590 				&debugfs_global_reg);
3591 
3592 	return 0;
3593 }
3594 DEFINE_SHOW_ATTRIBUTE(debugfs_global_v3_hw);
3595 
3596 static int debugfs_axi_v3_hw_show(struct seq_file *s, void *p)
3597 {
3598 	struct hisi_sas_debugfs_regs *axi = s->private;
3599 
3600 	debugfs_print_reg_v3_hw(axi->data, s,
3601 				&debugfs_axi_reg);
3602 
3603 	return 0;
3604 }
3605 DEFINE_SHOW_ATTRIBUTE(debugfs_axi_v3_hw);
3606 
3607 static int debugfs_ras_v3_hw_show(struct seq_file *s, void *p)
3608 {
3609 	struct hisi_sas_debugfs_regs *ras = s->private;
3610 
3611 	debugfs_print_reg_v3_hw(ras->data, s,
3612 				&debugfs_ras_reg);
3613 
3614 	return 0;
3615 }
3616 DEFINE_SHOW_ATTRIBUTE(debugfs_ras_v3_hw);
3617 
3618 static int debugfs_port_v3_hw_show(struct seq_file *s, void *p)
3619 {
3620 	struct hisi_sas_debugfs_port *port = s->private;
3621 	const struct hisi_sas_debugfs_reg *reg_port = &debugfs_port_reg;
3622 
3623 	debugfs_print_reg_v3_hw(port->data, s, reg_port);
3624 
3625 	return 0;
3626 }
3627 DEFINE_SHOW_ATTRIBUTE(debugfs_port_v3_hw);
3628 
3629 static void debugfs_show_row_64_v3_hw(struct seq_file *s, int index,
3630 				      int sz, __le64 *ptr)
3631 {
3632 	int i;
3633 
3634 	/* completion header size not fixed per HW version */
3635 	seq_printf(s, "index %04d:\n\t", index);
3636 	for (i = 1; i <= sz / 8; i++, ptr++) {
3637 		seq_printf(s, " 0x%016llx", le64_to_cpu(*ptr));
3638 		if (!(i % 2))
3639 			seq_puts(s, "\n\t");
3640 	}
3641 
3642 	seq_puts(s, "\n");
3643 }
3644 
3645 static void debugfs_show_row_32_v3_hw(struct seq_file *s, int index,
3646 				      int sz, __le32 *ptr)
3647 {
3648 	int i;
3649 
3650 	/* completion header size not fixed per HW version */
3651 	seq_printf(s, "index %04d:\n\t", index);
3652 	for (i = 1; i <= sz / 4; i++, ptr++) {
3653 		seq_printf(s, " 0x%08x", le32_to_cpu(*ptr));
3654 		if (!(i % 4))
3655 			seq_puts(s, "\n\t");
3656 	}
3657 	seq_puts(s, "\n");
3658 }
3659 
3660 static void debugfs_cq_show_slot_v3_hw(struct seq_file *s, int slot,
3661 				       struct hisi_sas_debugfs_cq *debugfs_cq)
3662 {
3663 	struct hisi_sas_cq *cq = debugfs_cq->cq;
3664 	struct hisi_hba *hisi_hba = cq->hisi_hba;
3665 	__le32 *complete_hdr = debugfs_cq->complete_hdr +
3666 			       (hisi_hba->hw->complete_hdr_size * slot);
3667 
3668 	debugfs_show_row_32_v3_hw(s, slot,
3669 				  hisi_hba->hw->complete_hdr_size,
3670 				  complete_hdr);
3671 }
3672 
3673 static int debugfs_cq_v3_hw_show(struct seq_file *s, void *p)
3674 {
3675 	struct hisi_sas_debugfs_cq *debugfs_cq = s->private;
3676 	int slot;
3677 
3678 	for (slot = 0; slot < HISI_SAS_QUEUE_SLOTS; slot++)
3679 		debugfs_cq_show_slot_v3_hw(s, slot, debugfs_cq);
3680 
3681 	return 0;
3682 }
3683 DEFINE_SHOW_ATTRIBUTE(debugfs_cq_v3_hw);
3684 
3685 static void debugfs_dq_show_slot_v3_hw(struct seq_file *s, int slot,
3686 				       void *dq_ptr)
3687 {
3688 	struct hisi_sas_debugfs_dq *debugfs_dq = dq_ptr;
3689 	void *cmd_queue = debugfs_dq->hdr;
3690 	__le32 *cmd_hdr = cmd_queue +
3691 		sizeof(struct hisi_sas_cmd_hdr) * slot;
3692 
3693 	debugfs_show_row_32_v3_hw(s, slot, sizeof(struct hisi_sas_cmd_hdr),
3694 				  cmd_hdr);
3695 }
3696 
3697 static int debugfs_dq_v3_hw_show(struct seq_file *s, void *p)
3698 {
3699 	int slot;
3700 
3701 	for (slot = 0; slot < HISI_SAS_QUEUE_SLOTS; slot++)
3702 		debugfs_dq_show_slot_v3_hw(s, slot, s->private);
3703 
3704 	return 0;
3705 }
3706 DEFINE_SHOW_ATTRIBUTE(debugfs_dq_v3_hw);
3707 
3708 static int debugfs_iost_v3_hw_show(struct seq_file *s, void *p)
3709 {
3710 	struct hisi_sas_debugfs_iost *debugfs_iost = s->private;
3711 	struct hisi_sas_iost *iost = debugfs_iost->iost;
3712 	int i, max_command_entries = HISI_SAS_MAX_COMMANDS;
3713 
3714 	for (i = 0; i < max_command_entries; i++, iost++) {
3715 		__le64 *data = &iost->qw0;
3716 
3717 		debugfs_show_row_64_v3_hw(s, i, sizeof(*iost), data);
3718 	}
3719 
3720 	return 0;
3721 }
3722 DEFINE_SHOW_ATTRIBUTE(debugfs_iost_v3_hw);
3723 
3724 static int debugfs_iost_cache_v3_hw_show(struct seq_file *s, void *p)
3725 {
3726 	struct hisi_sas_debugfs_iost_cache *debugfs_iost_cache = s->private;
3727 	struct hisi_sas_iost_itct_cache *iost_cache =
3728 						debugfs_iost_cache->cache;
3729 	u32 cache_size = HISI_SAS_IOST_ITCT_CACHE_DW_SZ * 4;
3730 	int i, tab_idx;
3731 	__le64 *iost;
3732 
3733 	for (i = 0; i < HISI_SAS_IOST_ITCT_CACHE_NUM; i++, iost_cache++) {
3734 		/*
3735 		 * Data struct of IOST cache:
3736 		 * Data[1]: BIT0~15: Table index
3737 		 *	    Bit16:   Valid mask
3738 		 * Data[2]~[9]: IOST table
3739 		 */
3740 		tab_idx = (iost_cache->data[1] & 0xffff);
3741 		iost = (__le64 *)iost_cache;
3742 
3743 		debugfs_show_row_64_v3_hw(s, tab_idx, cache_size, iost);
3744 	}
3745 
3746 	return 0;
3747 }
3748 DEFINE_SHOW_ATTRIBUTE(debugfs_iost_cache_v3_hw);
3749 
3750 static int debugfs_itct_v3_hw_show(struct seq_file *s, void *p)
3751 {
3752 	int i;
3753 	struct hisi_sas_debugfs_itct *debugfs_itct = s->private;
3754 	struct hisi_sas_itct *itct = debugfs_itct->itct;
3755 
3756 	for (i = 0; i < HISI_SAS_MAX_ITCT_ENTRIES; i++, itct++) {
3757 		__le64 *data = &itct->qw0;
3758 
3759 		debugfs_show_row_64_v3_hw(s, i, sizeof(*itct), data);
3760 	}
3761 
3762 	return 0;
3763 }
3764 DEFINE_SHOW_ATTRIBUTE(debugfs_itct_v3_hw);
3765 
3766 static int debugfs_itct_cache_v3_hw_show(struct seq_file *s, void *p)
3767 {
3768 	struct hisi_sas_debugfs_itct_cache *debugfs_itct_cache = s->private;
3769 	struct hisi_sas_iost_itct_cache *itct_cache =
3770 						debugfs_itct_cache->cache;
3771 	u32 cache_size = HISI_SAS_IOST_ITCT_CACHE_DW_SZ * 4;
3772 	int i, tab_idx;
3773 	__le64 *itct;
3774 
3775 	for (i = 0; i < HISI_SAS_IOST_ITCT_CACHE_NUM; i++, itct_cache++) {
3776 		/*
3777 		 * Data struct of ITCT cache:
3778 		 * Data[1]: BIT0~15: Table index
3779 		 *	    Bit16:   Valid mask
3780 		 * Data[2]~[9]: ITCT table
3781 		 */
3782 		tab_idx = itct_cache->data[1] & 0xffff;
3783 		itct = (__le64 *)itct_cache;
3784 
3785 		debugfs_show_row_64_v3_hw(s, tab_idx, cache_size, itct);
3786 	}
3787 
3788 	return 0;
3789 }
3790 DEFINE_SHOW_ATTRIBUTE(debugfs_itct_cache_v3_hw);
3791 
3792 static void debugfs_create_files_v3_hw(struct hisi_hba *hisi_hba)
3793 {
3794 	u64 *debugfs_timestamp;
3795 	int dump_index = hisi_hba->debugfs_dump_index;
3796 	struct dentry *dump_dentry;
3797 	struct dentry *dentry;
3798 	char name[256];
3799 	int p;
3800 	int c;
3801 	int d;
3802 
3803 	snprintf(name, 256, "%d", dump_index);
3804 
3805 	dump_dentry = debugfs_create_dir(name, hisi_hba->debugfs_dump_dentry);
3806 
3807 	debugfs_timestamp = &hisi_hba->debugfs_timestamp[dump_index];
3808 
3809 	debugfs_create_u64("timestamp", 0400, dump_dentry,
3810 			   debugfs_timestamp);
3811 
3812 	debugfs_create_file("global", 0400, dump_dentry,
3813 			    &hisi_hba->debugfs_regs[dump_index][DEBUGFS_GLOBAL],
3814 			    &debugfs_global_v3_hw_fops);
3815 
3816 	/* Create port dir and files */
3817 	dentry = debugfs_create_dir("port", dump_dentry);
3818 	for (p = 0; p < hisi_hba->n_phy; p++) {
3819 		snprintf(name, 256, "%d", p);
3820 
3821 		debugfs_create_file(name, 0400, dentry,
3822 				    &hisi_hba->debugfs_port_reg[dump_index][p],
3823 				    &debugfs_port_v3_hw_fops);
3824 	}
3825 
3826 	/* Create CQ dir and files */
3827 	dentry = debugfs_create_dir("cq", dump_dentry);
3828 	for (c = 0; c < hisi_hba->queue_count; c++) {
3829 		snprintf(name, 256, "%d", c);
3830 
3831 		debugfs_create_file(name, 0400, dentry,
3832 				    &hisi_hba->debugfs_cq[dump_index][c],
3833 				    &debugfs_cq_v3_hw_fops);
3834 	}
3835 
3836 	/* Create DQ dir and files */
3837 	dentry = debugfs_create_dir("dq", dump_dentry);
3838 	for (d = 0; d < hisi_hba->queue_count; d++) {
3839 		snprintf(name, 256, "%d", d);
3840 
3841 		debugfs_create_file(name, 0400, dentry,
3842 				    &hisi_hba->debugfs_dq[dump_index][d],
3843 				    &debugfs_dq_v3_hw_fops);
3844 	}
3845 
3846 	debugfs_create_file("iost", 0400, dump_dentry,
3847 			    &hisi_hba->debugfs_iost[dump_index],
3848 			    &debugfs_iost_v3_hw_fops);
3849 
3850 	debugfs_create_file("iost_cache", 0400, dump_dentry,
3851 			    &hisi_hba->debugfs_iost_cache[dump_index],
3852 			    &debugfs_iost_cache_v3_hw_fops);
3853 
3854 	debugfs_create_file("itct", 0400, dump_dentry,
3855 			    &hisi_hba->debugfs_itct[dump_index],
3856 			    &debugfs_itct_v3_hw_fops);
3857 
3858 	debugfs_create_file("itct_cache", 0400, dump_dentry,
3859 			    &hisi_hba->debugfs_itct_cache[dump_index],
3860 			    &debugfs_itct_cache_v3_hw_fops);
3861 
3862 	debugfs_create_file("axi", 0400, dump_dentry,
3863 			    &hisi_hba->debugfs_regs[dump_index][DEBUGFS_AXI],
3864 			    &debugfs_axi_v3_hw_fops);
3865 
3866 	debugfs_create_file("ras", 0400, dump_dentry,
3867 			    &hisi_hba->debugfs_regs[dump_index][DEBUGFS_RAS],
3868 			    &debugfs_ras_v3_hw_fops);
3869 }
3870 
3871 static void debugfs_snapshot_regs_v3_hw(struct hisi_hba *hisi_hba)
3872 {
3873 	int debugfs_dump_index = hisi_hba->debugfs_dump_index;
3874 	struct device *dev = hisi_hba->dev;
3875 	u64 timestamp = local_clock();
3876 
3877 	if (debugfs_dump_index >= hisi_sas_debugfs_dump_count) {
3878 		dev_warn(dev, "dump count exceeded!\n");
3879 		return;
3880 	}
3881 
3882 	do_div(timestamp, NSEC_PER_MSEC);
3883 	hisi_hba->debugfs_timestamp[debugfs_dump_index] = timestamp;
3884 
3885 	debugfs_snapshot_prepare_v3_hw(hisi_hba);
3886 
3887 	debugfs_snapshot_global_reg_v3_hw(hisi_hba);
3888 	debugfs_snapshot_port_reg_v3_hw(hisi_hba);
3889 	debugfs_snapshot_axi_reg_v3_hw(hisi_hba);
3890 	debugfs_snapshot_ras_reg_v3_hw(hisi_hba);
3891 	debugfs_snapshot_cq_reg_v3_hw(hisi_hba);
3892 	debugfs_snapshot_dq_reg_v3_hw(hisi_hba);
3893 	debugfs_snapshot_itct_reg_v3_hw(hisi_hba);
3894 	debugfs_snapshot_iost_reg_v3_hw(hisi_hba);
3895 
3896 	debugfs_create_files_v3_hw(hisi_hba);
3897 
3898 	debugfs_snapshot_restore_v3_hw(hisi_hba);
3899 	hisi_hba->debugfs_dump_index++;
3900 }
3901 
3902 static ssize_t debugfs_trigger_dump_v3_hw_write(struct file *file,
3903 						const char __user *user_buf,
3904 						size_t count, loff_t *ppos)
3905 {
3906 	struct hisi_hba *hisi_hba = file->f_inode->i_private;
3907 	char buf[8];
3908 
3909 	if (hisi_hba->debugfs_dump_index >= hisi_sas_debugfs_dump_count)
3910 		return -EFAULT;
3911 
3912 	if (count > 8)
3913 		return -EFAULT;
3914 
3915 	if (copy_from_user(buf, user_buf, count))
3916 		return -EFAULT;
3917 
3918 	if (buf[0] != '1')
3919 		return -EFAULT;
3920 
3921 	queue_work(hisi_hba->wq, &hisi_hba->debugfs_work);
3922 
3923 	return count;
3924 }
3925 
3926 static const struct file_operations debugfs_trigger_dump_v3_hw_fops = {
3927 	.write = &debugfs_trigger_dump_v3_hw_write,
3928 	.owner = THIS_MODULE,
3929 };
3930 
3931 enum {
3932 	HISI_SAS_BIST_LOOPBACK_MODE_DIGITAL = 0,
3933 	HISI_SAS_BIST_LOOPBACK_MODE_SERDES,
3934 	HISI_SAS_BIST_LOOPBACK_MODE_REMOTE,
3935 };
3936 
3937 static const struct {
3938 	int		value;
3939 	char		*name;
3940 } debugfs_loop_linkrate_v3_hw[] = {
3941 	{ SAS_LINK_RATE_1_5_GBPS, "1.5 Gbit" },
3942 	{ SAS_LINK_RATE_3_0_GBPS, "3.0 Gbit" },
3943 	{ SAS_LINK_RATE_6_0_GBPS, "6.0 Gbit" },
3944 	{ SAS_LINK_RATE_12_0_GBPS, "12.0 Gbit" },
3945 };
3946 
3947 static int debugfs_bist_linkrate_v3_hw_show(struct seq_file *s, void *p)
3948 {
3949 	struct hisi_hba *hisi_hba = s->private;
3950 	int i;
3951 
3952 	for (i = 0; i < ARRAY_SIZE(debugfs_loop_linkrate_v3_hw); i++) {
3953 		int match = (hisi_hba->debugfs_bist_linkrate ==
3954 			     debugfs_loop_linkrate_v3_hw[i].value);
3955 
3956 		seq_printf(s, "%s%s%s ", match ? "[" : "",
3957 			   debugfs_loop_linkrate_v3_hw[i].name,
3958 			   match ? "]" : "");
3959 	}
3960 	seq_puts(s, "\n");
3961 
3962 	return 0;
3963 }
3964 
3965 static ssize_t debugfs_bist_linkrate_v3_hw_write(struct file *filp,
3966 						 const char __user *buf,
3967 						 size_t count, loff_t *ppos)
3968 {
3969 	struct seq_file *m = filp->private_data;
3970 	struct hisi_hba *hisi_hba = m->private;
3971 	char kbuf[16] = {}, *pkbuf;
3972 	bool found = false;
3973 	int i;
3974 
3975 	if (hisi_hba->debugfs_bist_enable)
3976 		return -EPERM;
3977 
3978 	if (count >= sizeof(kbuf))
3979 		return -EOVERFLOW;
3980 
3981 	if (copy_from_user(kbuf, buf, count))
3982 		return -EINVAL;
3983 
3984 	pkbuf = strstrip(kbuf);
3985 
3986 	for (i = 0; i < ARRAY_SIZE(debugfs_loop_linkrate_v3_hw); i++) {
3987 		if (!strncmp(debugfs_loop_linkrate_v3_hw[i].name,
3988 			     pkbuf, 16)) {
3989 			hisi_hba->debugfs_bist_linkrate =
3990 				debugfs_loop_linkrate_v3_hw[i].value;
3991 			found = true;
3992 			break;
3993 		}
3994 	}
3995 
3996 	if (!found)
3997 		return -EINVAL;
3998 
3999 	return count;
4000 }
4001 
4002 static int debugfs_bist_linkrate_v3_hw_open(struct inode *inode,
4003 					    struct file *filp)
4004 {
4005 	return single_open(filp, debugfs_bist_linkrate_v3_hw_show,
4006 			   inode->i_private);
4007 }
4008 
4009 static const struct file_operations debugfs_bist_linkrate_v3_hw_fops = {
4010 	.open = debugfs_bist_linkrate_v3_hw_open,
4011 	.read = seq_read,
4012 	.write = debugfs_bist_linkrate_v3_hw_write,
4013 	.llseek = seq_lseek,
4014 	.release = single_release,
4015 	.owner = THIS_MODULE,
4016 };
4017 
4018 static const struct {
4019 	int		value;
4020 	char		*name;
4021 } debugfs_loop_code_mode_v3_hw[] = {
4022 	{ HISI_SAS_BIST_CODE_MODE_PRBS7, "PRBS7" },
4023 	{ HISI_SAS_BIST_CODE_MODE_PRBS23, "PRBS23" },
4024 	{ HISI_SAS_BIST_CODE_MODE_PRBS31, "PRBS31" },
4025 	{ HISI_SAS_BIST_CODE_MODE_JTPAT, "JTPAT" },
4026 	{ HISI_SAS_BIST_CODE_MODE_CJTPAT, "CJTPAT" },
4027 	{ HISI_SAS_BIST_CODE_MODE_SCRAMBED_0, "SCRAMBED_0" },
4028 	{ HISI_SAS_BIST_CODE_MODE_TRAIN, "TRAIN" },
4029 	{ HISI_SAS_BIST_CODE_MODE_TRAIN_DONE, "TRAIN_DONE" },
4030 	{ HISI_SAS_BIST_CODE_MODE_HFTP, "HFTP" },
4031 	{ HISI_SAS_BIST_CODE_MODE_MFTP, "MFTP" },
4032 	{ HISI_SAS_BIST_CODE_MODE_LFTP, "LFTP" },
4033 	{ HISI_SAS_BIST_CODE_MODE_FIXED_DATA, "FIXED_DATA" },
4034 };
4035 
4036 static int debugfs_bist_code_mode_v3_hw_show(struct seq_file *s, void *p)
4037 {
4038 	struct hisi_hba *hisi_hba = s->private;
4039 	int i;
4040 
4041 	for (i = 0; i < ARRAY_SIZE(debugfs_loop_code_mode_v3_hw); i++) {
4042 		int match = (hisi_hba->debugfs_bist_code_mode ==
4043 			     debugfs_loop_code_mode_v3_hw[i].value);
4044 
4045 		seq_printf(s, "%s%s%s ", match ? "[" : "",
4046 			   debugfs_loop_code_mode_v3_hw[i].name,
4047 			   match ? "]" : "");
4048 	}
4049 	seq_puts(s, "\n");
4050 
4051 	return 0;
4052 }
4053 
4054 static ssize_t debugfs_bist_code_mode_v3_hw_write(struct file *filp,
4055 						  const char __user *buf,
4056 						  size_t count,
4057 						  loff_t *ppos)
4058 {
4059 	struct seq_file *m = filp->private_data;
4060 	struct hisi_hba *hisi_hba = m->private;
4061 	char kbuf[16] = {}, *pkbuf;
4062 	bool found = false;
4063 	int i;
4064 
4065 	if (hisi_hba->debugfs_bist_enable)
4066 		return -EPERM;
4067 
4068 	if (count >= sizeof(kbuf))
4069 		return -EINVAL;
4070 
4071 	if (copy_from_user(kbuf, buf, count))
4072 		return -EOVERFLOW;
4073 
4074 	pkbuf = strstrip(kbuf);
4075 
4076 	for (i = 0; i < ARRAY_SIZE(debugfs_loop_code_mode_v3_hw); i++) {
4077 		if (!strncmp(debugfs_loop_code_mode_v3_hw[i].name,
4078 			     pkbuf, 16)) {
4079 			hisi_hba->debugfs_bist_code_mode =
4080 				debugfs_loop_code_mode_v3_hw[i].value;
4081 			found = true;
4082 			break;
4083 		}
4084 	}
4085 
4086 	if (!found)
4087 		return -EINVAL;
4088 
4089 	return count;
4090 }
4091 
4092 static int debugfs_bist_code_mode_v3_hw_open(struct inode *inode,
4093 					     struct file *filp)
4094 {
4095 	return single_open(filp, debugfs_bist_code_mode_v3_hw_show,
4096 			   inode->i_private);
4097 }
4098 
4099 static const struct file_operations debugfs_bist_code_mode_v3_hw_fops = {
4100 	.open = debugfs_bist_code_mode_v3_hw_open,
4101 	.read = seq_read,
4102 	.write = debugfs_bist_code_mode_v3_hw_write,
4103 	.llseek = seq_lseek,
4104 	.release = single_release,
4105 	.owner = THIS_MODULE,
4106 };
4107 
4108 static ssize_t debugfs_bist_phy_v3_hw_write(struct file *filp,
4109 					    const char __user *buf,
4110 					    size_t count, loff_t *ppos)
4111 {
4112 	struct seq_file *m = filp->private_data;
4113 	struct hisi_hba *hisi_hba = m->private;
4114 	unsigned int phy_no;
4115 	int val;
4116 
4117 	if (hisi_hba->debugfs_bist_enable)
4118 		return -EPERM;
4119 
4120 	val = kstrtouint_from_user(buf, count, 0, &phy_no);
4121 	if (val)
4122 		return val;
4123 
4124 	if (phy_no >= hisi_hba->n_phy)
4125 		return -EINVAL;
4126 
4127 	hisi_hba->debugfs_bist_phy_no = phy_no;
4128 
4129 	return count;
4130 }
4131 
4132 static int debugfs_bist_phy_v3_hw_show(struct seq_file *s, void *p)
4133 {
4134 	struct hisi_hba *hisi_hba = s->private;
4135 
4136 	seq_printf(s, "%d\n", hisi_hba->debugfs_bist_phy_no);
4137 
4138 	return 0;
4139 }
4140 
4141 static int debugfs_bist_phy_v3_hw_open(struct inode *inode,
4142 				       struct file *filp)
4143 {
4144 	return single_open(filp, debugfs_bist_phy_v3_hw_show,
4145 			   inode->i_private);
4146 }
4147 
4148 static const struct file_operations debugfs_bist_phy_v3_hw_fops = {
4149 	.open = debugfs_bist_phy_v3_hw_open,
4150 	.read = seq_read,
4151 	.write = debugfs_bist_phy_v3_hw_write,
4152 	.llseek = seq_lseek,
4153 	.release = single_release,
4154 	.owner = THIS_MODULE,
4155 };
4156 
4157 static ssize_t debugfs_bist_cnt_v3_hw_write(struct file *filp,
4158 					const char __user *buf,
4159 					size_t count, loff_t *ppos)
4160 {
4161 	struct seq_file *m = filp->private_data;
4162 	struct hisi_hba *hisi_hba = m->private;
4163 	unsigned int cnt;
4164 	int val;
4165 
4166 	if (hisi_hba->debugfs_bist_enable)
4167 		return -EPERM;
4168 
4169 	val = kstrtouint_from_user(buf, count, 0, &cnt);
4170 	if (val)
4171 		return val;
4172 
4173 	if (cnt)
4174 		return -EINVAL;
4175 
4176 	hisi_hba->debugfs_bist_cnt = 0;
4177 	return count;
4178 }
4179 
4180 static int debugfs_bist_cnt_v3_hw_show(struct seq_file *s, void *p)
4181 {
4182 	struct hisi_hba *hisi_hba = s->private;
4183 
4184 	seq_printf(s, "%u\n", hisi_hba->debugfs_bist_cnt);
4185 
4186 	return 0;
4187 }
4188 
4189 static int debugfs_bist_cnt_v3_hw_open(struct inode *inode,
4190 					  struct file *filp)
4191 {
4192 	return single_open(filp, debugfs_bist_cnt_v3_hw_show,
4193 			   inode->i_private);
4194 }
4195 
4196 static const struct file_operations debugfs_bist_cnt_v3_hw_ops = {
4197 	.open = debugfs_bist_cnt_v3_hw_open,
4198 	.read = seq_read,
4199 	.write = debugfs_bist_cnt_v3_hw_write,
4200 	.llseek = seq_lseek,
4201 	.release = single_release,
4202 	.owner = THIS_MODULE,
4203 };
4204 
4205 static const struct {
4206 	int		value;
4207 	char		*name;
4208 } debugfs_loop_modes_v3_hw[] = {
4209 	{ HISI_SAS_BIST_LOOPBACK_MODE_DIGITAL, "digital" },
4210 	{ HISI_SAS_BIST_LOOPBACK_MODE_SERDES, "serdes" },
4211 	{ HISI_SAS_BIST_LOOPBACK_MODE_REMOTE, "remote" },
4212 };
4213 
4214 static int debugfs_bist_mode_v3_hw_show(struct seq_file *s, void *p)
4215 {
4216 	struct hisi_hba *hisi_hba = s->private;
4217 	int i;
4218 
4219 	for (i = 0; i < ARRAY_SIZE(debugfs_loop_modes_v3_hw); i++) {
4220 		int match = (hisi_hba->debugfs_bist_mode ==
4221 			     debugfs_loop_modes_v3_hw[i].value);
4222 
4223 		seq_printf(s, "%s%s%s ", match ? "[" : "",
4224 			   debugfs_loop_modes_v3_hw[i].name,
4225 			   match ? "]" : "");
4226 	}
4227 	seq_puts(s, "\n");
4228 
4229 	return 0;
4230 }
4231 
4232 static ssize_t debugfs_bist_mode_v3_hw_write(struct file *filp,
4233 					     const char __user *buf,
4234 					     size_t count, loff_t *ppos)
4235 {
4236 	struct seq_file *m = filp->private_data;
4237 	struct hisi_hba *hisi_hba = m->private;
4238 	char kbuf[16] = {}, *pkbuf;
4239 	bool found = false;
4240 	int i;
4241 
4242 	if (hisi_hba->debugfs_bist_enable)
4243 		return -EPERM;
4244 
4245 	if (count >= sizeof(kbuf))
4246 		return -EINVAL;
4247 
4248 	if (copy_from_user(kbuf, buf, count))
4249 		return -EOVERFLOW;
4250 
4251 	pkbuf = strstrip(kbuf);
4252 
4253 	for (i = 0; i < ARRAY_SIZE(debugfs_loop_modes_v3_hw); i++) {
4254 		if (!strncmp(debugfs_loop_modes_v3_hw[i].name, pkbuf, 16)) {
4255 			hisi_hba->debugfs_bist_mode =
4256 				debugfs_loop_modes_v3_hw[i].value;
4257 			found = true;
4258 			break;
4259 		}
4260 	}
4261 
4262 	if (!found)
4263 		return -EINVAL;
4264 
4265 	return count;
4266 }
4267 
4268 static int debugfs_bist_mode_v3_hw_open(struct inode *inode,
4269 					struct file *filp)
4270 {
4271 	return single_open(filp, debugfs_bist_mode_v3_hw_show,
4272 			   inode->i_private);
4273 }
4274 
4275 static const struct file_operations debugfs_bist_mode_v3_hw_fops = {
4276 	.open = debugfs_bist_mode_v3_hw_open,
4277 	.read = seq_read,
4278 	.write = debugfs_bist_mode_v3_hw_write,
4279 	.llseek = seq_lseek,
4280 	.release = single_release,
4281 	.owner = THIS_MODULE,
4282 };
4283 
4284 static ssize_t debugfs_bist_enable_v3_hw_write(struct file *filp,
4285 					       const char __user *buf,
4286 					       size_t count, loff_t *ppos)
4287 {
4288 	struct seq_file *m = filp->private_data;
4289 	struct hisi_hba *hisi_hba = m->private;
4290 	unsigned int enable;
4291 	int val;
4292 
4293 	val = kstrtouint_from_user(buf, count, 0, &enable);
4294 	if (val)
4295 		return val;
4296 
4297 	if (enable > 1)
4298 		return -EINVAL;
4299 
4300 	if (enable == hisi_hba->debugfs_bist_enable)
4301 		return count;
4302 
4303 	val = debugfs_set_bist_v3_hw(hisi_hba, enable);
4304 	if (val < 0)
4305 		return val;
4306 
4307 	hisi_hba->debugfs_bist_enable = enable;
4308 
4309 	return count;
4310 }
4311 
4312 static int debugfs_bist_enable_v3_hw_show(struct seq_file *s, void *p)
4313 {
4314 	struct hisi_hba *hisi_hba = s->private;
4315 
4316 	seq_printf(s, "%d\n", hisi_hba->debugfs_bist_enable);
4317 
4318 	return 0;
4319 }
4320 
4321 static int debugfs_bist_enable_v3_hw_open(struct inode *inode,
4322 					  struct file *filp)
4323 {
4324 	return single_open(filp, debugfs_bist_enable_v3_hw_show,
4325 			   inode->i_private);
4326 }
4327 
4328 static const struct file_operations debugfs_bist_enable_v3_hw_fops = {
4329 	.open = debugfs_bist_enable_v3_hw_open,
4330 	.read = seq_read,
4331 	.write = debugfs_bist_enable_v3_hw_write,
4332 	.llseek = seq_lseek,
4333 	.release = single_release,
4334 	.owner = THIS_MODULE,
4335 };
4336 
4337 static const struct {
4338 	char *name;
4339 } debugfs_ffe_name_v3_hw[FFE_CFG_MAX] = {
4340 	{ "SAS_1_5_GBPS" },
4341 	{ "SAS_3_0_GBPS" },
4342 	{ "SAS_6_0_GBPS" },
4343 	{ "SAS_12_0_GBPS" },
4344 	{ "FFE_RESV" },
4345 	{ "SATA_1_5_GBPS" },
4346 	{ "SATA_3_0_GBPS" },
4347 	{ "SATA_6_0_GBPS" },
4348 };
4349 
4350 static ssize_t debugfs_v3_hw_write(struct file *filp,
4351 				   const char __user *buf,
4352 				   size_t count, loff_t *ppos)
4353 {
4354 	struct seq_file *m = filp->private_data;
4355 	u32 *val = m->private;
4356 	int res;
4357 
4358 	res = kstrtouint_from_user(buf, count, 0, val);
4359 	if (res)
4360 		return res;
4361 
4362 	return count;
4363 }
4364 
4365 static int debugfs_v3_hw_show(struct seq_file *s, void *p)
4366 {
4367 	u32 *val = s->private;
4368 
4369 	seq_printf(s, "0x%x\n", *val);
4370 
4371 	return 0;
4372 }
4373 
4374 static int debugfs_v3_hw_open(struct inode *inode, struct file *filp)
4375 {
4376 	return single_open(filp, debugfs_v3_hw_show,
4377 			   inode->i_private);
4378 }
4379 
4380 static const struct file_operations debugfs_v3_hw_fops = {
4381 	.open = debugfs_v3_hw_open,
4382 	.read = seq_read,
4383 	.write = debugfs_v3_hw_write,
4384 	.llseek = seq_lseek,
4385 	.release = single_release,
4386 	.owner = THIS_MODULE,
4387 };
4388 
4389 static ssize_t debugfs_phy_down_cnt_v3_hw_write(struct file *filp,
4390 						const char __user *buf,
4391 						size_t count, loff_t *ppos)
4392 {
4393 	struct seq_file *s = filp->private_data;
4394 	struct hisi_sas_phy *phy = s->private;
4395 	unsigned int set_val;
4396 	int res;
4397 
4398 	res = kstrtouint_from_user(buf, count, 0, &set_val);
4399 	if (res)
4400 		return res;
4401 
4402 	if (set_val > 0)
4403 		return -EINVAL;
4404 
4405 	atomic_set(&phy->down_cnt, 0);
4406 
4407 	return count;
4408 }
4409 
4410 static int debugfs_phy_down_cnt_v3_hw_show(struct seq_file *s, void *p)
4411 {
4412 	struct hisi_sas_phy *phy = s->private;
4413 
4414 	seq_printf(s, "%d\n", atomic_read(&phy->down_cnt));
4415 
4416 	return 0;
4417 }
4418 
4419 static int debugfs_phy_down_cnt_v3_hw_open(struct inode *inode,
4420 					   struct file *filp)
4421 {
4422 	return single_open(filp, debugfs_phy_down_cnt_v3_hw_show,
4423 			   inode->i_private);
4424 }
4425 
4426 static const struct file_operations debugfs_phy_down_cnt_v3_hw_fops = {
4427 	.open = debugfs_phy_down_cnt_v3_hw_open,
4428 	.read = seq_read,
4429 	.write = debugfs_phy_down_cnt_v3_hw_write,
4430 	.llseek = seq_lseek,
4431 	.release = single_release,
4432 	.owner = THIS_MODULE,
4433 };
4434 
4435 enum fifo_dump_mode_v3_hw {
4436 	FIFO_DUMP_FORVER =		(1U << 0),
4437 	FIFO_DUMP_AFTER_TRIGGER =	(1U << 1),
4438 	FIFO_DUMP_UNTILL_TRIGGER =	(1U << 2),
4439 };
4440 
4441 enum fifo_trigger_mode_v3_hw {
4442 	FIFO_TRIGGER_EDGE =		(1U << 0),
4443 	FIFO_TRIGGER_SAME_LEVEL =	(1U << 1),
4444 	FIFO_TRIGGER_DIFF_LEVEL =	(1U << 2),
4445 };
4446 
4447 static int debugfs_is_fifo_config_valid_v3_hw(struct hisi_sas_phy *phy)
4448 {
4449 	struct hisi_hba *hisi_hba = phy->hisi_hba;
4450 
4451 	if (phy->fifo.signal_sel > 0xf) {
4452 		dev_info(hisi_hba->dev, "Invalid signal select: %u\n",
4453 			 phy->fifo.signal_sel);
4454 		return -EINVAL;
4455 	}
4456 
4457 	switch (phy->fifo.dump_mode) {
4458 	case FIFO_DUMP_FORVER:
4459 	case FIFO_DUMP_AFTER_TRIGGER:
4460 	case FIFO_DUMP_UNTILL_TRIGGER:
4461 		break;
4462 	default:
4463 		dev_info(hisi_hba->dev, "Invalid dump mode: %u\n",
4464 			 phy->fifo.dump_mode);
4465 		return -EINVAL;
4466 	}
4467 
4468 	/* when FIFO_DUMP_FORVER, no need to check trigger_mode */
4469 	if (phy->fifo.dump_mode == FIFO_DUMP_FORVER)
4470 		return 0;
4471 
4472 	switch (phy->fifo.trigger_mode) {
4473 	case FIFO_TRIGGER_EDGE:
4474 	case FIFO_TRIGGER_SAME_LEVEL:
4475 	case FIFO_TRIGGER_DIFF_LEVEL:
4476 		break;
4477 	default:
4478 		dev_info(hisi_hba->dev, "Invalid trigger mode: %u\n",
4479 			 phy->fifo.trigger_mode);
4480 		return -EINVAL;
4481 	}
4482 	return 0;
4483 }
4484 
4485 static int debugfs_update_fifo_config_v3_hw(struct hisi_sas_phy *phy)
4486 {
4487 	u32 trigger_mode = phy->fifo.trigger_mode;
4488 	u32 signal_sel = phy->fifo.signal_sel;
4489 	u32 dump_mode = phy->fifo.dump_mode;
4490 	struct hisi_hba *hisi_hba = phy->hisi_hba;
4491 	int phy_no = phy->sas_phy.id;
4492 	u32 reg_val;
4493 	int res;
4494 
4495 	/* Check the validity of trace FIFO configuration */
4496 	res = debugfs_is_fifo_config_valid_v3_hw(phy);
4497 	if (res)
4498 		return res;
4499 
4500 	reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4501 	/* Disable trace FIFO before update configuration */
4502 	reg_val |= DFX_FIFO_CTRL_DUMP_DISABLE_MSK;
4503 
4504 	/* Update trace FIFO configuration */
4505 	reg_val &= ~(DFX_FIFO_CTRL_DUMP_MODE_MSK |
4506 		     DFX_FIFO_CTRL_SIGNAL_SEL_MSK |
4507 		     DFX_FIFO_CTRL_TRIGGER_MODE_MSK);
4508 
4509 	reg_val |= ((trigger_mode << DFX_FIFO_CTRL_TRIGGER_MODE_OFF) |
4510 		    (dump_mode << DFX_FIFO_CTRL_DUMP_MODE_OFF) |
4511 		    (signal_sel << DFX_FIFO_CTRL_SIGNAL_SEL_OFF));
4512 	hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, reg_val);
4513 
4514 	hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_DUMP_MSK,
4515 			     phy->fifo.dump_msk);
4516 
4517 	hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_TRIGGER,
4518 			     phy->fifo.trigger);
4519 
4520 	hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_TRIGGER_MSK,
4521 			     phy->fifo.trigger_msk);
4522 
4523 	/* Enable trace FIFO after updated configuration */
4524 	reg_val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4525 	reg_val &= ~DFX_FIFO_CTRL_DUMP_DISABLE_MSK;
4526 	hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, reg_val);
4527 
4528 	return 0;
4529 }
4530 
4531 static ssize_t debugfs_fifo_update_cfg_v3_hw_write(struct file *filp,
4532 						   const char __user *buf,
4533 						   size_t count, loff_t *ppos)
4534 {
4535 	struct hisi_sas_phy *phy = filp->private_data;
4536 	bool update;
4537 	int val;
4538 
4539 	val = kstrtobool_from_user(buf, count, &update);
4540 	if (val)
4541 		return val;
4542 
4543 	if (update != 1)
4544 		return -EINVAL;
4545 
4546 	val = debugfs_update_fifo_config_v3_hw(phy);
4547 	if (val)
4548 		return val;
4549 
4550 	return count;
4551 }
4552 
4553 static const struct file_operations debugfs_fifo_update_cfg_v3_hw_fops = {
4554 	.open = simple_open,
4555 	.write = debugfs_fifo_update_cfg_v3_hw_write,
4556 	.owner = THIS_MODULE,
4557 };
4558 
4559 static void debugfs_read_fifo_data_v3_hw(struct hisi_sas_phy *phy)
4560 {
4561 	struct hisi_hba *hisi_hba = phy->hisi_hba;
4562 	u32 *buf = phy->fifo.rd_data;
4563 	int phy_no = phy->sas_phy.id;
4564 	u32 val;
4565 	int i;
4566 
4567 	memset(buf, 0, sizeof(phy->fifo.rd_data));
4568 
4569 	/* Disable trace FIFO before read data */
4570 	val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4571 	val |= DFX_FIFO_CTRL_DUMP_DISABLE_MSK;
4572 	hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, val);
4573 
4574 	for (i = 0; i < HISI_SAS_FIFO_DATA_DW_SIZE; i++) {
4575 		val = hisi_sas_phy_read32(hisi_hba, phy_no,
4576 					  DFX_FIFO_RD_DATA);
4577 		buf[i] = val;
4578 	}
4579 
4580 	/* Enable trace FIFO after read data */
4581 	val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4582 	val &= ~DFX_FIFO_CTRL_DUMP_DISABLE_MSK;
4583 	hisi_sas_phy_write32(hisi_hba, phy_no, DFX_FIFO_CTRL, val);
4584 }
4585 
4586 static int debugfs_fifo_data_v3_hw_show(struct seq_file *s, void *p)
4587 {
4588 	struct hisi_sas_phy *phy = s->private;
4589 
4590 	debugfs_read_fifo_data_v3_hw(phy);
4591 
4592 	debugfs_show_row_32_v3_hw(s, 0, HISI_SAS_FIFO_DATA_DW_SIZE * 4,
4593 				  (__le32 *)phy->fifo.rd_data);
4594 
4595 	return 0;
4596 }
4597 DEFINE_SHOW_ATTRIBUTE(debugfs_fifo_data_v3_hw);
4598 
4599 static void debugfs_fifo_init_v3_hw(struct hisi_hba *hisi_hba)
4600 {
4601 	int phy_no;
4602 
4603 	hisi_hba->debugfs_fifo_dentry =
4604 			debugfs_create_dir("fifo", hisi_hba->debugfs_dir);
4605 
4606 	for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
4607 		struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
4608 		struct dentry *port_dentry;
4609 		char name[256];
4610 		u32 val;
4611 
4612 		/* get default configuration for trace FIFO */
4613 		val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4614 		val &= DFX_FIFO_CTRL_DUMP_MODE_MSK;
4615 		val >>= DFX_FIFO_CTRL_DUMP_MODE_OFF;
4616 		phy->fifo.dump_mode = val;
4617 
4618 		val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4619 		val &= DFX_FIFO_CTRL_TRIGGER_MODE_MSK;
4620 		val >>= DFX_FIFO_CTRL_TRIGGER_MODE_OFF;
4621 		phy->fifo.trigger_mode = val;
4622 
4623 		val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_CTRL);
4624 		val &= DFX_FIFO_CTRL_SIGNAL_SEL_MSK;
4625 		val >>= DFX_FIFO_CTRL_SIGNAL_SEL_OFF;
4626 		phy->fifo.signal_sel = val;
4627 
4628 		val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_DUMP_MSK);
4629 		phy->fifo.dump_msk = val;
4630 
4631 		val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_TRIGGER);
4632 		phy->fifo.trigger = val;
4633 		val = hisi_sas_phy_read32(hisi_hba, phy_no, DFX_FIFO_TRIGGER_MSK);
4634 		phy->fifo.trigger_msk = val;
4635 
4636 		snprintf(name, 256, "%d", phy_no);
4637 		port_dentry = debugfs_create_dir(name,
4638 						 hisi_hba->debugfs_fifo_dentry);
4639 
4640 		debugfs_create_file("update_config", 0200, port_dentry, phy,
4641 				    &debugfs_fifo_update_cfg_v3_hw_fops);
4642 
4643 		debugfs_create_file("signal_sel", 0600, port_dentry,
4644 				    &phy->fifo.signal_sel,
4645 				    &debugfs_v3_hw_fops);
4646 
4647 		debugfs_create_file("dump_msk", 0600, port_dentry,
4648 				    &phy->fifo.dump_msk,
4649 				    &debugfs_v3_hw_fops);
4650 
4651 		debugfs_create_file("dump_mode", 0600, port_dentry,
4652 				    &phy->fifo.dump_mode,
4653 				    &debugfs_v3_hw_fops);
4654 
4655 		debugfs_create_file("trigger_mode", 0600, port_dentry,
4656 				    &phy->fifo.trigger_mode,
4657 				    &debugfs_v3_hw_fops);
4658 
4659 		debugfs_create_file("trigger", 0600, port_dentry,
4660 				    &phy->fifo.trigger,
4661 				    &debugfs_v3_hw_fops);
4662 
4663 		debugfs_create_file("trigger_msk", 0600, port_dentry,
4664 				    &phy->fifo.trigger_msk,
4665 				    &debugfs_v3_hw_fops);
4666 
4667 		debugfs_create_file("fifo_data", 0400, port_dentry, phy,
4668 				    &debugfs_fifo_data_v3_hw_fops);
4669 	}
4670 }
4671 
4672 static void debugfs_work_handler_v3_hw(struct work_struct *work)
4673 {
4674 	struct hisi_hba *hisi_hba =
4675 		container_of(work, struct hisi_hba, debugfs_work);
4676 
4677 	debugfs_snapshot_regs_v3_hw(hisi_hba);
4678 }
4679 
4680 static void debugfs_release_v3_hw(struct hisi_hba *hisi_hba, int dump_index)
4681 {
4682 	struct device *dev = hisi_hba->dev;
4683 	int i;
4684 
4685 	devm_kfree(dev, hisi_hba->debugfs_iost_cache[dump_index].cache);
4686 	devm_kfree(dev, hisi_hba->debugfs_itct_cache[dump_index].cache);
4687 	devm_kfree(dev, hisi_hba->debugfs_iost[dump_index].iost);
4688 	devm_kfree(dev, hisi_hba->debugfs_itct[dump_index].itct);
4689 
4690 	for (i = 0; i < hisi_hba->queue_count; i++)
4691 		devm_kfree(dev, hisi_hba->debugfs_dq[dump_index][i].hdr);
4692 
4693 	for (i = 0; i < hisi_hba->queue_count; i++)
4694 		devm_kfree(dev,
4695 			   hisi_hba->debugfs_cq[dump_index][i].complete_hdr);
4696 
4697 	for (i = 0; i < DEBUGFS_REGS_NUM; i++)
4698 		devm_kfree(dev, hisi_hba->debugfs_regs[dump_index][i].data);
4699 
4700 	for (i = 0; i < hisi_hba->n_phy; i++)
4701 		devm_kfree(dev, hisi_hba->debugfs_port_reg[dump_index][i].data);
4702 }
4703 
4704 static const struct hisi_sas_debugfs_reg *debugfs_reg_array_v3_hw[DEBUGFS_REGS_NUM] = {
4705 	[DEBUGFS_GLOBAL] = &debugfs_global_reg,
4706 	[DEBUGFS_AXI] = &debugfs_axi_reg,
4707 	[DEBUGFS_RAS] = &debugfs_ras_reg,
4708 };
4709 
4710 static int debugfs_alloc_v3_hw(struct hisi_hba *hisi_hba, int dump_index)
4711 {
4712 	const struct hisi_sas_hw *hw = hisi_hba->hw;
4713 	struct device *dev = hisi_hba->dev;
4714 	int p, c, d, r, i;
4715 	size_t sz;
4716 
4717 	for (r = 0; r < DEBUGFS_REGS_NUM; r++) {
4718 		struct hisi_sas_debugfs_regs *regs =
4719 				&hisi_hba->debugfs_regs[dump_index][r];
4720 
4721 		sz = debugfs_reg_array_v3_hw[r]->count * 4;
4722 		regs->data = devm_kmalloc(dev, sz, GFP_KERNEL);
4723 		if (!regs->data)
4724 			goto fail;
4725 		regs->hisi_hba = hisi_hba;
4726 	}
4727 
4728 	sz = debugfs_port_reg.count * 4;
4729 	for (p = 0; p < hisi_hba->n_phy; p++) {
4730 		struct hisi_sas_debugfs_port *port =
4731 				&hisi_hba->debugfs_port_reg[dump_index][p];
4732 
4733 		port->data = devm_kmalloc(dev, sz, GFP_KERNEL);
4734 		if (!port->data)
4735 			goto fail;
4736 		port->phy = &hisi_hba->phy[p];
4737 	}
4738 
4739 	sz = hw->complete_hdr_size * HISI_SAS_QUEUE_SLOTS;
4740 	for (c = 0; c < hisi_hba->queue_count; c++) {
4741 		struct hisi_sas_debugfs_cq *cq =
4742 				&hisi_hba->debugfs_cq[dump_index][c];
4743 
4744 		cq->complete_hdr = devm_kmalloc(dev, sz, GFP_KERNEL);
4745 		if (!cq->complete_hdr)
4746 			goto fail;
4747 		cq->cq = &hisi_hba->cq[c];
4748 	}
4749 
4750 	sz = sizeof(struct hisi_sas_cmd_hdr) * HISI_SAS_QUEUE_SLOTS;
4751 	for (d = 0; d < hisi_hba->queue_count; d++) {
4752 		struct hisi_sas_debugfs_dq *dq =
4753 				&hisi_hba->debugfs_dq[dump_index][d];
4754 
4755 		dq->hdr = devm_kmalloc(dev, sz, GFP_KERNEL);
4756 		if (!dq->hdr)
4757 			goto fail;
4758 		dq->dq = &hisi_hba->dq[d];
4759 	}
4760 
4761 	sz = HISI_SAS_MAX_COMMANDS * sizeof(struct hisi_sas_iost);
4762 
4763 	hisi_hba->debugfs_iost[dump_index].iost =
4764 				devm_kmalloc(dev, sz, GFP_KERNEL);
4765 	if (!hisi_hba->debugfs_iost[dump_index].iost)
4766 		goto fail;
4767 
4768 	sz = HISI_SAS_IOST_ITCT_CACHE_NUM *
4769 	     sizeof(struct hisi_sas_iost_itct_cache);
4770 
4771 	hisi_hba->debugfs_iost_cache[dump_index].cache =
4772 				devm_kmalloc(dev, sz, GFP_KERNEL);
4773 	if (!hisi_hba->debugfs_iost_cache[dump_index].cache)
4774 		goto fail;
4775 
4776 	sz = HISI_SAS_IOST_ITCT_CACHE_NUM *
4777 	     sizeof(struct hisi_sas_iost_itct_cache);
4778 
4779 	hisi_hba->debugfs_itct_cache[dump_index].cache =
4780 				devm_kmalloc(dev, sz, GFP_KERNEL);
4781 	if (!hisi_hba->debugfs_itct_cache[dump_index].cache)
4782 		goto fail;
4783 
4784 	/* New memory allocation must be locate before itct */
4785 	sz = HISI_SAS_MAX_ITCT_ENTRIES * sizeof(struct hisi_sas_itct);
4786 
4787 	hisi_hba->debugfs_itct[dump_index].itct =
4788 				devm_kmalloc(dev, sz, GFP_KERNEL);
4789 	if (!hisi_hba->debugfs_itct[dump_index].itct)
4790 		goto fail;
4791 
4792 	return 0;
4793 fail:
4794 	for (i = 0; i < hisi_sas_debugfs_dump_count; i++)
4795 		debugfs_release_v3_hw(hisi_hba, i);
4796 	return -ENOMEM;
4797 }
4798 
4799 static void debugfs_phy_down_cnt_init_v3_hw(struct hisi_hba *hisi_hba)
4800 {
4801 	struct dentry *dir = debugfs_create_dir("phy_down_cnt",
4802 						hisi_hba->debugfs_dir);
4803 	char name[16];
4804 	int phy_no;
4805 
4806 	for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
4807 		snprintf(name, 16, "%d", phy_no);
4808 		debugfs_create_file(name, 0600, dir,
4809 				    &hisi_hba->phy[phy_no],
4810 				    &debugfs_phy_down_cnt_v3_hw_fops);
4811 	}
4812 }
4813 
4814 static void debugfs_bist_init_v3_hw(struct hisi_hba *hisi_hba)
4815 {
4816 	struct dentry *ports_dentry;
4817 	int phy_no;
4818 
4819 	hisi_hba->debugfs_bist_dentry =
4820 			debugfs_create_dir("bist", hisi_hba->debugfs_dir);
4821 	debugfs_create_file("link_rate", 0600,
4822 			    hisi_hba->debugfs_bist_dentry, hisi_hba,
4823 			    &debugfs_bist_linkrate_v3_hw_fops);
4824 
4825 	debugfs_create_file("code_mode", 0600,
4826 			    hisi_hba->debugfs_bist_dentry, hisi_hba,
4827 			    &debugfs_bist_code_mode_v3_hw_fops);
4828 
4829 	debugfs_create_file("fixed_code", 0600,
4830 			    hisi_hba->debugfs_bist_dentry,
4831 			    &hisi_hba->debugfs_bist_fixed_code[0],
4832 			    &debugfs_v3_hw_fops);
4833 
4834 	debugfs_create_file("fixed_code_1", 0600,
4835 			    hisi_hba->debugfs_bist_dentry,
4836 			    &hisi_hba->debugfs_bist_fixed_code[1],
4837 			    &debugfs_v3_hw_fops);
4838 
4839 	debugfs_create_file("phy_id", 0600, hisi_hba->debugfs_bist_dentry,
4840 			    hisi_hba, &debugfs_bist_phy_v3_hw_fops);
4841 
4842 	debugfs_create_file("cnt", 0600, hisi_hba->debugfs_bist_dentry,
4843 			    hisi_hba, &debugfs_bist_cnt_v3_hw_ops);
4844 
4845 	debugfs_create_file("loopback_mode", 0600,
4846 			    hisi_hba->debugfs_bist_dentry,
4847 			    hisi_hba, &debugfs_bist_mode_v3_hw_fops);
4848 
4849 	debugfs_create_file("enable", 0600, hisi_hba->debugfs_bist_dentry,
4850 			    hisi_hba, &debugfs_bist_enable_v3_hw_fops);
4851 
4852 	ports_dentry = debugfs_create_dir("port", hisi_hba->debugfs_bist_dentry);
4853 
4854 	for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
4855 		struct dentry *port_dentry;
4856 		struct dentry *ffe_dentry;
4857 		char name[256];
4858 		int i;
4859 
4860 		snprintf(name, 256, "%d", phy_no);
4861 		port_dentry = debugfs_create_dir(name, ports_dentry);
4862 		ffe_dentry = debugfs_create_dir("ffe", port_dentry);
4863 		for (i = 0; i < FFE_CFG_MAX; i++) {
4864 			if (i == FFE_RESV)
4865 				continue;
4866 			debugfs_create_file(debugfs_ffe_name_v3_hw[i].name,
4867 					    0600, ffe_dentry,
4868 					    &hisi_hba->debugfs_bist_ffe[phy_no][i],
4869 					    &debugfs_v3_hw_fops);
4870 		}
4871 	}
4872 
4873 	hisi_hba->debugfs_bist_linkrate = SAS_LINK_RATE_1_5_GBPS;
4874 }
4875 
4876 static void debugfs_exit_v3_hw(struct hisi_hba *hisi_hba)
4877 {
4878 	debugfs_remove_recursive(hisi_hba->debugfs_dir);
4879 	hisi_hba->debugfs_dir = NULL;
4880 }
4881 
4882 static void debugfs_init_v3_hw(struct hisi_hba *hisi_hba)
4883 {
4884 	struct device *dev = hisi_hba->dev;
4885 	int i;
4886 
4887 	hisi_hba->debugfs_dir = debugfs_create_dir(dev_name(dev),
4888 						   hisi_sas_debugfs_dir);
4889 	debugfs_create_file("trigger_dump", 0200,
4890 			    hisi_hba->debugfs_dir,
4891 			    hisi_hba,
4892 			    &debugfs_trigger_dump_v3_hw_fops);
4893 
4894 	/* create bist structures */
4895 	debugfs_bist_init_v3_hw(hisi_hba);
4896 
4897 	hisi_hba->debugfs_dump_dentry =
4898 			debugfs_create_dir("dump", hisi_hba->debugfs_dir);
4899 
4900 	debugfs_phy_down_cnt_init_v3_hw(hisi_hba);
4901 	debugfs_fifo_init_v3_hw(hisi_hba);
4902 
4903 	for (i = 0; i < hisi_sas_debugfs_dump_count; i++) {
4904 		if (debugfs_alloc_v3_hw(hisi_hba, i)) {
4905 			debugfs_exit_v3_hw(hisi_hba);
4906 			dev_dbg(dev, "failed to init debugfs!\n");
4907 			break;
4908 		}
4909 	}
4910 }
4911 
4912 static int
4913 hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id)
4914 {
4915 	struct Scsi_Host *shost;
4916 	struct hisi_hba *hisi_hba;
4917 	struct device *dev = &pdev->dev;
4918 	struct asd_sas_phy **arr_phy;
4919 	struct asd_sas_port **arr_port;
4920 	struct sas_ha_struct *sha;
4921 	int rc, phy_nr, port_nr, i;
4922 
4923 	rc = pcim_enable_device(pdev);
4924 	if (rc)
4925 		goto err_out;
4926 
4927 	pci_set_master(pdev);
4928 
4929 	rc = pcim_iomap_regions(pdev, 1 << BAR_NO_V3_HW, DRV_NAME);
4930 	if (rc)
4931 		goto err_out;
4932 
4933 	rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
4934 	if (rc) {
4935 		dev_err(dev, "No usable DMA addressing method\n");
4936 		rc = -ENODEV;
4937 		goto err_out;
4938 	}
4939 
4940 	shost = hisi_sas_shost_alloc_pci(pdev);
4941 	if (!shost) {
4942 		rc = -ENOMEM;
4943 		goto err_out;
4944 	}
4945 
4946 	sha = SHOST_TO_SAS_HA(shost);
4947 	hisi_hba = shost_priv(shost);
4948 	dev_set_drvdata(dev, sha);
4949 
4950 	hisi_hba->regs = pcim_iomap_table(pdev)[BAR_NO_V3_HW];
4951 	if (!hisi_hba->regs) {
4952 		dev_err(dev, "cannot map register\n");
4953 		rc = -ENOMEM;
4954 		goto err_out_free_host;
4955 	}
4956 
4957 	phy_nr = port_nr = hisi_hba->n_phy;
4958 
4959 	arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
4960 	arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
4961 	if (!arr_phy || !arr_port) {
4962 		rc = -ENOMEM;
4963 		goto err_out_free_host;
4964 	}
4965 
4966 	sha->sas_phy = arr_phy;
4967 	sha->sas_port = arr_port;
4968 	sha->shost = shost;
4969 	sha->lldd_ha = hisi_hba;
4970 
4971 	shost->transportt = hisi_sas_stt;
4972 	shost->max_id = HISI_SAS_MAX_DEVICES;
4973 	shost->max_lun = ~0;
4974 	shost->max_channel = 1;
4975 	shost->max_cmd_len = 16;
4976 	shost->can_queue = HISI_SAS_UNRESERVED_IPTT;
4977 	shost->cmd_per_lun = HISI_SAS_UNRESERVED_IPTT;
4978 	if (hisi_hba->iopoll_q_cnt)
4979 		shost->nr_maps = 3;
4980 	else
4981 		shost->nr_maps = 1;
4982 
4983 	sha->sas_ha_name = DRV_NAME;
4984 	sha->dev = dev;
4985 	sha->sas_addr = &hisi_hba->sas_addr[0];
4986 	sha->num_phys = hisi_hba->n_phy;
4987 
4988 	for (i = 0; i < hisi_hba->n_phy; i++) {
4989 		sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy;
4990 		sha->sas_port[i] = &hisi_hba->port[i].sas_port;
4991 	}
4992 
4993 	if (hisi_hba->prot_mask) {
4994 		dev_info(dev, "Registering for DIF/DIX prot_mask=0x%x\n",
4995 			 prot_mask);
4996 		scsi_host_set_prot(hisi_hba->shost, prot_mask);
4997 		if (hisi_hba->prot_mask & HISI_SAS_DIX_PROT_MASK)
4998 			scsi_host_set_guard(hisi_hba->shost,
4999 					    SHOST_DIX_GUARD_CRC);
5000 	}
5001 
5002 	if (hisi_sas_debugfs_enable)
5003 		debugfs_init_v3_hw(hisi_hba);
5004 
5005 	rc = interrupt_preinit_v3_hw(hisi_hba);
5006 	if (rc)
5007 		goto err_out_undo_debugfs;
5008 
5009 	rc = scsi_add_host(shost, dev);
5010 	if (rc)
5011 		goto err_out_undo_debugfs;
5012 
5013 	rc = sas_register_ha(sha);
5014 	if (rc)
5015 		goto err_out_remove_host;
5016 
5017 	rc = hisi_sas_v3_init(hisi_hba);
5018 	if (rc)
5019 		goto err_out_unregister_ha;
5020 
5021 	scsi_scan_host(shost);
5022 
5023 	pm_runtime_set_autosuspend_delay(dev, 5000);
5024 	pm_runtime_use_autosuspend(dev);
5025 	/*
5026 	 * For the situation that there are ATA disks connected with SAS
5027 	 * controller, it additionally creates ata_port which will affect the
5028 	 * child_count of hisi_hba->dev. Even if suspended all the disks,
5029 	 * ata_port is still and the child_count of hisi_hba->dev is not 0.
5030 	 * So use pm_suspend_ignore_children() to ignore the effect to
5031 	 * hisi_hba->dev.
5032 	 */
5033 	pm_suspend_ignore_children(dev, true);
5034 	pm_runtime_put_noidle(&pdev->dev);
5035 
5036 	return 0;
5037 
5038 err_out_unregister_ha:
5039 	sas_unregister_ha(sha);
5040 err_out_remove_host:
5041 	scsi_remove_host(shost);
5042 err_out_undo_debugfs:
5043 	debugfs_exit_v3_hw(hisi_hba);
5044 err_out_free_host:
5045 	hisi_sas_free(hisi_hba);
5046 	scsi_host_put(shost);
5047 err_out:
5048 	return rc;
5049 }
5050 
5051 static void
5052 hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba)
5053 {
5054 	int i;
5055 
5056 	devm_free_irq(&pdev->dev, pci_irq_vector(pdev, 1), hisi_hba);
5057 	devm_free_irq(&pdev->dev, pci_irq_vector(pdev, 2), hisi_hba);
5058 	devm_free_irq(&pdev->dev, pci_irq_vector(pdev, 11), hisi_hba);
5059 	for (i = 0; i < hisi_hba->cq_nvecs; i++) {
5060 		struct hisi_sas_cq *cq = &hisi_hba->cq[i];
5061 		int nr = hisi_sas_intr_conv ? 16 : 16 + i;
5062 
5063 		devm_free_irq(&pdev->dev, pci_irq_vector(pdev, nr), cq);
5064 	}
5065 }
5066 
5067 static void hisi_sas_v3_remove(struct pci_dev *pdev)
5068 {
5069 	struct device *dev = &pdev->dev;
5070 	struct sas_ha_struct *sha = dev_get_drvdata(dev);
5071 	struct hisi_hba *hisi_hba = sha->lldd_ha;
5072 	struct Scsi_Host *shost = sha->shost;
5073 
5074 	pm_runtime_get_noresume(dev);
5075 	del_timer_sync(&hisi_hba->timer);
5076 
5077 	sas_unregister_ha(sha);
5078 	flush_workqueue(hisi_hba->wq);
5079 	sas_remove_host(shost);
5080 
5081 	hisi_sas_v3_destroy_irqs(pdev, hisi_hba);
5082 	hisi_sas_free(hisi_hba);
5083 	debugfs_exit_v3_hw(hisi_hba);
5084 	scsi_host_put(shost);
5085 }
5086 
5087 static void hisi_sas_reset_prepare_v3_hw(struct pci_dev *pdev)
5088 {
5089 	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
5090 	struct hisi_hba *hisi_hba = sha->lldd_ha;
5091 	struct device *dev = hisi_hba->dev;
5092 	int rc;
5093 
5094 	dev_info(dev, "FLR prepare\n");
5095 	down(&hisi_hba->sem);
5096 	set_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags);
5097 	hisi_sas_controller_reset_prepare(hisi_hba);
5098 
5099 	interrupt_disable_v3_hw(hisi_hba);
5100 	rc = disable_host_v3_hw(hisi_hba);
5101 	if (rc)
5102 		dev_err(dev, "FLR: disable host failed rc=%d\n", rc);
5103 }
5104 
5105 static void hisi_sas_reset_done_v3_hw(struct pci_dev *pdev)
5106 {
5107 	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
5108 	struct hisi_hba *hisi_hba = sha->lldd_ha;
5109 	struct Scsi_Host *shost = hisi_hba->shost;
5110 	struct device *dev = hisi_hba->dev;
5111 	int rc;
5112 
5113 	hisi_sas_init_mem(hisi_hba);
5114 
5115 	rc = hw_init_v3_hw(hisi_hba);
5116 	if (rc) {
5117 		dev_err(dev, "FLR: hw init failed rc=%d\n", rc);
5118 		clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
5119 		scsi_unblock_requests(shost);
5120 		clear_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags);
5121 		up(&hisi_hba->sem);
5122 		return;
5123 	}
5124 
5125 	hisi_sas_controller_reset_done(hisi_hba);
5126 	dev_info(dev, "FLR done\n");
5127 }
5128 
5129 enum {
5130 	/* instances of the controller */
5131 	hip08,
5132 };
5133 
5134 static void enable_host_v3_hw(struct hisi_hba *hisi_hba)
5135 {
5136 	u32 reg_val;
5137 
5138 	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
5139 			 (u32)((1ULL << hisi_hba->queue_count) - 1));
5140 
5141 	phys_init_v3_hw(hisi_hba);
5142 	reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE +
5143 				  AM_CTRL_GLOBAL);
5144 	reg_val &= ~AM_CTRL_SHUTDOWN_REQ_MSK;
5145 	hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE +
5146 			 AM_CTRL_GLOBAL, reg_val);
5147 }
5148 
5149 static int _suspend_v3_hw(struct device *device)
5150 {
5151 	struct pci_dev *pdev = to_pci_dev(device);
5152 	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
5153 	struct hisi_hba *hisi_hba = sha->lldd_ha;
5154 	struct device *dev = hisi_hba->dev;
5155 	struct Scsi_Host *shost = hisi_hba->shost;
5156 	int rc;
5157 
5158 	if (!pdev->pm_cap) {
5159 		dev_err(dev, "PCI PM not supported\n");
5160 		return -ENODEV;
5161 	}
5162 
5163 	if (test_and_set_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags))
5164 		return -EPERM;
5165 
5166 	dev_warn(dev, "entering suspend state\n");
5167 
5168 	scsi_block_requests(shost);
5169 	set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
5170 	flush_workqueue(hisi_hba->wq);
5171 	interrupt_disable_v3_hw(hisi_hba);
5172 
5173 #ifdef CONFIG_PM
5174 	if (atomic_read(&device->power.usage_count)) {
5175 		dev_err(dev, "PM suspend: host status cannot be suspended\n");
5176 		rc = -EBUSY;
5177 		goto err_out;
5178 	}
5179 #endif
5180 
5181 	rc = disable_host_v3_hw(hisi_hba);
5182 	if (rc) {
5183 		dev_err(dev, "PM suspend: disable host failed rc=%d\n", rc);
5184 		goto err_out_recover_host;
5185 	}
5186 
5187 	hisi_sas_init_mem(hisi_hba);
5188 
5189 	hisi_sas_release_tasks(hisi_hba);
5190 
5191 	sas_suspend_ha(sha);
5192 
5193 	dev_warn(dev, "end of suspending controller\n");
5194 	return 0;
5195 
5196 err_out_recover_host:
5197 	enable_host_v3_hw(hisi_hba);
5198 #ifdef CONFIG_PM
5199 err_out:
5200 #endif
5201 	interrupt_enable_v3_hw(hisi_hba);
5202 	clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
5203 	clear_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags);
5204 	scsi_unblock_requests(shost);
5205 	return rc;
5206 }
5207 
5208 static int _resume_v3_hw(struct device *device)
5209 {
5210 	struct pci_dev *pdev = to_pci_dev(device);
5211 	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
5212 	struct hisi_hba *hisi_hba = sha->lldd_ha;
5213 	struct Scsi_Host *shost = hisi_hba->shost;
5214 	struct device *dev = hisi_hba->dev;
5215 	unsigned int rc;
5216 	pci_power_t device_state = pdev->current_state;
5217 
5218 	dev_warn(dev, "resuming from operating state [D%d]\n",
5219 		 device_state);
5220 
5221 	scsi_unblock_requests(shost);
5222 	clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
5223 
5224 	sas_prep_resume_ha(sha);
5225 	rc = hw_init_v3_hw(hisi_hba);
5226 	if (rc) {
5227 		scsi_remove_host(shost);
5228 		return rc;
5229 	}
5230 	phys_init_v3_hw(hisi_hba);
5231 
5232 	/*
5233 	 * If a directly-attached disk is removed during suspend, a deadlock
5234 	 * may occur, as the PHYE_RESUME_TIMEOUT processing will require the
5235 	 * hisi_hba->device to be active, which can only happen when resume
5236 	 * completes. So don't wait for the HA event workqueue to drain upon
5237 	 * resume.
5238 	 */
5239 	sas_resume_ha_no_sync(sha);
5240 	clear_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags);
5241 
5242 	dev_warn(dev, "end of resuming controller\n");
5243 
5244 	return 0;
5245 }
5246 
5247 static int __maybe_unused suspend_v3_hw(struct device *device)
5248 {
5249 	struct pci_dev *pdev = to_pci_dev(device);
5250 	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
5251 	struct hisi_hba *hisi_hba = sha->lldd_ha;
5252 	int rc;
5253 
5254 	set_bit(HISI_SAS_PM_BIT, &hisi_hba->flags);
5255 
5256 	rc = _suspend_v3_hw(device);
5257 	if (rc)
5258 		clear_bit(HISI_SAS_PM_BIT, &hisi_hba->flags);
5259 
5260 	return rc;
5261 }
5262 
5263 static int __maybe_unused resume_v3_hw(struct device *device)
5264 {
5265 	struct pci_dev *pdev = to_pci_dev(device);
5266 	struct sas_ha_struct *sha = pci_get_drvdata(pdev);
5267 	struct hisi_hba *hisi_hba = sha->lldd_ha;
5268 	int rc = _resume_v3_hw(device);
5269 
5270 	clear_bit(HISI_SAS_PM_BIT, &hisi_hba->flags);
5271 
5272 	return rc;
5273 }
5274 
5275 static const struct pci_device_id sas_v3_pci_table[] = {
5276 	{ PCI_VDEVICE(HUAWEI, 0xa230), hip08 },
5277 	{}
5278 };
5279 MODULE_DEVICE_TABLE(pci, sas_v3_pci_table);
5280 
5281 static const struct pci_error_handlers hisi_sas_err_handler = {
5282 	.reset_prepare	= hisi_sas_reset_prepare_v3_hw,
5283 	.reset_done	= hisi_sas_reset_done_v3_hw,
5284 };
5285 
5286 static UNIVERSAL_DEV_PM_OPS(hisi_sas_v3_pm_ops,
5287 			    suspend_v3_hw,
5288 			    resume_v3_hw,
5289 			    NULL);
5290 
5291 static struct pci_driver sas_v3_pci_driver = {
5292 	.name		= DRV_NAME,
5293 	.id_table	= sas_v3_pci_table,
5294 	.probe		= hisi_sas_v3_probe,
5295 	.remove		= hisi_sas_v3_remove,
5296 	.err_handler	= &hisi_sas_err_handler,
5297 	.driver.pm	= &hisi_sas_v3_pm_ops,
5298 };
5299 
5300 module_pci_driver(sas_v3_pci_driver);
5301 module_param_named(intr_conv, hisi_sas_intr_conv, bool, 0444);
5302 
5303 MODULE_LICENSE("GPL");
5304 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
5305 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device");
5306 MODULE_ALIAS("pci:" DRV_NAME);
5307