1 /* 2 * Copyright (c) 2017 Hisilicon Limited. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 */ 10 11 #include "hisi_sas.h" 12 #define DRV_NAME "hisi_sas_v3_hw" 13 14 /* global registers need init */ 15 #define DLVRY_QUEUE_ENABLE 0x0 16 #define IOST_BASE_ADDR_LO 0x8 17 #define IOST_BASE_ADDR_HI 0xc 18 #define ITCT_BASE_ADDR_LO 0x10 19 #define ITCT_BASE_ADDR_HI 0x14 20 #define IO_BROKEN_MSG_ADDR_LO 0x18 21 #define IO_BROKEN_MSG_ADDR_HI 0x1c 22 #define PHY_CONTEXT 0x20 23 #define PHY_STATE 0x24 24 #define PHY_PORT_NUM_MA 0x28 25 #define PHY_CONN_RATE 0x30 26 #define ITCT_CLR 0x44 27 #define ITCT_CLR_EN_OFF 16 28 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF) 29 #define ITCT_DEV_OFF 0 30 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF) 31 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58 32 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c 33 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60 34 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64 35 #define CFG_MAX_TAG 0x68 36 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84 37 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88 38 #define HGC_GET_ITV_TIME 0x90 39 #define DEVICE_MSG_WORK_MODE 0x94 40 #define OPENA_WT_CONTI_TIME 0x9c 41 #define I_T_NEXUS_LOSS_TIME 0xa0 42 #define MAX_CON_TIME_LIMIT_TIME 0xa4 43 #define BUS_INACTIVE_LIMIT_TIME 0xa8 44 #define REJECT_TO_OPEN_LIMIT_TIME 0xac 45 #define CQ_INT_CONVERGE_EN 0xb0 46 #define CFG_AGING_TIME 0xbc 47 #define HGC_DFX_CFG2 0xc0 48 #define CFG_ABT_SET_QUERY_IPTT 0xd4 49 #define CFG_SET_ABORTED_IPTT_OFF 0 50 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF) 51 #define CFG_SET_ABORTED_EN_OFF 12 52 #define CFG_ABT_SET_IPTT_DONE 0xd8 53 #define CFG_ABT_SET_IPTT_DONE_OFF 0 54 #define HGC_IOMB_PROC1_STATUS 0x104 55 #define HGC_LM_DFX_STATUS2 0x128 56 #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0 57 #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \ 58 HGC_LM_DFX_STATUS2_IOSTLIST_OFF) 59 #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF 12 60 #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \ 61 HGC_LM_DFX_STATUS2_ITCTLIST_OFF) 62 #define HGC_CQE_ECC_ADDR 0x13c 63 #define HGC_CQE_ECC_1B_ADDR_OFF 0 64 #define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF) 65 #define HGC_CQE_ECC_MB_ADDR_OFF 8 66 #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF) 67 #define HGC_IOST_ECC_ADDR 0x140 68 #define HGC_IOST_ECC_1B_ADDR_OFF 0 69 #define HGC_IOST_ECC_1B_ADDR_MSK (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF) 70 #define HGC_IOST_ECC_MB_ADDR_OFF 16 71 #define HGC_IOST_ECC_MB_ADDR_MSK (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF) 72 #define HGC_DQE_ECC_ADDR 0x144 73 #define HGC_DQE_ECC_1B_ADDR_OFF 0 74 #define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF) 75 #define HGC_DQE_ECC_MB_ADDR_OFF 16 76 #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF) 77 #define CHNL_INT_STATUS 0x148 78 #define HGC_ITCT_ECC_ADDR 0x150 79 #define HGC_ITCT_ECC_1B_ADDR_OFF 0 80 #define HGC_ITCT_ECC_1B_ADDR_MSK (0x3ff << \ 81 HGC_ITCT_ECC_1B_ADDR_OFF) 82 #define HGC_ITCT_ECC_MB_ADDR_OFF 16 83 #define HGC_ITCT_ECC_MB_ADDR_MSK (0x3ff << \ 84 HGC_ITCT_ECC_MB_ADDR_OFF) 85 #define HGC_AXI_FIFO_ERR_INFO 0x154 86 #define AXI_ERR_INFO_OFF 0 87 #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF) 88 #define FIFO_ERR_INFO_OFF 8 89 #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF) 90 #define INT_COAL_EN 0x19c 91 #define OQ_INT_COAL_TIME 0x1a0 92 #define OQ_INT_COAL_CNT 0x1a4 93 #define ENT_INT_COAL_TIME 0x1a8 94 #define ENT_INT_COAL_CNT 0x1ac 95 #define OQ_INT_SRC 0x1b0 96 #define OQ_INT_SRC_MSK 0x1b4 97 #define ENT_INT_SRC1 0x1b8 98 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0 99 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF) 100 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8 101 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF) 102 #define ENT_INT_SRC2 0x1bc 103 #define ENT_INT_SRC3 0x1c0 104 #define ENT_INT_SRC3_WP_DEPTH_OFF 8 105 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9 106 #define ENT_INT_SRC3_RP_DEPTH_OFF 10 107 #define ENT_INT_SRC3_AXI_OFF 11 108 #define ENT_INT_SRC3_FIFO_OFF 12 109 #define ENT_INT_SRC3_LM_OFF 14 110 #define ENT_INT_SRC3_ITC_INT_OFF 15 111 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF) 112 #define ENT_INT_SRC3_ABT_OFF 16 113 #define ENT_INT_SRC3_DQE_POISON_OFF 18 114 #define ENT_INT_SRC3_IOST_POISON_OFF 19 115 #define ENT_INT_SRC3_ITCT_POISON_OFF 20 116 #define ENT_INT_SRC3_ITCT_NCQ_POISON_OFF 21 117 #define ENT_INT_SRC_MSK1 0x1c4 118 #define ENT_INT_SRC_MSK2 0x1c8 119 #define ENT_INT_SRC_MSK3 0x1cc 120 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31 121 #define CHNL_PHYUPDOWN_INT_MSK 0x1d0 122 #define CHNL_ENT_INT_MSK 0x1d4 123 #define HGC_COM_INT_MSK 0x1d8 124 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF) 125 #define SAS_ECC_INTR 0x1e8 126 #define SAS_ECC_INTR_DQE_ECC_1B_OFF 0 127 #define SAS_ECC_INTR_DQE_ECC_MB_OFF 1 128 #define SAS_ECC_INTR_IOST_ECC_1B_OFF 2 129 #define SAS_ECC_INTR_IOST_ECC_MB_OFF 3 130 #define SAS_ECC_INTR_ITCT_ECC_1B_OFF 4 131 #define SAS_ECC_INTR_ITCT_ECC_MB_OFF 5 132 #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF 6 133 #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF 7 134 #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF 8 135 #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF 9 136 #define SAS_ECC_INTR_CQE_ECC_1B_OFF 10 137 #define SAS_ECC_INTR_CQE_ECC_MB_OFF 11 138 #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF 12 139 #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF 13 140 #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF 14 141 #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF 15 142 #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF 16 143 #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF 17 144 #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 18 145 #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF 19 146 #define SAS_ECC_INTR_OOO_RAM_ECC_1B_OFF 20 147 #define SAS_ECC_INTR_OOO_RAM_ECC_MB_OFF 21 148 #define SAS_ECC_INTR_MSK 0x1ec 149 #define HGC_ERR_STAT_EN 0x238 150 #define CQE_SEND_CNT 0x248 151 #define DLVRY_Q_0_BASE_ADDR_LO 0x260 152 #define DLVRY_Q_0_BASE_ADDR_HI 0x264 153 #define DLVRY_Q_0_DEPTH 0x268 154 #define DLVRY_Q_0_WR_PTR 0x26c 155 #define DLVRY_Q_0_RD_PTR 0x270 156 #define HYPER_STREAM_ID_EN_CFG 0xc80 157 #define OQ0_INT_SRC_MSK 0xc90 158 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0 159 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4 160 #define COMPL_Q_0_DEPTH 0x4e8 161 #define COMPL_Q_0_WR_PTR 0x4ec 162 #define COMPL_Q_0_RD_PTR 0x4f0 163 #define HGC_RXM_DFX_STATUS14 0xae8 164 #define HGC_RXM_DFX_STATUS14_MEM0_OFF 0 165 #define HGC_RXM_DFX_STATUS14_MEM0_MSK (0x1ff << \ 166 HGC_RXM_DFX_STATUS14_MEM0_OFF) 167 #define HGC_RXM_DFX_STATUS14_MEM1_OFF 9 168 #define HGC_RXM_DFX_STATUS14_MEM1_MSK (0x1ff << \ 169 HGC_RXM_DFX_STATUS14_MEM1_OFF) 170 #define HGC_RXM_DFX_STATUS14_MEM2_OFF 18 171 #define HGC_RXM_DFX_STATUS14_MEM2_MSK (0x1ff << \ 172 HGC_RXM_DFX_STATUS14_MEM2_OFF) 173 #define HGC_RXM_DFX_STATUS15 0xaec 174 #define HGC_RXM_DFX_STATUS15_MEM3_OFF 0 175 #define HGC_RXM_DFX_STATUS15_MEM3_MSK (0x1ff << \ 176 HGC_RXM_DFX_STATUS15_MEM3_OFF) 177 #define AWQOS_AWCACHE_CFG 0xc84 178 #define ARQOS_ARCACHE_CFG 0xc88 179 #define HILINK_ERR_DFX 0xe04 180 #define SAS_GPIO_CFG_0 0x1000 181 #define SAS_GPIO_CFG_1 0x1004 182 #define SAS_GPIO_TX_0_1 0x1040 183 #define SAS_CFG_DRIVE_VLD 0x1070 184 185 /* phy registers requiring init */ 186 #define PORT_BASE (0x2000) 187 #define PHY_CFG (PORT_BASE + 0x0) 188 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4) 189 #define PHY_CFG_ENA_OFF 0 190 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF) 191 #define PHY_CFG_DC_OPT_OFF 2 192 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF) 193 #define PHY_CFG_PHY_RST_OFF 3 194 #define PHY_CFG_PHY_RST_MSK (0x1 << PHY_CFG_PHY_RST_OFF) 195 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8) 196 #define PHY_CTRL (PORT_BASE + 0x14) 197 #define PHY_CTRL_RESET_OFF 0 198 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF) 199 #define CMD_HDR_PIR_OFF 8 200 #define CMD_HDR_PIR_MSK (0x1 << CMD_HDR_PIR_OFF) 201 #define SERDES_CFG (PORT_BASE + 0x1c) 202 #define SL_CFG (PORT_BASE + 0x84) 203 #define AIP_LIMIT (PORT_BASE + 0x90) 204 #define SL_CONTROL (PORT_BASE + 0x94) 205 #define SL_CONTROL_NOTIFY_EN_OFF 0 206 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF) 207 #define SL_CTA_OFF 17 208 #define SL_CTA_MSK (0x1 << SL_CTA_OFF) 209 #define RX_PRIMS_STATUS (PORT_BASE + 0x98) 210 #define RX_BCAST_CHG_OFF 1 211 #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF) 212 #define TX_ID_DWORD0 (PORT_BASE + 0x9c) 213 #define TX_ID_DWORD1 (PORT_BASE + 0xa0) 214 #define TX_ID_DWORD2 (PORT_BASE + 0xa4) 215 #define TX_ID_DWORD3 (PORT_BASE + 0xa8) 216 #define TX_ID_DWORD4 (PORT_BASE + 0xaC) 217 #define TX_ID_DWORD5 (PORT_BASE + 0xb0) 218 #define TX_ID_DWORD6 (PORT_BASE + 0xb4) 219 #define TXID_AUTO (PORT_BASE + 0xb8) 220 #define CT3_OFF 1 221 #define CT3_MSK (0x1 << CT3_OFF) 222 #define TX_HARDRST_OFF 2 223 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF) 224 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4) 225 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) 226 #define STP_LINK_TIMER (PORT_BASE + 0x120) 227 #define STP_LINK_TIMEOUT_STATE (PORT_BASE + 0x124) 228 #define CON_CFG_DRIVER (PORT_BASE + 0x130) 229 #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134) 230 #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138) 231 #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c) 232 #define CHL_INT0 (PORT_BASE + 0x1b4) 233 #define CHL_INT0_HOTPLUG_TOUT_OFF 0 234 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF) 235 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1 236 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF) 237 #define CHL_INT0_SL_PHY_ENABLE_OFF 2 238 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF) 239 #define CHL_INT0_NOT_RDY_OFF 4 240 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF) 241 #define CHL_INT0_PHY_RDY_OFF 5 242 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF) 243 #define CHL_INT1 (PORT_BASE + 0x1b8) 244 #define CHL_INT1_DMAC_TX_ECC_MB_ERR_OFF 15 245 #define CHL_INT1_DMAC_TX_ECC_1B_ERR_OFF 16 246 #define CHL_INT1_DMAC_RX_ECC_MB_ERR_OFF 17 247 #define CHL_INT1_DMAC_RX_ECC_1B_ERR_OFF 18 248 #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19 249 #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20 250 #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21 251 #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22 252 #define CHL_INT1_DMAC_TX_FIFO_ERR_OFF 23 253 #define CHL_INT1_DMAC_RX_FIFO_ERR_OFF 24 254 #define CHL_INT1_DMAC_TX_AXI_RUSER_ERR_OFF 26 255 #define CHL_INT1_DMAC_RX_AXI_RUSER_ERR_OFF 27 256 #define CHL_INT2 (PORT_BASE + 0x1bc) 257 #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0 258 #define CHL_INT2_RX_DISP_ERR_OFF 28 259 #define CHL_INT2_RX_CODE_ERR_OFF 29 260 #define CHL_INT2_RX_INVLD_DW_OFF 30 261 #define CHL_INT2_STP_LINK_TIMEOUT_OFF 31 262 #define CHL_INT0_MSK (PORT_BASE + 0x1c0) 263 #define CHL_INT1_MSK (PORT_BASE + 0x1c4) 264 #define CHL_INT2_MSK (PORT_BASE + 0x1c8) 265 #define SAS_EC_INT_COAL_TIME (PORT_BASE + 0x1cc) 266 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0) 267 #define SAS_RX_TRAIN_TIMER (PORT_BASE + 0x2a4) 268 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0) 269 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4) 270 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8) 271 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc) 272 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0) 273 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4) 274 #define DMA_TX_STATUS (PORT_BASE + 0x2d0) 275 #define DMA_TX_STATUS_BUSY_OFF 0 276 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF) 277 #define DMA_RX_STATUS (PORT_BASE + 0x2e8) 278 #define DMA_RX_STATUS_BUSY_OFF 0 279 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF) 280 281 #define COARSETUNE_TIME (PORT_BASE + 0x304) 282 #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380) 283 #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384) 284 #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390) 285 #define ERR_CNT_CODE_ERR (PORT_BASE + 0x394) 286 #define ERR_CNT_DISP_ERR (PORT_BASE + 0x398) 287 288 #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */ 289 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW) 290 #error Max ITCT exceeded 291 #endif 292 293 #define AXI_MASTER_CFG_BASE (0x5000) 294 #define AM_CTRL_GLOBAL (0x0) 295 #define AM_CTRL_SHUTDOWN_REQ_OFF 0 296 #define AM_CTRL_SHUTDOWN_REQ_MSK (0x1 << AM_CTRL_SHUTDOWN_REQ_OFF) 297 #define AM_CURR_TRANS_RETURN (0x150) 298 299 #define AM_CFG_MAX_TRANS (0x5010) 300 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014) 301 #define AXI_CFG (0x5100) 302 #define AM_ROB_ECC_ERR_ADDR (0x510c) 303 #define AM_ROB_ECC_ERR_ADDR_OFF 0 304 #define AM_ROB_ECC_ERR_ADDR_MSK 0xffffffff 305 306 /* RAS registers need init */ 307 #define RAS_BASE (0x6000) 308 #define SAS_RAS_INTR0 (RAS_BASE) 309 #define SAS_RAS_INTR1 (RAS_BASE + 0x04) 310 #define SAS_RAS_INTR0_MASK (RAS_BASE + 0x08) 311 #define SAS_RAS_INTR1_MASK (RAS_BASE + 0x0c) 312 #define CFG_SAS_RAS_INTR_MASK (RAS_BASE + 0x1c) 313 #define SAS_RAS_INTR2 (RAS_BASE + 0x20) 314 #define SAS_RAS_INTR2_MASK (RAS_BASE + 0x24) 315 316 /* HW dma structures */ 317 /* Delivery queue header */ 318 /* dw0 */ 319 #define CMD_HDR_ABORT_FLAG_OFF 0 320 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF) 321 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2 322 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) 323 #define CMD_HDR_RESP_REPORT_OFF 5 324 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF) 325 #define CMD_HDR_TLR_CTRL_OFF 6 326 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF) 327 #define CMD_HDR_PORT_OFF 18 328 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF) 329 #define CMD_HDR_PRIORITY_OFF 27 330 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF) 331 #define CMD_HDR_CMD_OFF 29 332 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF) 333 /* dw1 */ 334 #define CMD_HDR_UNCON_CMD_OFF 3 335 #define CMD_HDR_DIR_OFF 5 336 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF) 337 #define CMD_HDR_RESET_OFF 7 338 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF) 339 #define CMD_HDR_VDTL_OFF 10 340 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF) 341 #define CMD_HDR_FRAME_TYPE_OFF 11 342 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF) 343 #define CMD_HDR_DEV_ID_OFF 16 344 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF) 345 /* dw2 */ 346 #define CMD_HDR_CFL_OFF 0 347 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF) 348 #define CMD_HDR_NCQ_TAG_OFF 10 349 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF) 350 #define CMD_HDR_MRFL_OFF 15 351 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF) 352 #define CMD_HDR_SG_MOD_OFF 24 353 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF) 354 /* dw3 */ 355 #define CMD_HDR_IPTT_OFF 0 356 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF) 357 /* dw6 */ 358 #define CMD_HDR_DIF_SGL_LEN_OFF 0 359 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF) 360 #define CMD_HDR_DATA_SGL_LEN_OFF 16 361 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF) 362 /* dw7 */ 363 #define CMD_HDR_ADDR_MODE_SEL_OFF 15 364 #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF) 365 #define CMD_HDR_ABORT_IPTT_OFF 16 366 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF) 367 368 /* Completion header */ 369 /* dw0 */ 370 #define CMPLT_HDR_CMPLT_OFF 0 371 #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF) 372 #define CMPLT_HDR_ERROR_PHASE_OFF 2 373 #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF) 374 #define CMPLT_HDR_RSPNS_XFRD_OFF 10 375 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF) 376 #define CMPLT_HDR_ERX_OFF 12 377 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF) 378 #define CMPLT_HDR_ABORT_STAT_OFF 13 379 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF) 380 /* abort_stat */ 381 #define STAT_IO_NOT_VALID 0x1 382 #define STAT_IO_NO_DEVICE 0x2 383 #define STAT_IO_COMPLETE 0x3 384 #define STAT_IO_ABORTED 0x4 385 /* dw1 */ 386 #define CMPLT_HDR_IPTT_OFF 0 387 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF) 388 #define CMPLT_HDR_DEV_ID_OFF 16 389 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF) 390 /* dw3 */ 391 #define CMPLT_HDR_IO_IN_TARGET_OFF 17 392 #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF) 393 394 /* ITCT header */ 395 /* qw0 */ 396 #define ITCT_HDR_DEV_TYPE_OFF 0 397 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF) 398 #define ITCT_HDR_VALID_OFF 2 399 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF) 400 #define ITCT_HDR_MCR_OFF 5 401 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF) 402 #define ITCT_HDR_VLN_OFF 9 403 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF) 404 #define ITCT_HDR_SMP_TIMEOUT_OFF 16 405 #define ITCT_HDR_AWT_CONTINUE_OFF 25 406 #define ITCT_HDR_PORT_ID_OFF 28 407 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF) 408 /* qw2 */ 409 #define ITCT_HDR_INLT_OFF 0 410 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF) 411 #define ITCT_HDR_RTOLT_OFF 48 412 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF) 413 414 struct hisi_sas_protect_iu_v3_hw { 415 u32 dw0; 416 u32 lbrtcv; 417 u32 lbrtgv; 418 u32 dw3; 419 u32 dw4; 420 u32 dw5; 421 u32 rsv; 422 }; 423 424 struct hisi_sas_complete_v3_hdr { 425 __le32 dw0; 426 __le32 dw1; 427 __le32 act; 428 __le32 dw3; 429 }; 430 431 struct hisi_sas_err_record_v3 { 432 /* dw0 */ 433 __le32 trans_tx_fail_type; 434 435 /* dw1 */ 436 __le32 trans_rx_fail_type; 437 438 /* dw2 */ 439 __le16 dma_tx_err_type; 440 __le16 sipc_rx_err_type; 441 442 /* dw3 */ 443 __le32 dma_rx_err_type; 444 }; 445 446 #define RX_DATA_LEN_UNDERFLOW_OFF 6 447 #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF) 448 449 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096 450 #define HISI_SAS_MSI_COUNT_V3_HW 32 451 452 #define DIR_NO_DATA 0 453 #define DIR_TO_INI 1 454 #define DIR_TO_DEVICE 2 455 #define DIR_RESERVED 3 456 457 #define FIS_CMD_IS_UNCONSTRAINED(fis) \ 458 ((fis.command == ATA_CMD_READ_LOG_EXT) || \ 459 (fis.command == ATA_CMD_READ_LOG_DMA_EXT) || \ 460 ((fis.command == ATA_CMD_DEV_RESET) && \ 461 ((fis.control & ATA_SRST) != 0))) 462 463 #define T10_INSRT_EN_OFF 0 464 #define T10_INSRT_EN_MSK (1 << T10_INSRT_EN_OFF) 465 #define T10_RMV_EN_OFF 1 466 #define T10_RMV_EN_MSK (1 << T10_RMV_EN_OFF) 467 #define T10_RPLC_EN_OFF 2 468 #define T10_RPLC_EN_MSK (1 << T10_RPLC_EN_OFF) 469 #define T10_CHK_EN_OFF 3 470 #define T10_CHK_EN_MSK (1 << T10_CHK_EN_OFF) 471 #define INCR_LBRT_OFF 5 472 #define INCR_LBRT_MSK (1 << INCR_LBRT_OFF) 473 #define USR_DATA_BLOCK_SZ_OFF 20 474 #define USR_DATA_BLOCK_SZ_MSK (0x3 << USR_DATA_BLOCK_SZ_OFF) 475 #define T10_CHK_MSK_OFF 16 476 #define T10_CHK_REF_TAG_MSK (0xf0 << T10_CHK_MSK_OFF) 477 #define T10_CHK_APP_TAG_MSK (0xc << T10_CHK_MSK_OFF) 478 479 #define BASE_VECTORS_V3_HW 16 480 #define MIN_AFFINE_VECTORS_V3_HW (BASE_VECTORS_V3_HW + 1) 481 482 enum { 483 DSM_FUNC_ERR_HANDLE_MSI = 0, 484 }; 485 486 static bool hisi_sas_intr_conv; 487 MODULE_PARM_DESC(intr_conv, "interrupt converge enable (0-1)"); 488 489 /* permit overriding the host protection capabilities mask (EEDP/T10 PI) */ 490 static int prot_mask; 491 module_param(prot_mask, int, 0); 492 MODULE_PARM_DESC(prot_mask, " host protection capabilities mask, def=0x0 "); 493 494 static bool auto_affine_msi_experimental; 495 module_param(auto_affine_msi_experimental, bool, 0444); 496 MODULE_PARM_DESC(auto_affine_msi_experimental, "Enable auto-affinity of MSI IRQs as experimental:\n" 497 "default is off"); 498 499 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) 500 { 501 void __iomem *regs = hisi_hba->regs + off; 502 503 return readl(regs); 504 } 505 506 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off) 507 { 508 void __iomem *regs = hisi_hba->regs + off; 509 510 return readl_relaxed(regs); 511 } 512 513 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val) 514 { 515 void __iomem *regs = hisi_hba->regs + off; 516 517 writel(val, regs); 518 } 519 520 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no, 521 u32 off, u32 val) 522 { 523 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 524 525 writel(val, regs); 526 } 527 528 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba, 529 int phy_no, u32 off) 530 { 531 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 532 533 return readl(regs); 534 } 535 536 #define hisi_sas_read32_poll_timeout(off, val, cond, delay_us, \ 537 timeout_us) \ 538 ({ \ 539 void __iomem *regs = hisi_hba->regs + off; \ 540 readl_poll_timeout(regs, val, cond, delay_us, timeout_us); \ 541 }) 542 543 #define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us, \ 544 timeout_us) \ 545 ({ \ 546 void __iomem *regs = hisi_hba->regs + off; \ 547 readl_poll_timeout_atomic(regs, val, cond, delay_us, timeout_us);\ 548 }) 549 550 static void init_reg_v3_hw(struct hisi_hba *hisi_hba) 551 { 552 int i; 553 554 /* Global registers init */ 555 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 556 (u32)((1ULL << hisi_hba->queue_count) - 1)); 557 hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400); 558 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108); 559 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1); 560 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); 561 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); 562 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); 563 hisi_sas_write32(hisi_hba, CQ_INT_CONVERGE_EN, 564 hisi_sas_intr_conv); 565 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff); 566 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff); 567 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff); 568 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff); 569 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe); 570 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe); 571 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffc220ff); 572 hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0); 573 hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0); 574 hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0); 575 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x155555); 576 hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0); 577 hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0); 578 for (i = 0; i < hisi_hba->queue_count; i++) 579 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0); 580 581 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1); 582 583 for (i = 0; i < hisi_hba->n_phy; i++) { 584 struct hisi_sas_phy *phy = &hisi_hba->phy[i]; 585 struct asd_sas_phy *sas_phy = &phy->sas_phy; 586 u32 prog_phy_link_rate = 0x800; 587 588 if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate < 589 SAS_LINK_RATE_1_5_GBPS)) { 590 prog_phy_link_rate = 0x855; 591 } else { 592 enum sas_linkrate max = sas_phy->phy->maximum_linkrate; 593 594 prog_phy_link_rate = 595 hisi_sas_get_prog_phy_linkrate_mask(max) | 596 0x800; 597 } 598 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 599 prog_phy_link_rate); 600 hisi_sas_phy_write32(hisi_hba, i, SERDES_CFG, 0xffc00); 601 hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80); 602 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff); 603 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff); 604 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff); 605 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000); 606 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xf2057fff); 607 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe); 608 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0); 609 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0); 610 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0); 611 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0); 612 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0); 613 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1); 614 hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120); 615 hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x2a0a01); 616 hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG, 0x32); 617 hisi_sas_phy_write32(hisi_hba, i, SAS_EC_INT_COAL_TIME, 618 0x30f4240); 619 /* used for 12G negotiate */ 620 hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e); 621 hisi_sas_phy_write32(hisi_hba, i, AIP_LIMIT, 0x2ffff); 622 } 623 624 for (i = 0; i < hisi_hba->queue_count; i++) { 625 /* Delivery queue */ 626 hisi_sas_write32(hisi_hba, 627 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14), 628 upper_32_bits(hisi_hba->cmd_hdr_dma[i])); 629 630 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14), 631 lower_32_bits(hisi_hba->cmd_hdr_dma[i])); 632 633 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14), 634 HISI_SAS_QUEUE_SLOTS); 635 636 /* Completion queue */ 637 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14), 638 upper_32_bits(hisi_hba->complete_hdr_dma[i])); 639 640 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14), 641 lower_32_bits(hisi_hba->complete_hdr_dma[i])); 642 643 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14), 644 HISI_SAS_QUEUE_SLOTS); 645 } 646 647 /* itct */ 648 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO, 649 lower_32_bits(hisi_hba->itct_dma)); 650 651 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI, 652 upper_32_bits(hisi_hba->itct_dma)); 653 654 /* iost */ 655 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO, 656 lower_32_bits(hisi_hba->iost_dma)); 657 658 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI, 659 upper_32_bits(hisi_hba->iost_dma)); 660 661 /* breakpoint */ 662 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO, 663 lower_32_bits(hisi_hba->breakpoint_dma)); 664 665 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI, 666 upper_32_bits(hisi_hba->breakpoint_dma)); 667 668 /* SATA broken msg */ 669 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO, 670 lower_32_bits(hisi_hba->sata_breakpoint_dma)); 671 672 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI, 673 upper_32_bits(hisi_hba->sata_breakpoint_dma)); 674 675 /* SATA initial fis */ 676 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO, 677 lower_32_bits(hisi_hba->initial_fis_dma)); 678 679 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI, 680 upper_32_bits(hisi_hba->initial_fis_dma)); 681 682 /* RAS registers init */ 683 hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0); 684 hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0); 685 hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, 0x0); 686 hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, 0x0); 687 688 /* LED registers init */ 689 hisi_sas_write32(hisi_hba, SAS_CFG_DRIVE_VLD, 0x80000ff); 690 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1, 0x80808080); 691 hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1 + 0x4, 0x80808080); 692 /* Configure blink generator rate A to 1Hz and B to 4Hz */ 693 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_1, 0x121700); 694 hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_0, 0x800000); 695 } 696 697 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 698 { 699 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 700 701 cfg &= ~PHY_CFG_DC_OPT_MSK; 702 cfg |= 1 << PHY_CFG_DC_OPT_OFF; 703 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 704 } 705 706 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 707 { 708 struct sas_identify_frame identify_frame; 709 u32 *identify_buffer; 710 711 memset(&identify_frame, 0, sizeof(identify_frame)); 712 identify_frame.dev_type = SAS_END_DEVICE; 713 identify_frame.frame_type = 0; 714 identify_frame._un1 = 1; 715 identify_frame.initiator_bits = SAS_PROTOCOL_ALL; 716 identify_frame.target_bits = SAS_PROTOCOL_NONE; 717 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 718 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 719 identify_frame.phy_id = phy_no; 720 identify_buffer = (u32 *)(&identify_frame); 721 722 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0, 723 __swab32(identify_buffer[0])); 724 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1, 725 __swab32(identify_buffer[1])); 726 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2, 727 __swab32(identify_buffer[2])); 728 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3, 729 __swab32(identify_buffer[3])); 730 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4, 731 __swab32(identify_buffer[4])); 732 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5, 733 __swab32(identify_buffer[5])); 734 } 735 736 static void setup_itct_v3_hw(struct hisi_hba *hisi_hba, 737 struct hisi_sas_device *sas_dev) 738 { 739 struct domain_device *device = sas_dev->sas_device; 740 struct device *dev = hisi_hba->dev; 741 u64 qw0, device_id = sas_dev->device_id; 742 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id]; 743 struct domain_device *parent_dev = device->parent; 744 struct asd_sas_port *sas_port = device->port; 745 struct hisi_sas_port *port = to_hisi_sas_port(sas_port); 746 u64 sas_addr; 747 748 memset(itct, 0, sizeof(*itct)); 749 750 /* qw0 */ 751 qw0 = 0; 752 switch (sas_dev->dev_type) { 753 case SAS_END_DEVICE: 754 case SAS_EDGE_EXPANDER_DEVICE: 755 case SAS_FANOUT_EXPANDER_DEVICE: 756 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF; 757 break; 758 case SAS_SATA_DEV: 759 case SAS_SATA_PENDING: 760 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) 761 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF; 762 else 763 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF; 764 break; 765 default: 766 dev_warn(dev, "setup itct: unsupported dev type (%d)\n", 767 sas_dev->dev_type); 768 } 769 770 qw0 |= ((1 << ITCT_HDR_VALID_OFF) | 771 (device->linkrate << ITCT_HDR_MCR_OFF) | 772 (1 << ITCT_HDR_VLN_OFF) | 773 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) | 774 (1 << ITCT_HDR_AWT_CONTINUE_OFF) | 775 (port->id << ITCT_HDR_PORT_ID_OFF)); 776 itct->qw0 = cpu_to_le64(qw0); 777 778 /* qw1 */ 779 memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE); 780 itct->sas_addr = cpu_to_le64(__swab64(sas_addr)); 781 782 /* qw2 */ 783 if (!dev_is_sata(device)) 784 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) | 785 (0x1ULL << ITCT_HDR_RTOLT_OFF)); 786 } 787 788 static void clear_itct_v3_hw(struct hisi_hba *hisi_hba, 789 struct hisi_sas_device *sas_dev) 790 { 791 DECLARE_COMPLETION_ONSTACK(completion); 792 u64 dev_id = sas_dev->device_id; 793 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id]; 794 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); 795 796 sas_dev->completion = &completion; 797 798 /* clear the itct interrupt state */ 799 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) 800 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 801 ENT_INT_SRC3_ITC_INT_MSK); 802 803 /* clear the itct table */ 804 reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK); 805 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val); 806 807 wait_for_completion(sas_dev->completion); 808 memset(itct, 0, sizeof(struct hisi_sas_itct)); 809 } 810 811 static void dereg_device_v3_hw(struct hisi_hba *hisi_hba, 812 struct domain_device *device) 813 { 814 struct hisi_sas_slot *slot, *slot2; 815 struct hisi_sas_device *sas_dev = device->lldd_dev; 816 u32 cfg_abt_set_query_iptt; 817 818 cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba, 819 CFG_ABT_SET_QUERY_IPTT); 820 list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) { 821 cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK; 822 cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) | 823 (slot->idx << CFG_SET_ABORTED_IPTT_OFF); 824 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, 825 cfg_abt_set_query_iptt); 826 } 827 cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF); 828 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, 829 cfg_abt_set_query_iptt); 830 hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE, 831 1 << CFG_ABT_SET_IPTT_DONE_OFF); 832 } 833 834 static int reset_hw_v3_hw(struct hisi_hba *hisi_hba) 835 { 836 struct device *dev = hisi_hba->dev; 837 int ret; 838 u32 val; 839 840 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0); 841 842 /* Disable all of the PHYs */ 843 hisi_sas_stop_phys(hisi_hba); 844 udelay(50); 845 846 /* Ensure axi bus idle */ 847 ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val, 848 20000, 1000000); 849 if (ret) { 850 dev_err(dev, "axi bus is not idle, ret = %d!\n", ret); 851 return -EIO; 852 } 853 854 if (ACPI_HANDLE(dev)) { 855 acpi_status s; 856 857 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL); 858 if (ACPI_FAILURE(s)) { 859 dev_err(dev, "Reset failed\n"); 860 return -EIO; 861 } 862 } else { 863 dev_err(dev, "no reset method!\n"); 864 return -EINVAL; 865 } 866 867 return 0; 868 } 869 870 static int hw_init_v3_hw(struct hisi_hba *hisi_hba) 871 { 872 struct device *dev = hisi_hba->dev; 873 union acpi_object *obj; 874 guid_t guid; 875 int rc; 876 877 rc = reset_hw_v3_hw(hisi_hba); 878 if (rc) { 879 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc); 880 return rc; 881 } 882 883 msleep(100); 884 init_reg_v3_hw(hisi_hba); 885 886 if (guid_parse("D5918B4B-37AE-4E10-A99F-E5E8A6EF4C1F", &guid)) { 887 dev_err(dev, "Parse GUID failed\n"); 888 return -EINVAL; 889 } 890 891 /* Switch over to MSI handling , from PCI AER default */ 892 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &guid, 0, 893 DSM_FUNC_ERR_HANDLE_MSI, NULL); 894 if (!obj) 895 dev_warn(dev, "Switch over to MSI handling failed\n"); 896 else 897 ACPI_FREE(obj); 898 899 return 0; 900 } 901 902 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 903 { 904 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 905 906 cfg |= PHY_CFG_ENA_MSK; 907 cfg &= ~PHY_CFG_PHY_RST_MSK; 908 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 909 } 910 911 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 912 { 913 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 914 u32 state; 915 916 cfg &= ~PHY_CFG_ENA_MSK; 917 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 918 919 mdelay(50); 920 921 state = hisi_sas_read32(hisi_hba, PHY_STATE); 922 if (state & BIT(phy_no)) { 923 cfg |= PHY_CFG_PHY_RST_MSK; 924 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 925 } 926 } 927 928 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 929 { 930 config_id_frame_v3_hw(hisi_hba, phy_no); 931 config_phy_opt_mode_v3_hw(hisi_hba, phy_no); 932 enable_phy_v3_hw(hisi_hba, phy_no); 933 } 934 935 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 936 { 937 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 938 u32 txid_auto; 939 940 hisi_sas_phy_enable(hisi_hba, phy_no, 0); 941 if (phy->identify.device_type == SAS_END_DEVICE) { 942 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); 943 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, 944 txid_auto | TX_HARDRST_MSK); 945 } 946 msleep(100); 947 hisi_sas_phy_enable(hisi_hba, phy_no, 1); 948 } 949 950 static enum sas_linkrate phy_get_max_linkrate_v3_hw(void) 951 { 952 return SAS_LINK_RATE_12_0_GBPS; 953 } 954 955 static void phys_init_v3_hw(struct hisi_hba *hisi_hba) 956 { 957 int i; 958 959 for (i = 0; i < hisi_hba->n_phy; i++) { 960 struct hisi_sas_phy *phy = &hisi_hba->phy[i]; 961 struct asd_sas_phy *sas_phy = &phy->sas_phy; 962 963 if (!sas_phy->phy->enabled) 964 continue; 965 966 hisi_sas_phy_enable(hisi_hba, i, 1); 967 } 968 } 969 970 static void sl_notify_ssp_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 971 { 972 u32 sl_control; 973 974 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 975 sl_control |= SL_CONTROL_NOTIFY_EN_MSK; 976 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 977 msleep(1); 978 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 979 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK; 980 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 981 } 982 983 static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id) 984 { 985 int i, bitmap = 0; 986 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 987 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 988 989 for (i = 0; i < hisi_hba->n_phy; i++) 990 if (phy_state & BIT(i)) 991 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id) 992 bitmap |= BIT(i); 993 994 return bitmap; 995 } 996 997 /** 998 * The callpath to this function and upto writing the write 999 * queue pointer should be safe from interruption. 1000 */ 1001 static int 1002 get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq) 1003 { 1004 struct device *dev = hisi_hba->dev; 1005 int queue = dq->id; 1006 u32 r, w; 1007 1008 w = dq->wr_point; 1009 r = hisi_sas_read32_relaxed(hisi_hba, 1010 DLVRY_Q_0_RD_PTR + (queue * 0x14)); 1011 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) { 1012 dev_warn(dev, "full queue=%d r=%d w=%d\n", 1013 queue, r, w); 1014 return -EAGAIN; 1015 } 1016 1017 dq->wr_point = (dq->wr_point + 1) % HISI_SAS_QUEUE_SLOTS; 1018 1019 return w; 1020 } 1021 1022 static void start_delivery_v3_hw(struct hisi_sas_dq *dq) 1023 { 1024 struct hisi_hba *hisi_hba = dq->hisi_hba; 1025 struct hisi_sas_slot *s, *s1, *s2 = NULL; 1026 int dlvry_queue = dq->id; 1027 int wp; 1028 1029 list_for_each_entry_safe(s, s1, &dq->list, delivery) { 1030 if (!s->ready) 1031 break; 1032 s2 = s; 1033 list_del(&s->delivery); 1034 } 1035 1036 if (!s2) 1037 return; 1038 1039 /* 1040 * Ensure that memories for slots built on other CPUs is observed. 1041 */ 1042 smp_rmb(); 1043 wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS; 1044 1045 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp); 1046 } 1047 1048 static void prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba, 1049 struct hisi_sas_slot *slot, 1050 struct hisi_sas_cmd_hdr *hdr, 1051 struct scatterlist *scatter, 1052 int n_elem) 1053 { 1054 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot); 1055 struct scatterlist *sg; 1056 int i; 1057 1058 for_each_sg(scatter, sg, n_elem, i) { 1059 struct hisi_sas_sge *entry = &sge_page->sge[i]; 1060 1061 entry->addr = cpu_to_le64(sg_dma_address(sg)); 1062 entry->page_ctrl_0 = entry->page_ctrl_1 = 0; 1063 entry->data_len = cpu_to_le32(sg_dma_len(sg)); 1064 entry->data_off = 0; 1065 } 1066 1067 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot)); 1068 1069 hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF); 1070 } 1071 1072 static void prep_prd_sge_dif_v3_hw(struct hisi_hba *hisi_hba, 1073 struct hisi_sas_slot *slot, 1074 struct hisi_sas_cmd_hdr *hdr, 1075 struct scatterlist *scatter, 1076 int n_elem) 1077 { 1078 struct hisi_sas_sge_dif_page *sge_dif_page; 1079 struct scatterlist *sg; 1080 int i; 1081 1082 sge_dif_page = hisi_sas_sge_dif_addr_mem(slot); 1083 1084 for_each_sg(scatter, sg, n_elem, i) { 1085 struct hisi_sas_sge *entry = &sge_dif_page->sge[i]; 1086 1087 entry->addr = cpu_to_le64(sg_dma_address(sg)); 1088 entry->page_ctrl_0 = 0; 1089 entry->page_ctrl_1 = 0; 1090 entry->data_len = cpu_to_le32(sg_dma_len(sg)); 1091 entry->data_off = 0; 1092 } 1093 1094 hdr->dif_prd_table_addr = 1095 cpu_to_le64(hisi_sas_sge_dif_addr_dma(slot)); 1096 1097 hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DIF_SGL_LEN_OFF); 1098 } 1099 1100 static u32 get_prot_chk_msk_v3_hw(struct scsi_cmnd *scsi_cmnd) 1101 { 1102 unsigned char prot_flags = scsi_cmnd->prot_flags; 1103 1104 if (prot_flags & SCSI_PROT_REF_CHECK) 1105 return T10_CHK_APP_TAG_MSK; 1106 return T10_CHK_REF_TAG_MSK | T10_CHK_APP_TAG_MSK; 1107 } 1108 1109 static void fill_prot_v3_hw(struct scsi_cmnd *scsi_cmnd, 1110 struct hisi_sas_protect_iu_v3_hw *prot) 1111 { 1112 unsigned char prot_op = scsi_get_prot_op(scsi_cmnd); 1113 unsigned int interval = scsi_prot_interval(scsi_cmnd); 1114 u32 lbrt_chk_val = t10_pi_ref_tag(scsi_cmnd->request); 1115 1116 switch (prot_op) { 1117 case SCSI_PROT_READ_INSERT: 1118 prot->dw0 |= T10_INSRT_EN_MSK; 1119 prot->lbrtgv = lbrt_chk_val; 1120 break; 1121 case SCSI_PROT_READ_STRIP: 1122 prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK); 1123 prot->lbrtcv = lbrt_chk_val; 1124 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd); 1125 break; 1126 case SCSI_PROT_READ_PASS: 1127 prot->dw0 |= T10_CHK_EN_MSK; 1128 prot->lbrtcv = lbrt_chk_val; 1129 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd); 1130 break; 1131 case SCSI_PROT_WRITE_INSERT: 1132 prot->dw0 |= T10_INSRT_EN_MSK; 1133 prot->lbrtgv = lbrt_chk_val; 1134 break; 1135 case SCSI_PROT_WRITE_STRIP: 1136 prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK); 1137 prot->lbrtcv = lbrt_chk_val; 1138 break; 1139 case SCSI_PROT_WRITE_PASS: 1140 prot->dw0 |= T10_CHK_EN_MSK; 1141 prot->lbrtcv = lbrt_chk_val; 1142 prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd); 1143 break; 1144 default: 1145 WARN(1, "prot_op(0x%x) is not valid\n", prot_op); 1146 break; 1147 } 1148 1149 switch (interval) { 1150 case 512: 1151 break; 1152 case 4096: 1153 prot->dw0 |= (0x1 << USR_DATA_BLOCK_SZ_OFF); 1154 break; 1155 case 520: 1156 prot->dw0 |= (0x2 << USR_DATA_BLOCK_SZ_OFF); 1157 break; 1158 default: 1159 WARN(1, "protection interval (0x%x) invalid\n", 1160 interval); 1161 break; 1162 } 1163 1164 prot->dw0 |= INCR_LBRT_MSK; 1165 } 1166 1167 static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba, 1168 struct hisi_sas_slot *slot) 1169 { 1170 struct sas_task *task = slot->task; 1171 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1172 struct domain_device *device = task->dev; 1173 struct hisi_sas_device *sas_dev = device->lldd_dev; 1174 struct hisi_sas_port *port = slot->port; 1175 struct sas_ssp_task *ssp_task = &task->ssp_task; 1176 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd; 1177 struct hisi_sas_tmf_task *tmf = slot->tmf; 1178 int has_data = 0, priority = !!tmf; 1179 unsigned char prot_op; 1180 u8 *buf_cmd; 1181 u32 dw1 = 0, dw2 = 0, len = 0; 1182 1183 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) | 1184 (2 << CMD_HDR_TLR_CTRL_OFF) | 1185 (port->id << CMD_HDR_PORT_OFF) | 1186 (priority << CMD_HDR_PRIORITY_OFF) | 1187 (1 << CMD_HDR_CMD_OFF)); /* ssp */ 1188 1189 dw1 = 1 << CMD_HDR_VDTL_OFF; 1190 if (tmf) { 1191 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF; 1192 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF; 1193 } else { 1194 prot_op = scsi_get_prot_op(scsi_cmnd); 1195 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF; 1196 switch (scsi_cmnd->sc_data_direction) { 1197 case DMA_TO_DEVICE: 1198 has_data = 1; 1199 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; 1200 break; 1201 case DMA_FROM_DEVICE: 1202 has_data = 1; 1203 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; 1204 break; 1205 default: 1206 dw1 &= ~CMD_HDR_DIR_MSK; 1207 } 1208 } 1209 1210 /* map itct entry */ 1211 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; 1212 1213 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr) 1214 + 3) / 4) << CMD_HDR_CFL_OFF) | 1215 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) | 1216 (2 << CMD_HDR_SG_MOD_OFF); 1217 hdr->dw2 = cpu_to_le32(dw2); 1218 hdr->transfer_tags = cpu_to_le32(slot->idx); 1219 1220 if (has_data) { 1221 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, 1222 slot->n_elem); 1223 1224 if (scsi_prot_sg_count(scsi_cmnd)) 1225 prep_prd_sge_dif_v3_hw(hisi_hba, slot, hdr, 1226 scsi_prot_sglist(scsi_cmnd), 1227 slot->n_elem_dif); 1228 } 1229 1230 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); 1231 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1232 1233 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) + 1234 sizeof(struct ssp_frame_hdr); 1235 1236 memcpy(buf_cmd, &task->ssp_task.LUN, 8); 1237 if (!tmf) { 1238 buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3); 1239 memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len); 1240 } else { 1241 buf_cmd[10] = tmf->tmf; 1242 switch (tmf->tmf) { 1243 case TMF_ABORT_TASK: 1244 case TMF_QUERY_TASK: 1245 buf_cmd[12] = 1246 (tmf->tag_of_task_to_be_managed >> 8) & 0xff; 1247 buf_cmd[13] = 1248 tmf->tag_of_task_to_be_managed & 0xff; 1249 break; 1250 default: 1251 break; 1252 } 1253 } 1254 1255 if (has_data && (prot_op != SCSI_PROT_NORMAL)) { 1256 struct hisi_sas_protect_iu_v3_hw prot; 1257 u8 *buf_cmd_prot; 1258 1259 hdr->dw7 |= cpu_to_le32(1 << CMD_HDR_ADDR_MODE_SEL_OFF); 1260 dw1 |= CMD_HDR_PIR_MSK; 1261 buf_cmd_prot = hisi_sas_cmd_hdr_addr_mem(slot) + 1262 sizeof(struct ssp_frame_hdr) + 1263 sizeof(struct ssp_command_iu); 1264 1265 memset(&prot, 0, sizeof(struct hisi_sas_protect_iu_v3_hw)); 1266 fill_prot_v3_hw(scsi_cmnd, &prot); 1267 memcpy(buf_cmd_prot, &prot, 1268 sizeof(struct hisi_sas_protect_iu_v3_hw)); 1269 /* 1270 * For READ, we need length of info read to memory, while for 1271 * WRITE we need length of data written to the disk. 1272 */ 1273 if (prot_op == SCSI_PROT_WRITE_INSERT || 1274 prot_op == SCSI_PROT_READ_INSERT || 1275 prot_op == SCSI_PROT_WRITE_PASS || 1276 prot_op == SCSI_PROT_READ_PASS) { 1277 unsigned int interval = scsi_prot_interval(scsi_cmnd); 1278 unsigned int ilog2_interval = ilog2(interval); 1279 1280 len = (task->total_xfer_len >> ilog2_interval) * 8; 1281 } 1282 } 1283 1284 hdr->dw1 = cpu_to_le32(dw1); 1285 1286 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len + len); 1287 } 1288 1289 static void prep_smp_v3_hw(struct hisi_hba *hisi_hba, 1290 struct hisi_sas_slot *slot) 1291 { 1292 struct sas_task *task = slot->task; 1293 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1294 struct domain_device *device = task->dev; 1295 struct hisi_sas_port *port = slot->port; 1296 struct scatterlist *sg_req; 1297 struct hisi_sas_device *sas_dev = device->lldd_dev; 1298 dma_addr_t req_dma_addr; 1299 unsigned int req_len; 1300 1301 /* req */ 1302 sg_req = &task->smp_task.smp_req; 1303 req_len = sg_dma_len(sg_req); 1304 req_dma_addr = sg_dma_address(sg_req); 1305 1306 /* create header */ 1307 /* dw0 */ 1308 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) | 1309 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */ 1310 (2 << CMD_HDR_CMD_OFF)); /* smp */ 1311 1312 /* map itct entry */ 1313 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) | 1314 (1 << CMD_HDR_FRAME_TYPE_OFF) | 1315 (DIR_NO_DATA << CMD_HDR_DIR_OFF)); 1316 1317 /* dw2 */ 1318 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) | 1319 (HISI_SAS_MAX_SMP_RESP_SZ / 4 << 1320 CMD_HDR_MRFL_OFF)); 1321 1322 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF); 1323 1324 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr); 1325 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1326 1327 } 1328 1329 static void prep_ata_v3_hw(struct hisi_hba *hisi_hba, 1330 struct hisi_sas_slot *slot) 1331 { 1332 struct sas_task *task = slot->task; 1333 struct domain_device *device = task->dev; 1334 struct domain_device *parent_dev = device->parent; 1335 struct hisi_sas_device *sas_dev = device->lldd_dev; 1336 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1337 struct asd_sas_port *sas_port = device->port; 1338 struct hisi_sas_port *port = to_hisi_sas_port(sas_port); 1339 u8 *buf_cmd; 1340 int has_data = 0, hdr_tag = 0; 1341 u32 dw1 = 0, dw2 = 0; 1342 1343 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF); 1344 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) 1345 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF); 1346 else 1347 hdr->dw0 |= cpu_to_le32(4U << CMD_HDR_CMD_OFF); 1348 1349 switch (task->data_dir) { 1350 case DMA_TO_DEVICE: 1351 has_data = 1; 1352 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; 1353 break; 1354 case DMA_FROM_DEVICE: 1355 has_data = 1; 1356 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; 1357 break; 1358 default: 1359 dw1 &= ~CMD_HDR_DIR_MSK; 1360 } 1361 1362 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) && 1363 (task->ata_task.fis.control & ATA_SRST)) 1364 dw1 |= 1 << CMD_HDR_RESET_OFF; 1365 1366 dw1 |= (hisi_sas_get_ata_protocol( 1367 &task->ata_task.fis, task->data_dir)) 1368 << CMD_HDR_FRAME_TYPE_OFF; 1369 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; 1370 1371 if (FIS_CMD_IS_UNCONSTRAINED(task->ata_task.fis)) 1372 dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF; 1373 1374 hdr->dw1 = cpu_to_le32(dw1); 1375 1376 /* dw2 */ 1377 if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) { 1378 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); 1379 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF; 1380 } 1381 1382 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF | 1383 2 << CMD_HDR_SG_MOD_OFF; 1384 hdr->dw2 = cpu_to_le32(dw2); 1385 1386 /* dw3 */ 1387 hdr->transfer_tags = cpu_to_le32(slot->idx); 1388 1389 if (has_data) 1390 prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, 1391 slot->n_elem); 1392 1393 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); 1394 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); 1395 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1396 1397 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot); 1398 1399 if (likely(!task->ata_task.device_control_reg_update)) 1400 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */ 1401 /* fill in command FIS */ 1402 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis)); 1403 } 1404 1405 static void prep_abort_v3_hw(struct hisi_hba *hisi_hba, 1406 struct hisi_sas_slot *slot, 1407 int device_id, int abort_flag, int tag_to_abort) 1408 { 1409 struct sas_task *task = slot->task; 1410 struct domain_device *dev = task->dev; 1411 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1412 struct hisi_sas_port *port = slot->port; 1413 1414 /* dw0 */ 1415 hdr->dw0 = cpu_to_le32((5U << CMD_HDR_CMD_OFF) | /*abort*/ 1416 (port->id << CMD_HDR_PORT_OFF) | 1417 (dev_is_sata(dev) 1418 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) | 1419 (abort_flag 1420 << CMD_HDR_ABORT_FLAG_OFF)); 1421 1422 /* dw1 */ 1423 hdr->dw1 = cpu_to_le32(device_id 1424 << CMD_HDR_DEV_ID_OFF); 1425 1426 /* dw7 */ 1427 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF); 1428 hdr->transfer_tags = cpu_to_le32(slot->idx); 1429 1430 } 1431 1432 static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1433 { 1434 int i; 1435 irqreturn_t res; 1436 u32 context, port_id, link_rate; 1437 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1438 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1439 struct device *dev = hisi_hba->dev; 1440 unsigned long flags; 1441 1442 del_timer(&phy->timer); 1443 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1); 1444 1445 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 1446 port_id = (port_id >> (4 * phy_no)) & 0xf; 1447 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); 1448 link_rate = (link_rate >> (phy_no * 4)) & 0xf; 1449 1450 if (port_id == 0xf) { 1451 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no); 1452 res = IRQ_NONE; 1453 goto end; 1454 } 1455 sas_phy->linkrate = link_rate; 1456 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); 1457 1458 /* Check for SATA dev */ 1459 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT); 1460 if (context & (1 << phy_no)) { 1461 struct hisi_sas_initial_fis *initial_fis; 1462 struct dev_to_host_fis *fis; 1463 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0}; 1464 struct Scsi_Host *shost = hisi_hba->shost; 1465 1466 dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate); 1467 initial_fis = &hisi_hba->initial_fis[phy_no]; 1468 fis = &initial_fis->fis; 1469 1470 /* check ERR bit of Status Register */ 1471 if (fis->status & ATA_ERR) { 1472 dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", 1473 phy_no, fis->status); 1474 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1475 res = IRQ_NONE; 1476 goto end; 1477 } 1478 1479 sas_phy->oob_mode = SATA_OOB_MODE; 1480 attached_sas_addr[0] = 0x50; 1481 attached_sas_addr[6] = shost->host_no; 1482 attached_sas_addr[7] = phy_no; 1483 memcpy(sas_phy->attached_sas_addr, 1484 attached_sas_addr, 1485 SAS_ADDR_SIZE); 1486 memcpy(sas_phy->frame_rcvd, fis, 1487 sizeof(struct dev_to_host_fis)); 1488 phy->phy_type |= PORT_TYPE_SATA; 1489 phy->identify.device_type = SAS_SATA_DEV; 1490 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 1491 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 1492 } else { 1493 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd; 1494 struct sas_identify_frame *id = 1495 (struct sas_identify_frame *)frame_rcvd; 1496 1497 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate); 1498 for (i = 0; i < 6; i++) { 1499 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no, 1500 RX_IDAF_DWORD0 + (i * 4)); 1501 frame_rcvd[i] = __swab32(idaf); 1502 } 1503 sas_phy->oob_mode = SAS_OOB_MODE; 1504 memcpy(sas_phy->attached_sas_addr, 1505 &id->sas_addr, 1506 SAS_ADDR_SIZE); 1507 phy->phy_type |= PORT_TYPE_SAS; 1508 phy->identify.device_type = id->dev_type; 1509 phy->frame_rcvd_size = sizeof(struct sas_identify_frame); 1510 if (phy->identify.device_type == SAS_END_DEVICE) 1511 phy->identify.target_port_protocols = 1512 SAS_PROTOCOL_SSP; 1513 else if (phy->identify.device_type != SAS_PHY_UNUSED) 1514 phy->identify.target_port_protocols = 1515 SAS_PROTOCOL_SMP; 1516 } 1517 1518 phy->port_id = port_id; 1519 phy->phy_attached = 1; 1520 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP); 1521 res = IRQ_HANDLED; 1522 spin_lock_irqsave(&phy->lock, flags); 1523 if (phy->reset_completion) { 1524 phy->in_reset = 0; 1525 complete(phy->reset_completion); 1526 } 1527 spin_unlock_irqrestore(&phy->lock, flags); 1528 end: 1529 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1530 CHL_INT0_SL_PHY_ENABLE_MSK); 1531 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0); 1532 1533 return res; 1534 } 1535 1536 static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1537 { 1538 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1539 u32 phy_state, sl_ctrl, txid_auto; 1540 struct device *dev = hisi_hba->dev; 1541 1542 del_timer(&phy->timer); 1543 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1); 1544 1545 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1546 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state); 1547 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0); 1548 1549 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 1550 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, 1551 sl_ctrl&(~SL_CTA_MSK)); 1552 1553 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); 1554 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, 1555 txid_auto | CT3_MSK); 1556 1557 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK); 1558 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0); 1559 1560 return IRQ_HANDLED; 1561 } 1562 1563 static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba) 1564 { 1565 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1566 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1567 struct sas_ha_struct *sas_ha = &hisi_hba->sha; 1568 u32 bcast_status; 1569 1570 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1); 1571 bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS); 1572 if ((bcast_status & RX_BCAST_CHG_MSK) && 1573 !test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)) 1574 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 1575 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1576 CHL_INT0_SL_RX_BCST_ACK_MSK); 1577 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0); 1578 1579 return IRQ_HANDLED; 1580 } 1581 1582 static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p) 1583 { 1584 struct hisi_hba *hisi_hba = p; 1585 u32 irq_msk; 1586 int phy_no = 0; 1587 irqreturn_t res = IRQ_NONE; 1588 1589 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) 1590 & 0x11111111; 1591 while (irq_msk) { 1592 if (irq_msk & 1) { 1593 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, 1594 CHL_INT0); 1595 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1596 int rdy = phy_state & (1 << phy_no); 1597 1598 if (rdy) { 1599 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK) 1600 /* phy up */ 1601 if (phy_up_v3_hw(phy_no, hisi_hba) 1602 == IRQ_HANDLED) 1603 res = IRQ_HANDLED; 1604 if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK) 1605 /* phy bcast */ 1606 if (phy_bcast_v3_hw(phy_no, hisi_hba) 1607 == IRQ_HANDLED) 1608 res = IRQ_HANDLED; 1609 } else { 1610 if (irq_value & CHL_INT0_NOT_RDY_MSK) 1611 /* phy down */ 1612 if (phy_down_v3_hw(phy_no, hisi_hba) 1613 == IRQ_HANDLED) 1614 res = IRQ_HANDLED; 1615 } 1616 } 1617 irq_msk >>= 4; 1618 phy_no++; 1619 } 1620 1621 return res; 1622 } 1623 1624 static const struct hisi_sas_hw_error port_axi_error[] = { 1625 { 1626 .irq_msk = BIT(CHL_INT1_DMAC_TX_ECC_MB_ERR_OFF), 1627 .msg = "dmac_tx_ecc_bad_err", 1628 }, 1629 { 1630 .irq_msk = BIT(CHL_INT1_DMAC_RX_ECC_MB_ERR_OFF), 1631 .msg = "dmac_rx_ecc_bad_err", 1632 }, 1633 { 1634 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF), 1635 .msg = "dma_tx_axi_wr_err", 1636 }, 1637 { 1638 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF), 1639 .msg = "dma_tx_axi_rd_err", 1640 }, 1641 { 1642 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF), 1643 .msg = "dma_rx_axi_wr_err", 1644 }, 1645 { 1646 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF), 1647 .msg = "dma_rx_axi_rd_err", 1648 }, 1649 { 1650 .irq_msk = BIT(CHL_INT1_DMAC_TX_FIFO_ERR_OFF), 1651 .msg = "dma_tx_fifo_err", 1652 }, 1653 { 1654 .irq_msk = BIT(CHL_INT1_DMAC_RX_FIFO_ERR_OFF), 1655 .msg = "dma_rx_fifo_err", 1656 }, 1657 { 1658 .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RUSER_ERR_OFF), 1659 .msg = "dma_tx_axi_ruser_err", 1660 }, 1661 { 1662 .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RUSER_ERR_OFF), 1663 .msg = "dma_rx_axi_ruser_err", 1664 }, 1665 }; 1666 1667 static void handle_chl_int1_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 1668 { 1669 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1); 1670 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1_MSK); 1671 struct device *dev = hisi_hba->dev; 1672 int i; 1673 1674 irq_value &= ~irq_msk; 1675 if (!irq_value) 1676 return; 1677 1678 for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) { 1679 const struct hisi_sas_hw_error *error = &port_axi_error[i]; 1680 1681 if (!(irq_value & error->irq_msk)) 1682 continue; 1683 1684 dev_err(dev, "%s error (phy%d 0x%x) found!\n", 1685 error->msg, phy_no, irq_value); 1686 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1687 } 1688 1689 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT1, irq_value); 1690 } 1691 1692 static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 1693 { 1694 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1695 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1696 struct sas_phy *sphy = sas_phy->phy; 1697 unsigned long flags; 1698 u32 reg_value; 1699 1700 spin_lock_irqsave(&phy->lock, flags); 1701 1702 /* loss dword sync */ 1703 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST); 1704 sphy->loss_of_dword_sync_count += reg_value; 1705 1706 /* phy reset problem */ 1707 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB); 1708 sphy->phy_reset_problem_count += reg_value; 1709 1710 /* invalid dword */ 1711 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW); 1712 sphy->invalid_dword_count += reg_value; 1713 1714 /* disparity err */ 1715 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR); 1716 sphy->running_disparity_error_count += reg_value; 1717 1718 /* code violation error */ 1719 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR); 1720 phy->code_violation_err_count += reg_value; 1721 1722 spin_unlock_irqrestore(&phy->lock, flags); 1723 } 1724 1725 static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 1726 { 1727 u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK); 1728 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2); 1729 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1730 struct pci_dev *pci_dev = hisi_hba->pci_dev; 1731 struct device *dev = hisi_hba->dev; 1732 static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) | 1733 BIT(CHL_INT2_RX_CODE_ERR_OFF) | 1734 BIT(CHL_INT2_RX_INVLD_DW_OFF); 1735 1736 irq_value &= ~irq_msk; 1737 if (!irq_value) 1738 return; 1739 1740 if (irq_value & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) { 1741 dev_warn(dev, "phy%d identify timeout\n", phy_no); 1742 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1743 } 1744 1745 if (irq_value & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) { 1746 u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, 1747 STP_LINK_TIMEOUT_STATE); 1748 1749 dev_warn(dev, "phy%d stp link timeout (0x%x)\n", 1750 phy_no, reg_value); 1751 if (reg_value & BIT(4)) 1752 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1753 } 1754 1755 if (pci_dev->revision > 0x20 && (irq_value & msk)) { 1756 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1757 struct sas_phy *sphy = sas_phy->phy; 1758 1759 phy_get_events_v3_hw(hisi_hba, phy_no); 1760 1761 if (irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) 1762 dev_info(dev, "phy%d invalid dword cnt: %u\n", phy_no, 1763 sphy->invalid_dword_count); 1764 1765 if (irq_value & BIT(CHL_INT2_RX_CODE_ERR_OFF)) 1766 dev_info(dev, "phy%d code violation cnt: %u\n", phy_no, 1767 phy->code_violation_err_count); 1768 1769 if (irq_value & BIT(CHL_INT2_RX_DISP_ERR_OFF)) 1770 dev_info(dev, "phy%d disparity error cnt: %u\n", phy_no, 1771 sphy->running_disparity_error_count); 1772 } 1773 1774 if ((irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) && 1775 (pci_dev->revision == 0x20)) { 1776 u32 reg_value; 1777 int rc; 1778 1779 rc = hisi_sas_read32_poll_timeout_atomic( 1780 HILINK_ERR_DFX, reg_value, 1781 !((reg_value >> 8) & BIT(phy_no)), 1782 1000, 10000); 1783 if (rc) 1784 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); 1785 } 1786 1787 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value); 1788 } 1789 1790 static void handle_chl_int0_v3_hw(struct hisi_hba *hisi_hba, int phy_no) 1791 { 1792 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0); 1793 1794 if (irq_value0 & CHL_INT0_PHY_RDY_MSK) 1795 hisi_sas_phy_oob_ready(hisi_hba, phy_no); 1796 1797 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1798 irq_value0 & (~CHL_INT0_SL_RX_BCST_ACK_MSK) 1799 & (~CHL_INT0_SL_PHY_ENABLE_MSK) 1800 & (~CHL_INT0_NOT_RDY_MSK)); 1801 } 1802 1803 static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) 1804 { 1805 struct hisi_hba *hisi_hba = p; 1806 u32 irq_msk; 1807 int phy_no = 0; 1808 1809 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) 1810 & 0xeeeeeeee; 1811 1812 while (irq_msk) { 1813 if (irq_msk & (2 << (phy_no * 4))) 1814 handle_chl_int0_v3_hw(hisi_hba, phy_no); 1815 1816 if (irq_msk & (4 << (phy_no * 4))) 1817 handle_chl_int1_v3_hw(hisi_hba, phy_no); 1818 1819 if (irq_msk & (8 << (phy_no * 4))) 1820 handle_chl_int2_v3_hw(hisi_hba, phy_no); 1821 1822 irq_msk &= ~(0xe << (phy_no * 4)); 1823 phy_no++; 1824 } 1825 1826 return IRQ_HANDLED; 1827 } 1828 1829 static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = { 1830 { 1831 .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF), 1832 .msk = HGC_DQE_ECC_MB_ADDR_MSK, 1833 .shift = HGC_DQE_ECC_MB_ADDR_OFF, 1834 .msg = "hgc_dqe_eccbad_intr", 1835 .reg = HGC_DQE_ECC_ADDR, 1836 }, 1837 { 1838 .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF), 1839 .msk = HGC_IOST_ECC_MB_ADDR_MSK, 1840 .shift = HGC_IOST_ECC_MB_ADDR_OFF, 1841 .msg = "hgc_iost_eccbad_intr", 1842 .reg = HGC_IOST_ECC_ADDR, 1843 }, 1844 { 1845 .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF), 1846 .msk = HGC_ITCT_ECC_MB_ADDR_MSK, 1847 .shift = HGC_ITCT_ECC_MB_ADDR_OFF, 1848 .msg = "hgc_itct_eccbad_intr", 1849 .reg = HGC_ITCT_ECC_ADDR, 1850 }, 1851 { 1852 .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF), 1853 .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK, 1854 .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF, 1855 .msg = "hgc_iostl_eccbad_intr", 1856 .reg = HGC_LM_DFX_STATUS2, 1857 }, 1858 { 1859 .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF), 1860 .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK, 1861 .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF, 1862 .msg = "hgc_itctl_eccbad_intr", 1863 .reg = HGC_LM_DFX_STATUS2, 1864 }, 1865 { 1866 .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF), 1867 .msk = HGC_CQE_ECC_MB_ADDR_MSK, 1868 .shift = HGC_CQE_ECC_MB_ADDR_OFF, 1869 .msg = "hgc_cqe_eccbad_intr", 1870 .reg = HGC_CQE_ECC_ADDR, 1871 }, 1872 { 1873 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF), 1874 .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK, 1875 .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF, 1876 .msg = "rxm_mem0_eccbad_intr", 1877 .reg = HGC_RXM_DFX_STATUS14, 1878 }, 1879 { 1880 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF), 1881 .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK, 1882 .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF, 1883 .msg = "rxm_mem1_eccbad_intr", 1884 .reg = HGC_RXM_DFX_STATUS14, 1885 }, 1886 { 1887 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF), 1888 .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK, 1889 .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF, 1890 .msg = "rxm_mem2_eccbad_intr", 1891 .reg = HGC_RXM_DFX_STATUS14, 1892 }, 1893 { 1894 .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF), 1895 .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK, 1896 .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF, 1897 .msg = "rxm_mem3_eccbad_intr", 1898 .reg = HGC_RXM_DFX_STATUS15, 1899 }, 1900 { 1901 .irq_msk = BIT(SAS_ECC_INTR_OOO_RAM_ECC_MB_OFF), 1902 .msk = AM_ROB_ECC_ERR_ADDR_MSK, 1903 .shift = AM_ROB_ECC_ERR_ADDR_OFF, 1904 .msg = "ooo_ram_eccbad_intr", 1905 .reg = AM_ROB_ECC_ERR_ADDR, 1906 }, 1907 }; 1908 1909 static void multi_bit_ecc_error_process_v3_hw(struct hisi_hba *hisi_hba, 1910 u32 irq_value) 1911 { 1912 struct device *dev = hisi_hba->dev; 1913 const struct hisi_sas_hw_error *ecc_error; 1914 u32 val; 1915 int i; 1916 1917 for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) { 1918 ecc_error = &multi_bit_ecc_errors[i]; 1919 if (irq_value & ecc_error->irq_msk) { 1920 val = hisi_sas_read32(hisi_hba, ecc_error->reg); 1921 val &= ecc_error->msk; 1922 val >>= ecc_error->shift; 1923 dev_err(dev, "%s (0x%x) found: mem addr is 0x%08X\n", 1924 ecc_error->msg, irq_value, val); 1925 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 1926 } 1927 } 1928 } 1929 1930 static void fatal_ecc_int_v3_hw(struct hisi_hba *hisi_hba) 1931 { 1932 u32 irq_value, irq_msk; 1933 1934 irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK); 1935 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk | 0xffffffff); 1936 1937 irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR); 1938 if (irq_value) 1939 multi_bit_ecc_error_process_v3_hw(hisi_hba, irq_value); 1940 1941 hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value); 1942 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk); 1943 } 1944 1945 static const struct hisi_sas_hw_error axi_error[] = { 1946 { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" }, 1947 { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" }, 1948 { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" }, 1949 { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" }, 1950 { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" }, 1951 { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" }, 1952 { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" }, 1953 { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" }, 1954 {} 1955 }; 1956 1957 static const struct hisi_sas_hw_error fifo_error[] = { 1958 { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" }, 1959 { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" }, 1960 { .msk = BIT(10), .msg = "GETDQE_FIFO" }, 1961 { .msk = BIT(11), .msg = "CMDP_FIFO" }, 1962 { .msk = BIT(12), .msg = "AWTCTRL_FIFO" }, 1963 {} 1964 }; 1965 1966 static const struct hisi_sas_hw_error fatal_axi_error[] = { 1967 { 1968 .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF), 1969 .msg = "write pointer and depth", 1970 }, 1971 { 1972 .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF), 1973 .msg = "iptt no match slot", 1974 }, 1975 { 1976 .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF), 1977 .msg = "read pointer and depth", 1978 }, 1979 { 1980 .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF), 1981 .reg = HGC_AXI_FIFO_ERR_INFO, 1982 .sub = axi_error, 1983 }, 1984 { 1985 .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF), 1986 .reg = HGC_AXI_FIFO_ERR_INFO, 1987 .sub = fifo_error, 1988 }, 1989 { 1990 .irq_msk = BIT(ENT_INT_SRC3_LM_OFF), 1991 .msg = "LM add/fetch list", 1992 }, 1993 { 1994 .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF), 1995 .msg = "SAS_HGC_ABT fetch LM list", 1996 }, 1997 { 1998 .irq_msk = BIT(ENT_INT_SRC3_DQE_POISON_OFF), 1999 .msg = "read dqe poison", 2000 }, 2001 { 2002 .irq_msk = BIT(ENT_INT_SRC3_IOST_POISON_OFF), 2003 .msg = "read iost poison", 2004 }, 2005 { 2006 .irq_msk = BIT(ENT_INT_SRC3_ITCT_POISON_OFF), 2007 .msg = "read itct poison", 2008 }, 2009 { 2010 .irq_msk = BIT(ENT_INT_SRC3_ITCT_NCQ_POISON_OFF), 2011 .msg = "read itct ncq poison", 2012 }, 2013 2014 }; 2015 2016 static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p) 2017 { 2018 u32 irq_value, irq_msk; 2019 struct hisi_hba *hisi_hba = p; 2020 struct device *dev = hisi_hba->dev; 2021 struct pci_dev *pdev = hisi_hba->pci_dev; 2022 int i; 2023 2024 irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3); 2025 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00); 2026 2027 irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); 2028 irq_value &= ~irq_msk; 2029 2030 for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) { 2031 const struct hisi_sas_hw_error *error = &fatal_axi_error[i]; 2032 2033 if (!(irq_value & error->irq_msk)) 2034 continue; 2035 2036 if (error->sub) { 2037 const struct hisi_sas_hw_error *sub = error->sub; 2038 u32 err_value = hisi_sas_read32(hisi_hba, error->reg); 2039 2040 for (; sub->msk || sub->msg; sub++) { 2041 if (!(err_value & sub->msk)) 2042 continue; 2043 2044 dev_err(dev, "%s error (0x%x) found!\n", 2045 sub->msg, irq_value); 2046 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 2047 } 2048 } else { 2049 dev_err(dev, "%s error (0x%x) found!\n", 2050 error->msg, irq_value); 2051 queue_work(hisi_hba->wq, &hisi_hba->rst_work); 2052 } 2053 2054 if (pdev->revision < 0x21) { 2055 u32 reg_val; 2056 2057 reg_val = hisi_sas_read32(hisi_hba, 2058 AXI_MASTER_CFG_BASE + 2059 AM_CTRL_GLOBAL); 2060 reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK; 2061 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + 2062 AM_CTRL_GLOBAL, reg_val); 2063 } 2064 } 2065 2066 fatal_ecc_int_v3_hw(hisi_hba); 2067 2068 if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) { 2069 u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR); 2070 u32 dev_id = reg_val & ITCT_DEV_MSK; 2071 struct hisi_sas_device *sas_dev = 2072 &hisi_hba->devices[dev_id]; 2073 2074 hisi_sas_write32(hisi_hba, ITCT_CLR, 0); 2075 dev_dbg(dev, "clear ITCT ok\n"); 2076 complete(sas_dev->completion); 2077 } 2078 2079 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00); 2080 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk); 2081 2082 return IRQ_HANDLED; 2083 } 2084 2085 static void 2086 slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task, 2087 struct hisi_sas_slot *slot) 2088 { 2089 struct task_status_struct *ts = &task->task_status; 2090 struct hisi_sas_complete_v3_hdr *complete_queue = 2091 hisi_hba->complete_hdr[slot->cmplt_queue]; 2092 struct hisi_sas_complete_v3_hdr *complete_hdr = 2093 &complete_queue[slot->cmplt_queue_slot]; 2094 struct hisi_sas_err_record_v3 *record = 2095 hisi_sas_status_buf_addr_mem(slot); 2096 u32 dma_rx_err_type = le32_to_cpu(record->dma_rx_err_type); 2097 u32 trans_tx_fail_type = le32_to_cpu(record->trans_tx_fail_type); 2098 u32 dw3 = le32_to_cpu(complete_hdr->dw3); 2099 2100 switch (task->task_proto) { 2101 case SAS_PROTOCOL_SSP: 2102 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) { 2103 ts->residual = trans_tx_fail_type; 2104 ts->stat = SAS_DATA_UNDERRUN; 2105 } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { 2106 ts->stat = SAS_QUEUE_FULL; 2107 slot->abort = 1; 2108 } else { 2109 ts->stat = SAS_OPEN_REJECT; 2110 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2111 } 2112 break; 2113 case SAS_PROTOCOL_SATA: 2114 case SAS_PROTOCOL_STP: 2115 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 2116 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) { 2117 ts->residual = trans_tx_fail_type; 2118 ts->stat = SAS_DATA_UNDERRUN; 2119 } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { 2120 ts->stat = SAS_PHY_DOWN; 2121 slot->abort = 1; 2122 } else { 2123 ts->stat = SAS_OPEN_REJECT; 2124 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 2125 } 2126 hisi_sas_sata_done(task, slot); 2127 break; 2128 case SAS_PROTOCOL_SMP: 2129 ts->stat = SAM_STAT_CHECK_CONDITION; 2130 break; 2131 default: 2132 break; 2133 } 2134 } 2135 2136 static int 2137 slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot) 2138 { 2139 struct sas_task *task = slot->task; 2140 struct hisi_sas_device *sas_dev; 2141 struct device *dev = hisi_hba->dev; 2142 struct task_status_struct *ts; 2143 struct domain_device *device; 2144 struct sas_ha_struct *ha; 2145 enum exec_status sts; 2146 struct hisi_sas_complete_v3_hdr *complete_queue = 2147 hisi_hba->complete_hdr[slot->cmplt_queue]; 2148 struct hisi_sas_complete_v3_hdr *complete_hdr = 2149 &complete_queue[slot->cmplt_queue_slot]; 2150 unsigned long flags; 2151 bool is_internal = slot->is_internal; 2152 u32 dw0, dw1, dw3; 2153 2154 if (unlikely(!task || !task->lldd_task || !task->dev)) 2155 return -EINVAL; 2156 2157 ts = &task->task_status; 2158 device = task->dev; 2159 ha = device->port->ha; 2160 sas_dev = device->lldd_dev; 2161 2162 spin_lock_irqsave(&task->task_state_lock, flags); 2163 task->task_state_flags &= 2164 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR); 2165 spin_unlock_irqrestore(&task->task_state_lock, flags); 2166 2167 memset(ts, 0, sizeof(*ts)); 2168 ts->resp = SAS_TASK_COMPLETE; 2169 2170 if (unlikely(!sas_dev)) { 2171 dev_dbg(dev, "slot complete: port has not device\n"); 2172 ts->stat = SAS_PHY_DOWN; 2173 goto out; 2174 } 2175 2176 dw0 = le32_to_cpu(complete_hdr->dw0); 2177 dw1 = le32_to_cpu(complete_hdr->dw1); 2178 dw3 = le32_to_cpu(complete_hdr->dw3); 2179 2180 /* 2181 * Use SAS+TMF status codes 2182 */ 2183 switch ((dw0 & CMPLT_HDR_ABORT_STAT_MSK) >> CMPLT_HDR_ABORT_STAT_OFF) { 2184 case STAT_IO_ABORTED: 2185 /* this IO has been aborted by abort command */ 2186 ts->stat = SAS_ABORTED_TASK; 2187 goto out; 2188 case STAT_IO_COMPLETE: 2189 /* internal abort command complete */ 2190 ts->stat = TMF_RESP_FUNC_SUCC; 2191 goto out; 2192 case STAT_IO_NO_DEVICE: 2193 ts->stat = TMF_RESP_FUNC_COMPLETE; 2194 goto out; 2195 case STAT_IO_NOT_VALID: 2196 /* 2197 * abort single IO, the controller can't find the IO 2198 */ 2199 ts->stat = TMF_RESP_FUNC_FAILED; 2200 goto out; 2201 default: 2202 break; 2203 } 2204 2205 /* check for erroneous completion */ 2206 if ((dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) { 2207 u32 *error_info = hisi_sas_status_buf_addr_mem(slot); 2208 2209 slot_err_v3_hw(hisi_hba, task, slot); 2210 if (ts->stat != SAS_DATA_UNDERRUN) 2211 dev_info(dev, "erroneous completion iptt=%d task=%p dev id=%d CQ hdr: 0x%x 0x%x 0x%x 0x%x Error info: 0x%x 0x%x 0x%x 0x%x\n", 2212 slot->idx, task, sas_dev->device_id, 2213 dw0, dw1, complete_hdr->act, dw3, 2214 error_info[0], error_info[1], 2215 error_info[2], error_info[3]); 2216 if (unlikely(slot->abort)) 2217 return ts->stat; 2218 goto out; 2219 } 2220 2221 switch (task->task_proto) { 2222 case SAS_PROTOCOL_SSP: { 2223 struct ssp_response_iu *iu = 2224 hisi_sas_status_buf_addr_mem(slot) + 2225 sizeof(struct hisi_sas_err_record); 2226 2227 sas_ssp_task_response(dev, task, iu); 2228 break; 2229 } 2230 case SAS_PROTOCOL_SMP: { 2231 struct scatterlist *sg_resp = &task->smp_task.smp_resp; 2232 void *to; 2233 2234 ts->stat = SAM_STAT_GOOD; 2235 to = kmap_atomic(sg_page(sg_resp)); 2236 2237 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1, 2238 DMA_FROM_DEVICE); 2239 dma_unmap_sg(dev, &task->smp_task.smp_req, 1, 2240 DMA_TO_DEVICE); 2241 memcpy(to + sg_resp->offset, 2242 hisi_sas_status_buf_addr_mem(slot) + 2243 sizeof(struct hisi_sas_err_record), 2244 sg_dma_len(sg_resp)); 2245 kunmap_atomic(to); 2246 break; 2247 } 2248 case SAS_PROTOCOL_SATA: 2249 case SAS_PROTOCOL_STP: 2250 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 2251 ts->stat = SAM_STAT_GOOD; 2252 hisi_sas_sata_done(task, slot); 2253 break; 2254 default: 2255 ts->stat = SAM_STAT_CHECK_CONDITION; 2256 break; 2257 } 2258 2259 if (!slot->port->port_attached) { 2260 dev_warn(dev, "slot complete: port %d has removed\n", 2261 slot->port->sas_port.id); 2262 ts->stat = SAS_PHY_DOWN; 2263 } 2264 2265 out: 2266 sts = ts->stat; 2267 spin_lock_irqsave(&task->task_state_lock, flags); 2268 if (task->task_state_flags & SAS_TASK_STATE_ABORTED) { 2269 spin_unlock_irqrestore(&task->task_state_lock, flags); 2270 dev_info(dev, "slot complete: task(%p) aborted\n", task); 2271 return SAS_ABORTED_TASK; 2272 } 2273 task->task_state_flags |= SAS_TASK_STATE_DONE; 2274 spin_unlock_irqrestore(&task->task_state_lock, flags); 2275 hisi_sas_slot_task_free(hisi_hba, task, slot); 2276 2277 if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) { 2278 spin_lock_irqsave(&device->done_lock, flags); 2279 if (test_bit(SAS_HA_FROZEN, &ha->state)) { 2280 spin_unlock_irqrestore(&device->done_lock, flags); 2281 dev_info(dev, "slot complete: task(%p) ignored\n ", 2282 task); 2283 return sts; 2284 } 2285 spin_unlock_irqrestore(&device->done_lock, flags); 2286 } 2287 2288 if (task->task_done) 2289 task->task_done(task); 2290 2291 return sts; 2292 } 2293 2294 static void cq_tasklet_v3_hw(unsigned long val) 2295 { 2296 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val; 2297 struct hisi_hba *hisi_hba = cq->hisi_hba; 2298 struct hisi_sas_slot *slot; 2299 struct hisi_sas_complete_v3_hdr *complete_queue; 2300 u32 rd_point = cq->rd_point, wr_point; 2301 int queue = cq->id; 2302 2303 complete_queue = hisi_hba->complete_hdr[queue]; 2304 2305 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR + 2306 (0x14 * queue)); 2307 2308 while (rd_point != wr_point) { 2309 struct hisi_sas_complete_v3_hdr *complete_hdr; 2310 struct device *dev = hisi_hba->dev; 2311 u32 dw1; 2312 int iptt; 2313 2314 complete_hdr = &complete_queue[rd_point]; 2315 dw1 = le32_to_cpu(complete_hdr->dw1); 2316 2317 iptt = dw1 & CMPLT_HDR_IPTT_MSK; 2318 if (likely(iptt < HISI_SAS_COMMAND_ENTRIES_V3_HW)) { 2319 slot = &hisi_hba->slot_info[iptt]; 2320 slot->cmplt_queue_slot = rd_point; 2321 slot->cmplt_queue = queue; 2322 slot_complete_v3_hw(hisi_hba, slot); 2323 } else 2324 dev_err(dev, "IPTT %d is invalid, discard it.\n", iptt); 2325 2326 if (++rd_point >= HISI_SAS_QUEUE_SLOTS) 2327 rd_point = 0; 2328 } 2329 2330 /* update rd_point */ 2331 cq->rd_point = rd_point; 2332 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point); 2333 } 2334 2335 static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p) 2336 { 2337 struct hisi_sas_cq *cq = p; 2338 struct hisi_hba *hisi_hba = cq->hisi_hba; 2339 int queue = cq->id; 2340 2341 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue); 2342 2343 tasklet_schedule(&cq->tasklet); 2344 2345 return IRQ_HANDLED; 2346 } 2347 2348 static void setup_reply_map_v3_hw(struct hisi_hba *hisi_hba, int nvecs) 2349 { 2350 const struct cpumask *mask; 2351 int queue, cpu; 2352 2353 for (queue = 0; queue < nvecs; queue++) { 2354 struct hisi_sas_cq *cq = &hisi_hba->cq[queue]; 2355 2356 mask = pci_irq_get_affinity(hisi_hba->pci_dev, queue + 2357 BASE_VECTORS_V3_HW); 2358 if (!mask) 2359 goto fallback; 2360 cq->pci_irq_mask = mask; 2361 for_each_cpu(cpu, mask) 2362 hisi_hba->reply_map[cpu] = queue; 2363 } 2364 return; 2365 2366 fallback: 2367 for_each_possible_cpu(cpu) 2368 hisi_hba->reply_map[cpu] = cpu % hisi_hba->queue_count; 2369 /* Don't clean all CQ masks */ 2370 } 2371 2372 static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba) 2373 { 2374 struct device *dev = hisi_hba->dev; 2375 struct pci_dev *pdev = hisi_hba->pci_dev; 2376 int vectors, rc; 2377 int i, k; 2378 int max_msi = HISI_SAS_MSI_COUNT_V3_HW, min_msi; 2379 2380 if (auto_affine_msi_experimental) { 2381 struct irq_affinity desc = { 2382 .pre_vectors = BASE_VECTORS_V3_HW, 2383 }; 2384 2385 min_msi = MIN_AFFINE_VECTORS_V3_HW; 2386 2387 hisi_hba->reply_map = devm_kcalloc(dev, nr_cpu_ids, 2388 sizeof(unsigned int), 2389 GFP_KERNEL); 2390 if (!hisi_hba->reply_map) 2391 return -ENOMEM; 2392 vectors = pci_alloc_irq_vectors_affinity(hisi_hba->pci_dev, 2393 min_msi, max_msi, 2394 PCI_IRQ_MSI | 2395 PCI_IRQ_AFFINITY, 2396 &desc); 2397 if (vectors < 0) 2398 return -ENOENT; 2399 setup_reply_map_v3_hw(hisi_hba, vectors - BASE_VECTORS_V3_HW); 2400 } else { 2401 min_msi = max_msi; 2402 vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, min_msi, 2403 max_msi, PCI_IRQ_MSI); 2404 if (vectors < 0) 2405 return vectors; 2406 } 2407 2408 hisi_hba->cq_nvecs = vectors - BASE_VECTORS_V3_HW; 2409 2410 rc = devm_request_irq(dev, pci_irq_vector(pdev, 1), 2411 int_phy_up_down_bcast_v3_hw, 0, 2412 DRV_NAME " phy", hisi_hba); 2413 if (rc) { 2414 dev_err(dev, "could not request phy interrupt, rc=%d\n", rc); 2415 rc = -ENOENT; 2416 goto free_irq_vectors; 2417 } 2418 2419 rc = devm_request_irq(dev, pci_irq_vector(pdev, 2), 2420 int_chnl_int_v3_hw, 0, 2421 DRV_NAME " channel", hisi_hba); 2422 if (rc) { 2423 dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc); 2424 rc = -ENOENT; 2425 goto free_phy_irq; 2426 } 2427 2428 rc = devm_request_irq(dev, pci_irq_vector(pdev, 11), 2429 fatal_axi_int_v3_hw, 0, 2430 DRV_NAME " fatal", hisi_hba); 2431 if (rc) { 2432 dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc); 2433 rc = -ENOENT; 2434 goto free_chnl_interrupt; 2435 } 2436 2437 /* Init tasklets for cq only */ 2438 for (i = 0; i < hisi_hba->cq_nvecs; i++) { 2439 struct hisi_sas_cq *cq = &hisi_hba->cq[i]; 2440 struct tasklet_struct *t = &cq->tasklet; 2441 int nr = hisi_sas_intr_conv ? 16 : 16 + i; 2442 unsigned long irqflags = hisi_sas_intr_conv ? IRQF_SHARED : 0; 2443 2444 rc = devm_request_irq(dev, pci_irq_vector(pdev, nr), 2445 cq_interrupt_v3_hw, irqflags, 2446 DRV_NAME " cq", cq); 2447 if (rc) { 2448 dev_err(dev, "could not request cq%d interrupt, rc=%d\n", 2449 i, rc); 2450 rc = -ENOENT; 2451 goto free_cq_irqs; 2452 } 2453 2454 tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq); 2455 } 2456 2457 return 0; 2458 2459 free_cq_irqs: 2460 for (k = 0; k < i; k++) { 2461 struct hisi_sas_cq *cq = &hisi_hba->cq[k]; 2462 int nr = hisi_sas_intr_conv ? 16 : 16 + k; 2463 2464 free_irq(pci_irq_vector(pdev, nr), cq); 2465 } 2466 free_irq(pci_irq_vector(pdev, 11), hisi_hba); 2467 free_chnl_interrupt: 2468 free_irq(pci_irq_vector(pdev, 2), hisi_hba); 2469 free_phy_irq: 2470 free_irq(pci_irq_vector(pdev, 1), hisi_hba); 2471 free_irq_vectors: 2472 pci_free_irq_vectors(pdev); 2473 return rc; 2474 } 2475 2476 static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) 2477 { 2478 int rc; 2479 2480 rc = hw_init_v3_hw(hisi_hba); 2481 if (rc) 2482 return rc; 2483 2484 rc = interrupt_init_v3_hw(hisi_hba); 2485 if (rc) 2486 return rc; 2487 2488 return 0; 2489 } 2490 2491 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no, 2492 struct sas_phy_linkrates *r) 2493 { 2494 enum sas_linkrate max = r->maximum_linkrate; 2495 u32 prog_phy_link_rate = 0x800; 2496 2497 prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max); 2498 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, 2499 prog_phy_link_rate); 2500 } 2501 2502 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba) 2503 { 2504 struct pci_dev *pdev = hisi_hba->pci_dev; 2505 int i; 2506 2507 synchronize_irq(pci_irq_vector(pdev, 1)); 2508 synchronize_irq(pci_irq_vector(pdev, 2)); 2509 synchronize_irq(pci_irq_vector(pdev, 11)); 2510 for (i = 0; i < hisi_hba->queue_count; i++) { 2511 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1); 2512 synchronize_irq(pci_irq_vector(pdev, i + 16)); 2513 } 2514 2515 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff); 2516 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff); 2517 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff); 2518 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff); 2519 2520 for (i = 0; i < hisi_hba->n_phy; i++) { 2521 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff); 2522 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff); 2523 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1); 2524 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1); 2525 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1); 2526 } 2527 } 2528 2529 static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba) 2530 { 2531 return hisi_sas_read32(hisi_hba, PHY_STATE); 2532 } 2533 2534 static int disable_host_v3_hw(struct hisi_hba *hisi_hba) 2535 { 2536 struct device *dev = hisi_hba->dev; 2537 u32 status, reg_val; 2538 int rc; 2539 2540 interrupt_disable_v3_hw(hisi_hba); 2541 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0); 2542 hisi_sas_kill_tasklets(hisi_hba); 2543 2544 hisi_sas_stop_phys(hisi_hba); 2545 2546 mdelay(10); 2547 2548 reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE + 2549 AM_CTRL_GLOBAL); 2550 reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK; 2551 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + 2552 AM_CTRL_GLOBAL, reg_val); 2553 2554 /* wait until bus idle */ 2555 rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE + 2556 AM_CURR_TRANS_RETURN, status, 2557 status == 0x3, 10, 100); 2558 if (rc) { 2559 dev_err(dev, "axi bus is not idle, rc=%d\n", rc); 2560 return rc; 2561 } 2562 2563 return 0; 2564 } 2565 2566 static int soft_reset_v3_hw(struct hisi_hba *hisi_hba) 2567 { 2568 struct device *dev = hisi_hba->dev; 2569 int rc; 2570 2571 rc = disable_host_v3_hw(hisi_hba); 2572 if (rc) { 2573 dev_err(dev, "soft reset: disable host failed rc=%d\n", rc); 2574 return rc; 2575 } 2576 2577 hisi_sas_init_mem(hisi_hba); 2578 2579 return hw_init_v3_hw(hisi_hba); 2580 } 2581 2582 static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type, 2583 u8 reg_index, u8 reg_count, u8 *write_data) 2584 { 2585 struct device *dev = hisi_hba->dev; 2586 u32 *data = (u32 *)write_data; 2587 int i; 2588 2589 switch (reg_type) { 2590 case SAS_GPIO_REG_TX: 2591 if ((reg_index + reg_count) > ((hisi_hba->n_phy + 3) / 4)) { 2592 dev_err(dev, "write gpio: invalid reg range[%d, %d]\n", 2593 reg_index, reg_index + reg_count - 1); 2594 return -EINVAL; 2595 } 2596 2597 for (i = 0; i < reg_count; i++) 2598 hisi_sas_write32(hisi_hba, 2599 SAS_GPIO_TX_0_1 + (reg_index + i) * 4, 2600 data[i]); 2601 break; 2602 default: 2603 dev_err(dev, "write gpio: unsupported or bad reg type %d\n", 2604 reg_type); 2605 return -EINVAL; 2606 } 2607 2608 return 0; 2609 } 2610 2611 static int wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba, 2612 int delay_ms, int timeout_ms) 2613 { 2614 struct device *dev = hisi_hba->dev; 2615 int entries, entries_old = 0, time; 2616 2617 for (time = 0; time < timeout_ms; time += delay_ms) { 2618 entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT); 2619 if (entries == entries_old) 2620 break; 2621 2622 entries_old = entries; 2623 msleep(delay_ms); 2624 } 2625 2626 if (time >= timeout_ms) 2627 return -ETIMEDOUT; 2628 2629 dev_dbg(dev, "wait commands complete %dms\n", time); 2630 2631 return 0; 2632 } 2633 2634 static ssize_t intr_conv_v3_hw_show(struct device *dev, 2635 struct device_attribute *attr, char *buf) 2636 { 2637 return scnprintf(buf, PAGE_SIZE, "%u\n", hisi_sas_intr_conv); 2638 } 2639 static DEVICE_ATTR_RO(intr_conv_v3_hw); 2640 2641 static void config_intr_coal_v3_hw(struct hisi_hba *hisi_hba) 2642 { 2643 /* config those registers between enable and disable PHYs */ 2644 hisi_sas_stop_phys(hisi_hba); 2645 2646 if (hisi_hba->intr_coal_ticks == 0 || 2647 hisi_hba->intr_coal_count == 0) { 2648 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); 2649 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); 2650 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); 2651 } else { 2652 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x3); 2653 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 2654 hisi_hba->intr_coal_ticks); 2655 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 2656 hisi_hba->intr_coal_count); 2657 } 2658 phys_init_v3_hw(hisi_hba); 2659 } 2660 2661 static ssize_t intr_coal_ticks_v3_hw_show(struct device *dev, 2662 struct device_attribute *attr, 2663 char *buf) 2664 { 2665 struct Scsi_Host *shost = class_to_shost(dev); 2666 struct hisi_hba *hisi_hba = shost_priv(shost); 2667 2668 return scnprintf(buf, PAGE_SIZE, "%u\n", 2669 hisi_hba->intr_coal_ticks); 2670 } 2671 2672 static ssize_t intr_coal_ticks_v3_hw_store(struct device *dev, 2673 struct device_attribute *attr, 2674 const char *buf, size_t count) 2675 { 2676 struct Scsi_Host *shost = class_to_shost(dev); 2677 struct hisi_hba *hisi_hba = shost_priv(shost); 2678 u32 intr_coal_ticks; 2679 int ret; 2680 2681 ret = kstrtou32(buf, 10, &intr_coal_ticks); 2682 if (ret) { 2683 dev_err(dev, "Input data of interrupt coalesce unmatch\n"); 2684 return -EINVAL; 2685 } 2686 2687 if (intr_coal_ticks >= BIT(24)) { 2688 dev_err(dev, "intr_coal_ticks must be less than 2^24!\n"); 2689 return -EINVAL; 2690 } 2691 2692 hisi_hba->intr_coal_ticks = intr_coal_ticks; 2693 2694 config_intr_coal_v3_hw(hisi_hba); 2695 2696 return count; 2697 } 2698 static DEVICE_ATTR_RW(intr_coal_ticks_v3_hw); 2699 2700 static ssize_t intr_coal_count_v3_hw_show(struct device *dev, 2701 struct device_attribute 2702 *attr, char *buf) 2703 { 2704 struct Scsi_Host *shost = class_to_shost(dev); 2705 struct hisi_hba *hisi_hba = shost_priv(shost); 2706 2707 return scnprintf(buf, PAGE_SIZE, "%u\n", 2708 hisi_hba->intr_coal_count); 2709 } 2710 2711 static ssize_t intr_coal_count_v3_hw_store(struct device *dev, 2712 struct device_attribute 2713 *attr, const char *buf, size_t count) 2714 { 2715 struct Scsi_Host *shost = class_to_shost(dev); 2716 struct hisi_hba *hisi_hba = shost_priv(shost); 2717 u32 intr_coal_count; 2718 int ret; 2719 2720 ret = kstrtou32(buf, 10, &intr_coal_count); 2721 if (ret) { 2722 dev_err(dev, "Input data of interrupt coalesce unmatch\n"); 2723 return -EINVAL; 2724 } 2725 2726 if (intr_coal_count >= BIT(8)) { 2727 dev_err(dev, "intr_coal_count must be less than 2^8!\n"); 2728 return -EINVAL; 2729 } 2730 2731 hisi_hba->intr_coal_count = intr_coal_count; 2732 2733 config_intr_coal_v3_hw(hisi_hba); 2734 2735 return count; 2736 } 2737 static DEVICE_ATTR_RW(intr_coal_count_v3_hw); 2738 2739 static struct device_attribute *host_attrs_v3_hw[] = { 2740 &dev_attr_phy_event_threshold, 2741 &dev_attr_intr_conv_v3_hw, 2742 &dev_attr_intr_coal_ticks_v3_hw, 2743 &dev_attr_intr_coal_count_v3_hw, 2744 NULL 2745 }; 2746 2747 static const struct hisi_sas_debugfs_reg_lu debugfs_port_reg_lu[] = { 2748 HISI_SAS_DEBUGFS_REG(PHY_CFG), 2749 HISI_SAS_DEBUGFS_REG(HARD_PHY_LINKRATE), 2750 HISI_SAS_DEBUGFS_REG(PROG_PHY_LINK_RATE), 2751 HISI_SAS_DEBUGFS_REG(PHY_CTRL), 2752 HISI_SAS_DEBUGFS_REG(SL_CFG), 2753 HISI_SAS_DEBUGFS_REG(AIP_LIMIT), 2754 HISI_SAS_DEBUGFS_REG(SL_CONTROL), 2755 HISI_SAS_DEBUGFS_REG(RX_PRIMS_STATUS), 2756 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD0), 2757 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD1), 2758 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD2), 2759 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD3), 2760 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD4), 2761 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD5), 2762 HISI_SAS_DEBUGFS_REG(TX_ID_DWORD6), 2763 HISI_SAS_DEBUGFS_REG(TXID_AUTO), 2764 HISI_SAS_DEBUGFS_REG(RX_IDAF_DWORD0), 2765 HISI_SAS_DEBUGFS_REG(RXOP_CHECK_CFG_H), 2766 HISI_SAS_DEBUGFS_REG(STP_LINK_TIMER), 2767 HISI_SAS_DEBUGFS_REG(STP_LINK_TIMEOUT_STATE), 2768 HISI_SAS_DEBUGFS_REG(CON_CFG_DRIVER), 2769 HISI_SAS_DEBUGFS_REG(SAS_SSP_CON_TIMER_CFG), 2770 HISI_SAS_DEBUGFS_REG(SAS_SMP_CON_TIMER_CFG), 2771 HISI_SAS_DEBUGFS_REG(SAS_STP_CON_TIMER_CFG), 2772 HISI_SAS_DEBUGFS_REG(CHL_INT0), 2773 HISI_SAS_DEBUGFS_REG(CHL_INT1), 2774 HISI_SAS_DEBUGFS_REG(CHL_INT2), 2775 HISI_SAS_DEBUGFS_REG(CHL_INT0_MSK), 2776 HISI_SAS_DEBUGFS_REG(CHL_INT1_MSK), 2777 HISI_SAS_DEBUGFS_REG(CHL_INT2_MSK), 2778 HISI_SAS_DEBUGFS_REG(SAS_EC_INT_COAL_TIME), 2779 HISI_SAS_DEBUGFS_REG(CHL_INT_COAL_EN), 2780 HISI_SAS_DEBUGFS_REG(SAS_RX_TRAIN_TIMER), 2781 HISI_SAS_DEBUGFS_REG(PHY_CTRL_RDY_MSK), 2782 HISI_SAS_DEBUGFS_REG(PHYCTRL_NOT_RDY_MSK), 2783 HISI_SAS_DEBUGFS_REG(PHYCTRL_DWS_RESET_MSK), 2784 HISI_SAS_DEBUGFS_REG(PHYCTRL_PHY_ENA_MSK), 2785 HISI_SAS_DEBUGFS_REG(SL_RX_BCAST_CHK_MSK), 2786 HISI_SAS_DEBUGFS_REG(PHYCTRL_OOB_RESTART_MSK), 2787 HISI_SAS_DEBUGFS_REG(DMA_TX_STATUS), 2788 HISI_SAS_DEBUGFS_REG(DMA_RX_STATUS), 2789 HISI_SAS_DEBUGFS_REG(COARSETUNE_TIME), 2790 HISI_SAS_DEBUGFS_REG(ERR_CNT_DWS_LOST), 2791 HISI_SAS_DEBUGFS_REG(ERR_CNT_RESET_PROB), 2792 HISI_SAS_DEBUGFS_REG(ERR_CNT_INVLD_DW), 2793 HISI_SAS_DEBUGFS_REG(ERR_CNT_CODE_ERR), 2794 HISI_SAS_DEBUGFS_REG(ERR_CNT_DISP_ERR), 2795 {} 2796 }; 2797 2798 static const struct hisi_sas_debugfs_reg debugfs_port_reg = { 2799 .lu = debugfs_port_reg_lu, 2800 .count = 0x100, 2801 .base_off = PORT_BASE, 2802 .read_port_reg = hisi_sas_phy_read32, 2803 }; 2804 2805 static const struct hisi_sas_debugfs_reg_lu debugfs_global_reg_lu[] = { 2806 HISI_SAS_DEBUGFS_REG(DLVRY_QUEUE_ENABLE), 2807 HISI_SAS_DEBUGFS_REG(PHY_CONTEXT), 2808 HISI_SAS_DEBUGFS_REG(PHY_STATE), 2809 HISI_SAS_DEBUGFS_REG(PHY_PORT_NUM_MA), 2810 HISI_SAS_DEBUGFS_REG(PHY_CONN_RATE), 2811 HISI_SAS_DEBUGFS_REG(ITCT_CLR), 2812 HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_LO), 2813 HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_HI), 2814 HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_LO), 2815 HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_HI), 2816 HISI_SAS_DEBUGFS_REG(CFG_MAX_TAG), 2817 HISI_SAS_DEBUGFS_REG(HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL), 2818 HISI_SAS_DEBUGFS_REG(HGC_SAS_TXFAIL_RETRY_CTRL), 2819 HISI_SAS_DEBUGFS_REG(HGC_GET_ITV_TIME), 2820 HISI_SAS_DEBUGFS_REG(DEVICE_MSG_WORK_MODE), 2821 HISI_SAS_DEBUGFS_REG(OPENA_WT_CONTI_TIME), 2822 HISI_SAS_DEBUGFS_REG(I_T_NEXUS_LOSS_TIME), 2823 HISI_SAS_DEBUGFS_REG(MAX_CON_TIME_LIMIT_TIME), 2824 HISI_SAS_DEBUGFS_REG(BUS_INACTIVE_LIMIT_TIME), 2825 HISI_SAS_DEBUGFS_REG(REJECT_TO_OPEN_LIMIT_TIME), 2826 HISI_SAS_DEBUGFS_REG(CQ_INT_CONVERGE_EN), 2827 HISI_SAS_DEBUGFS_REG(CFG_AGING_TIME), 2828 HISI_SAS_DEBUGFS_REG(HGC_DFX_CFG2), 2829 HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_QUERY_IPTT), 2830 HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_IPTT_DONE), 2831 HISI_SAS_DEBUGFS_REG(HGC_IOMB_PROC1_STATUS), 2832 HISI_SAS_DEBUGFS_REG(CHNL_INT_STATUS), 2833 HISI_SAS_DEBUGFS_REG(HGC_AXI_FIFO_ERR_INFO), 2834 HISI_SAS_DEBUGFS_REG(INT_COAL_EN), 2835 HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_TIME), 2836 HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_CNT), 2837 HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_TIME), 2838 HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_CNT), 2839 HISI_SAS_DEBUGFS_REG(OQ_INT_SRC), 2840 HISI_SAS_DEBUGFS_REG(OQ_INT_SRC_MSK), 2841 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC1), 2842 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC2), 2843 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC3), 2844 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK1), 2845 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK2), 2846 HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK3), 2847 HISI_SAS_DEBUGFS_REG(CHNL_PHYUPDOWN_INT_MSK), 2848 HISI_SAS_DEBUGFS_REG(CHNL_ENT_INT_MSK), 2849 HISI_SAS_DEBUGFS_REG(HGC_COM_INT_MSK), 2850 HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR), 2851 HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR_MSK), 2852 HISI_SAS_DEBUGFS_REG(HGC_ERR_STAT_EN), 2853 HISI_SAS_DEBUGFS_REG(CQE_SEND_CNT), 2854 HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_DEPTH), 2855 HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_WR_PTR), 2856 HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_RD_PTR), 2857 HISI_SAS_DEBUGFS_REG(HYPER_STREAM_ID_EN_CFG), 2858 HISI_SAS_DEBUGFS_REG(OQ0_INT_SRC_MSK), 2859 HISI_SAS_DEBUGFS_REG(COMPL_Q_0_DEPTH), 2860 HISI_SAS_DEBUGFS_REG(COMPL_Q_0_WR_PTR), 2861 HISI_SAS_DEBUGFS_REG(COMPL_Q_0_RD_PTR), 2862 HISI_SAS_DEBUGFS_REG(AWQOS_AWCACHE_CFG), 2863 HISI_SAS_DEBUGFS_REG(ARQOS_ARCACHE_CFG), 2864 HISI_SAS_DEBUGFS_REG(HILINK_ERR_DFX), 2865 HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_0), 2866 HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_1), 2867 HISI_SAS_DEBUGFS_REG(SAS_GPIO_TX_0_1), 2868 HISI_SAS_DEBUGFS_REG(SAS_CFG_DRIVE_VLD), 2869 {} 2870 }; 2871 2872 static const struct hisi_sas_debugfs_reg debugfs_global_reg = { 2873 .lu = debugfs_global_reg_lu, 2874 .count = 0x800, 2875 .read_global_reg = hisi_sas_read32, 2876 }; 2877 2878 static void debugfs_snapshot_prepare_v3_hw(struct hisi_hba *hisi_hba) 2879 { 2880 struct device *dev = hisi_hba->dev; 2881 2882 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 2883 2884 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0); 2885 2886 if (wait_cmds_complete_timeout_v3_hw(hisi_hba, 100, 5000) == -ETIMEDOUT) 2887 dev_dbg(dev, "Wait commands complete timeout!\n"); 2888 2889 hisi_sas_kill_tasklets(hisi_hba); 2890 } 2891 2892 static void debugfs_snapshot_restore_v3_hw(struct hisi_hba *hisi_hba) 2893 { 2894 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 2895 (u32)((1ULL << hisi_hba->queue_count) - 1)); 2896 2897 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 2898 } 2899 2900 static struct scsi_host_template sht_v3_hw = { 2901 .name = DRV_NAME, 2902 .module = THIS_MODULE, 2903 .queuecommand = sas_queuecommand, 2904 .target_alloc = sas_target_alloc, 2905 .slave_configure = hisi_sas_slave_configure, 2906 .scan_finished = hisi_sas_scan_finished, 2907 .scan_start = hisi_sas_scan_start, 2908 .change_queue_depth = sas_change_queue_depth, 2909 .bios_param = sas_bios_param, 2910 .this_id = -1, 2911 .sg_tablesize = HISI_SAS_SGE_PAGE_CNT, 2912 .sg_prot_tablesize = HISI_SAS_SGE_PAGE_CNT, 2913 .max_sectors = SCSI_DEFAULT_MAX_SECTORS, 2914 .eh_device_reset_handler = sas_eh_device_reset_handler, 2915 .eh_target_reset_handler = sas_eh_target_reset_handler, 2916 .target_destroy = sas_target_destroy, 2917 .ioctl = sas_ioctl, 2918 .shost_attrs = host_attrs_v3_hw, 2919 .tag_alloc_policy = BLK_TAG_ALLOC_RR, 2920 .host_reset = hisi_sas_host_reset, 2921 }; 2922 2923 static const struct hisi_sas_hw hisi_sas_v3_hw = { 2924 .hw_init = hisi_sas_v3_init, 2925 .setup_itct = setup_itct_v3_hw, 2926 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW, 2927 .get_wideport_bitmap = get_wideport_bitmap_v3_hw, 2928 .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr), 2929 .clear_itct = clear_itct_v3_hw, 2930 .sl_notify_ssp = sl_notify_ssp_v3_hw, 2931 .prep_ssp = prep_ssp_v3_hw, 2932 .prep_smp = prep_smp_v3_hw, 2933 .prep_stp = prep_ata_v3_hw, 2934 .prep_abort = prep_abort_v3_hw, 2935 .get_free_slot = get_free_slot_v3_hw, 2936 .start_delivery = start_delivery_v3_hw, 2937 .slot_complete = slot_complete_v3_hw, 2938 .phys_init = phys_init_v3_hw, 2939 .phy_start = start_phy_v3_hw, 2940 .phy_disable = disable_phy_v3_hw, 2941 .phy_hard_reset = phy_hard_reset_v3_hw, 2942 .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw, 2943 .phy_set_linkrate = phy_set_linkrate_v3_hw, 2944 .dereg_device = dereg_device_v3_hw, 2945 .soft_reset = soft_reset_v3_hw, 2946 .get_phys_state = get_phys_state_v3_hw, 2947 .get_events = phy_get_events_v3_hw, 2948 .write_gpio = write_gpio_v3_hw, 2949 .wait_cmds_complete_timeout = wait_cmds_complete_timeout_v3_hw, 2950 .debugfs_reg_global = &debugfs_global_reg, 2951 .debugfs_reg_port = &debugfs_port_reg, 2952 .snapshot_prepare = debugfs_snapshot_prepare_v3_hw, 2953 .snapshot_restore = debugfs_snapshot_restore_v3_hw, 2954 }; 2955 2956 static struct Scsi_Host * 2957 hisi_sas_shost_alloc_pci(struct pci_dev *pdev) 2958 { 2959 struct Scsi_Host *shost; 2960 struct hisi_hba *hisi_hba; 2961 struct device *dev = &pdev->dev; 2962 2963 shost = scsi_host_alloc(&sht_v3_hw, sizeof(*hisi_hba)); 2964 if (!shost) { 2965 dev_err(dev, "shost alloc failed\n"); 2966 return NULL; 2967 } 2968 hisi_hba = shost_priv(shost); 2969 2970 INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler); 2971 INIT_WORK(&hisi_hba->debugfs_work, hisi_sas_debugfs_work_handler); 2972 hisi_hba->hw = &hisi_sas_v3_hw; 2973 hisi_hba->pci_dev = pdev; 2974 hisi_hba->dev = dev; 2975 hisi_hba->shost = shost; 2976 SHOST_TO_SAS_HA(shost) = &hisi_hba->sha; 2977 2978 if (prot_mask & ~HISI_SAS_PROT_MASK) 2979 dev_err(dev, "unsupported protection mask 0x%x, using default (0x0)\n", 2980 prot_mask); 2981 else 2982 hisi_hba->prot_mask = prot_mask; 2983 2984 timer_setup(&hisi_hba->timer, NULL, 0); 2985 2986 if (hisi_sas_get_fw_info(hisi_hba) < 0) 2987 goto err_out; 2988 2989 if (hisi_sas_alloc(hisi_hba)) { 2990 hisi_sas_free(hisi_hba); 2991 goto err_out; 2992 } 2993 2994 return shost; 2995 err_out: 2996 scsi_host_put(shost); 2997 dev_err(dev, "shost alloc failed\n"); 2998 return NULL; 2999 } 3000 3001 static int 3002 hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id) 3003 { 3004 struct Scsi_Host *shost; 3005 struct hisi_hba *hisi_hba; 3006 struct device *dev = &pdev->dev; 3007 struct asd_sas_phy **arr_phy; 3008 struct asd_sas_port **arr_port; 3009 struct sas_ha_struct *sha; 3010 int rc, phy_nr, port_nr, i; 3011 3012 rc = pci_enable_device(pdev); 3013 if (rc) 3014 goto err_out; 3015 3016 pci_set_master(pdev); 3017 3018 rc = pci_request_regions(pdev, DRV_NAME); 3019 if (rc) 3020 goto err_out_disable_device; 3021 3022 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3023 if (rc) 3024 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3025 if (rc) { 3026 dev_err(dev, "No usable DMA addressing method\n"); 3027 rc = -ENODEV; 3028 goto err_out_regions; 3029 } 3030 3031 shost = hisi_sas_shost_alloc_pci(pdev); 3032 if (!shost) { 3033 rc = -ENOMEM; 3034 goto err_out_regions; 3035 } 3036 3037 sha = SHOST_TO_SAS_HA(shost); 3038 hisi_hba = shost_priv(shost); 3039 dev_set_drvdata(dev, sha); 3040 3041 hisi_hba->regs = pcim_iomap(pdev, 5, 0); 3042 if (!hisi_hba->regs) { 3043 dev_err(dev, "cannot map register\n"); 3044 rc = -ENOMEM; 3045 goto err_out_ha; 3046 } 3047 3048 phy_nr = port_nr = hisi_hba->n_phy; 3049 3050 arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL); 3051 arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL); 3052 if (!arr_phy || !arr_port) { 3053 rc = -ENOMEM; 3054 goto err_out_ha; 3055 } 3056 3057 sha->sas_phy = arr_phy; 3058 sha->sas_port = arr_port; 3059 sha->core.shost = shost; 3060 sha->lldd_ha = hisi_hba; 3061 3062 shost->transportt = hisi_sas_stt; 3063 shost->max_id = HISI_SAS_MAX_DEVICES; 3064 shost->max_lun = ~0; 3065 shost->max_channel = 1; 3066 shost->max_cmd_len = 16; 3067 shost->can_queue = hisi_hba->hw->max_command_entries - 3068 HISI_SAS_RESERVED_IPTT_CNT; 3069 shost->cmd_per_lun = hisi_hba->hw->max_command_entries - 3070 HISI_SAS_RESERVED_IPTT_CNT; 3071 3072 sha->sas_ha_name = DRV_NAME; 3073 sha->dev = dev; 3074 sha->lldd_module = THIS_MODULE; 3075 sha->sas_addr = &hisi_hba->sas_addr[0]; 3076 sha->num_phys = hisi_hba->n_phy; 3077 sha->core.shost = hisi_hba->shost; 3078 3079 for (i = 0; i < hisi_hba->n_phy; i++) { 3080 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy; 3081 sha->sas_port[i] = &hisi_hba->port[i].sas_port; 3082 } 3083 3084 if (hisi_hba->prot_mask) { 3085 dev_info(dev, "Registering for DIF/DIX prot_mask=0x%x\n", 3086 prot_mask); 3087 scsi_host_set_prot(hisi_hba->shost, prot_mask); 3088 if (hisi_hba->prot_mask & HISI_SAS_DIX_PROT_MASK) 3089 scsi_host_set_guard(hisi_hba->shost, 3090 SHOST_DIX_GUARD_CRC); 3091 } 3092 3093 if (hisi_sas_debugfs_enable) 3094 hisi_sas_debugfs_init(hisi_hba); 3095 3096 rc = scsi_add_host(shost, dev); 3097 if (rc) 3098 goto err_out_ha; 3099 3100 rc = sas_register_ha(sha); 3101 if (rc) 3102 goto err_out_register_ha; 3103 3104 rc = hisi_hba->hw->hw_init(hisi_hba); 3105 if (rc) 3106 goto err_out_register_ha; 3107 3108 scsi_scan_host(shost); 3109 3110 return 0; 3111 3112 err_out_register_ha: 3113 scsi_remove_host(shost); 3114 err_out_ha: 3115 scsi_host_put(shost); 3116 err_out_regions: 3117 pci_release_regions(pdev); 3118 err_out_disable_device: 3119 pci_disable_device(pdev); 3120 err_out: 3121 return rc; 3122 } 3123 3124 static void 3125 hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba) 3126 { 3127 int i; 3128 3129 free_irq(pci_irq_vector(pdev, 1), hisi_hba); 3130 free_irq(pci_irq_vector(pdev, 2), hisi_hba); 3131 free_irq(pci_irq_vector(pdev, 11), hisi_hba); 3132 for (i = 0; i < hisi_hba->cq_nvecs; i++) { 3133 struct hisi_sas_cq *cq = &hisi_hba->cq[i]; 3134 int nr = hisi_sas_intr_conv ? 16 : 16 + i; 3135 3136 free_irq(pci_irq_vector(pdev, nr), cq); 3137 } 3138 pci_free_irq_vectors(pdev); 3139 } 3140 3141 static void hisi_sas_v3_remove(struct pci_dev *pdev) 3142 { 3143 struct device *dev = &pdev->dev; 3144 struct sas_ha_struct *sha = dev_get_drvdata(dev); 3145 struct hisi_hba *hisi_hba = sha->lldd_ha; 3146 struct Scsi_Host *shost = sha->core.shost; 3147 3148 hisi_sas_debugfs_exit(hisi_hba); 3149 3150 if (timer_pending(&hisi_hba->timer)) 3151 del_timer(&hisi_hba->timer); 3152 3153 sas_unregister_ha(sha); 3154 sas_remove_host(sha->core.shost); 3155 3156 hisi_sas_v3_destroy_irqs(pdev, hisi_hba); 3157 hisi_sas_kill_tasklets(hisi_hba); 3158 pci_release_regions(pdev); 3159 pci_disable_device(pdev); 3160 hisi_sas_free(hisi_hba); 3161 scsi_host_put(shost); 3162 } 3163 3164 static void hisi_sas_reset_prepare_v3_hw(struct pci_dev *pdev) 3165 { 3166 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 3167 struct hisi_hba *hisi_hba = sha->lldd_ha; 3168 struct device *dev = hisi_hba->dev; 3169 int rc; 3170 3171 dev_info(dev, "FLR prepare\n"); 3172 set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 3173 hisi_sas_controller_reset_prepare(hisi_hba); 3174 3175 rc = disable_host_v3_hw(hisi_hba); 3176 if (rc) 3177 dev_err(dev, "FLR: disable host failed rc=%d\n", rc); 3178 } 3179 3180 static void hisi_sas_reset_done_v3_hw(struct pci_dev *pdev) 3181 { 3182 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 3183 struct hisi_hba *hisi_hba = sha->lldd_ha; 3184 struct device *dev = hisi_hba->dev; 3185 int rc; 3186 3187 hisi_sas_init_mem(hisi_hba); 3188 3189 rc = hw_init_v3_hw(hisi_hba); 3190 if (rc) { 3191 dev_err(dev, "FLR: hw init failed rc=%d\n", rc); 3192 return; 3193 } 3194 3195 hisi_sas_controller_reset_done(hisi_hba); 3196 dev_info(dev, "FLR done\n"); 3197 } 3198 3199 enum { 3200 /* instances of the controller */ 3201 hip08, 3202 }; 3203 3204 static int hisi_sas_v3_suspend(struct pci_dev *pdev, pm_message_t state) 3205 { 3206 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 3207 struct hisi_hba *hisi_hba = sha->lldd_ha; 3208 struct device *dev = hisi_hba->dev; 3209 struct Scsi_Host *shost = hisi_hba->shost; 3210 pci_power_t device_state; 3211 int rc; 3212 3213 if (!pdev->pm_cap) { 3214 dev_err(dev, "PCI PM not supported\n"); 3215 return -ENODEV; 3216 } 3217 3218 if (test_and_set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)) 3219 return -1; 3220 3221 scsi_block_requests(shost); 3222 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 3223 flush_workqueue(hisi_hba->wq); 3224 3225 rc = disable_host_v3_hw(hisi_hba); 3226 if (rc) { 3227 dev_err(dev, "PM suspend: disable host failed rc=%d\n", rc); 3228 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 3229 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 3230 scsi_unblock_requests(shost); 3231 return rc; 3232 } 3233 3234 hisi_sas_init_mem(hisi_hba); 3235 3236 device_state = pci_choose_state(pdev, state); 3237 dev_warn(dev, "entering operating state [D%d]\n", 3238 device_state); 3239 pci_save_state(pdev); 3240 pci_disable_device(pdev); 3241 pci_set_power_state(pdev, device_state); 3242 3243 hisi_sas_release_tasks(hisi_hba); 3244 3245 sas_suspend_ha(sha); 3246 return 0; 3247 } 3248 3249 static int hisi_sas_v3_resume(struct pci_dev *pdev) 3250 { 3251 struct sas_ha_struct *sha = pci_get_drvdata(pdev); 3252 struct hisi_hba *hisi_hba = sha->lldd_ha; 3253 struct Scsi_Host *shost = hisi_hba->shost; 3254 struct device *dev = hisi_hba->dev; 3255 unsigned int rc; 3256 pci_power_t device_state = pdev->current_state; 3257 3258 dev_warn(dev, "resuming from operating state [D%d]\n", 3259 device_state); 3260 pci_set_power_state(pdev, PCI_D0); 3261 pci_enable_wake(pdev, PCI_D0, 0); 3262 pci_restore_state(pdev); 3263 rc = pci_enable_device(pdev); 3264 if (rc) 3265 dev_err(dev, "enable device failed during resume (%d)\n", rc); 3266 3267 pci_set_master(pdev); 3268 scsi_unblock_requests(shost); 3269 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); 3270 3271 sas_prep_resume_ha(sha); 3272 init_reg_v3_hw(hisi_hba); 3273 hisi_hba->hw->phys_init(hisi_hba); 3274 sas_resume_ha(sha); 3275 clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); 3276 3277 return 0; 3278 } 3279 3280 static const struct pci_device_id sas_v3_pci_table[] = { 3281 { PCI_VDEVICE(HUAWEI, 0xa230), hip08 }, 3282 {} 3283 }; 3284 MODULE_DEVICE_TABLE(pci, sas_v3_pci_table); 3285 3286 static const struct pci_error_handlers hisi_sas_err_handler = { 3287 .reset_prepare = hisi_sas_reset_prepare_v3_hw, 3288 .reset_done = hisi_sas_reset_done_v3_hw, 3289 }; 3290 3291 static struct pci_driver sas_v3_pci_driver = { 3292 .name = DRV_NAME, 3293 .id_table = sas_v3_pci_table, 3294 .probe = hisi_sas_v3_probe, 3295 .remove = hisi_sas_v3_remove, 3296 .suspend = hisi_sas_v3_suspend, 3297 .resume = hisi_sas_v3_resume, 3298 .err_handler = &hisi_sas_err_handler, 3299 }; 3300 3301 module_pci_driver(sas_v3_pci_driver); 3302 module_param_named(intr_conv, hisi_sas_intr_conv, bool, 0444); 3303 3304 MODULE_LICENSE("GPL"); 3305 MODULE_AUTHOR("John Garry <john.garry@huawei.com>"); 3306 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device"); 3307 MODULE_ALIAS("pci:" DRV_NAME); 3308