1 /* 2 * Copyright (c) 2016 Linaro Ltd. 3 * Copyright (c) 2016 Hisilicon Limited. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 */ 11 12 #include "hisi_sas.h" 13 #define DRV_NAME "hisi_sas_v2_hw" 14 15 /* global registers need init*/ 16 #define DLVRY_QUEUE_ENABLE 0x0 17 #define IOST_BASE_ADDR_LO 0x8 18 #define IOST_BASE_ADDR_HI 0xc 19 #define ITCT_BASE_ADDR_LO 0x10 20 #define ITCT_BASE_ADDR_HI 0x14 21 #define IO_BROKEN_MSG_ADDR_LO 0x18 22 #define IO_BROKEN_MSG_ADDR_HI 0x1c 23 #define PHY_CONTEXT 0x20 24 #define PHY_STATE 0x24 25 #define PHY_PORT_NUM_MA 0x28 26 #define PORT_STATE 0x2c 27 #define PORT_STATE_PHY8_PORT_NUM_OFF 16 28 #define PORT_STATE_PHY8_PORT_NUM_MSK (0xf << PORT_STATE_PHY8_PORT_NUM_OFF) 29 #define PORT_STATE_PHY8_CONN_RATE_OFF 20 30 #define PORT_STATE_PHY8_CONN_RATE_MSK (0xf << PORT_STATE_PHY8_CONN_RATE_OFF) 31 #define PHY_CONN_RATE 0x30 32 #define HGC_TRANS_TASK_CNT_LIMIT 0x38 33 #define AXI_AHB_CLK_CFG 0x3c 34 #define ITCT_CLR 0x44 35 #define ITCT_CLR_EN_OFF 16 36 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF) 37 #define ITCT_DEV_OFF 0 38 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF) 39 #define AXI_USER1 0x48 40 #define AXI_USER2 0x4c 41 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58 42 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c 43 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60 44 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64 45 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84 46 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88 47 #define HGC_GET_ITV_TIME 0x90 48 #define DEVICE_MSG_WORK_MODE 0x94 49 #define OPENA_WT_CONTI_TIME 0x9c 50 #define I_T_NEXUS_LOSS_TIME 0xa0 51 #define MAX_CON_TIME_LIMIT_TIME 0xa4 52 #define BUS_INACTIVE_LIMIT_TIME 0xa8 53 #define REJECT_TO_OPEN_LIMIT_TIME 0xac 54 #define CFG_AGING_TIME 0xbc 55 #define HGC_DFX_CFG2 0xc0 56 #define HGC_IOMB_PROC1_STATUS 0x104 57 #define CFG_1US_TIMER_TRSH 0xcc 58 #define HGC_INVLD_DQE_INFO 0x148 59 #define HGC_INVLD_DQE_INFO_FB_CH0_OFF 9 60 #define HGC_INVLD_DQE_INFO_FB_CH0_MSK (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF) 61 #define HGC_INVLD_DQE_INFO_FB_CH3_OFF 18 62 #define INT_COAL_EN 0x19c 63 #define OQ_INT_COAL_TIME 0x1a0 64 #define OQ_INT_COAL_CNT 0x1a4 65 #define ENT_INT_COAL_TIME 0x1a8 66 #define ENT_INT_COAL_CNT 0x1ac 67 #define OQ_INT_SRC 0x1b0 68 #define OQ_INT_SRC_MSK 0x1b4 69 #define ENT_INT_SRC1 0x1b8 70 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0 71 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF) 72 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8 73 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF) 74 #define ENT_INT_SRC2 0x1bc 75 #define ENT_INT_SRC3 0x1c0 76 #define ENT_INT_SRC3_ITC_INT_OFF 15 77 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF) 78 #define ENT_INT_SRC_MSK1 0x1c4 79 #define ENT_INT_SRC_MSK2 0x1c8 80 #define ENT_INT_SRC_MSK3 0x1cc 81 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31 82 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF) 83 #define SAS_ECC_INTR_MSK 0x1ec 84 #define HGC_ERR_STAT_EN 0x238 85 #define DLVRY_Q_0_BASE_ADDR_LO 0x260 86 #define DLVRY_Q_0_BASE_ADDR_HI 0x264 87 #define DLVRY_Q_0_DEPTH 0x268 88 #define DLVRY_Q_0_WR_PTR 0x26c 89 #define DLVRY_Q_0_RD_PTR 0x270 90 #define HYPER_STREAM_ID_EN_CFG 0xc80 91 #define OQ0_INT_SRC_MSK 0xc90 92 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0 93 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4 94 #define COMPL_Q_0_DEPTH 0x4e8 95 #define COMPL_Q_0_WR_PTR 0x4ec 96 #define COMPL_Q_0_RD_PTR 0x4f0 97 98 /* phy registers need init */ 99 #define PORT_BASE (0x2000) 100 101 #define PHY_CFG (PORT_BASE + 0x0) 102 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4) 103 #define PHY_CFG_ENA_OFF 0 104 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF) 105 #define PHY_CFG_DC_OPT_OFF 2 106 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF) 107 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8) 108 #define PROG_PHY_LINK_RATE_MAX_OFF 0 109 #define PROG_PHY_LINK_RATE_MAX_MSK (0xff << PROG_PHY_LINK_RATE_MAX_OFF) 110 #define PHY_CTRL (PORT_BASE + 0x14) 111 #define PHY_CTRL_RESET_OFF 0 112 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF) 113 #define SAS_PHY_CTRL (PORT_BASE + 0x20) 114 #define SL_CFG (PORT_BASE + 0x84) 115 #define PHY_PCN (PORT_BASE + 0x44) 116 #define SL_TOUT_CFG (PORT_BASE + 0x8c) 117 #define SL_CONTROL (PORT_BASE + 0x94) 118 #define SL_CONTROL_NOTIFY_EN_OFF 0 119 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF) 120 #define SL_CONTROL_CTA_OFF 17 121 #define SL_CONTROL_CTA_MSK (0x1 << SL_CONTROL_CTA_OFF) 122 #define TX_ID_DWORD0 (PORT_BASE + 0x9c) 123 #define TX_ID_DWORD1 (PORT_BASE + 0xa0) 124 #define TX_ID_DWORD2 (PORT_BASE + 0xa4) 125 #define TX_ID_DWORD3 (PORT_BASE + 0xa8) 126 #define TX_ID_DWORD4 (PORT_BASE + 0xaC) 127 #define TX_ID_DWORD5 (PORT_BASE + 0xb0) 128 #define TX_ID_DWORD6 (PORT_BASE + 0xb4) 129 #define TXID_AUTO (PORT_BASE + 0xb8) 130 #define TXID_AUTO_CT3_OFF 1 131 #define TXID_AUTO_CT3_MSK (0x1 << TXID_AUTO_CT3_OFF) 132 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4) 133 #define RX_IDAF_DWORD1 (PORT_BASE + 0xc8) 134 #define RX_IDAF_DWORD2 (PORT_BASE + 0xcc) 135 #define RX_IDAF_DWORD3 (PORT_BASE + 0xd0) 136 #define RX_IDAF_DWORD4 (PORT_BASE + 0xd4) 137 #define RX_IDAF_DWORD5 (PORT_BASE + 0xd8) 138 #define RX_IDAF_DWORD6 (PORT_BASE + 0xdc) 139 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) 140 #define DONE_RECEIVED_TIME (PORT_BASE + 0x11c) 141 #define CHL_INT0 (PORT_BASE + 0x1b4) 142 #define CHL_INT0_HOTPLUG_TOUT_OFF 0 143 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF) 144 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1 145 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF) 146 #define CHL_INT0_SL_PHY_ENABLE_OFF 2 147 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF) 148 #define CHL_INT0_NOT_RDY_OFF 4 149 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF) 150 #define CHL_INT0_PHY_RDY_OFF 5 151 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF) 152 #define CHL_INT1 (PORT_BASE + 0x1b8) 153 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15 154 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF) 155 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17 156 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF) 157 #define CHL_INT2 (PORT_BASE + 0x1bc) 158 #define CHL_INT0_MSK (PORT_BASE + 0x1c0) 159 #define CHL_INT1_MSK (PORT_BASE + 0x1c4) 160 #define CHL_INT2_MSK (PORT_BASE + 0x1c8) 161 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0) 162 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0) 163 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4) 164 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8) 165 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc) 166 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0) 167 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4) 168 #define DMA_TX_STATUS (PORT_BASE + 0x2d0) 169 #define DMA_TX_STATUS_BUSY_OFF 0 170 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF) 171 #define DMA_RX_STATUS (PORT_BASE + 0x2e8) 172 #define DMA_RX_STATUS_BUSY_OFF 0 173 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF) 174 175 #define AXI_CFG (0x5100) 176 #define AM_CFG_MAX_TRANS (0x5010) 177 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014) 178 179 /* HW dma structures */ 180 /* Delivery queue header */ 181 /* dw0 */ 182 #define CMD_HDR_ABORT_FLAG_OFF 0 183 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF) 184 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2 185 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) 186 #define CMD_HDR_RESP_REPORT_OFF 5 187 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF) 188 #define CMD_HDR_TLR_CTRL_OFF 6 189 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF) 190 #define CMD_HDR_PORT_OFF 18 191 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF) 192 #define CMD_HDR_PRIORITY_OFF 27 193 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF) 194 #define CMD_HDR_CMD_OFF 29 195 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF) 196 /* dw1 */ 197 #define CMD_HDR_DIR_OFF 5 198 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF) 199 #define CMD_HDR_RESET_OFF 7 200 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF) 201 #define CMD_HDR_VDTL_OFF 10 202 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF) 203 #define CMD_HDR_FRAME_TYPE_OFF 11 204 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF) 205 #define CMD_HDR_DEV_ID_OFF 16 206 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF) 207 /* dw2 */ 208 #define CMD_HDR_CFL_OFF 0 209 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF) 210 #define CMD_HDR_NCQ_TAG_OFF 10 211 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF) 212 #define CMD_HDR_MRFL_OFF 15 213 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF) 214 #define CMD_HDR_SG_MOD_OFF 24 215 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF) 216 #define CMD_HDR_FIRST_BURST_OFF 26 217 #define CMD_HDR_FIRST_BURST_MSK (0x1 << CMD_HDR_SG_MOD_OFF) 218 /* dw3 */ 219 #define CMD_HDR_IPTT_OFF 0 220 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF) 221 /* dw6 */ 222 #define CMD_HDR_DIF_SGL_LEN_OFF 0 223 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF) 224 #define CMD_HDR_DATA_SGL_LEN_OFF 16 225 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF) 226 #define CMD_HDR_ABORT_IPTT_OFF 16 227 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF) 228 229 /* Completion header */ 230 /* dw0 */ 231 #define CMPLT_HDR_RSPNS_XFRD_OFF 10 232 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF) 233 #define CMPLT_HDR_ERX_OFF 12 234 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF) 235 #define CMPLT_HDR_ABORT_STAT_OFF 13 236 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF) 237 /* abort_stat */ 238 #define STAT_IO_NOT_VALID 0x1 239 #define STAT_IO_NO_DEVICE 0x2 240 #define STAT_IO_COMPLETE 0x3 241 #define STAT_IO_ABORTED 0x4 242 /* dw1 */ 243 #define CMPLT_HDR_IPTT_OFF 0 244 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF) 245 #define CMPLT_HDR_DEV_ID_OFF 16 246 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF) 247 248 /* ITCT header */ 249 /* qw0 */ 250 #define ITCT_HDR_DEV_TYPE_OFF 0 251 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF) 252 #define ITCT_HDR_VALID_OFF 2 253 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF) 254 #define ITCT_HDR_MCR_OFF 5 255 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF) 256 #define ITCT_HDR_VLN_OFF 9 257 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF) 258 #define ITCT_HDR_PORT_ID_OFF 28 259 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF) 260 /* qw2 */ 261 #define ITCT_HDR_INLT_OFF 0 262 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF) 263 #define ITCT_HDR_BITLT_OFF 16 264 #define ITCT_HDR_BITLT_MSK (0xffffULL << ITCT_HDR_BITLT_OFF) 265 #define ITCT_HDR_MCTLT_OFF 32 266 #define ITCT_HDR_MCTLT_MSK (0xffffULL << ITCT_HDR_MCTLT_OFF) 267 #define ITCT_HDR_RTOLT_OFF 48 268 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF) 269 270 struct hisi_sas_complete_v2_hdr { 271 __le32 dw0; 272 __le32 dw1; 273 __le32 act; 274 __le32 dw3; 275 }; 276 277 struct hisi_sas_err_record_v2 { 278 /* dw0 */ 279 __le32 trans_tx_fail_type; 280 281 /* dw1 */ 282 __le32 trans_rx_fail_type; 283 284 /* dw2 */ 285 __le16 dma_tx_err_type; 286 __le16 sipc_rx_err_type; 287 288 /* dw3 */ 289 __le32 dma_rx_err_type; 290 }; 291 292 enum { 293 HISI_SAS_PHY_PHY_UPDOWN, 294 HISI_SAS_PHY_CHNL_INT, 295 HISI_SAS_PHY_INT_NR 296 }; 297 298 enum { 299 TRANS_TX_FAIL_BASE = 0x0, /* dw0 */ 300 TRANS_RX_FAIL_BASE = 0x100, /* dw1 */ 301 DMA_TX_ERR_BASE = 0x200, /* dw2 bit 15-0 */ 302 SIPC_RX_ERR_BASE = 0x300, /* dw2 bit 31-16*/ 303 DMA_RX_ERR_BASE = 0x400, /* dw3 */ 304 305 /* trans tx*/ 306 TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS = TRANS_TX_FAIL_BASE, /* 0x0 */ 307 TRANS_TX_ERR_PHY_NOT_ENABLE, /* 0x1 */ 308 TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION, /* 0x2 */ 309 TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION, /* 0x3 */ 310 TRANS_TX_OPEN_CNX_ERR_BY_OTHER, /* 0x4 */ 311 RESERVED0, /* 0x5 */ 312 TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT, /* 0x6 */ 313 TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY, /* 0x7 */ 314 TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED, /* 0x8 */ 315 TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED, /* 0x9 */ 316 TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION, /* 0xa */ 317 TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD, /* 0xb */ 318 TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER, /* 0xc */ 319 TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED, /* 0xd */ 320 TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT, /* 0xe */ 321 TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION, /* 0xf */ 322 TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED, /* 0x10 */ 323 TRANS_TX_ERR_FRAME_TXED, /* 0x11 */ 324 TRANS_TX_ERR_WITH_BREAK_TIMEOUT, /* 0x12 */ 325 TRANS_TX_ERR_WITH_BREAK_REQUEST, /* 0x13 */ 326 TRANS_TX_ERR_WITH_BREAK_RECEVIED, /* 0x14 */ 327 TRANS_TX_ERR_WITH_CLOSE_TIMEOUT, /* 0x15 */ 328 TRANS_TX_ERR_WITH_CLOSE_NORMAL, /* 0x16 for ssp*/ 329 TRANS_TX_ERR_WITH_CLOSE_PHYDISALE, /* 0x17 */ 330 TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x18 */ 331 TRANS_TX_ERR_WITH_CLOSE_COMINIT, /* 0x19 */ 332 TRANS_TX_ERR_WITH_NAK_RECEVIED, /* 0x1a for ssp*/ 333 TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT, /* 0x1b for ssp*/ 334 /*IO_TX_ERR_WITH_R_ERR_RECEVIED, [> 0x1b for sata/stp<] */ 335 TRANS_TX_ERR_WITH_CREDIT_TIMEOUT, /* 0x1c for ssp */ 336 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST 0x1c for sata/stp */ 337 TRANS_TX_ERR_WITH_IPTT_CONFLICT, /* 0x1d for ssp/smp */ 338 TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS, /* 0x1e */ 339 /*IO_TX_ERR_WITH_SYNC_RXD, [> 0x1e <] for sata/stp */ 340 TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT, /* 0x1f for sata/stp */ 341 342 /* trans rx */ 343 TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x100 */ 344 TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR, /* 0x101 for sata/stp */ 345 TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM, /* 0x102 for ssp/smp */ 346 /*IO_ERR_WITH_RXFIS_8B10B_CODE_ERR, [> 0x102 <] for sata/stp */ 347 TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR, /* 0x103 for sata/stp */ 348 TRANS_RX_ERR_WITH_RXFIS_CRC_ERR, /* 0x104 for sata/stp */ 349 TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN, /* 0x105 for smp */ 350 /*IO_ERR_WITH_RXFIS_TX SYNCP, [> 0x105 <] for sata/stp */ 351 TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP, /* 0x106 for sata/stp*/ 352 TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN, /* 0x107 */ 353 TRANS_RX_ERR_WITH_BREAK_TIMEOUT, /* 0x108 */ 354 TRANS_RX_ERR_WITH_BREAK_REQUEST, /* 0x109 */ 355 TRANS_RX_ERR_WITH_BREAK_RECEVIED, /* 0x10a */ 356 RESERVED1, /* 0x10b */ 357 TRANS_RX_ERR_WITH_CLOSE_NORMAL, /* 0x10c */ 358 TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE, /* 0x10d */ 359 TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x10e */ 360 TRANS_RX_ERR_WITH_CLOSE_COMINIT, /* 0x10f */ 361 TRANS_RX_ERR_WITH_DATA_LEN0, /* 0x110 for ssp/smp */ 362 TRANS_RX_ERR_WITH_BAD_HASH, /* 0x111 for ssp */ 363 /*IO_RX_ERR_WITH_FIS_TOO_SHORT, [> 0x111 <] for sata/stp */ 364 TRANS_RX_XRDY_WLEN_ZERO_ERR, /* 0x112 for ssp*/ 365 /*IO_RX_ERR_WITH_FIS_TOO_LONG, [> 0x112 <] for sata/stp */ 366 TRANS_RX_SSP_FRM_LEN_ERR, /* 0x113 for ssp */ 367 /*IO_RX_ERR_WITH_SATA_DEVICE_LOST, [> 0x113 <] for sata */ 368 RESERVED2, /* 0x114 */ 369 RESERVED3, /* 0x115 */ 370 RESERVED4, /* 0x116 */ 371 RESERVED5, /* 0x117 */ 372 TRANS_RX_ERR_WITH_BAD_FRM_TYPE, /* 0x118 */ 373 TRANS_RX_SMP_FRM_LEN_ERR, /* 0x119 */ 374 TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x11a */ 375 RESERVED6, /* 0x11b */ 376 RESERVED7, /* 0x11c */ 377 RESERVED8, /* 0x11d */ 378 RESERVED9, /* 0x11e */ 379 TRANS_RX_R_ERR, /* 0x11f */ 380 381 /* dma tx */ 382 DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x200 */ 383 DMA_TX_DIF_APP_ERR, /* 0x201 */ 384 DMA_TX_DIF_RPP_ERR, /* 0x202 */ 385 DMA_TX_DATA_SGL_OVERFLOW, /* 0x203 */ 386 DMA_TX_DIF_SGL_OVERFLOW, /* 0x204 */ 387 DMA_TX_UNEXP_XFER_ERR, /* 0x205 */ 388 DMA_TX_UNEXP_RETRANS_ERR, /* 0x206 */ 389 DMA_TX_XFER_LEN_OVERFLOW, /* 0x207 */ 390 DMA_TX_XFER_OFFSET_ERR, /* 0x208 */ 391 DMA_TX_RAM_ECC_ERR, /* 0x209 */ 392 DMA_TX_DIF_LEN_ALIGN_ERR, /* 0x20a */ 393 394 /* sipc rx */ 395 SIPC_RX_FIS_STATUS_ERR_BIT_VLD = SIPC_RX_ERR_BASE, /* 0x300 */ 396 SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR, /* 0x301 */ 397 SIPC_RX_FIS_STATUS_BSY_BIT_ERR, /* 0x302 */ 398 SIPC_RX_WRSETUP_LEN_ODD_ERR, /* 0x303 */ 399 SIPC_RX_WRSETUP_LEN_ZERO_ERR, /* 0x304 */ 400 SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR, /* 0x305 */ 401 SIPC_RX_NCQ_WRSETUP_OFFSET_ERR, /* 0x306 */ 402 SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR, /* 0x307 */ 403 SIPC_RX_SATA_UNEXP_FIS_ERR, /* 0x308 */ 404 SIPC_RX_WRSETUP_ESTATUS_ERR, /* 0x309 */ 405 SIPC_RX_DATA_UNDERFLOW_ERR, /* 0x30a */ 406 407 /* dma rx */ 408 DMA_RX_DIF_CRC_ERR = DMA_RX_ERR_BASE, /* 0x400 */ 409 DMA_RX_DIF_APP_ERR, /* 0x401 */ 410 DMA_RX_DIF_RPP_ERR, /* 0x402 */ 411 DMA_RX_DATA_SGL_OVERFLOW, /* 0x403 */ 412 DMA_RX_DIF_SGL_OVERFLOW, /* 0x404 */ 413 DMA_RX_DATA_LEN_OVERFLOW, /* 0x405 */ 414 DMA_RX_DATA_LEN_UNDERFLOW, /* 0x406 */ 415 DMA_RX_DATA_OFFSET_ERR, /* 0x407 */ 416 RESERVED10, /* 0x408 */ 417 DMA_RX_SATA_FRAME_TYPE_ERR, /* 0x409 */ 418 DMA_RX_RESP_BUF_OVERFLOW, /* 0x40a */ 419 DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x40b */ 420 DMA_RX_UNEXP_NORM_RESP_ERR, /* 0x40c */ 421 DMA_RX_UNEXP_RDFRAME_ERR, /* 0x40d */ 422 DMA_RX_PIO_DATA_LEN_ERR, /* 0x40e */ 423 DMA_RX_RDSETUP_STATUS_ERR, /* 0x40f */ 424 DMA_RX_RDSETUP_STATUS_DRQ_ERR, /* 0x410 */ 425 DMA_RX_RDSETUP_STATUS_BSY_ERR, /* 0x411 */ 426 DMA_RX_RDSETUP_LEN_ODD_ERR, /* 0x412 */ 427 DMA_RX_RDSETUP_LEN_ZERO_ERR, /* 0x413 */ 428 DMA_RX_RDSETUP_LEN_OVER_ERR, /* 0x414 */ 429 DMA_RX_RDSETUP_OFFSET_ERR, /* 0x415 */ 430 DMA_RX_RDSETUP_ACTIVE_ERR, /* 0x416 */ 431 DMA_RX_RDSETUP_ESTATUS_ERR, /* 0x417 */ 432 DMA_RX_RAM_ECC_ERR, /* 0x418 */ 433 DMA_RX_UNKNOWN_FRM_ERR, /* 0x419 */ 434 }; 435 436 #define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096 437 438 #define DIR_NO_DATA 0 439 #define DIR_TO_INI 1 440 #define DIR_TO_DEVICE 2 441 #define DIR_RESERVED 3 442 443 #define SATA_PROTOCOL_NONDATA 0x1 444 #define SATA_PROTOCOL_PIO 0x2 445 #define SATA_PROTOCOL_DMA 0x4 446 #define SATA_PROTOCOL_FPDMA 0x8 447 #define SATA_PROTOCOL_ATAPI 0x10 448 449 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) 450 { 451 void __iomem *regs = hisi_hba->regs + off; 452 453 return readl(regs); 454 } 455 456 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off) 457 { 458 void __iomem *regs = hisi_hba->regs + off; 459 460 return readl_relaxed(regs); 461 } 462 463 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val) 464 { 465 void __iomem *regs = hisi_hba->regs + off; 466 467 writel(val, regs); 468 } 469 470 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no, 471 u32 off, u32 val) 472 { 473 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 474 475 writel(val, regs); 476 } 477 478 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba, 479 int phy_no, u32 off) 480 { 481 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 482 483 return readl(regs); 484 } 485 486 /* This function needs to be protected from pre-emption. */ 487 static int 488 slot_index_alloc_quirk_v2_hw(struct hisi_hba *hisi_hba, int *slot_idx, 489 struct domain_device *device) 490 { 491 unsigned int index = 0; 492 void *bitmap = hisi_hba->slot_index_tags; 493 int sata_dev = dev_is_sata(device); 494 495 while (1) { 496 index = find_next_zero_bit(bitmap, hisi_hba->slot_index_count, 497 index); 498 if (index >= hisi_hba->slot_index_count) 499 return -SAS_QUEUE_FULL; 500 /* 501 * SAS IPTT bit0 should be 1 502 */ 503 if (sata_dev || (index & 1)) 504 break; 505 index++; 506 } 507 508 set_bit(index, bitmap); 509 *slot_idx = index; 510 return 0; 511 } 512 513 static struct 514 hisi_sas_device *alloc_dev_quirk_v2_hw(struct domain_device *device) 515 { 516 struct hisi_hba *hisi_hba = device->port->ha->lldd_ha; 517 struct hisi_sas_device *sas_dev = NULL; 518 int i, sata_dev = dev_is_sata(device); 519 520 spin_lock(&hisi_hba->lock); 521 for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) { 522 /* 523 * SATA device id bit0 should be 0 524 */ 525 if (sata_dev && (i & 1)) 526 continue; 527 if (hisi_hba->devices[i].dev_type == SAS_PHY_UNUSED) { 528 hisi_hba->devices[i].device_id = i; 529 sas_dev = &hisi_hba->devices[i]; 530 sas_dev->dev_status = HISI_SAS_DEV_NORMAL; 531 sas_dev->dev_type = device->dev_type; 532 sas_dev->hisi_hba = hisi_hba; 533 sas_dev->sas_device = device; 534 break; 535 } 536 } 537 spin_unlock(&hisi_hba->lock); 538 539 return sas_dev; 540 } 541 542 static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no) 543 { 544 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 545 546 cfg &= ~PHY_CFG_DC_OPT_MSK; 547 cfg |= 1 << PHY_CFG_DC_OPT_OFF; 548 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 549 } 550 551 static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no) 552 { 553 struct sas_identify_frame identify_frame; 554 u32 *identify_buffer; 555 556 memset(&identify_frame, 0, sizeof(identify_frame)); 557 identify_frame.dev_type = SAS_END_DEVICE; 558 identify_frame.frame_type = 0; 559 identify_frame._un1 = 1; 560 identify_frame.initiator_bits = SAS_PROTOCOL_ALL; 561 identify_frame.target_bits = SAS_PROTOCOL_NONE; 562 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 563 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 564 identify_frame.phy_id = phy_no; 565 identify_buffer = (u32 *)(&identify_frame); 566 567 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0, 568 __swab32(identify_buffer[0])); 569 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1, 570 __swab32(identify_buffer[1])); 571 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2, 572 __swab32(identify_buffer[2])); 573 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3, 574 __swab32(identify_buffer[3])); 575 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4, 576 __swab32(identify_buffer[4])); 577 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5, 578 __swab32(identify_buffer[5])); 579 } 580 581 static void setup_itct_v2_hw(struct hisi_hba *hisi_hba, 582 struct hisi_sas_device *sas_dev) 583 { 584 struct domain_device *device = sas_dev->sas_device; 585 struct device *dev = &hisi_hba->pdev->dev; 586 u64 qw0, device_id = sas_dev->device_id; 587 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id]; 588 struct domain_device *parent_dev = device->parent; 589 struct hisi_sas_port *port = device->port->lldd_port; 590 591 memset(itct, 0, sizeof(*itct)); 592 593 /* qw0 */ 594 qw0 = 0; 595 switch (sas_dev->dev_type) { 596 case SAS_END_DEVICE: 597 case SAS_EDGE_EXPANDER_DEVICE: 598 case SAS_FANOUT_EXPANDER_DEVICE: 599 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF; 600 break; 601 case SAS_SATA_DEV: 602 case SAS_SATA_PENDING: 603 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) 604 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF; 605 else 606 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF; 607 break; 608 default: 609 dev_warn(dev, "setup itct: unsupported dev type (%d)\n", 610 sas_dev->dev_type); 611 } 612 613 qw0 |= ((1 << ITCT_HDR_VALID_OFF) | 614 (device->linkrate << ITCT_HDR_MCR_OFF) | 615 (1 << ITCT_HDR_VLN_OFF) | 616 (port->id << ITCT_HDR_PORT_ID_OFF)); 617 itct->qw0 = cpu_to_le64(qw0); 618 619 /* qw1 */ 620 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE); 621 itct->sas_addr = __swab64(itct->sas_addr); 622 623 /* qw2 */ 624 if (!dev_is_sata(device)) 625 itct->qw2 = cpu_to_le64((500ULL << ITCT_HDR_INLT_OFF) | 626 (0x1ULL << ITCT_HDR_BITLT_OFF) | 627 (0x32ULL << ITCT_HDR_MCTLT_OFF) | 628 (0x1ULL << ITCT_HDR_RTOLT_OFF)); 629 } 630 631 static void free_device_v2_hw(struct hisi_hba *hisi_hba, 632 struct hisi_sas_device *sas_dev) 633 { 634 u64 qw0, dev_id = sas_dev->device_id; 635 struct device *dev = &hisi_hba->pdev->dev; 636 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id]; 637 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); 638 int i; 639 640 /* clear the itct interrupt state */ 641 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) 642 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 643 ENT_INT_SRC3_ITC_INT_MSK); 644 645 /* clear the itct int*/ 646 for (i = 0; i < 2; i++) { 647 /* clear the itct table*/ 648 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR); 649 reg_val |= ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK); 650 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val); 651 652 udelay(10); 653 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); 654 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) { 655 dev_dbg(dev, "got clear ITCT done interrupt\n"); 656 657 /* invalid the itct state*/ 658 qw0 = cpu_to_le64(itct->qw0); 659 qw0 &= ~(1 << ITCT_HDR_VALID_OFF); 660 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 661 ENT_INT_SRC3_ITC_INT_MSK); 662 hisi_hba->devices[dev_id].dev_type = SAS_PHY_UNUSED; 663 hisi_hba->devices[dev_id].dev_status = HISI_SAS_DEV_NORMAL; 664 665 /* clear the itct */ 666 hisi_sas_write32(hisi_hba, ITCT_CLR, 0); 667 dev_dbg(dev, "clear ITCT ok\n"); 668 break; 669 } 670 } 671 } 672 673 static int reset_hw_v2_hw(struct hisi_hba *hisi_hba) 674 { 675 int i, reset_val; 676 u32 val; 677 unsigned long end_time; 678 struct device *dev = &hisi_hba->pdev->dev; 679 680 /* The mask needs to be set depending on the number of phys */ 681 if (hisi_hba->n_phy == 9) 682 reset_val = 0x1fffff; 683 else 684 reset_val = 0x7ffff; 685 686 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0); 687 688 /* Disable all of the PHYs */ 689 for (i = 0; i < hisi_hba->n_phy; i++) { 690 u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG); 691 692 phy_cfg &= ~PHY_CTRL_RESET_MSK; 693 hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg); 694 } 695 udelay(50); 696 697 /* Ensure DMA tx & rx idle */ 698 for (i = 0; i < hisi_hba->n_phy; i++) { 699 u32 dma_tx_status, dma_rx_status; 700 701 end_time = jiffies + msecs_to_jiffies(1000); 702 703 while (1) { 704 dma_tx_status = hisi_sas_phy_read32(hisi_hba, i, 705 DMA_TX_STATUS); 706 dma_rx_status = hisi_sas_phy_read32(hisi_hba, i, 707 DMA_RX_STATUS); 708 709 if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) && 710 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK)) 711 break; 712 713 msleep(20); 714 if (time_after(jiffies, end_time)) 715 return -EIO; 716 } 717 } 718 719 /* Ensure axi bus idle */ 720 end_time = jiffies + msecs_to_jiffies(1000); 721 while (1) { 722 u32 axi_status = 723 hisi_sas_read32(hisi_hba, AXI_CFG); 724 725 if (axi_status == 0) 726 break; 727 728 msleep(20); 729 if (time_after(jiffies, end_time)) 730 return -EIO; 731 } 732 733 if (ACPI_HANDLE(dev)) { 734 acpi_status s; 735 736 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL); 737 if (ACPI_FAILURE(s)) { 738 dev_err(dev, "Reset failed\n"); 739 return -EIO; 740 } 741 } else if (hisi_hba->ctrl) { 742 /* reset and disable clock*/ 743 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg, 744 reset_val); 745 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4, 746 reset_val); 747 msleep(1); 748 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val); 749 if (reset_val != (val & reset_val)) { 750 dev_err(dev, "SAS reset fail.\n"); 751 return -EIO; 752 } 753 754 /* De-reset and enable clock*/ 755 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4, 756 reset_val); 757 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg, 758 reset_val); 759 msleep(1); 760 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, 761 &val); 762 if (val & reset_val) { 763 dev_err(dev, "SAS de-reset fail.\n"); 764 return -EIO; 765 } 766 } else 767 dev_warn(dev, "no reset method\n"); 768 769 return 0; 770 } 771 772 static void init_reg_v2_hw(struct hisi_hba *hisi_hba) 773 { 774 struct device *dev = &hisi_hba->pdev->dev; 775 int i; 776 777 /* Global registers init */ 778 779 /* Deal with am-max-transmissions quirk */ 780 if (device_property_present(dev, "hip06-sas-v2-quirk-amt")) { 781 hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020); 782 hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS, 783 0x2020); 784 } /* Else, use defaults -> do nothing */ 785 786 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 787 (u32)((1ULL << hisi_hba->queue_count) - 1)); 788 hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000); 789 hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000); 790 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108); 791 hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF); 792 hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1); 793 hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4); 794 hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x32); 795 hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1); 796 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1); 797 hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1); 798 hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1); 799 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); 800 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); 801 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); 802 hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1); 803 hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1); 804 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0); 805 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff); 806 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff); 807 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff); 808 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe); 809 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe); 810 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffffffe); 811 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfffff3c0); 812 for (i = 0; i < hisi_hba->queue_count; i++) 813 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0); 814 815 hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1); 816 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1); 817 818 for (i = 0; i < hisi_hba->n_phy; i++) { 819 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855); 820 hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, 0x30b9908); 821 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d); 822 hisi_sas_phy_write32(hisi_hba, i, SL_CONTROL, 0x0); 823 hisi_sas_phy_write32(hisi_hba, i, TXID_AUTO, 0x2); 824 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x10); 825 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff); 826 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff); 827 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff); 828 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000); 829 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff); 830 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbff); 831 hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x23f801fc); 832 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0); 833 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0); 834 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0); 835 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0); 836 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0); 837 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0); 838 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0); 839 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694); 840 } 841 842 for (i = 0; i < hisi_hba->queue_count; i++) { 843 /* Delivery queue */ 844 hisi_sas_write32(hisi_hba, 845 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14), 846 upper_32_bits(hisi_hba->cmd_hdr_dma[i])); 847 848 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14), 849 lower_32_bits(hisi_hba->cmd_hdr_dma[i])); 850 851 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14), 852 HISI_SAS_QUEUE_SLOTS); 853 854 /* Completion queue */ 855 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14), 856 upper_32_bits(hisi_hba->complete_hdr_dma[i])); 857 858 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14), 859 lower_32_bits(hisi_hba->complete_hdr_dma[i])); 860 861 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14), 862 HISI_SAS_QUEUE_SLOTS); 863 } 864 865 /* itct */ 866 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO, 867 lower_32_bits(hisi_hba->itct_dma)); 868 869 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI, 870 upper_32_bits(hisi_hba->itct_dma)); 871 872 /* iost */ 873 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO, 874 lower_32_bits(hisi_hba->iost_dma)); 875 876 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI, 877 upper_32_bits(hisi_hba->iost_dma)); 878 879 /* breakpoint */ 880 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO, 881 lower_32_bits(hisi_hba->breakpoint_dma)); 882 883 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI, 884 upper_32_bits(hisi_hba->breakpoint_dma)); 885 886 /* SATA broken msg */ 887 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO, 888 lower_32_bits(hisi_hba->sata_breakpoint_dma)); 889 890 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI, 891 upper_32_bits(hisi_hba->sata_breakpoint_dma)); 892 893 /* SATA initial fis */ 894 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO, 895 lower_32_bits(hisi_hba->initial_fis_dma)); 896 897 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI, 898 upper_32_bits(hisi_hba->initial_fis_dma)); 899 } 900 901 static int hw_init_v2_hw(struct hisi_hba *hisi_hba) 902 { 903 struct device *dev = &hisi_hba->pdev->dev; 904 int rc; 905 906 rc = reset_hw_v2_hw(hisi_hba); 907 if (rc) { 908 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc); 909 return rc; 910 } 911 912 msleep(100); 913 init_reg_v2_hw(hisi_hba); 914 915 return 0; 916 } 917 918 static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no) 919 { 920 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 921 922 cfg |= PHY_CFG_ENA_MSK; 923 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 924 } 925 926 static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no) 927 { 928 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 929 930 cfg &= ~PHY_CFG_ENA_MSK; 931 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 932 } 933 934 static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no) 935 { 936 config_id_frame_v2_hw(hisi_hba, phy_no); 937 config_phy_opt_mode_v2_hw(hisi_hba, phy_no); 938 enable_phy_v2_hw(hisi_hba, phy_no); 939 } 940 941 static void stop_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no) 942 { 943 disable_phy_v2_hw(hisi_hba, phy_no); 944 } 945 946 static void phy_hard_reset_v2_hw(struct hisi_hba *hisi_hba, int phy_no) 947 { 948 stop_phy_v2_hw(hisi_hba, phy_no); 949 msleep(100); 950 start_phy_v2_hw(hisi_hba, phy_no); 951 } 952 953 static void start_phys_v2_hw(unsigned long data) 954 { 955 struct hisi_hba *hisi_hba = (struct hisi_hba *)data; 956 int i; 957 958 for (i = 0; i < hisi_hba->n_phy; i++) 959 start_phy_v2_hw(hisi_hba, i); 960 } 961 962 static void phys_init_v2_hw(struct hisi_hba *hisi_hba) 963 { 964 struct timer_list *timer = &hisi_hba->timer; 965 966 setup_timer(timer, start_phys_v2_hw, (unsigned long)hisi_hba); 967 mod_timer(timer, jiffies + HZ); 968 } 969 970 static void sl_notify_v2_hw(struct hisi_hba *hisi_hba, int phy_no) 971 { 972 u32 sl_control; 973 974 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 975 sl_control |= SL_CONTROL_NOTIFY_EN_MSK; 976 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 977 msleep(1); 978 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 979 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK; 980 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 981 } 982 983 static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id) 984 { 985 int i, bitmap = 0; 986 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 987 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 988 989 for (i = 0; i < (hisi_hba->n_phy < 9 ? hisi_hba->n_phy : 8); i++) 990 if (phy_state & 1 << i) 991 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id) 992 bitmap |= 1 << i; 993 994 if (hisi_hba->n_phy == 9) { 995 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE); 996 997 if (phy_state & 1 << 8) 998 if (((port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >> 999 PORT_STATE_PHY8_PORT_NUM_OFF) == port_id) 1000 bitmap |= 1 << 9; 1001 } 1002 1003 return bitmap; 1004 } 1005 1006 /** 1007 * This function allocates across all queues to load balance. 1008 * Slots are allocated from queues in a round-robin fashion. 1009 * 1010 * The callpath to this function and upto writing the write 1011 * queue pointer should be safe from interruption. 1012 */ 1013 static int get_free_slot_v2_hw(struct hisi_hba *hisi_hba, int *q, int *s) 1014 { 1015 struct device *dev = &hisi_hba->pdev->dev; 1016 struct hisi_sas_dq *dq; 1017 u32 r, w; 1018 int queue = hisi_hba->queue; 1019 1020 while (1) { 1021 dq = &hisi_hba->dq[queue]; 1022 w = dq->wr_point; 1023 r = hisi_sas_read32_relaxed(hisi_hba, 1024 DLVRY_Q_0_RD_PTR + (queue * 0x14)); 1025 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) { 1026 queue = (queue + 1) % hisi_hba->queue_count; 1027 if (queue == hisi_hba->queue) { 1028 dev_warn(dev, "could not find free slot\n"); 1029 return -EAGAIN; 1030 } 1031 continue; 1032 } 1033 break; 1034 } 1035 hisi_hba->queue = (queue + 1) % hisi_hba->queue_count; 1036 *q = queue; 1037 *s = w; 1038 return 0; 1039 } 1040 1041 static void start_delivery_v2_hw(struct hisi_hba *hisi_hba) 1042 { 1043 int dlvry_queue = hisi_hba->slot_prep->dlvry_queue; 1044 int dlvry_queue_slot = hisi_hba->slot_prep->dlvry_queue_slot; 1045 struct hisi_sas_dq *dq = &hisi_hba->dq[dlvry_queue]; 1046 1047 dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS; 1048 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), 1049 dq->wr_point); 1050 } 1051 1052 static int prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba, 1053 struct hisi_sas_slot *slot, 1054 struct hisi_sas_cmd_hdr *hdr, 1055 struct scatterlist *scatter, 1056 int n_elem) 1057 { 1058 struct device *dev = &hisi_hba->pdev->dev; 1059 struct scatterlist *sg; 1060 int i; 1061 1062 if (n_elem > HISI_SAS_SGE_PAGE_CNT) { 1063 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT", 1064 n_elem); 1065 return -EINVAL; 1066 } 1067 1068 slot->sge_page = dma_pool_alloc(hisi_hba->sge_page_pool, GFP_ATOMIC, 1069 &slot->sge_page_dma); 1070 if (!slot->sge_page) 1071 return -ENOMEM; 1072 1073 for_each_sg(scatter, sg, n_elem, i) { 1074 struct hisi_sas_sge *entry = &slot->sge_page->sge[i]; 1075 1076 entry->addr = cpu_to_le64(sg_dma_address(sg)); 1077 entry->page_ctrl_0 = entry->page_ctrl_1 = 0; 1078 entry->data_len = cpu_to_le32(sg_dma_len(sg)); 1079 entry->data_off = 0; 1080 } 1081 1082 hdr->prd_table_addr = cpu_to_le64(slot->sge_page_dma); 1083 1084 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF); 1085 1086 return 0; 1087 } 1088 1089 static int prep_smp_v2_hw(struct hisi_hba *hisi_hba, 1090 struct hisi_sas_slot *slot) 1091 { 1092 struct sas_task *task = slot->task; 1093 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1094 struct domain_device *device = task->dev; 1095 struct device *dev = &hisi_hba->pdev->dev; 1096 struct hisi_sas_port *port = slot->port; 1097 struct scatterlist *sg_req, *sg_resp; 1098 struct hisi_sas_device *sas_dev = device->lldd_dev; 1099 dma_addr_t req_dma_addr; 1100 unsigned int req_len, resp_len; 1101 int elem, rc; 1102 1103 /* 1104 * DMA-map SMP request, response buffers 1105 */ 1106 /* req */ 1107 sg_req = &task->smp_task.smp_req; 1108 elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE); 1109 if (!elem) 1110 return -ENOMEM; 1111 req_len = sg_dma_len(sg_req); 1112 req_dma_addr = sg_dma_address(sg_req); 1113 1114 /* resp */ 1115 sg_resp = &task->smp_task.smp_resp; 1116 elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE); 1117 if (!elem) { 1118 rc = -ENOMEM; 1119 goto err_out_req; 1120 } 1121 resp_len = sg_dma_len(sg_resp); 1122 if ((req_len & 0x3) || (resp_len & 0x3)) { 1123 rc = -EINVAL; 1124 goto err_out_resp; 1125 } 1126 1127 /* create header */ 1128 /* dw0 */ 1129 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) | 1130 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */ 1131 (2 << CMD_HDR_CMD_OFF)); /* smp */ 1132 1133 /* map itct entry */ 1134 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) | 1135 (1 << CMD_HDR_FRAME_TYPE_OFF) | 1136 (DIR_NO_DATA << CMD_HDR_DIR_OFF)); 1137 1138 /* dw2 */ 1139 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) | 1140 (HISI_SAS_MAX_SMP_RESP_SZ / 4 << 1141 CMD_HDR_MRFL_OFF)); 1142 1143 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF); 1144 1145 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr); 1146 hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma); 1147 1148 return 0; 1149 1150 err_out_resp: 1151 dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1, 1152 DMA_FROM_DEVICE); 1153 err_out_req: 1154 dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1, 1155 DMA_TO_DEVICE); 1156 return rc; 1157 } 1158 1159 static int prep_ssp_v2_hw(struct hisi_hba *hisi_hba, 1160 struct hisi_sas_slot *slot, int is_tmf, 1161 struct hisi_sas_tmf_task *tmf) 1162 { 1163 struct sas_task *task = slot->task; 1164 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1165 struct domain_device *device = task->dev; 1166 struct hisi_sas_device *sas_dev = device->lldd_dev; 1167 struct hisi_sas_port *port = slot->port; 1168 struct sas_ssp_task *ssp_task = &task->ssp_task; 1169 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd; 1170 int has_data = 0, rc, priority = is_tmf; 1171 u8 *buf_cmd; 1172 u32 dw1 = 0, dw2 = 0; 1173 1174 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) | 1175 (2 << CMD_HDR_TLR_CTRL_OFF) | 1176 (port->id << CMD_HDR_PORT_OFF) | 1177 (priority << CMD_HDR_PRIORITY_OFF) | 1178 (1 << CMD_HDR_CMD_OFF)); /* ssp */ 1179 1180 dw1 = 1 << CMD_HDR_VDTL_OFF; 1181 if (is_tmf) { 1182 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF; 1183 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF; 1184 } else { 1185 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF; 1186 switch (scsi_cmnd->sc_data_direction) { 1187 case DMA_TO_DEVICE: 1188 has_data = 1; 1189 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; 1190 break; 1191 case DMA_FROM_DEVICE: 1192 has_data = 1; 1193 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; 1194 break; 1195 default: 1196 dw1 &= ~CMD_HDR_DIR_MSK; 1197 } 1198 } 1199 1200 /* map itct entry */ 1201 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; 1202 hdr->dw1 = cpu_to_le32(dw1); 1203 1204 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr) 1205 + 3) / 4) << CMD_HDR_CFL_OFF) | 1206 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) | 1207 (2 << CMD_HDR_SG_MOD_OFF); 1208 hdr->dw2 = cpu_to_le32(dw2); 1209 1210 hdr->transfer_tags = cpu_to_le32(slot->idx); 1211 1212 if (has_data) { 1213 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter, 1214 slot->n_elem); 1215 if (rc) 1216 return rc; 1217 } 1218 1219 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); 1220 hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma); 1221 hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma); 1222 1223 buf_cmd = slot->command_table + sizeof(struct ssp_frame_hdr); 1224 1225 memcpy(buf_cmd, &task->ssp_task.LUN, 8); 1226 if (!is_tmf) { 1227 buf_cmd[9] = task->ssp_task.task_attr | 1228 (task->ssp_task.task_prio << 3); 1229 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd, 1230 task->ssp_task.cmd->cmd_len); 1231 } else { 1232 buf_cmd[10] = tmf->tmf; 1233 switch (tmf->tmf) { 1234 case TMF_ABORT_TASK: 1235 case TMF_QUERY_TASK: 1236 buf_cmd[12] = 1237 (tmf->tag_of_task_to_be_managed >> 8) & 0xff; 1238 buf_cmd[13] = 1239 tmf->tag_of_task_to_be_managed & 0xff; 1240 break; 1241 default: 1242 break; 1243 } 1244 } 1245 1246 return 0; 1247 } 1248 1249 static void sata_done_v2_hw(struct hisi_hba *hisi_hba, struct sas_task *task, 1250 struct hisi_sas_slot *slot) 1251 { 1252 struct task_status_struct *ts = &task->task_status; 1253 struct ata_task_resp *resp = (struct ata_task_resp *)ts->buf; 1254 struct dev_to_host_fis *d2h = slot->status_buffer + 1255 sizeof(struct hisi_sas_err_record); 1256 1257 resp->frame_len = sizeof(struct dev_to_host_fis); 1258 memcpy(&resp->ending_fis[0], d2h, sizeof(struct dev_to_host_fis)); 1259 1260 ts->buf_valid_size = sizeof(*resp); 1261 } 1262 1263 /* by default, task resp is complete */ 1264 static void slot_err_v2_hw(struct hisi_hba *hisi_hba, 1265 struct sas_task *task, 1266 struct hisi_sas_slot *slot) 1267 { 1268 struct task_status_struct *ts = &task->task_status; 1269 struct hisi_sas_err_record_v2 *err_record = slot->status_buffer; 1270 u32 trans_tx_fail_type = cpu_to_le32(err_record->trans_tx_fail_type); 1271 u32 trans_rx_fail_type = cpu_to_le32(err_record->trans_rx_fail_type); 1272 u16 dma_tx_err_type = cpu_to_le16(err_record->dma_tx_err_type); 1273 u16 sipc_rx_err_type = cpu_to_le16(err_record->sipc_rx_err_type); 1274 u32 dma_rx_err_type = cpu_to_le32(err_record->dma_rx_err_type); 1275 int error = -1; 1276 1277 if (dma_rx_err_type) { 1278 error = ffs(dma_rx_err_type) 1279 - 1 + DMA_RX_ERR_BASE; 1280 } else if (sipc_rx_err_type) { 1281 error = ffs(sipc_rx_err_type) 1282 - 1 + SIPC_RX_ERR_BASE; 1283 } else if (dma_tx_err_type) { 1284 error = ffs(dma_tx_err_type) 1285 - 1 + DMA_TX_ERR_BASE; 1286 } else if (trans_rx_fail_type) { 1287 error = ffs(trans_rx_fail_type) 1288 - 1 + TRANS_RX_FAIL_BASE; 1289 } else if (trans_tx_fail_type) { 1290 error = ffs(trans_tx_fail_type) 1291 - 1 + TRANS_TX_FAIL_BASE; 1292 } 1293 1294 switch (task->task_proto) { 1295 case SAS_PROTOCOL_SSP: 1296 { 1297 switch (error) { 1298 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION: 1299 { 1300 ts->stat = SAS_OPEN_REJECT; 1301 ts->open_rej_reason = SAS_OREJ_NO_DEST; 1302 break; 1303 } 1304 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED: 1305 { 1306 ts->stat = SAS_OPEN_REJECT; 1307 ts->open_rej_reason = SAS_OREJ_PATH_BLOCKED; 1308 break; 1309 } 1310 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED: 1311 { 1312 ts->stat = SAS_OPEN_REJECT; 1313 ts->open_rej_reason = SAS_OREJ_EPROTO; 1314 break; 1315 } 1316 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED: 1317 { 1318 ts->stat = SAS_OPEN_REJECT; 1319 ts->open_rej_reason = SAS_OREJ_CONN_RATE; 1320 break; 1321 } 1322 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION: 1323 { 1324 ts->stat = SAS_OPEN_REJECT; 1325 ts->open_rej_reason = SAS_OREJ_BAD_DEST; 1326 break; 1327 } 1328 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD: 1329 { 1330 ts->stat = SAS_OPEN_REJECT; 1331 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; 1332 break; 1333 } 1334 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION: 1335 { 1336 ts->stat = SAS_OPEN_REJECT; 1337 ts->open_rej_reason = SAS_OREJ_WRONG_DEST; 1338 break; 1339 } 1340 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION: 1341 { 1342 ts->stat = SAS_OPEN_REJECT; 1343 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1344 break; 1345 } 1346 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER: 1347 { 1348 /* not sure */ 1349 ts->stat = SAS_DEV_NO_RESPONSE; 1350 break; 1351 } 1352 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE: 1353 { 1354 ts->stat = SAS_PHY_DOWN; 1355 break; 1356 } 1357 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT: 1358 { 1359 ts->stat = SAS_OPEN_TO; 1360 break; 1361 } 1362 case DMA_RX_DATA_LEN_OVERFLOW: 1363 { 1364 ts->stat = SAS_DATA_OVERRUN; 1365 ts->residual = 0; 1366 break; 1367 } 1368 case DMA_RX_DATA_LEN_UNDERFLOW: 1369 case SIPC_RX_DATA_UNDERFLOW_ERR: 1370 { 1371 ts->residual = trans_tx_fail_type; 1372 ts->stat = SAS_DATA_UNDERRUN; 1373 break; 1374 } 1375 case TRANS_TX_ERR_FRAME_TXED: 1376 { 1377 /* This will request a retry */ 1378 ts->stat = SAS_QUEUE_FULL; 1379 slot->abort = 1; 1380 break; 1381 } 1382 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS: 1383 case TRANS_TX_ERR_PHY_NOT_ENABLE: 1384 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER: 1385 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT: 1386 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED: 1387 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT: 1388 case TRANS_TX_ERR_WITH_BREAK_REQUEST: 1389 case TRANS_TX_ERR_WITH_BREAK_RECEVIED: 1390 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT: 1391 case TRANS_TX_ERR_WITH_CLOSE_NORMAL: 1392 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT: 1393 case TRANS_TX_ERR_WITH_CLOSE_COMINIT: 1394 case TRANS_TX_ERR_WITH_NAK_RECEVIED: 1395 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT: 1396 case TRANS_TX_ERR_WITH_IPTT_CONFLICT: 1397 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT: 1398 case TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR: 1399 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR: 1400 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM: 1401 case TRANS_RX_ERR_WITH_BREAK_TIMEOUT: 1402 case TRANS_RX_ERR_WITH_BREAK_REQUEST: 1403 case TRANS_RX_ERR_WITH_BREAK_RECEVIED: 1404 case TRANS_RX_ERR_WITH_CLOSE_NORMAL: 1405 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT: 1406 case TRANS_RX_ERR_WITH_CLOSE_COMINIT: 1407 case TRANS_RX_ERR_WITH_DATA_LEN0: 1408 case TRANS_RX_ERR_WITH_BAD_HASH: 1409 case TRANS_RX_XRDY_WLEN_ZERO_ERR: 1410 case TRANS_RX_SSP_FRM_LEN_ERR: 1411 case TRANS_RX_ERR_WITH_BAD_FRM_TYPE: 1412 case DMA_TX_UNEXP_XFER_ERR: 1413 case DMA_TX_UNEXP_RETRANS_ERR: 1414 case DMA_TX_XFER_LEN_OVERFLOW: 1415 case DMA_TX_XFER_OFFSET_ERR: 1416 case DMA_RX_DATA_OFFSET_ERR: 1417 case DMA_RX_UNEXP_NORM_RESP_ERR: 1418 case DMA_RX_UNEXP_RDFRAME_ERR: 1419 case DMA_RX_UNKNOWN_FRM_ERR: 1420 { 1421 ts->stat = SAS_OPEN_REJECT; 1422 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1423 break; 1424 } 1425 default: 1426 break; 1427 } 1428 } 1429 break; 1430 case SAS_PROTOCOL_SMP: 1431 ts->stat = SAM_STAT_CHECK_CONDITION; 1432 break; 1433 1434 case SAS_PROTOCOL_SATA: 1435 case SAS_PROTOCOL_STP: 1436 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 1437 { 1438 switch (error) { 1439 case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER: 1440 case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED: 1441 case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION: 1442 { 1443 ts->resp = SAS_TASK_UNDELIVERED; 1444 ts->stat = SAS_DEV_NO_RESPONSE; 1445 break; 1446 } 1447 case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED: 1448 case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED: 1449 case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION: 1450 case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD: 1451 case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION: 1452 case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION: 1453 case TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY: 1454 { 1455 ts->stat = SAS_OPEN_REJECT; 1456 break; 1457 } 1458 case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT: 1459 { 1460 ts->stat = SAS_OPEN_TO; 1461 break; 1462 } 1463 case DMA_RX_DATA_LEN_OVERFLOW: 1464 { 1465 ts->stat = SAS_DATA_OVERRUN; 1466 break; 1467 } 1468 case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS: 1469 case TRANS_TX_ERR_PHY_NOT_ENABLE: 1470 case TRANS_TX_OPEN_CNX_ERR_BY_OTHER: 1471 case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT: 1472 case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED: 1473 case TRANS_TX_ERR_WITH_BREAK_TIMEOUT: 1474 case TRANS_TX_ERR_WITH_BREAK_REQUEST: 1475 case TRANS_TX_ERR_WITH_BREAK_RECEVIED: 1476 case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT: 1477 case TRANS_TX_ERR_WITH_CLOSE_NORMAL: 1478 case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT: 1479 case TRANS_TX_ERR_WITH_CLOSE_COMINIT: 1480 case TRANS_TX_ERR_WITH_NAK_RECEVIED: 1481 case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT: 1482 case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT: 1483 case TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT: 1484 case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR: 1485 case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM: 1486 case TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR: 1487 case TRANS_RX_ERR_WITH_RXFIS_CRC_ERR: 1488 case TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN: 1489 case TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP: 1490 case TRANS_RX_ERR_WITH_CLOSE_NORMAL: 1491 case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE: 1492 case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT: 1493 case TRANS_RX_ERR_WITH_CLOSE_COMINIT: 1494 case TRANS_RX_ERR_WITH_DATA_LEN0: 1495 case TRANS_RX_ERR_WITH_BAD_HASH: 1496 case TRANS_RX_XRDY_WLEN_ZERO_ERR: 1497 case TRANS_RX_SSP_FRM_LEN_ERR: 1498 case SIPC_RX_FIS_STATUS_ERR_BIT_VLD: 1499 case SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR: 1500 case SIPC_RX_FIS_STATUS_BSY_BIT_ERR: 1501 case SIPC_RX_WRSETUP_LEN_ODD_ERR: 1502 case SIPC_RX_WRSETUP_LEN_ZERO_ERR: 1503 case SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR: 1504 case SIPC_RX_SATA_UNEXP_FIS_ERR: 1505 case DMA_RX_SATA_FRAME_TYPE_ERR: 1506 case DMA_RX_UNEXP_RDFRAME_ERR: 1507 case DMA_RX_PIO_DATA_LEN_ERR: 1508 case DMA_RX_RDSETUP_STATUS_ERR: 1509 case DMA_RX_RDSETUP_STATUS_DRQ_ERR: 1510 case DMA_RX_RDSETUP_STATUS_BSY_ERR: 1511 case DMA_RX_RDSETUP_LEN_ODD_ERR: 1512 case DMA_RX_RDSETUP_LEN_ZERO_ERR: 1513 case DMA_RX_RDSETUP_LEN_OVER_ERR: 1514 case DMA_RX_RDSETUP_OFFSET_ERR: 1515 case DMA_RX_RDSETUP_ACTIVE_ERR: 1516 case DMA_RX_RDSETUP_ESTATUS_ERR: 1517 case DMA_RX_UNKNOWN_FRM_ERR: 1518 { 1519 ts->stat = SAS_OPEN_REJECT; 1520 break; 1521 } 1522 default: 1523 { 1524 ts->stat = SAS_PROTO_RESPONSE; 1525 break; 1526 } 1527 } 1528 sata_done_v2_hw(hisi_hba, task, slot); 1529 } 1530 break; 1531 default: 1532 break; 1533 } 1534 } 1535 1536 static int 1537 slot_complete_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot, 1538 int abort) 1539 { 1540 struct sas_task *task = slot->task; 1541 struct hisi_sas_device *sas_dev; 1542 struct device *dev = &hisi_hba->pdev->dev; 1543 struct task_status_struct *ts; 1544 struct domain_device *device; 1545 enum exec_status sts; 1546 struct hisi_sas_complete_v2_hdr *complete_queue = 1547 hisi_hba->complete_hdr[slot->cmplt_queue]; 1548 struct hisi_sas_complete_v2_hdr *complete_hdr = 1549 &complete_queue[slot->cmplt_queue_slot]; 1550 1551 if (unlikely(!task || !task->lldd_task || !task->dev)) 1552 return -EINVAL; 1553 1554 ts = &task->task_status; 1555 device = task->dev; 1556 sas_dev = device->lldd_dev; 1557 1558 task->task_state_flags &= 1559 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR); 1560 task->task_state_flags |= SAS_TASK_STATE_DONE; 1561 1562 memset(ts, 0, sizeof(*ts)); 1563 ts->resp = SAS_TASK_COMPLETE; 1564 1565 if (unlikely(!sas_dev || abort)) { 1566 if (!sas_dev) 1567 dev_dbg(dev, "slot complete: port has not device\n"); 1568 ts->stat = SAS_PHY_DOWN; 1569 goto out; 1570 } 1571 1572 /* Use SAS+TMF status codes */ 1573 switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK) 1574 >> CMPLT_HDR_ABORT_STAT_OFF) { 1575 case STAT_IO_ABORTED: 1576 /* this io has been aborted by abort command */ 1577 ts->stat = SAS_ABORTED_TASK; 1578 goto out; 1579 case STAT_IO_COMPLETE: 1580 /* internal abort command complete */ 1581 ts->stat = TMF_RESP_FUNC_COMPLETE; 1582 goto out; 1583 case STAT_IO_NO_DEVICE: 1584 ts->stat = TMF_RESP_FUNC_COMPLETE; 1585 goto out; 1586 case STAT_IO_NOT_VALID: 1587 /* abort single io, controller don't find 1588 * the io need to abort 1589 */ 1590 ts->stat = TMF_RESP_FUNC_FAILED; 1591 goto out; 1592 default: 1593 break; 1594 } 1595 1596 if ((complete_hdr->dw0 & CMPLT_HDR_ERX_MSK) && 1597 (!(complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) { 1598 1599 slot_err_v2_hw(hisi_hba, task, slot); 1600 if (unlikely(slot->abort)) { 1601 queue_work(hisi_hba->wq, &slot->abort_slot); 1602 /* immediately return and do not complete */ 1603 return ts->stat; 1604 } 1605 goto out; 1606 } 1607 1608 switch (task->task_proto) { 1609 case SAS_PROTOCOL_SSP: 1610 { 1611 struct ssp_response_iu *iu = slot->status_buffer + 1612 sizeof(struct hisi_sas_err_record); 1613 1614 sas_ssp_task_response(dev, task, iu); 1615 break; 1616 } 1617 case SAS_PROTOCOL_SMP: 1618 { 1619 struct scatterlist *sg_resp = &task->smp_task.smp_resp; 1620 void *to; 1621 1622 ts->stat = SAM_STAT_GOOD; 1623 to = kmap_atomic(sg_page(sg_resp)); 1624 1625 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1, 1626 DMA_FROM_DEVICE); 1627 dma_unmap_sg(dev, &task->smp_task.smp_req, 1, 1628 DMA_TO_DEVICE); 1629 memcpy(to + sg_resp->offset, 1630 slot->status_buffer + 1631 sizeof(struct hisi_sas_err_record), 1632 sg_dma_len(sg_resp)); 1633 kunmap_atomic(to); 1634 break; 1635 } 1636 case SAS_PROTOCOL_SATA: 1637 case SAS_PROTOCOL_STP: 1638 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 1639 { 1640 ts->stat = SAM_STAT_GOOD; 1641 sata_done_v2_hw(hisi_hba, task, slot); 1642 break; 1643 } 1644 default: 1645 ts->stat = SAM_STAT_CHECK_CONDITION; 1646 break; 1647 } 1648 1649 if (!slot->port->port_attached) { 1650 dev_err(dev, "slot complete: port %d has removed\n", 1651 slot->port->sas_port.id); 1652 ts->stat = SAS_PHY_DOWN; 1653 } 1654 1655 out: 1656 if (sas_dev && sas_dev->running_req) 1657 sas_dev->running_req--; 1658 1659 hisi_sas_slot_task_free(hisi_hba, task, slot); 1660 sts = ts->stat; 1661 1662 if (task->task_done) 1663 task->task_done(task); 1664 1665 return sts; 1666 } 1667 1668 static u8 get_ata_protocol(u8 cmd, int direction) 1669 { 1670 switch (cmd) { 1671 case ATA_CMD_FPDMA_WRITE: 1672 case ATA_CMD_FPDMA_READ: 1673 case ATA_CMD_FPDMA_RECV: 1674 case ATA_CMD_FPDMA_SEND: 1675 case ATA_CMD_NCQ_NON_DATA: 1676 return SATA_PROTOCOL_FPDMA; 1677 1678 case ATA_CMD_ID_ATA: 1679 case ATA_CMD_PMP_READ: 1680 case ATA_CMD_READ_LOG_EXT: 1681 case ATA_CMD_PIO_READ: 1682 case ATA_CMD_PIO_READ_EXT: 1683 case ATA_CMD_PMP_WRITE: 1684 case ATA_CMD_WRITE_LOG_EXT: 1685 case ATA_CMD_PIO_WRITE: 1686 case ATA_CMD_PIO_WRITE_EXT: 1687 return SATA_PROTOCOL_PIO; 1688 1689 case ATA_CMD_READ: 1690 case ATA_CMD_READ_EXT: 1691 case ATA_CMD_READ_LOG_DMA_EXT: 1692 case ATA_CMD_WRITE: 1693 case ATA_CMD_WRITE_EXT: 1694 case ATA_CMD_WRITE_QUEUED: 1695 case ATA_CMD_WRITE_LOG_DMA_EXT: 1696 return SATA_PROTOCOL_DMA; 1697 1698 case ATA_CMD_DOWNLOAD_MICRO: 1699 case ATA_CMD_DEV_RESET: 1700 case ATA_CMD_CHK_POWER: 1701 case ATA_CMD_FLUSH: 1702 case ATA_CMD_FLUSH_EXT: 1703 case ATA_CMD_VERIFY: 1704 case ATA_CMD_VERIFY_EXT: 1705 case ATA_CMD_SET_FEATURES: 1706 case ATA_CMD_STANDBY: 1707 case ATA_CMD_STANDBYNOW1: 1708 return SATA_PROTOCOL_NONDATA; 1709 default: 1710 if (direction == DMA_NONE) 1711 return SATA_PROTOCOL_NONDATA; 1712 return SATA_PROTOCOL_PIO; 1713 } 1714 } 1715 1716 static int get_ncq_tag_v2_hw(struct sas_task *task, u32 *tag) 1717 { 1718 struct ata_queued_cmd *qc = task->uldd_task; 1719 1720 if (qc) { 1721 if (qc->tf.command == ATA_CMD_FPDMA_WRITE || 1722 qc->tf.command == ATA_CMD_FPDMA_READ) { 1723 *tag = qc->tag; 1724 return 1; 1725 } 1726 } 1727 return 0; 1728 } 1729 1730 static int prep_ata_v2_hw(struct hisi_hba *hisi_hba, 1731 struct hisi_sas_slot *slot) 1732 { 1733 struct sas_task *task = slot->task; 1734 struct domain_device *device = task->dev; 1735 struct domain_device *parent_dev = device->parent; 1736 struct hisi_sas_device *sas_dev = device->lldd_dev; 1737 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1738 struct hisi_sas_port *port = device->port->lldd_port; 1739 u8 *buf_cmd; 1740 int has_data = 0, rc = 0, hdr_tag = 0; 1741 u32 dw1 = 0, dw2 = 0; 1742 1743 /* create header */ 1744 /* dw0 */ 1745 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF); 1746 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) 1747 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF); 1748 else 1749 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF); 1750 1751 /* dw1 */ 1752 switch (task->data_dir) { 1753 case DMA_TO_DEVICE: 1754 has_data = 1; 1755 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; 1756 break; 1757 case DMA_FROM_DEVICE: 1758 has_data = 1; 1759 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; 1760 break; 1761 default: 1762 dw1 &= ~CMD_HDR_DIR_MSK; 1763 } 1764 1765 if (0 == task->ata_task.fis.command) 1766 dw1 |= 1 << CMD_HDR_RESET_OFF; 1767 1768 dw1 |= (get_ata_protocol(task->ata_task.fis.command, task->data_dir)) 1769 << CMD_HDR_FRAME_TYPE_OFF; 1770 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; 1771 hdr->dw1 = cpu_to_le32(dw1); 1772 1773 /* dw2 */ 1774 if (task->ata_task.use_ncq && get_ncq_tag_v2_hw(task, &hdr_tag)) { 1775 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); 1776 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF; 1777 } 1778 1779 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF | 1780 2 << CMD_HDR_SG_MOD_OFF; 1781 hdr->dw2 = cpu_to_le32(dw2); 1782 1783 /* dw3 */ 1784 hdr->transfer_tags = cpu_to_le32(slot->idx); 1785 1786 if (has_data) { 1787 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter, 1788 slot->n_elem); 1789 if (rc) 1790 return rc; 1791 } 1792 1793 1794 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); 1795 hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma); 1796 hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma); 1797 1798 buf_cmd = slot->command_table; 1799 1800 if (likely(!task->ata_task.device_control_reg_update)) 1801 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */ 1802 /* fill in command FIS */ 1803 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis)); 1804 1805 return 0; 1806 } 1807 1808 static int prep_abort_v2_hw(struct hisi_hba *hisi_hba, 1809 struct hisi_sas_slot *slot, 1810 int device_id, int abort_flag, int tag_to_abort) 1811 { 1812 struct sas_task *task = slot->task; 1813 struct domain_device *dev = task->dev; 1814 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 1815 struct hisi_sas_port *port = slot->port; 1816 1817 /* dw0 */ 1818 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/ 1819 (port->id << CMD_HDR_PORT_OFF) | 1820 ((dev_is_sata(dev) ? 1:0) << 1821 CMD_HDR_ABORT_DEVICE_TYPE_OFF) | 1822 (abort_flag << CMD_HDR_ABORT_FLAG_OFF)); 1823 1824 /* dw1 */ 1825 hdr->dw1 = cpu_to_le32(device_id << CMD_HDR_DEV_ID_OFF); 1826 1827 /* dw7 */ 1828 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF); 1829 hdr->transfer_tags = cpu_to_le32(slot->idx); 1830 1831 return 0; 1832 } 1833 1834 static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba) 1835 { 1836 int i, res = 0; 1837 u32 context, port_id, link_rate, hard_phy_linkrate; 1838 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1839 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1840 struct device *dev = &hisi_hba->pdev->dev; 1841 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd; 1842 struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd; 1843 1844 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1); 1845 1846 /* Check for SATA dev */ 1847 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT); 1848 if (context & (1 << phy_no)) 1849 goto end; 1850 1851 if (phy_no == 8) { 1852 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE); 1853 1854 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >> 1855 PORT_STATE_PHY8_PORT_NUM_OFF; 1856 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >> 1857 PORT_STATE_PHY8_CONN_RATE_OFF; 1858 } else { 1859 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 1860 port_id = (port_id >> (4 * phy_no)) & 0xf; 1861 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); 1862 link_rate = (link_rate >> (phy_no * 4)) & 0xf; 1863 } 1864 1865 if (port_id == 0xf) { 1866 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no); 1867 res = IRQ_NONE; 1868 goto end; 1869 } 1870 1871 for (i = 0; i < 6; i++) { 1872 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no, 1873 RX_IDAF_DWORD0 + (i * 4)); 1874 frame_rcvd[i] = __swab32(idaf); 1875 } 1876 1877 sas_phy->linkrate = link_rate; 1878 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no, 1879 HARD_PHY_LINKRATE); 1880 phy->maximum_linkrate = hard_phy_linkrate & 0xf; 1881 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf; 1882 1883 sas_phy->oob_mode = SAS_OOB_MODE; 1884 memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE); 1885 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate); 1886 phy->port_id = port_id; 1887 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); 1888 phy->phy_type |= PORT_TYPE_SAS; 1889 phy->phy_attached = 1; 1890 phy->identify.device_type = id->dev_type; 1891 phy->frame_rcvd_size = sizeof(struct sas_identify_frame); 1892 if (phy->identify.device_type == SAS_END_DEVICE) 1893 phy->identify.target_port_protocols = 1894 SAS_PROTOCOL_SSP; 1895 else if (phy->identify.device_type != SAS_PHY_UNUSED) 1896 phy->identify.target_port_protocols = 1897 SAS_PROTOCOL_SMP; 1898 queue_work(hisi_hba->wq, &phy->phyup_ws); 1899 1900 end: 1901 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1902 CHL_INT0_SL_PHY_ENABLE_MSK); 1903 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0); 1904 1905 return res; 1906 } 1907 1908 static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba) 1909 { 1910 int res = 0; 1911 u32 phy_state, sl_ctrl, txid_auto; 1912 1913 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1); 1914 1915 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1916 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0); 1917 1918 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 1919 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, 1920 sl_ctrl & ~SL_CONTROL_CTA_MSK); 1921 1922 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); 1923 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, 1924 txid_auto | TXID_AUTO_CT3_MSK); 1925 1926 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK); 1927 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0); 1928 1929 return res; 1930 } 1931 1932 static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p) 1933 { 1934 struct hisi_hba *hisi_hba = p; 1935 u32 irq_msk; 1936 int phy_no = 0; 1937 irqreturn_t res = IRQ_HANDLED; 1938 1939 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) 1940 >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff; 1941 while (irq_msk) { 1942 if (irq_msk & 1) { 1943 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, 1944 CHL_INT0); 1945 1946 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK) 1947 /* phy up */ 1948 if (phy_up_v2_hw(phy_no, hisi_hba)) { 1949 res = IRQ_NONE; 1950 goto end; 1951 } 1952 1953 if (irq_value & CHL_INT0_NOT_RDY_MSK) 1954 /* phy down */ 1955 if (phy_down_v2_hw(phy_no, hisi_hba)) { 1956 res = IRQ_NONE; 1957 goto end; 1958 } 1959 } 1960 irq_msk >>= 1; 1961 phy_no++; 1962 } 1963 1964 end: 1965 return res; 1966 } 1967 1968 static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba) 1969 { 1970 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; 1971 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1972 struct sas_ha_struct *sas_ha = &hisi_hba->sha; 1973 1974 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1); 1975 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 1976 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, 1977 CHL_INT0_SL_RX_BCST_ACK_MSK); 1978 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0); 1979 } 1980 1981 static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p) 1982 { 1983 struct hisi_hba *hisi_hba = p; 1984 struct device *dev = &hisi_hba->pdev->dev; 1985 u32 ent_msk, ent_tmp, irq_msk; 1986 int phy_no = 0; 1987 1988 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3); 1989 ent_tmp = ent_msk; 1990 ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK; 1991 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk); 1992 1993 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) >> 1994 HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff; 1995 1996 while (irq_msk) { 1997 if (irq_msk & (1 << phy_no)) { 1998 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, 1999 CHL_INT0); 2000 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no, 2001 CHL_INT1); 2002 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no, 2003 CHL_INT2); 2004 2005 if (irq_value1) { 2006 if (irq_value1 & (CHL_INT1_DMAC_RX_ECC_ERR_MSK | 2007 CHL_INT1_DMAC_TX_ECC_ERR_MSK)) 2008 panic("%s: DMAC RX/TX ecc bad error! (0x%x)", 2009 dev_name(dev), irq_value1); 2010 2011 hisi_sas_phy_write32(hisi_hba, phy_no, 2012 CHL_INT1, irq_value1); 2013 } 2014 2015 if (irq_value2) 2016 hisi_sas_phy_write32(hisi_hba, phy_no, 2017 CHL_INT2, irq_value2); 2018 2019 2020 if (irq_value0) { 2021 if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK) 2022 phy_bcast_v2_hw(phy_no, hisi_hba); 2023 2024 hisi_sas_phy_write32(hisi_hba, phy_no, 2025 CHL_INT0, irq_value0 2026 & (~CHL_INT0_HOTPLUG_TOUT_MSK) 2027 & (~CHL_INT0_SL_PHY_ENABLE_MSK) 2028 & (~CHL_INT0_NOT_RDY_MSK)); 2029 } 2030 } 2031 irq_msk &= ~(1 << phy_no); 2032 phy_no++; 2033 } 2034 2035 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp); 2036 2037 return IRQ_HANDLED; 2038 } 2039 2040 static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p) 2041 { 2042 struct hisi_sas_cq *cq = p; 2043 struct hisi_hba *hisi_hba = cq->hisi_hba; 2044 struct hisi_sas_slot *slot; 2045 struct hisi_sas_itct *itct; 2046 struct hisi_sas_complete_v2_hdr *complete_queue; 2047 u32 irq_value, rd_point = cq->rd_point, wr_point, dev_id; 2048 int queue = cq->id; 2049 2050 complete_queue = hisi_hba->complete_hdr[queue]; 2051 irq_value = hisi_sas_read32(hisi_hba, OQ_INT_SRC); 2052 2053 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue); 2054 2055 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR + 2056 (0x14 * queue)); 2057 2058 while (rd_point != wr_point) { 2059 struct hisi_sas_complete_v2_hdr *complete_hdr; 2060 int iptt; 2061 2062 complete_hdr = &complete_queue[rd_point]; 2063 2064 /* Check for NCQ completion */ 2065 if (complete_hdr->act) { 2066 u32 act_tmp = complete_hdr->act; 2067 int ncq_tag_count = ffs(act_tmp); 2068 2069 dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >> 2070 CMPLT_HDR_DEV_ID_OFF; 2071 itct = &hisi_hba->itct[dev_id]; 2072 2073 /* The NCQ tags are held in the itct header */ 2074 while (ncq_tag_count) { 2075 __le64 *ncq_tag = &itct->qw4_15[0]; 2076 2077 ncq_tag_count -= 1; 2078 iptt = (ncq_tag[ncq_tag_count / 5] 2079 >> (ncq_tag_count % 5) * 12) & 0xfff; 2080 2081 slot = &hisi_hba->slot_info[iptt]; 2082 slot->cmplt_queue_slot = rd_point; 2083 slot->cmplt_queue = queue; 2084 slot_complete_v2_hw(hisi_hba, slot, 0); 2085 2086 act_tmp &= ~(1 << ncq_tag_count); 2087 ncq_tag_count = ffs(act_tmp); 2088 } 2089 } else { 2090 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK; 2091 slot = &hisi_hba->slot_info[iptt]; 2092 slot->cmplt_queue_slot = rd_point; 2093 slot->cmplt_queue = queue; 2094 slot_complete_v2_hw(hisi_hba, slot, 0); 2095 } 2096 2097 if (++rd_point >= HISI_SAS_QUEUE_SLOTS) 2098 rd_point = 0; 2099 } 2100 2101 /* update rd_point */ 2102 cq->rd_point = rd_point; 2103 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point); 2104 return IRQ_HANDLED; 2105 } 2106 2107 static irqreturn_t sata_int_v2_hw(int irq_no, void *p) 2108 { 2109 struct hisi_sas_phy *phy = p; 2110 struct hisi_hba *hisi_hba = phy->hisi_hba; 2111 struct asd_sas_phy *sas_phy = &phy->sas_phy; 2112 struct device *dev = &hisi_hba->pdev->dev; 2113 struct hisi_sas_initial_fis *initial_fis; 2114 struct dev_to_host_fis *fis; 2115 u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate; 2116 irqreturn_t res = IRQ_HANDLED; 2117 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0}; 2118 int phy_no, offset; 2119 2120 phy_no = sas_phy->id; 2121 initial_fis = &hisi_hba->initial_fis[phy_no]; 2122 fis = &initial_fis->fis; 2123 2124 offset = 4 * (phy_no / 4); 2125 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK1 + offset); 2126 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset, 2127 ent_msk | 1 << ((phy_no % 4) * 8)); 2128 2129 ent_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC1 + offset); 2130 ent_tmp = ent_int & (1 << (ENT_INT_SRC1_D2H_FIS_CH1_OFF * 2131 (phy_no % 4))); 2132 ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4); 2133 if ((ent_int & ENT_INT_SRC1_D2H_FIS_CH0_MSK) == 0) { 2134 dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no); 2135 res = IRQ_NONE; 2136 goto end; 2137 } 2138 2139 if (unlikely(phy_no == 8)) { 2140 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE); 2141 2142 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >> 2143 PORT_STATE_PHY8_PORT_NUM_OFF; 2144 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >> 2145 PORT_STATE_PHY8_CONN_RATE_OFF; 2146 } else { 2147 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 2148 port_id = (port_id >> (4 * phy_no)) & 0xf; 2149 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); 2150 link_rate = (link_rate >> (phy_no * 4)) & 0xf; 2151 } 2152 2153 if (port_id == 0xf) { 2154 dev_err(dev, "sata int: phy%d invalid portid\n", phy_no); 2155 res = IRQ_NONE; 2156 goto end; 2157 } 2158 2159 sas_phy->linkrate = link_rate; 2160 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no, 2161 HARD_PHY_LINKRATE); 2162 phy->maximum_linkrate = hard_phy_linkrate & 0xf; 2163 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf; 2164 2165 sas_phy->oob_mode = SATA_OOB_MODE; 2166 /* Make up some unique SAS address */ 2167 attached_sas_addr[0] = 0x50; 2168 attached_sas_addr[7] = phy_no; 2169 memcpy(sas_phy->attached_sas_addr, attached_sas_addr, SAS_ADDR_SIZE); 2170 memcpy(sas_phy->frame_rcvd, fis, sizeof(struct dev_to_host_fis)); 2171 dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate); 2172 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); 2173 phy->port_id = port_id; 2174 phy->phy_type |= PORT_TYPE_SATA; 2175 phy->phy_attached = 1; 2176 phy->identify.device_type = SAS_SATA_DEV; 2177 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); 2178 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; 2179 queue_work(hisi_hba->wq, &phy->phyup_ws); 2180 2181 end: 2182 hisi_sas_write32(hisi_hba, ENT_INT_SRC1 + offset, ent_tmp); 2183 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset, ent_msk); 2184 2185 return res; 2186 } 2187 2188 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = { 2189 int_phy_updown_v2_hw, 2190 int_chnl_int_v2_hw, 2191 }; 2192 2193 /** 2194 * There is a limitation in the hip06 chipset that we need 2195 * to map in all mbigen interrupts, even if they are not used. 2196 */ 2197 static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba) 2198 { 2199 struct platform_device *pdev = hisi_hba->pdev; 2200 struct device *dev = &pdev->dev; 2201 int i, irq, rc, irq_map[128]; 2202 2203 2204 for (i = 0; i < 128; i++) 2205 irq_map[i] = platform_get_irq(pdev, i); 2206 2207 for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) { 2208 int idx = i; 2209 2210 irq = irq_map[idx + 1]; /* Phy up/down is irq1 */ 2211 if (!irq) { 2212 dev_err(dev, "irq init: fail map phy interrupt %d\n", 2213 idx); 2214 return -ENOENT; 2215 } 2216 2217 rc = devm_request_irq(dev, irq, phy_interrupts[i], 0, 2218 DRV_NAME " phy", hisi_hba); 2219 if (rc) { 2220 dev_err(dev, "irq init: could not request " 2221 "phy interrupt %d, rc=%d\n", 2222 irq, rc); 2223 return -ENOENT; 2224 } 2225 } 2226 2227 for (i = 0; i < hisi_hba->n_phy; i++) { 2228 struct hisi_sas_phy *phy = &hisi_hba->phy[i]; 2229 int idx = i + 72; /* First SATA interrupt is irq72 */ 2230 2231 irq = irq_map[idx]; 2232 if (!irq) { 2233 dev_err(dev, "irq init: fail map phy interrupt %d\n", 2234 idx); 2235 return -ENOENT; 2236 } 2237 2238 rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0, 2239 DRV_NAME " sata", phy); 2240 if (rc) { 2241 dev_err(dev, "irq init: could not request " 2242 "sata interrupt %d, rc=%d\n", 2243 irq, rc); 2244 return -ENOENT; 2245 } 2246 } 2247 2248 for (i = 0; i < hisi_hba->queue_count; i++) { 2249 int idx = i + 96; /* First cq interrupt is irq96 */ 2250 2251 irq = irq_map[idx]; 2252 if (!irq) { 2253 dev_err(dev, 2254 "irq init: could not map cq interrupt %d\n", 2255 idx); 2256 return -ENOENT; 2257 } 2258 rc = devm_request_irq(dev, irq, cq_interrupt_v2_hw, 0, 2259 DRV_NAME " cq", &hisi_hba->cq[i]); 2260 if (rc) { 2261 dev_err(dev, 2262 "irq init: could not request cq interrupt %d, rc=%d\n", 2263 irq, rc); 2264 return -ENOENT; 2265 } 2266 } 2267 2268 return 0; 2269 } 2270 2271 static int hisi_sas_v2_init(struct hisi_hba *hisi_hba) 2272 { 2273 int rc; 2274 2275 rc = hw_init_v2_hw(hisi_hba); 2276 if (rc) 2277 return rc; 2278 2279 rc = interrupt_init_v2_hw(hisi_hba); 2280 if (rc) 2281 return rc; 2282 2283 phys_init_v2_hw(hisi_hba); 2284 2285 return 0; 2286 } 2287 2288 static const struct hisi_sas_hw hisi_sas_v2_hw = { 2289 .hw_init = hisi_sas_v2_init, 2290 .setup_itct = setup_itct_v2_hw, 2291 .slot_index_alloc = slot_index_alloc_quirk_v2_hw, 2292 .alloc_dev = alloc_dev_quirk_v2_hw, 2293 .sl_notify = sl_notify_v2_hw, 2294 .get_wideport_bitmap = get_wideport_bitmap_v2_hw, 2295 .free_device = free_device_v2_hw, 2296 .prep_smp = prep_smp_v2_hw, 2297 .prep_ssp = prep_ssp_v2_hw, 2298 .prep_stp = prep_ata_v2_hw, 2299 .prep_abort = prep_abort_v2_hw, 2300 .get_free_slot = get_free_slot_v2_hw, 2301 .start_delivery = start_delivery_v2_hw, 2302 .slot_complete = slot_complete_v2_hw, 2303 .phy_enable = enable_phy_v2_hw, 2304 .phy_disable = disable_phy_v2_hw, 2305 .phy_hard_reset = phy_hard_reset_v2_hw, 2306 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V2_HW, 2307 .complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr), 2308 }; 2309 2310 static int hisi_sas_v2_probe(struct platform_device *pdev) 2311 { 2312 return hisi_sas_probe(pdev, &hisi_sas_v2_hw); 2313 } 2314 2315 static int hisi_sas_v2_remove(struct platform_device *pdev) 2316 { 2317 return hisi_sas_remove(pdev); 2318 } 2319 2320 static const struct of_device_id sas_v2_of_match[] = { 2321 { .compatible = "hisilicon,hip06-sas-v2",}, 2322 {}, 2323 }; 2324 MODULE_DEVICE_TABLE(of, sas_v2_of_match); 2325 2326 static const struct acpi_device_id sas_v2_acpi_match[] = { 2327 { "HISI0162", 0 }, 2328 { } 2329 }; 2330 2331 MODULE_DEVICE_TABLE(acpi, sas_v2_acpi_match); 2332 2333 static struct platform_driver hisi_sas_v2_driver = { 2334 .probe = hisi_sas_v2_probe, 2335 .remove = hisi_sas_v2_remove, 2336 .driver = { 2337 .name = DRV_NAME, 2338 .of_match_table = sas_v2_of_match, 2339 .acpi_match_table = ACPI_PTR(sas_v2_acpi_match), 2340 }, 2341 }; 2342 2343 module_platform_driver(hisi_sas_v2_driver); 2344 2345 MODULE_LICENSE("GPL"); 2346 MODULE_AUTHOR("John Garry <john.garry@huawei.com>"); 2347 MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver"); 2348 MODULE_ALIAS("platform:" DRV_NAME); 2349