1 /* 2 * Copyright (c) 2015 Linaro Ltd. 3 * Copyright (c) 2015 Hisilicon Limited. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 */ 11 12 #include "hisi_sas.h" 13 #define DRV_NAME "hisi_sas_v1_hw" 14 15 /* global registers need init*/ 16 #define DLVRY_QUEUE_ENABLE 0x0 17 #define IOST_BASE_ADDR_LO 0x8 18 #define IOST_BASE_ADDR_HI 0xc 19 #define ITCT_BASE_ADDR_LO 0x10 20 #define ITCT_BASE_ADDR_HI 0x14 21 #define BROKEN_MSG_ADDR_LO 0x18 22 #define BROKEN_MSG_ADDR_HI 0x1c 23 #define PHY_CONTEXT 0x20 24 #define PHY_STATE 0x24 25 #define PHY_PORT_NUM_MA 0x28 26 #define PORT_STATE 0x2c 27 #define PHY_CONN_RATE 0x30 28 #define HGC_TRANS_TASK_CNT_LIMIT 0x38 29 #define AXI_AHB_CLK_CFG 0x3c 30 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x84 31 #define HGC_GET_ITV_TIME 0x90 32 #define DEVICE_MSG_WORK_MODE 0x94 33 #define I_T_NEXUS_LOSS_TIME 0xa0 34 #define BUS_INACTIVE_LIMIT_TIME 0xa8 35 #define REJECT_TO_OPEN_LIMIT_TIME 0xac 36 #define CFG_AGING_TIME 0xbc 37 #define CFG_AGING_TIME_ITCT_REL_OFF 0 38 #define CFG_AGING_TIME_ITCT_REL_MSK (0x1 << CFG_AGING_TIME_ITCT_REL_OFF) 39 #define HGC_DFX_CFG2 0xc0 40 #define FIS_LIST_BADDR_L 0xc4 41 #define CFG_1US_TIMER_TRSH 0xcc 42 #define CFG_SAS_CONFIG 0xd4 43 #define HGC_IOST_ECC_ADDR 0x140 44 #define HGC_IOST_ECC_ADDR_BAD_OFF 16 45 #define HGC_IOST_ECC_ADDR_BAD_MSK (0x3ff << HGC_IOST_ECC_ADDR_BAD_OFF) 46 #define HGC_DQ_ECC_ADDR 0x144 47 #define HGC_DQ_ECC_ADDR_BAD_OFF 16 48 #define HGC_DQ_ECC_ADDR_BAD_MSK (0xfff << HGC_DQ_ECC_ADDR_BAD_OFF) 49 #define HGC_INVLD_DQE_INFO 0x148 50 #define HGC_INVLD_DQE_INFO_DQ_OFF 0 51 #define HGC_INVLD_DQE_INFO_DQ_MSK (0xffff << HGC_INVLD_DQE_INFO_DQ_OFF) 52 #define HGC_INVLD_DQE_INFO_TYPE_OFF 16 53 #define HGC_INVLD_DQE_INFO_TYPE_MSK (0x1 << HGC_INVLD_DQE_INFO_TYPE_OFF) 54 #define HGC_INVLD_DQE_INFO_FORCE_OFF 17 55 #define HGC_INVLD_DQE_INFO_FORCE_MSK (0x1 << HGC_INVLD_DQE_INFO_FORCE_OFF) 56 #define HGC_INVLD_DQE_INFO_PHY_OFF 18 57 #define HGC_INVLD_DQE_INFO_PHY_MSK (0x1 << HGC_INVLD_DQE_INFO_PHY_OFF) 58 #define HGC_INVLD_DQE_INFO_ABORT_OFF 19 59 #define HGC_INVLD_DQE_INFO_ABORT_MSK (0x1 << HGC_INVLD_DQE_INFO_ABORT_OFF) 60 #define HGC_INVLD_DQE_INFO_IPTT_OF_OFF 20 61 #define HGC_INVLD_DQE_INFO_IPTT_OF_MSK (0x1 << HGC_INVLD_DQE_INFO_IPTT_OF_OFF) 62 #define HGC_INVLD_DQE_INFO_SSP_ERR_OFF 21 63 #define HGC_INVLD_DQE_INFO_SSP_ERR_MSK (0x1 << HGC_INVLD_DQE_INFO_SSP_ERR_OFF) 64 #define HGC_INVLD_DQE_INFO_OFL_OFF 22 65 #define HGC_INVLD_DQE_INFO_OFL_MSK (0x1 << HGC_INVLD_DQE_INFO_OFL_OFF) 66 #define HGC_ITCT_ECC_ADDR 0x150 67 #define HGC_ITCT_ECC_ADDR_BAD_OFF 16 68 #define HGC_ITCT_ECC_ADDR_BAD_MSK (0x3ff << HGC_ITCT_ECC_ADDR_BAD_OFF) 69 #define HGC_AXI_FIFO_ERR_INFO 0x154 70 #define INT_COAL_EN 0x1bc 71 #define OQ_INT_COAL_TIME 0x1c0 72 #define OQ_INT_COAL_CNT 0x1c4 73 #define ENT_INT_COAL_TIME 0x1c8 74 #define ENT_INT_COAL_CNT 0x1cc 75 #define OQ_INT_SRC 0x1d0 76 #define OQ_INT_SRC_MSK 0x1d4 77 #define ENT_INT_SRC1 0x1d8 78 #define ENT_INT_SRC2 0x1dc 79 #define ENT_INT_SRC2_DQ_CFG_ERR_OFF 25 80 #define ENT_INT_SRC2_DQ_CFG_ERR_MSK (0x1 << ENT_INT_SRC2_DQ_CFG_ERR_OFF) 81 #define ENT_INT_SRC2_CQ_CFG_ERR_OFF 27 82 #define ENT_INT_SRC2_CQ_CFG_ERR_MSK (0x1 << ENT_INT_SRC2_CQ_CFG_ERR_OFF) 83 #define ENT_INT_SRC2_AXI_WRONG_INT_OFF 28 84 #define ENT_INT_SRC2_AXI_WRONG_INT_MSK (0x1 << ENT_INT_SRC2_AXI_WRONG_INT_OFF) 85 #define ENT_INT_SRC2_AXI_OVERLF_INT_OFF 29 86 #define ENT_INT_SRC2_AXI_OVERLF_INT_MSK (0x1 << ENT_INT_SRC2_AXI_OVERLF_INT_OFF) 87 #define ENT_INT_SRC_MSK1 0x1e0 88 #define ENT_INT_SRC_MSK2 0x1e4 89 #define SAS_ECC_INTR 0x1e8 90 #define SAS_ECC_INTR_DQ_ECC1B_OFF 0 91 #define SAS_ECC_INTR_DQ_ECC1B_MSK (0x1 << SAS_ECC_INTR_DQ_ECC1B_OFF) 92 #define SAS_ECC_INTR_DQ_ECCBAD_OFF 1 93 #define SAS_ECC_INTR_DQ_ECCBAD_MSK (0x1 << SAS_ECC_INTR_DQ_ECCBAD_OFF) 94 #define SAS_ECC_INTR_IOST_ECC1B_OFF 2 95 #define SAS_ECC_INTR_IOST_ECC1B_MSK (0x1 << SAS_ECC_INTR_IOST_ECC1B_OFF) 96 #define SAS_ECC_INTR_IOST_ECCBAD_OFF 3 97 #define SAS_ECC_INTR_IOST_ECCBAD_MSK (0x1 << SAS_ECC_INTR_IOST_ECCBAD_OFF) 98 #define SAS_ECC_INTR_ITCT_ECC1B_OFF 4 99 #define SAS_ECC_INTR_ITCT_ECC1B_MSK (0x1 << SAS_ECC_INTR_ITCT_ECC1B_OFF) 100 #define SAS_ECC_INTR_ITCT_ECCBAD_OFF 5 101 #define SAS_ECC_INTR_ITCT_ECCBAD_MSK (0x1 << SAS_ECC_INTR_ITCT_ECCBAD_OFF) 102 #define SAS_ECC_INTR_MSK 0x1ec 103 #define HGC_ERR_STAT_EN 0x238 104 #define DLVRY_Q_0_BASE_ADDR_LO 0x260 105 #define DLVRY_Q_0_BASE_ADDR_HI 0x264 106 #define DLVRY_Q_0_DEPTH 0x268 107 #define DLVRY_Q_0_WR_PTR 0x26c 108 #define DLVRY_Q_0_RD_PTR 0x270 109 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0 110 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4 111 #define COMPL_Q_0_DEPTH 0x4e8 112 #define COMPL_Q_0_WR_PTR 0x4ec 113 #define COMPL_Q_0_RD_PTR 0x4f0 114 #define HGC_ECC_ERR 0x7d0 115 116 /* phy registers need init */ 117 #define PORT_BASE (0x800) 118 119 #define PHY_CFG (PORT_BASE + 0x0) 120 #define PHY_CFG_ENA_OFF 0 121 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF) 122 #define PHY_CFG_DC_OPT_OFF 2 123 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF) 124 #define PROG_PHY_LINK_RATE (PORT_BASE + 0xc) 125 #define PROG_PHY_LINK_RATE_MAX_OFF 0 126 #define PROG_PHY_LINK_RATE_MAX_MSK (0xf << PROG_PHY_LINK_RATE_MAX_OFF) 127 #define PROG_PHY_LINK_RATE_MIN_OFF 4 128 #define PROG_PHY_LINK_RATE_MIN_MSK (0xf << PROG_PHY_LINK_RATE_MIN_OFF) 129 #define PROG_PHY_LINK_RATE_OOB_OFF 8 130 #define PROG_PHY_LINK_RATE_OOB_MSK (0xf << PROG_PHY_LINK_RATE_OOB_OFF) 131 #define PHY_CTRL (PORT_BASE + 0x14) 132 #define PHY_CTRL_RESET_OFF 0 133 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF) 134 #define PHY_RATE_NEGO (PORT_BASE + 0x30) 135 #define PHY_PCN (PORT_BASE + 0x44) 136 #define SL_TOUT_CFG (PORT_BASE + 0x8c) 137 #define SL_CONTROL (PORT_BASE + 0x94) 138 #define SL_CONTROL_NOTIFY_EN_OFF 0 139 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF) 140 #define TX_ID_DWORD0 (PORT_BASE + 0x9c) 141 #define TX_ID_DWORD1 (PORT_BASE + 0xa0) 142 #define TX_ID_DWORD2 (PORT_BASE + 0xa4) 143 #define TX_ID_DWORD3 (PORT_BASE + 0xa8) 144 #define TX_ID_DWORD4 (PORT_BASE + 0xaC) 145 #define TX_ID_DWORD5 (PORT_BASE + 0xb0) 146 #define TX_ID_DWORD6 (PORT_BASE + 0xb4) 147 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4) 148 #define RX_IDAF_DWORD1 (PORT_BASE + 0xc8) 149 #define RX_IDAF_DWORD2 (PORT_BASE + 0xcc) 150 #define RX_IDAF_DWORD3 (PORT_BASE + 0xd0) 151 #define RX_IDAF_DWORD4 (PORT_BASE + 0xd4) 152 #define RX_IDAF_DWORD5 (PORT_BASE + 0xd8) 153 #define RX_IDAF_DWORD6 (PORT_BASE + 0xdc) 154 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) 155 #define DONE_RECEIVED_TIME (PORT_BASE + 0x12c) 156 #define CON_CFG_DRIVER (PORT_BASE + 0x130) 157 #define PHY_CONFIG2 (PORT_BASE + 0x1a8) 158 #define PHY_CONFIG2_FORCE_TXDEEMPH_OFF 3 159 #define PHY_CONFIG2_FORCE_TXDEEMPH_MSK (0x1 << PHY_CONFIG2_FORCE_TXDEEMPH_OFF) 160 #define PHY_CONFIG2_TX_TRAIN_COMP_OFF 24 161 #define PHY_CONFIG2_TX_TRAIN_COMP_MSK (0x1 << PHY_CONFIG2_TX_TRAIN_COMP_OFF) 162 #define CHL_INT0 (PORT_BASE + 0x1b0) 163 #define CHL_INT0_PHYCTRL_NOTRDY_OFF 0 164 #define CHL_INT0_PHYCTRL_NOTRDY_MSK (0x1 << CHL_INT0_PHYCTRL_NOTRDY_OFF) 165 #define CHL_INT0_SN_FAIL_NGR_OFF 2 166 #define CHL_INT0_SN_FAIL_NGR_MSK (0x1 << CHL_INT0_SN_FAIL_NGR_OFF) 167 #define CHL_INT0_DWS_LOST_OFF 4 168 #define CHL_INT0_DWS_LOST_MSK (0x1 << CHL_INT0_DWS_LOST_OFF) 169 #define CHL_INT0_SL_IDAF_FAIL_OFF 10 170 #define CHL_INT0_SL_IDAF_FAIL_MSK (0x1 << CHL_INT0_SL_IDAF_FAIL_OFF) 171 #define CHL_INT0_ID_TIMEOUT_OFF 11 172 #define CHL_INT0_ID_TIMEOUT_MSK (0x1 << CHL_INT0_ID_TIMEOUT_OFF) 173 #define CHL_INT0_SL_OPAF_FAIL_OFF 12 174 #define CHL_INT0_SL_OPAF_FAIL_MSK (0x1 << CHL_INT0_SL_OPAF_FAIL_OFF) 175 #define CHL_INT0_SL_PS_FAIL_OFF 21 176 #define CHL_INT0_SL_PS_FAIL_MSK (0x1 << CHL_INT0_SL_PS_FAIL_OFF) 177 #define CHL_INT1 (PORT_BASE + 0x1b4) 178 #define CHL_INT2 (PORT_BASE + 0x1b8) 179 #define CHL_INT2_SL_RX_BC_ACK_OFF 2 180 #define CHL_INT2_SL_RX_BC_ACK_MSK (0x1 << CHL_INT2_SL_RX_BC_ACK_OFF) 181 #define CHL_INT2_SL_PHY_ENA_OFF 6 182 #define CHL_INT2_SL_PHY_ENA_MSK (0x1 << CHL_INT2_SL_PHY_ENA_OFF) 183 #define CHL_INT0_MSK (PORT_BASE + 0x1bc) 184 #define CHL_INT0_MSK_PHYCTRL_NOTRDY_OFF 0 185 #define CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK (0x1 << CHL_INT0_MSK_PHYCTRL_NOTRDY_OFF) 186 #define CHL_INT1_MSK (PORT_BASE + 0x1c0) 187 #define CHL_INT2_MSK (PORT_BASE + 0x1c4) 188 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0) 189 #define DMA_TX_STATUS (PORT_BASE + 0x2d0) 190 #define DMA_TX_STATUS_BUSY_OFF 0 191 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF) 192 #define DMA_RX_STATUS (PORT_BASE + 0x2e8) 193 #define DMA_RX_STATUS_BUSY_OFF 0 194 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF) 195 196 #define AXI_CFG 0x5100 197 #define RESET_VALUE 0x7ffff 198 199 /* HW dma structures */ 200 /* Delivery queue header */ 201 /* dw0 */ 202 #define CMD_HDR_RESP_REPORT_OFF 5 203 #define CMD_HDR_RESP_REPORT_MSK 0x20 204 #define CMD_HDR_TLR_CTRL_OFF 6 205 #define CMD_HDR_TLR_CTRL_MSK 0xc0 206 #define CMD_HDR_PORT_OFF 17 207 #define CMD_HDR_PORT_MSK 0xe0000 208 #define CMD_HDR_PRIORITY_OFF 27 209 #define CMD_HDR_PRIORITY_MSK 0x8000000 210 #define CMD_HDR_MODE_OFF 28 211 #define CMD_HDR_MODE_MSK 0x10000000 212 #define CMD_HDR_CMD_OFF 29 213 #define CMD_HDR_CMD_MSK 0xe0000000 214 /* dw1 */ 215 #define CMD_HDR_VERIFY_DTL_OFF 10 216 #define CMD_HDR_VERIFY_DTL_MSK 0x400 217 #define CMD_HDR_SSP_FRAME_TYPE_OFF 13 218 #define CMD_HDR_SSP_FRAME_TYPE_MSK 0xe000 219 #define CMD_HDR_DEVICE_ID_OFF 16 220 #define CMD_HDR_DEVICE_ID_MSK 0xffff0000 221 /* dw2 */ 222 #define CMD_HDR_CFL_OFF 0 223 #define CMD_HDR_CFL_MSK 0x1ff 224 #define CMD_HDR_MRFL_OFF 15 225 #define CMD_HDR_MRFL_MSK 0xff8000 226 #define CMD_HDR_FIRST_BURST_OFF 25 227 #define CMD_HDR_FIRST_BURST_MSK 0x2000000 228 /* dw3 */ 229 #define CMD_HDR_IPTT_OFF 0 230 #define CMD_HDR_IPTT_MSK 0xffff 231 /* dw6 */ 232 #define CMD_HDR_DATA_SGL_LEN_OFF 16 233 #define CMD_HDR_DATA_SGL_LEN_MSK 0xffff0000 234 235 /* Completion header */ 236 #define CMPLT_HDR_IPTT_OFF 0 237 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF) 238 #define CMPLT_HDR_CMD_CMPLT_OFF 17 239 #define CMPLT_HDR_CMD_CMPLT_MSK (0x1 << CMPLT_HDR_CMD_CMPLT_OFF) 240 #define CMPLT_HDR_ERR_RCRD_XFRD_OFF 18 241 #define CMPLT_HDR_ERR_RCRD_XFRD_MSK (0x1 << CMPLT_HDR_ERR_RCRD_XFRD_OFF) 242 #define CMPLT_HDR_RSPNS_XFRD_OFF 19 243 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF) 244 #define CMPLT_HDR_IO_CFG_ERR_OFF 27 245 #define CMPLT_HDR_IO_CFG_ERR_MSK (0x1 << CMPLT_HDR_IO_CFG_ERR_OFF) 246 247 /* ITCT header */ 248 /* qw0 */ 249 #define ITCT_HDR_DEV_TYPE_OFF 0 250 #define ITCT_HDR_DEV_TYPE_MSK (0x3ULL << ITCT_HDR_DEV_TYPE_OFF) 251 #define ITCT_HDR_VALID_OFF 2 252 #define ITCT_HDR_VALID_MSK (0x1ULL << ITCT_HDR_VALID_OFF) 253 #define ITCT_HDR_AWT_CONTROL_OFF 4 254 #define ITCT_HDR_AWT_CONTROL_MSK (0x1ULL << ITCT_HDR_AWT_CONTROL_OFF) 255 #define ITCT_HDR_MAX_CONN_RATE_OFF 5 256 #define ITCT_HDR_MAX_CONN_RATE_MSK (0xfULL << ITCT_HDR_MAX_CONN_RATE_OFF) 257 #define ITCT_HDR_VALID_LINK_NUM_OFF 9 258 #define ITCT_HDR_VALID_LINK_NUM_MSK (0xfULL << ITCT_HDR_VALID_LINK_NUM_OFF) 259 #define ITCT_HDR_PORT_ID_OFF 13 260 #define ITCT_HDR_PORT_ID_MSK (0x7ULL << ITCT_HDR_PORT_ID_OFF) 261 #define ITCT_HDR_SMP_TIMEOUT_OFF 16 262 #define ITCT_HDR_SMP_TIMEOUT_MSK (0xffffULL << ITCT_HDR_SMP_TIMEOUT_OFF) 263 /* qw1 */ 264 #define ITCT_HDR_MAX_SAS_ADDR_OFF 0 265 #define ITCT_HDR_MAX_SAS_ADDR_MSK (0xffffffffffffffff << \ 266 ITCT_HDR_MAX_SAS_ADDR_OFF) 267 /* qw2 */ 268 #define ITCT_HDR_IT_NEXUS_LOSS_TL_OFF 0 269 #define ITCT_HDR_IT_NEXUS_LOSS_TL_MSK (0xffffULL << \ 270 ITCT_HDR_IT_NEXUS_LOSS_TL_OFF) 271 #define ITCT_HDR_BUS_INACTIVE_TL_OFF 16 272 #define ITCT_HDR_BUS_INACTIVE_TL_MSK (0xffffULL << \ 273 ITCT_HDR_BUS_INACTIVE_TL_OFF) 274 #define ITCT_HDR_MAX_CONN_TL_OFF 32 275 #define ITCT_HDR_MAX_CONN_TL_MSK (0xffffULL << \ 276 ITCT_HDR_MAX_CONN_TL_OFF) 277 #define ITCT_HDR_REJ_OPEN_TL_OFF 48 278 #define ITCT_HDR_REJ_OPEN_TL_MSK (0xffffULL << \ 279 ITCT_HDR_REJ_OPEN_TL_OFF) 280 281 /* Err record header */ 282 #define ERR_HDR_DMA_TX_ERR_TYPE_OFF 0 283 #define ERR_HDR_DMA_TX_ERR_TYPE_MSK (0xffff << ERR_HDR_DMA_TX_ERR_TYPE_OFF) 284 #define ERR_HDR_DMA_RX_ERR_TYPE_OFF 16 285 #define ERR_HDR_DMA_RX_ERR_TYPE_MSK (0xffff << ERR_HDR_DMA_RX_ERR_TYPE_OFF) 286 287 struct hisi_sas_complete_v1_hdr { 288 __le32 data; 289 }; 290 291 struct hisi_sas_err_record_v1 { 292 /* dw0 */ 293 __le32 dma_err_type; 294 295 /* dw1 */ 296 __le32 trans_tx_fail_type; 297 298 /* dw2 */ 299 __le32 trans_rx_fail_type; 300 301 /* dw3 */ 302 u32 rsvd; 303 }; 304 305 enum { 306 HISI_SAS_PHY_BCAST_ACK = 0, 307 HISI_SAS_PHY_SL_PHY_ENABLED, 308 HISI_SAS_PHY_INT_ABNORMAL, 309 HISI_SAS_PHY_INT_NR 310 }; 311 312 enum { 313 DMA_TX_ERR_BASE = 0x0, 314 DMA_RX_ERR_BASE = 0x100, 315 TRANS_TX_FAIL_BASE = 0x200, 316 TRANS_RX_FAIL_BASE = 0x300, 317 318 /* dma tx */ 319 DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x0 */ 320 DMA_TX_DIF_APP_ERR, /* 0x1 */ 321 DMA_TX_DIF_RPP_ERR, /* 0x2 */ 322 DMA_TX_AXI_BUS_ERR, /* 0x3 */ 323 DMA_TX_DATA_SGL_OVERFLOW_ERR, /* 0x4 */ 324 DMA_TX_DIF_SGL_OVERFLOW_ERR, /* 0x5 */ 325 DMA_TX_UNEXP_XFER_RDY_ERR, /* 0x6 */ 326 DMA_TX_XFER_RDY_OFFSET_ERR, /* 0x7 */ 327 DMA_TX_DATA_UNDERFLOW_ERR, /* 0x8 */ 328 DMA_TX_XFER_RDY_LENGTH_OVERFLOW_ERR, /* 0x9 */ 329 330 /* dma rx */ 331 DMA_RX_BUFFER_ECC_ERR = DMA_RX_ERR_BASE, /* 0x100 */ 332 DMA_RX_DIF_CRC_ERR, /* 0x101 */ 333 DMA_RX_DIF_APP_ERR, /* 0x102 */ 334 DMA_RX_DIF_RPP_ERR, /* 0x103 */ 335 DMA_RX_RESP_BUFFER_OVERFLOW_ERR, /* 0x104 */ 336 DMA_RX_AXI_BUS_ERR, /* 0x105 */ 337 DMA_RX_DATA_SGL_OVERFLOW_ERR, /* 0x106 */ 338 DMA_RX_DIF_SGL_OVERFLOW_ERR, /* 0x107 */ 339 DMA_RX_DATA_OFFSET_ERR, /* 0x108 */ 340 DMA_RX_UNEXP_RX_DATA_ERR, /* 0x109 */ 341 DMA_RX_DATA_OVERFLOW_ERR, /* 0x10a */ 342 DMA_RX_DATA_UNDERFLOW_ERR, /* 0x10b */ 343 DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x10c */ 344 345 /* trans tx */ 346 TRANS_TX_RSVD0_ERR = TRANS_TX_FAIL_BASE, /* 0x200 */ 347 TRANS_TX_PHY_NOT_ENABLE_ERR, /* 0x201 */ 348 TRANS_TX_OPEN_REJCT_WRONG_DEST_ERR, /* 0x202 */ 349 TRANS_TX_OPEN_REJCT_ZONE_VIOLATION_ERR, /* 0x203 */ 350 TRANS_TX_OPEN_REJCT_BY_OTHER_ERR, /* 0x204 */ 351 TRANS_TX_RSVD1_ERR, /* 0x205 */ 352 TRANS_TX_OPEN_REJCT_AIP_TIMEOUT_ERR, /* 0x206 */ 353 TRANS_TX_OPEN_REJCT_STP_BUSY_ERR, /* 0x207 */ 354 TRANS_TX_OPEN_REJCT_PROTOCOL_NOT_SUPPORT_ERR, /* 0x208 */ 355 TRANS_TX_OPEN_REJCT_RATE_NOT_SUPPORT_ERR, /* 0x209 */ 356 TRANS_TX_OPEN_REJCT_BAD_DEST_ERR, /* 0x20a */ 357 TRANS_TX_OPEN_BREAK_RECEIVE_ERR, /* 0x20b */ 358 TRANS_TX_LOW_PHY_POWER_ERR, /* 0x20c */ 359 TRANS_TX_OPEN_REJCT_PATHWAY_BLOCKED_ERR, /* 0x20d */ 360 TRANS_TX_OPEN_TIMEOUT_ERR, /* 0x20e */ 361 TRANS_TX_OPEN_REJCT_NO_DEST_ERR, /* 0x20f */ 362 TRANS_TX_OPEN_RETRY_ERR, /* 0x210 */ 363 TRANS_TX_RSVD2_ERR, /* 0x211 */ 364 TRANS_TX_BREAK_TIMEOUT_ERR, /* 0x212 */ 365 TRANS_TX_BREAK_REQUEST_ERR, /* 0x213 */ 366 TRANS_TX_BREAK_RECEIVE_ERR, /* 0x214 */ 367 TRANS_TX_CLOSE_TIMEOUT_ERR, /* 0x215 */ 368 TRANS_TX_CLOSE_NORMAL_ERR, /* 0x216 */ 369 TRANS_TX_CLOSE_PHYRESET_ERR, /* 0x217 */ 370 TRANS_TX_WITH_CLOSE_DWS_TIMEOUT_ERR, /* 0x218 */ 371 TRANS_TX_WITH_CLOSE_COMINIT_ERR, /* 0x219 */ 372 TRANS_TX_NAK_RECEIVE_ERR, /* 0x21a */ 373 TRANS_TX_ACK_NAK_TIMEOUT_ERR, /* 0x21b */ 374 TRANS_TX_CREDIT_TIMEOUT_ERR, /* 0x21c */ 375 TRANS_TX_IPTT_CONFLICT_ERR, /* 0x21d */ 376 TRANS_TX_TXFRM_TYPE_ERR, /* 0x21e */ 377 TRANS_TX_TXSMP_LENGTH_ERR, /* 0x21f */ 378 379 /* trans rx */ 380 TRANS_RX_FRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x300 */ 381 TRANS_RX_FRAME_DONE_ERR, /* 0x301 */ 382 TRANS_RX_FRAME_ERRPRM_ERR, /* 0x302 */ 383 TRANS_RX_FRAME_NO_CREDIT_ERR, /* 0x303 */ 384 TRANS_RX_RSVD0_ERR, /* 0x304 */ 385 TRANS_RX_FRAME_OVERRUN_ERR, /* 0x305 */ 386 TRANS_RX_FRAME_NO_EOF_ERR, /* 0x306 */ 387 TRANS_RX_LINK_BUF_OVERRUN_ERR, /* 0x307 */ 388 TRANS_RX_BREAK_TIMEOUT_ERR, /* 0x308 */ 389 TRANS_RX_BREAK_REQUEST_ERR, /* 0x309 */ 390 TRANS_RX_BREAK_RECEIVE_ERR, /* 0x30a */ 391 TRANS_RX_CLOSE_TIMEOUT_ERR, /* 0x30b */ 392 TRANS_RX_CLOSE_NORMAL_ERR, /* 0x30c */ 393 TRANS_RX_CLOSE_PHYRESET_ERR, /* 0x30d */ 394 TRANS_RX_WITH_CLOSE_DWS_TIMEOUT_ERR, /* 0x30e */ 395 TRANS_RX_WITH_CLOSE_COMINIT_ERR, /* 0x30f */ 396 TRANS_RX_DATA_LENGTH0_ERR, /* 0x310 */ 397 TRANS_RX_BAD_HASH_ERR, /* 0x311 */ 398 TRANS_RX_XRDY_ZERO_ERR, /* 0x312 */ 399 TRANS_RX_SSP_FRAME_LEN_ERR, /* 0x313 */ 400 TRANS_RX_TRANS_RX_RSVD1_ERR, /* 0x314 */ 401 TRANS_RX_NO_BALANCE_ERR, /* 0x315 */ 402 TRANS_RX_TRANS_RX_RSVD2_ERR, /* 0x316 */ 403 TRANS_RX_TRANS_RX_RSVD3_ERR, /* 0x317 */ 404 TRANS_RX_BAD_FRAME_TYPE_ERR, /* 0x318 */ 405 TRANS_RX_SMP_FRAME_LEN_ERR, /* 0x319 */ 406 TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x31a */ 407 }; 408 409 #define HISI_SAS_COMMAND_ENTRIES_V1_HW 8192 410 411 #define HISI_SAS_PHY_MAX_INT_NR (HISI_SAS_PHY_INT_NR * HISI_SAS_MAX_PHYS) 412 #define HISI_SAS_CQ_MAX_INT_NR (HISI_SAS_MAX_QUEUES) 413 #define HISI_SAS_FATAL_INT_NR (2) 414 415 #define HISI_SAS_MAX_INT_NR \ 416 (HISI_SAS_PHY_MAX_INT_NR + HISI_SAS_CQ_MAX_INT_NR +\ 417 HISI_SAS_FATAL_INT_NR) 418 419 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) 420 { 421 void __iomem *regs = hisi_hba->regs + off; 422 423 return readl(regs); 424 } 425 426 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off) 427 { 428 void __iomem *regs = hisi_hba->regs + off; 429 430 return readl_relaxed(regs); 431 } 432 433 static void hisi_sas_write32(struct hisi_hba *hisi_hba, 434 u32 off, u32 val) 435 { 436 void __iomem *regs = hisi_hba->regs + off; 437 438 writel(val, regs); 439 } 440 441 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, 442 int phy_no, u32 off, u32 val) 443 { 444 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 445 446 writel(val, regs); 447 } 448 449 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba, 450 int phy_no, u32 off) 451 { 452 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 453 454 return readl(regs); 455 } 456 457 static void config_phy_opt_mode_v1_hw(struct hisi_hba *hisi_hba, int phy_no) 458 { 459 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 460 461 cfg &= ~PHY_CFG_DC_OPT_MSK; 462 cfg |= 1 << PHY_CFG_DC_OPT_OFF; 463 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 464 } 465 466 static void config_tx_tfe_autoneg_v1_hw(struct hisi_hba *hisi_hba, int phy_no) 467 { 468 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CONFIG2); 469 470 cfg &= ~PHY_CONFIG2_FORCE_TXDEEMPH_MSK; 471 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CONFIG2, cfg); 472 } 473 474 static void config_id_frame_v1_hw(struct hisi_hba *hisi_hba, int phy_no) 475 { 476 struct sas_identify_frame identify_frame; 477 u32 *identify_buffer; 478 479 memset(&identify_frame, 0, sizeof(identify_frame)); 480 identify_frame.dev_type = SAS_END_DEVICE; 481 identify_frame.frame_type = 0; 482 identify_frame._un1 = 1; 483 identify_frame.initiator_bits = SAS_PROTOCOL_ALL; 484 identify_frame.target_bits = SAS_PROTOCOL_NONE; 485 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 486 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 487 identify_frame.phy_id = phy_no; 488 identify_buffer = (u32 *)(&identify_frame); 489 490 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0, 491 __swab32(identify_buffer[0])); 492 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1, 493 __swab32(identify_buffer[1])); 494 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2, 495 __swab32(identify_buffer[2])); 496 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3, 497 __swab32(identify_buffer[3])); 498 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4, 499 __swab32(identify_buffer[4])); 500 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5, 501 __swab32(identify_buffer[5])); 502 } 503 504 static void setup_itct_v1_hw(struct hisi_hba *hisi_hba, 505 struct hisi_sas_device *sas_dev) 506 { 507 struct domain_device *device = sas_dev->sas_device; 508 struct device *dev = hisi_hba->dev; 509 u64 qw0, device_id = sas_dev->device_id; 510 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id]; 511 struct asd_sas_port *sas_port = device->port; 512 struct hisi_sas_port *port = to_hisi_sas_port(sas_port); 513 u64 sas_addr; 514 515 memset(itct, 0, sizeof(*itct)); 516 517 /* qw0 */ 518 qw0 = 0; 519 switch (sas_dev->dev_type) { 520 case SAS_END_DEVICE: 521 case SAS_EDGE_EXPANDER_DEVICE: 522 case SAS_FANOUT_EXPANDER_DEVICE: 523 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF; 524 break; 525 default: 526 dev_warn(dev, "setup itct: unsupported dev type (%d)\n", 527 sas_dev->dev_type); 528 } 529 530 qw0 |= ((1 << ITCT_HDR_VALID_OFF) | 531 (1 << ITCT_HDR_AWT_CONTROL_OFF) | 532 (device->max_linkrate << ITCT_HDR_MAX_CONN_RATE_OFF) | 533 (1 << ITCT_HDR_VALID_LINK_NUM_OFF) | 534 (port->id << ITCT_HDR_PORT_ID_OFF)); 535 itct->qw0 = cpu_to_le64(qw0); 536 537 /* qw1 */ 538 memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE); 539 itct->sas_addr = cpu_to_le64(__swab64(sas_addr)); 540 541 /* qw2 */ 542 itct->qw2 = cpu_to_le64((500ULL << ITCT_HDR_IT_NEXUS_LOSS_TL_OFF) | 543 (0xff00ULL << ITCT_HDR_BUS_INACTIVE_TL_OFF) | 544 (0xff00ULL << ITCT_HDR_MAX_CONN_TL_OFF) | 545 (0xff00ULL << ITCT_HDR_REJ_OPEN_TL_OFF)); 546 } 547 548 static void clear_itct_v1_hw(struct hisi_hba *hisi_hba, 549 struct hisi_sas_device *sas_dev) 550 { 551 u64 dev_id = sas_dev->device_id; 552 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id]; 553 u64 qw0; 554 u32 reg_val = hisi_sas_read32(hisi_hba, CFG_AGING_TIME); 555 556 reg_val |= CFG_AGING_TIME_ITCT_REL_MSK; 557 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, reg_val); 558 559 /* free itct */ 560 udelay(1); 561 reg_val = hisi_sas_read32(hisi_hba, CFG_AGING_TIME); 562 reg_val &= ~CFG_AGING_TIME_ITCT_REL_MSK; 563 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, reg_val); 564 565 qw0 = le64_to_cpu(itct->qw0); 566 qw0 &= ~ITCT_HDR_VALID_MSK; 567 itct->qw0 = cpu_to_le64(qw0); 568 } 569 570 static int reset_hw_v1_hw(struct hisi_hba *hisi_hba) 571 { 572 int i; 573 unsigned long end_time; 574 u32 val; 575 struct device *dev = hisi_hba->dev; 576 577 for (i = 0; i < hisi_hba->n_phy; i++) { 578 u32 phy_ctrl = hisi_sas_phy_read32(hisi_hba, i, PHY_CTRL); 579 580 phy_ctrl |= PHY_CTRL_RESET_MSK; 581 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, phy_ctrl); 582 } 583 msleep(1); /* It is safe to wait for 50us */ 584 585 /* Ensure DMA tx & rx idle */ 586 for (i = 0; i < hisi_hba->n_phy; i++) { 587 u32 dma_tx_status, dma_rx_status; 588 589 end_time = jiffies + msecs_to_jiffies(1000); 590 591 while (1) { 592 dma_tx_status = hisi_sas_phy_read32(hisi_hba, i, 593 DMA_TX_STATUS); 594 dma_rx_status = hisi_sas_phy_read32(hisi_hba, i, 595 DMA_RX_STATUS); 596 597 if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) && 598 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK)) 599 break; 600 601 msleep(20); 602 if (time_after(jiffies, end_time)) 603 return -EIO; 604 } 605 } 606 607 /* Ensure axi bus idle */ 608 end_time = jiffies + msecs_to_jiffies(1000); 609 while (1) { 610 u32 axi_status = 611 hisi_sas_read32(hisi_hba, AXI_CFG); 612 613 if (axi_status == 0) 614 break; 615 616 msleep(20); 617 if (time_after(jiffies, end_time)) 618 return -EIO; 619 } 620 621 if (ACPI_HANDLE(dev)) { 622 acpi_status s; 623 624 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL); 625 if (ACPI_FAILURE(s)) { 626 dev_err(dev, "Reset failed\n"); 627 return -EIO; 628 } 629 } else if (hisi_hba->ctrl) { 630 /* Apply reset and disable clock */ 631 /* clk disable reg is offset by +4 bytes from clk enable reg */ 632 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg, 633 RESET_VALUE); 634 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4, 635 RESET_VALUE); 636 msleep(1); 637 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val); 638 if (RESET_VALUE != (val & RESET_VALUE)) { 639 dev_err(dev, "Reset failed\n"); 640 return -EIO; 641 } 642 643 /* De-reset and enable clock */ 644 /* deassert rst reg is offset by +4 bytes from assert reg */ 645 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4, 646 RESET_VALUE); 647 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg, 648 RESET_VALUE); 649 msleep(1); 650 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val); 651 if (val & RESET_VALUE) { 652 dev_err(dev, "De-reset failed\n"); 653 return -EIO; 654 } 655 } else { 656 dev_warn(dev, "no reset method\n"); 657 return -EINVAL; 658 } 659 660 return 0; 661 } 662 663 static void init_reg_v1_hw(struct hisi_hba *hisi_hba) 664 { 665 int i; 666 667 /* Global registers init*/ 668 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 669 (u32)((1ULL << hisi_hba->queue_count) - 1)); 670 hisi_sas_write32(hisi_hba, HGC_TRANS_TASK_CNT_LIMIT, 0x11); 671 hisi_sas_write32(hisi_hba, DEVICE_MSG_WORK_MODE, 0x1); 672 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x1ff); 673 hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x401); 674 hisi_sas_write32(hisi_hba, CFG_1US_TIMER_TRSH, 0x64); 675 hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1); 676 hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x64); 677 hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x2710); 678 hisi_sas_write32(hisi_hba, REJECT_TO_OPEN_LIMIT_TIME, 0x1); 679 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x7a12); 680 hisi_sas_write32(hisi_hba, HGC_DFX_CFG2, 0x9c40); 681 hisi_sas_write32(hisi_hba, FIS_LIST_BADDR_L, 0x2); 682 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0xc); 683 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x186a0); 684 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 1); 685 hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1); 686 hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1); 687 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffffffff); 688 hisi_sas_write32(hisi_hba, OQ_INT_SRC_MSK, 0); 689 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff); 690 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0); 691 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff); 692 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0); 693 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0); 694 hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 0x2); 695 hisi_sas_write32(hisi_hba, CFG_SAS_CONFIG, 0x22000000); 696 697 for (i = 0; i < hisi_hba->n_phy; i++) { 698 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x88a); 699 hisi_sas_phy_write32(hisi_hba, i, PHY_CONFIG2, 0x7c080); 700 hisi_sas_phy_write32(hisi_hba, i, PHY_RATE_NEGO, 0x415ee00); 701 hisi_sas_phy_write32(hisi_hba, i, PHY_PCN, 0x80a80000); 702 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d); 703 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x0); 704 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000); 705 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0); 706 hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x13f0a); 707 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 3); 708 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 8); 709 } 710 711 for (i = 0; i < hisi_hba->queue_count; i++) { 712 /* Delivery queue */ 713 hisi_sas_write32(hisi_hba, 714 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14), 715 upper_32_bits(hisi_hba->cmd_hdr_dma[i])); 716 717 hisi_sas_write32(hisi_hba, 718 DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14), 719 lower_32_bits(hisi_hba->cmd_hdr_dma[i])); 720 721 hisi_sas_write32(hisi_hba, 722 DLVRY_Q_0_DEPTH + (i * 0x14), 723 HISI_SAS_QUEUE_SLOTS); 724 725 /* Completion queue */ 726 hisi_sas_write32(hisi_hba, 727 COMPL_Q_0_BASE_ADDR_HI + (i * 0x14), 728 upper_32_bits(hisi_hba->complete_hdr_dma[i])); 729 730 hisi_sas_write32(hisi_hba, 731 COMPL_Q_0_BASE_ADDR_LO + (i * 0x14), 732 lower_32_bits(hisi_hba->complete_hdr_dma[i])); 733 734 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14), 735 HISI_SAS_QUEUE_SLOTS); 736 } 737 738 /* itct */ 739 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO, 740 lower_32_bits(hisi_hba->itct_dma)); 741 742 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI, 743 upper_32_bits(hisi_hba->itct_dma)); 744 745 /* iost */ 746 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO, 747 lower_32_bits(hisi_hba->iost_dma)); 748 749 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI, 750 upper_32_bits(hisi_hba->iost_dma)); 751 752 /* breakpoint */ 753 hisi_sas_write32(hisi_hba, BROKEN_MSG_ADDR_LO, 754 lower_32_bits(hisi_hba->breakpoint_dma)); 755 756 hisi_sas_write32(hisi_hba, BROKEN_MSG_ADDR_HI, 757 upper_32_bits(hisi_hba->breakpoint_dma)); 758 } 759 760 static int hw_init_v1_hw(struct hisi_hba *hisi_hba) 761 { 762 struct device *dev = hisi_hba->dev; 763 int rc; 764 765 rc = reset_hw_v1_hw(hisi_hba); 766 if (rc) { 767 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc); 768 return rc; 769 } 770 771 msleep(100); 772 init_reg_v1_hw(hisi_hba); 773 774 return 0; 775 } 776 777 static void enable_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no) 778 { 779 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 780 781 cfg |= PHY_CFG_ENA_MSK; 782 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 783 } 784 785 static void disable_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no) 786 { 787 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 788 789 cfg &= ~PHY_CFG_ENA_MSK; 790 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 791 } 792 793 static void start_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no) 794 { 795 config_id_frame_v1_hw(hisi_hba, phy_no); 796 config_phy_opt_mode_v1_hw(hisi_hba, phy_no); 797 config_tx_tfe_autoneg_v1_hw(hisi_hba, phy_no); 798 enable_phy_v1_hw(hisi_hba, phy_no); 799 } 800 801 static void phy_hard_reset_v1_hw(struct hisi_hba *hisi_hba, int phy_no) 802 { 803 hisi_sas_phy_enable(hisi_hba, phy_no, 0); 804 msleep(100); 805 hisi_sas_phy_enable(hisi_hba, phy_no, 1); 806 } 807 808 static void start_phys_v1_hw(struct timer_list *t) 809 { 810 struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer); 811 int i; 812 813 for (i = 0; i < hisi_hba->n_phy; i++) { 814 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x12a); 815 hisi_sas_phy_enable(hisi_hba, i, 1); 816 } 817 } 818 819 static void phys_init_v1_hw(struct hisi_hba *hisi_hba) 820 { 821 int i; 822 struct timer_list *timer = &hisi_hba->timer; 823 824 for (i = 0; i < hisi_hba->n_phy; i++) { 825 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x6a); 826 hisi_sas_phy_read32(hisi_hba, i, CHL_INT2_MSK); 827 } 828 829 timer_setup(timer, start_phys_v1_hw, 0); 830 mod_timer(timer, jiffies + HZ); 831 } 832 833 static void sl_notify_ssp_v1_hw(struct hisi_hba *hisi_hba, int phy_no) 834 { 835 u32 sl_control; 836 837 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 838 sl_control |= SL_CONTROL_NOTIFY_EN_MSK; 839 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 840 msleep(1); 841 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 842 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK; 843 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 844 } 845 846 static enum sas_linkrate phy_get_max_linkrate_v1_hw(void) 847 { 848 return SAS_LINK_RATE_6_0_GBPS; 849 } 850 851 static void phy_set_linkrate_v1_hw(struct hisi_hba *hisi_hba, int phy_no, 852 struct sas_phy_linkrates *r) 853 { 854 enum sas_linkrate max = r->maximum_linkrate; 855 u32 prog_phy_link_rate = 0x800; 856 857 prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max); 858 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, 859 prog_phy_link_rate); 860 } 861 862 static int get_wideport_bitmap_v1_hw(struct hisi_hba *hisi_hba, int port_id) 863 { 864 int i, bitmap = 0; 865 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 866 867 for (i = 0; i < hisi_hba->n_phy; i++) 868 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id) 869 bitmap |= 1 << i; 870 871 return bitmap; 872 } 873 874 /* 875 * The callpath to this function and upto writing the write 876 * queue pointer should be safe from interruption. 877 */ 878 static int 879 get_free_slot_v1_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq) 880 { 881 struct device *dev = hisi_hba->dev; 882 int queue = dq->id; 883 u32 r, w; 884 885 w = dq->wr_point; 886 r = hisi_sas_read32_relaxed(hisi_hba, 887 DLVRY_Q_0_RD_PTR + (queue * 0x14)); 888 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) { 889 dev_warn(dev, "could not find free slot\n"); 890 return -EAGAIN; 891 } 892 893 dq->wr_point = (dq->wr_point + 1) % HISI_SAS_QUEUE_SLOTS; 894 895 return w; 896 } 897 898 /* DQ lock must be taken here */ 899 static void start_delivery_v1_hw(struct hisi_sas_dq *dq) 900 { 901 struct hisi_hba *hisi_hba = dq->hisi_hba; 902 struct hisi_sas_slot *s, *s1, *s2 = NULL; 903 int dlvry_queue = dq->id; 904 int wp; 905 906 list_for_each_entry_safe(s, s1, &dq->list, delivery) { 907 if (!s->ready) 908 break; 909 s2 = s; 910 list_del(&s->delivery); 911 } 912 913 if (!s2) 914 return; 915 916 /* 917 * Ensure that memories for slots built on other CPUs is observed. 918 */ 919 smp_rmb(); 920 wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS; 921 922 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp); 923 } 924 925 static void prep_prd_sge_v1_hw(struct hisi_hba *hisi_hba, 926 struct hisi_sas_slot *slot, 927 struct hisi_sas_cmd_hdr *hdr, 928 struct scatterlist *scatter, 929 int n_elem) 930 { 931 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot); 932 struct scatterlist *sg; 933 int i; 934 935 for_each_sg(scatter, sg, n_elem, i) { 936 struct hisi_sas_sge *entry = &sge_page->sge[i]; 937 938 entry->addr = cpu_to_le64(sg_dma_address(sg)); 939 entry->page_ctrl_0 = entry->page_ctrl_1 = 0; 940 entry->data_len = cpu_to_le32(sg_dma_len(sg)); 941 entry->data_off = 0; 942 } 943 944 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot)); 945 946 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF); 947 } 948 949 static void prep_smp_v1_hw(struct hisi_hba *hisi_hba, 950 struct hisi_sas_slot *slot) 951 { 952 struct sas_task *task = slot->task; 953 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 954 struct domain_device *device = task->dev; 955 struct hisi_sas_port *port = slot->port; 956 struct scatterlist *sg_req; 957 struct hisi_sas_device *sas_dev = device->lldd_dev; 958 dma_addr_t req_dma_addr; 959 unsigned int req_len; 960 961 /* req */ 962 sg_req = &task->smp_task.smp_req; 963 req_len = sg_dma_len(sg_req); 964 req_dma_addr = sg_dma_address(sg_req); 965 966 /* create header */ 967 /* dw0 */ 968 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) | 969 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */ 970 (1 << CMD_HDR_MODE_OFF) | /* ini mode */ 971 (2 << CMD_HDR_CMD_OFF)); /* smp */ 972 973 /* map itct entry */ 974 hdr->dw1 = cpu_to_le32(sas_dev->device_id << CMD_HDR_DEVICE_ID_OFF); 975 976 /* dw2 */ 977 hdr->dw2 = cpu_to_le32((((req_len-4)/4) << CMD_HDR_CFL_OFF) | 978 (HISI_SAS_MAX_SMP_RESP_SZ/4 << 979 CMD_HDR_MRFL_OFF)); 980 981 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF); 982 983 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr); 984 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 985 } 986 987 static void prep_ssp_v1_hw(struct hisi_hba *hisi_hba, 988 struct hisi_sas_slot *slot) 989 { 990 struct sas_task *task = slot->task; 991 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 992 struct domain_device *device = task->dev; 993 struct hisi_sas_device *sas_dev = device->lldd_dev; 994 struct hisi_sas_port *port = slot->port; 995 struct sas_ssp_task *ssp_task = &task->ssp_task; 996 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd; 997 struct hisi_sas_tmf_task *tmf = slot->tmf; 998 int has_data = 0, priority = !!tmf; 999 u8 *buf_cmd, fburst = 0; 1000 u32 dw1, dw2; 1001 1002 /* create header */ 1003 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) | 1004 (0x2 << CMD_HDR_TLR_CTRL_OFF) | 1005 (port->id << CMD_HDR_PORT_OFF) | 1006 (priority << CMD_HDR_PRIORITY_OFF) | 1007 (1 << CMD_HDR_MODE_OFF) | /* ini mode */ 1008 (1 << CMD_HDR_CMD_OFF)); /* ssp */ 1009 1010 dw1 = 1 << CMD_HDR_VERIFY_DTL_OFF; 1011 1012 if (tmf) { 1013 dw1 |= 3 << CMD_HDR_SSP_FRAME_TYPE_OFF; 1014 } else { 1015 switch (scsi_cmnd->sc_data_direction) { 1016 case DMA_TO_DEVICE: 1017 dw1 |= 2 << CMD_HDR_SSP_FRAME_TYPE_OFF; 1018 has_data = 1; 1019 break; 1020 case DMA_FROM_DEVICE: 1021 dw1 |= 1 << CMD_HDR_SSP_FRAME_TYPE_OFF; 1022 has_data = 1; 1023 break; 1024 default: 1025 dw1 |= 0 << CMD_HDR_SSP_FRAME_TYPE_OFF; 1026 } 1027 } 1028 1029 /* map itct entry */ 1030 dw1 |= sas_dev->device_id << CMD_HDR_DEVICE_ID_OFF; 1031 hdr->dw1 = cpu_to_le32(dw1); 1032 1033 if (tmf) { 1034 dw2 = ((sizeof(struct ssp_tmf_iu) + 1035 sizeof(struct ssp_frame_hdr)+3)/4) << 1036 CMD_HDR_CFL_OFF; 1037 } else { 1038 dw2 = ((sizeof(struct ssp_command_iu) + 1039 sizeof(struct ssp_frame_hdr)+3)/4) << 1040 CMD_HDR_CFL_OFF; 1041 } 1042 1043 dw2 |= (HISI_SAS_MAX_SSP_RESP_SZ/4) << CMD_HDR_MRFL_OFF; 1044 1045 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF); 1046 1047 if (has_data) 1048 prep_prd_sge_v1_hw(hisi_hba, slot, hdr, task->scatter, 1049 slot->n_elem); 1050 1051 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); 1052 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); 1053 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1054 1055 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) + 1056 sizeof(struct ssp_frame_hdr); 1057 if (task->ssp_task.enable_first_burst) { 1058 fburst = (1 << 7); 1059 dw2 |= 1 << CMD_HDR_FIRST_BURST_OFF; 1060 } 1061 hdr->dw2 = cpu_to_le32(dw2); 1062 1063 memcpy(buf_cmd, &task->ssp_task.LUN, 8); 1064 if (!tmf) { 1065 buf_cmd[9] = fburst | task->ssp_task.task_attr | 1066 (task->ssp_task.task_prio << 3); 1067 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd, 1068 task->ssp_task.cmd->cmd_len); 1069 } else { 1070 buf_cmd[10] = tmf->tmf; 1071 switch (tmf->tmf) { 1072 case TMF_ABORT_TASK: 1073 case TMF_QUERY_TASK: 1074 buf_cmd[12] = 1075 (tmf->tag_of_task_to_be_managed >> 8) & 0xff; 1076 buf_cmd[13] = 1077 tmf->tag_of_task_to_be_managed & 0xff; 1078 break; 1079 default: 1080 break; 1081 } 1082 } 1083 } 1084 1085 /* by default, task resp is complete */ 1086 static void slot_err_v1_hw(struct hisi_hba *hisi_hba, 1087 struct sas_task *task, 1088 struct hisi_sas_slot *slot) 1089 { 1090 struct task_status_struct *ts = &task->task_status; 1091 struct hisi_sas_err_record_v1 *err_record = 1092 hisi_sas_status_buf_addr_mem(slot); 1093 struct device *dev = hisi_hba->dev; 1094 1095 switch (task->task_proto) { 1096 case SAS_PROTOCOL_SSP: 1097 { 1098 int error = -1; 1099 u32 dma_err_type = le32_to_cpu(err_record->dma_err_type); 1100 u32 dma_tx_err_type = ((dma_err_type & 1101 ERR_HDR_DMA_TX_ERR_TYPE_MSK)) >> 1102 ERR_HDR_DMA_TX_ERR_TYPE_OFF; 1103 u32 dma_rx_err_type = ((dma_err_type & 1104 ERR_HDR_DMA_RX_ERR_TYPE_MSK)) >> 1105 ERR_HDR_DMA_RX_ERR_TYPE_OFF; 1106 u32 trans_tx_fail_type = 1107 le32_to_cpu(err_record->trans_tx_fail_type); 1108 u32 trans_rx_fail_type = 1109 le32_to_cpu(err_record->trans_rx_fail_type); 1110 1111 if (dma_tx_err_type) { 1112 /* dma tx err */ 1113 error = ffs(dma_tx_err_type) 1114 - 1 + DMA_TX_ERR_BASE; 1115 } else if (dma_rx_err_type) { 1116 /* dma rx err */ 1117 error = ffs(dma_rx_err_type) 1118 - 1 + DMA_RX_ERR_BASE; 1119 } else if (trans_tx_fail_type) { 1120 /* trans tx err */ 1121 error = ffs(trans_tx_fail_type) 1122 - 1 + TRANS_TX_FAIL_BASE; 1123 } else if (trans_rx_fail_type) { 1124 /* trans rx err */ 1125 error = ffs(trans_rx_fail_type) 1126 - 1 + TRANS_RX_FAIL_BASE; 1127 } 1128 1129 switch (error) { 1130 case DMA_TX_DATA_UNDERFLOW_ERR: 1131 case DMA_RX_DATA_UNDERFLOW_ERR: 1132 { 1133 ts->residual = 0; 1134 ts->stat = SAS_DATA_UNDERRUN; 1135 break; 1136 } 1137 case DMA_TX_DATA_SGL_OVERFLOW_ERR: 1138 case DMA_TX_DIF_SGL_OVERFLOW_ERR: 1139 case DMA_TX_XFER_RDY_LENGTH_OVERFLOW_ERR: 1140 case DMA_RX_DATA_OVERFLOW_ERR: 1141 case TRANS_RX_FRAME_OVERRUN_ERR: 1142 case TRANS_RX_LINK_BUF_OVERRUN_ERR: 1143 { 1144 ts->stat = SAS_DATA_OVERRUN; 1145 ts->residual = 0; 1146 break; 1147 } 1148 case TRANS_TX_PHY_NOT_ENABLE_ERR: 1149 { 1150 ts->stat = SAS_PHY_DOWN; 1151 break; 1152 } 1153 case TRANS_TX_OPEN_REJCT_WRONG_DEST_ERR: 1154 case TRANS_TX_OPEN_REJCT_ZONE_VIOLATION_ERR: 1155 case TRANS_TX_OPEN_REJCT_BY_OTHER_ERR: 1156 case TRANS_TX_OPEN_REJCT_AIP_TIMEOUT_ERR: 1157 case TRANS_TX_OPEN_REJCT_STP_BUSY_ERR: 1158 case TRANS_TX_OPEN_REJCT_PROTOCOL_NOT_SUPPORT_ERR: 1159 case TRANS_TX_OPEN_REJCT_RATE_NOT_SUPPORT_ERR: 1160 case TRANS_TX_OPEN_REJCT_BAD_DEST_ERR: 1161 case TRANS_TX_OPEN_BREAK_RECEIVE_ERR: 1162 case TRANS_TX_OPEN_REJCT_PATHWAY_BLOCKED_ERR: 1163 case TRANS_TX_OPEN_REJCT_NO_DEST_ERR: 1164 case TRANS_TX_OPEN_RETRY_ERR: 1165 { 1166 ts->stat = SAS_OPEN_REJECT; 1167 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1168 break; 1169 } 1170 case TRANS_TX_OPEN_TIMEOUT_ERR: 1171 { 1172 ts->stat = SAS_OPEN_TO; 1173 break; 1174 } 1175 case TRANS_TX_NAK_RECEIVE_ERR: 1176 case TRANS_TX_ACK_NAK_TIMEOUT_ERR: 1177 { 1178 ts->stat = SAS_NAK_R_ERR; 1179 break; 1180 } 1181 case TRANS_TX_CREDIT_TIMEOUT_ERR: 1182 case TRANS_TX_CLOSE_NORMAL_ERR: 1183 { 1184 /* This will request a retry */ 1185 ts->stat = SAS_QUEUE_FULL; 1186 slot->abort = 1; 1187 break; 1188 } 1189 default: 1190 { 1191 ts->stat = SAM_STAT_CHECK_CONDITION; 1192 break; 1193 } 1194 } 1195 } 1196 break; 1197 case SAS_PROTOCOL_SMP: 1198 ts->stat = SAM_STAT_CHECK_CONDITION; 1199 break; 1200 1201 case SAS_PROTOCOL_SATA: 1202 case SAS_PROTOCOL_STP: 1203 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 1204 { 1205 dev_err(dev, "slot err: SATA/STP not supported"); 1206 } 1207 break; 1208 default: 1209 break; 1210 } 1211 1212 } 1213 1214 static int slot_complete_v1_hw(struct hisi_hba *hisi_hba, 1215 struct hisi_sas_slot *slot) 1216 { 1217 struct sas_task *task = slot->task; 1218 struct hisi_sas_device *sas_dev; 1219 struct device *dev = hisi_hba->dev; 1220 struct task_status_struct *ts; 1221 struct domain_device *device; 1222 enum exec_status sts; 1223 struct hisi_sas_complete_v1_hdr *complete_queue = 1224 hisi_hba->complete_hdr[slot->cmplt_queue]; 1225 struct hisi_sas_complete_v1_hdr *complete_hdr; 1226 unsigned long flags; 1227 u32 cmplt_hdr_data; 1228 1229 complete_hdr = &complete_queue[slot->cmplt_queue_slot]; 1230 cmplt_hdr_data = le32_to_cpu(complete_hdr->data); 1231 1232 if (unlikely(!task || !task->lldd_task || !task->dev)) 1233 return -EINVAL; 1234 1235 ts = &task->task_status; 1236 device = task->dev; 1237 sas_dev = device->lldd_dev; 1238 1239 spin_lock_irqsave(&task->task_state_lock, flags); 1240 task->task_state_flags &= 1241 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR); 1242 task->task_state_flags |= SAS_TASK_STATE_DONE; 1243 spin_unlock_irqrestore(&task->task_state_lock, flags); 1244 1245 memset(ts, 0, sizeof(*ts)); 1246 ts->resp = SAS_TASK_COMPLETE; 1247 1248 if (unlikely(!sas_dev)) { 1249 dev_dbg(dev, "slot complete: port has no device\n"); 1250 ts->stat = SAS_PHY_DOWN; 1251 goto out; 1252 } 1253 1254 if (cmplt_hdr_data & CMPLT_HDR_IO_CFG_ERR_MSK) { 1255 u32 info_reg = hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO); 1256 1257 if (info_reg & HGC_INVLD_DQE_INFO_DQ_MSK) 1258 dev_err(dev, "slot complete: [%d:%d] has dq IPTT err", 1259 slot->cmplt_queue, slot->cmplt_queue_slot); 1260 1261 if (info_reg & HGC_INVLD_DQE_INFO_TYPE_MSK) 1262 dev_err(dev, "slot complete: [%d:%d] has dq type err", 1263 slot->cmplt_queue, slot->cmplt_queue_slot); 1264 1265 if (info_reg & HGC_INVLD_DQE_INFO_FORCE_MSK) 1266 dev_err(dev, "slot complete: [%d:%d] has dq force phy err", 1267 slot->cmplt_queue, slot->cmplt_queue_slot); 1268 1269 if (info_reg & HGC_INVLD_DQE_INFO_PHY_MSK) 1270 dev_err(dev, "slot complete: [%d:%d] has dq phy id err", 1271 slot->cmplt_queue, slot->cmplt_queue_slot); 1272 1273 if (info_reg & HGC_INVLD_DQE_INFO_ABORT_MSK) 1274 dev_err(dev, "slot complete: [%d:%d] has dq abort flag err", 1275 slot->cmplt_queue, slot->cmplt_queue_slot); 1276 1277 if (info_reg & HGC_INVLD_DQE_INFO_IPTT_OF_MSK) 1278 dev_err(dev, "slot complete: [%d:%d] has dq IPTT or ICT err", 1279 slot->cmplt_queue, slot->cmplt_queue_slot); 1280 1281 if (info_reg & HGC_INVLD_DQE_INFO_SSP_ERR_MSK) 1282 dev_err(dev, "slot complete: [%d:%d] has dq SSP frame type err", 1283 slot->cmplt_queue, slot->cmplt_queue_slot); 1284 1285 if (info_reg & HGC_INVLD_DQE_INFO_OFL_MSK) 1286 dev_err(dev, "slot complete: [%d:%d] has dq order frame len err", 1287 slot->cmplt_queue, slot->cmplt_queue_slot); 1288 1289 ts->stat = SAS_OPEN_REJECT; 1290 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1291 goto out; 1292 } 1293 1294 if (cmplt_hdr_data & CMPLT_HDR_ERR_RCRD_XFRD_MSK && 1295 !(cmplt_hdr_data & CMPLT_HDR_RSPNS_XFRD_MSK)) { 1296 1297 slot_err_v1_hw(hisi_hba, task, slot); 1298 if (unlikely(slot->abort)) 1299 return ts->stat; 1300 goto out; 1301 } 1302 1303 switch (task->task_proto) { 1304 case SAS_PROTOCOL_SSP: 1305 { 1306 struct hisi_sas_status_buffer *status_buffer = 1307 hisi_sas_status_buf_addr_mem(slot); 1308 struct ssp_response_iu *iu = (struct ssp_response_iu *) 1309 &status_buffer->iu[0]; 1310 1311 sas_ssp_task_response(dev, task, iu); 1312 break; 1313 } 1314 case SAS_PROTOCOL_SMP: 1315 { 1316 void *to; 1317 struct scatterlist *sg_resp = &task->smp_task.smp_resp; 1318 1319 ts->stat = SAM_STAT_GOOD; 1320 to = kmap_atomic(sg_page(sg_resp)); 1321 1322 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1, 1323 DMA_FROM_DEVICE); 1324 dma_unmap_sg(dev, &task->smp_task.smp_req, 1, 1325 DMA_TO_DEVICE); 1326 memcpy(to + sg_resp->offset, 1327 hisi_sas_status_buf_addr_mem(slot) + 1328 sizeof(struct hisi_sas_err_record), 1329 sg_dma_len(sg_resp)); 1330 kunmap_atomic(to); 1331 break; 1332 } 1333 case SAS_PROTOCOL_SATA: 1334 case SAS_PROTOCOL_STP: 1335 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 1336 dev_err(dev, "slot complete: SATA/STP not supported"); 1337 break; 1338 1339 default: 1340 ts->stat = SAM_STAT_CHECK_CONDITION; 1341 break; 1342 } 1343 1344 if (!slot->port->port_attached) { 1345 dev_err(dev, "slot complete: port %d has removed\n", 1346 slot->port->sas_port.id); 1347 ts->stat = SAS_PHY_DOWN; 1348 } 1349 1350 out: 1351 hisi_sas_slot_task_free(hisi_hba, task, slot); 1352 sts = ts->stat; 1353 1354 if (task->task_done) 1355 task->task_done(task); 1356 1357 return sts; 1358 } 1359 1360 /* Interrupts */ 1361 static irqreturn_t int_phyup_v1_hw(int irq_no, void *p) 1362 { 1363 struct hisi_sas_phy *phy = p; 1364 struct hisi_hba *hisi_hba = phy->hisi_hba; 1365 struct device *dev = hisi_hba->dev; 1366 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1367 int i, phy_no = sas_phy->id; 1368 u32 irq_value, context, port_id, link_rate; 1369 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd; 1370 struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd; 1371 irqreturn_t res = IRQ_HANDLED; 1372 unsigned long flags; 1373 1374 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2); 1375 if (!(irq_value & CHL_INT2_SL_PHY_ENA_MSK)) { 1376 dev_dbg(dev, "phyup: irq_value = %x not set enable bit\n", 1377 irq_value); 1378 res = IRQ_NONE; 1379 goto end; 1380 } 1381 1382 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT); 1383 if (context & 1 << phy_no) { 1384 dev_err(dev, "phyup: phy%d SATA attached equipment\n", 1385 phy_no); 1386 goto end; 1387 } 1388 1389 port_id = (hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA) >> (4 * phy_no)) 1390 & 0xf; 1391 if (port_id == 0xf) { 1392 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no); 1393 res = IRQ_NONE; 1394 goto end; 1395 } 1396 1397 for (i = 0; i < 6; i++) { 1398 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no, 1399 RX_IDAF_DWORD0 + (i * 4)); 1400 frame_rcvd[i] = __swab32(idaf); 1401 } 1402 1403 /* Get the linkrate */ 1404 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); 1405 link_rate = (link_rate >> (phy_no * 4)) & 0xf; 1406 sas_phy->linkrate = link_rate; 1407 sas_phy->oob_mode = SAS_OOB_MODE; 1408 memcpy(sas_phy->attached_sas_addr, 1409 &id->sas_addr, SAS_ADDR_SIZE); 1410 dev_info(dev, "phyup: phy%d link_rate=%d\n", 1411 phy_no, link_rate); 1412 phy->port_id = port_id; 1413 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); 1414 phy->phy_type |= PORT_TYPE_SAS; 1415 phy->phy_attached = 1; 1416 phy->identify.device_type = id->dev_type; 1417 phy->frame_rcvd_size = sizeof(struct sas_identify_frame); 1418 if (phy->identify.device_type == SAS_END_DEVICE) 1419 phy->identify.target_port_protocols = 1420 SAS_PROTOCOL_SSP; 1421 else if (phy->identify.device_type != SAS_PHY_UNUSED) 1422 phy->identify.target_port_protocols = 1423 SAS_PROTOCOL_SMP; 1424 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP); 1425 1426 spin_lock_irqsave(&phy->lock, flags); 1427 if (phy->reset_completion) { 1428 phy->in_reset = 0; 1429 complete(phy->reset_completion); 1430 } 1431 spin_unlock_irqrestore(&phy->lock, flags); 1432 1433 end: 1434 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, 1435 CHL_INT2_SL_PHY_ENA_MSK); 1436 1437 if (irq_value & CHL_INT2_SL_PHY_ENA_MSK) { 1438 u32 chl_int0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0); 1439 1440 chl_int0 &= ~CHL_INT0_PHYCTRL_NOTRDY_MSK; 1441 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, chl_int0); 1442 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, 0x3ce3ee); 1443 } 1444 1445 return res; 1446 } 1447 1448 static irqreturn_t int_bcast_v1_hw(int irq, void *p) 1449 { 1450 struct hisi_sas_phy *phy = p; 1451 struct hisi_hba *hisi_hba = phy->hisi_hba; 1452 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1453 struct sas_ha_struct *sha = &hisi_hba->sha; 1454 struct device *dev = hisi_hba->dev; 1455 int phy_no = sas_phy->id; 1456 u32 irq_value; 1457 irqreturn_t res = IRQ_HANDLED; 1458 1459 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2); 1460 1461 if (!(irq_value & CHL_INT2_SL_RX_BC_ACK_MSK)) { 1462 dev_err(dev, "bcast: irq_value = %x not set enable bit", 1463 irq_value); 1464 res = IRQ_NONE; 1465 goto end; 1466 } 1467 1468 if (!test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)) 1469 sha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 1470 1471 end: 1472 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, 1473 CHL_INT2_SL_RX_BC_ACK_MSK); 1474 1475 return res; 1476 } 1477 1478 static irqreturn_t int_abnormal_v1_hw(int irq, void *p) 1479 { 1480 struct hisi_sas_phy *phy = p; 1481 struct hisi_hba *hisi_hba = phy->hisi_hba; 1482 struct device *dev = hisi_hba->dev; 1483 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1484 u32 irq_value, irq_mask_old; 1485 int phy_no = sas_phy->id; 1486 1487 /* mask_int0 */ 1488 irq_mask_old = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0_MSK); 1489 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, 0x3fffff); 1490 1491 /* read int0 */ 1492 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0); 1493 1494 if (irq_value & CHL_INT0_PHYCTRL_NOTRDY_MSK) { 1495 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1496 1497 hisi_sas_phy_down(hisi_hba, phy_no, 1498 (phy_state & 1 << phy_no) ? 1 : 0); 1499 } 1500 1501 if (irq_value & CHL_INT0_ID_TIMEOUT_MSK) 1502 dev_dbg(dev, "abnormal: ID_TIMEOUT phy%d identify timeout\n", 1503 phy_no); 1504 1505 if (irq_value & CHL_INT0_DWS_LOST_MSK) 1506 dev_dbg(dev, "abnormal: DWS_LOST phy%d dws lost\n", phy_no); 1507 1508 if (irq_value & CHL_INT0_SN_FAIL_NGR_MSK) 1509 dev_dbg(dev, "abnormal: SN_FAIL_NGR phy%d sn fail ngr\n", 1510 phy_no); 1511 1512 if (irq_value & CHL_INT0_SL_IDAF_FAIL_MSK || 1513 irq_value & CHL_INT0_SL_OPAF_FAIL_MSK) 1514 dev_dbg(dev, "abnormal: SL_ID/OPAF_FAIL phy%d check adr frm err\n", 1515 phy_no); 1516 1517 if (irq_value & CHL_INT0_SL_PS_FAIL_OFF) 1518 dev_dbg(dev, "abnormal: SL_PS_FAIL phy%d fail\n", phy_no); 1519 1520 /* write to zero */ 1521 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, irq_value); 1522 1523 if (irq_value & CHL_INT0_PHYCTRL_NOTRDY_MSK) 1524 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, 1525 0x3fffff & ~CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK); 1526 else 1527 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, 1528 irq_mask_old); 1529 1530 return IRQ_HANDLED; 1531 } 1532 1533 static irqreturn_t cq_interrupt_v1_hw(int irq, void *p) 1534 { 1535 struct hisi_sas_cq *cq = p; 1536 struct hisi_hba *hisi_hba = cq->hisi_hba; 1537 struct hisi_sas_slot *slot; 1538 int queue = cq->id; 1539 struct hisi_sas_complete_v1_hdr *complete_queue = 1540 (struct hisi_sas_complete_v1_hdr *) 1541 hisi_hba->complete_hdr[queue]; 1542 u32 irq_value, rd_point = cq->rd_point, wr_point; 1543 1544 spin_lock(&hisi_hba->lock); 1545 irq_value = hisi_sas_read32(hisi_hba, OQ_INT_SRC); 1546 1547 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue); 1548 wr_point = hisi_sas_read32(hisi_hba, 1549 COMPL_Q_0_WR_PTR + (0x14 * queue)); 1550 1551 while (rd_point != wr_point) { 1552 struct hisi_sas_complete_v1_hdr *complete_hdr; 1553 int idx; 1554 u32 cmplt_hdr_data; 1555 1556 complete_hdr = &complete_queue[rd_point]; 1557 cmplt_hdr_data = le32_to_cpu(complete_hdr->data); 1558 idx = (cmplt_hdr_data & CMPLT_HDR_IPTT_MSK) >> 1559 CMPLT_HDR_IPTT_OFF; 1560 slot = &hisi_hba->slot_info[idx]; 1561 1562 /* The completion queue and queue slot index are not 1563 * necessarily the same as the delivery queue and 1564 * queue slot index. 1565 */ 1566 slot->cmplt_queue_slot = rd_point; 1567 slot->cmplt_queue = queue; 1568 slot_complete_v1_hw(hisi_hba, slot); 1569 1570 if (++rd_point >= HISI_SAS_QUEUE_SLOTS) 1571 rd_point = 0; 1572 } 1573 1574 /* update rd_point */ 1575 cq->rd_point = rd_point; 1576 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point); 1577 spin_unlock(&hisi_hba->lock); 1578 1579 return IRQ_HANDLED; 1580 } 1581 1582 static irqreturn_t fatal_ecc_int_v1_hw(int irq, void *p) 1583 { 1584 struct hisi_hba *hisi_hba = p; 1585 struct device *dev = hisi_hba->dev; 1586 u32 ecc_int = hisi_sas_read32(hisi_hba, SAS_ECC_INTR); 1587 1588 if (ecc_int & SAS_ECC_INTR_DQ_ECC1B_MSK) { 1589 u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR); 1590 1591 panic("%s: Fatal DQ 1b ECC interrupt (0x%x)\n", 1592 dev_name(dev), ecc_err); 1593 } 1594 1595 if (ecc_int & SAS_ECC_INTR_DQ_ECCBAD_MSK) { 1596 u32 addr = (hisi_sas_read32(hisi_hba, HGC_DQ_ECC_ADDR) & 1597 HGC_DQ_ECC_ADDR_BAD_MSK) >> 1598 HGC_DQ_ECC_ADDR_BAD_OFF; 1599 1600 panic("%s: Fatal DQ RAM ECC interrupt @ 0x%08x\n", 1601 dev_name(dev), addr); 1602 } 1603 1604 if (ecc_int & SAS_ECC_INTR_IOST_ECC1B_MSK) { 1605 u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR); 1606 1607 panic("%s: Fatal IOST 1b ECC interrupt (0x%x)\n", 1608 dev_name(dev), ecc_err); 1609 } 1610 1611 if (ecc_int & SAS_ECC_INTR_IOST_ECCBAD_MSK) { 1612 u32 addr = (hisi_sas_read32(hisi_hba, HGC_IOST_ECC_ADDR) & 1613 HGC_IOST_ECC_ADDR_BAD_MSK) >> 1614 HGC_IOST_ECC_ADDR_BAD_OFF; 1615 1616 panic("%s: Fatal IOST RAM ECC interrupt @ 0x%08x\n", 1617 dev_name(dev), addr); 1618 } 1619 1620 if (ecc_int & SAS_ECC_INTR_ITCT_ECCBAD_MSK) { 1621 u32 addr = (hisi_sas_read32(hisi_hba, HGC_ITCT_ECC_ADDR) & 1622 HGC_ITCT_ECC_ADDR_BAD_MSK) >> 1623 HGC_ITCT_ECC_ADDR_BAD_OFF; 1624 1625 panic("%s: Fatal TCT RAM ECC interrupt @ 0x%08x\n", 1626 dev_name(dev), addr); 1627 } 1628 1629 if (ecc_int & SAS_ECC_INTR_ITCT_ECC1B_MSK) { 1630 u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR); 1631 1632 panic("%s: Fatal ITCT 1b ECC interrupt (0x%x)\n", 1633 dev_name(dev), ecc_err); 1634 } 1635 1636 hisi_sas_write32(hisi_hba, SAS_ECC_INTR, ecc_int | 0x3f); 1637 1638 return IRQ_HANDLED; 1639 } 1640 1641 static irqreturn_t fatal_axi_int_v1_hw(int irq, void *p) 1642 { 1643 struct hisi_hba *hisi_hba = p; 1644 struct device *dev = hisi_hba->dev; 1645 u32 axi_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC2); 1646 u32 axi_info = hisi_sas_read32(hisi_hba, HGC_AXI_FIFO_ERR_INFO); 1647 1648 if (axi_int & ENT_INT_SRC2_DQ_CFG_ERR_MSK) 1649 panic("%s: Fatal DQ_CFG_ERR interrupt (0x%x)\n", 1650 dev_name(dev), axi_info); 1651 1652 if (axi_int & ENT_INT_SRC2_CQ_CFG_ERR_MSK) 1653 panic("%s: Fatal CQ_CFG_ERR interrupt (0x%x)\n", 1654 dev_name(dev), axi_info); 1655 1656 if (axi_int & ENT_INT_SRC2_AXI_WRONG_INT_MSK) 1657 panic("%s: Fatal AXI_WRONG_INT interrupt (0x%x)\n", 1658 dev_name(dev), axi_info); 1659 1660 if (axi_int & ENT_INT_SRC2_AXI_OVERLF_INT_MSK) 1661 panic("%s: Fatal AXI_OVERLF_INT incorrect interrupt (0x%x)\n", 1662 dev_name(dev), axi_info); 1663 1664 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, axi_int | 0x30000000); 1665 1666 return IRQ_HANDLED; 1667 } 1668 1669 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = { 1670 int_bcast_v1_hw, 1671 int_phyup_v1_hw, 1672 int_abnormal_v1_hw 1673 }; 1674 1675 static irq_handler_t fatal_interrupts[HISI_SAS_MAX_QUEUES] = { 1676 fatal_ecc_int_v1_hw, 1677 fatal_axi_int_v1_hw 1678 }; 1679 1680 static int interrupt_init_v1_hw(struct hisi_hba *hisi_hba) 1681 { 1682 struct platform_device *pdev = hisi_hba->platform_dev; 1683 struct device *dev = &pdev->dev; 1684 int i, j, irq, rc, idx; 1685 1686 for (i = 0; i < hisi_hba->n_phy; i++) { 1687 struct hisi_sas_phy *phy = &hisi_hba->phy[i]; 1688 1689 idx = i * HISI_SAS_PHY_INT_NR; 1690 for (j = 0; j < HISI_SAS_PHY_INT_NR; j++, idx++) { 1691 irq = platform_get_irq(pdev, idx); 1692 if (!irq) { 1693 dev_err(dev, "irq init: fail map phy interrupt %d\n", 1694 idx); 1695 return -ENOENT; 1696 } 1697 1698 rc = devm_request_irq(dev, irq, phy_interrupts[j], 0, 1699 DRV_NAME " phy", phy); 1700 if (rc) { 1701 dev_err(dev, "irq init: could not request phy interrupt %d, rc=%d\n", 1702 irq, rc); 1703 return -ENOENT; 1704 } 1705 } 1706 } 1707 1708 idx = hisi_hba->n_phy * HISI_SAS_PHY_INT_NR; 1709 for (i = 0; i < hisi_hba->queue_count; i++, idx++) { 1710 irq = platform_get_irq(pdev, idx); 1711 if (!irq) { 1712 dev_err(dev, "irq init: could not map cq interrupt %d\n", 1713 idx); 1714 return -ENOENT; 1715 } 1716 1717 rc = devm_request_irq(dev, irq, cq_interrupt_v1_hw, 0, 1718 DRV_NAME " cq", &hisi_hba->cq[i]); 1719 if (rc) { 1720 dev_err(dev, "irq init: could not request cq interrupt %d, rc=%d\n", 1721 irq, rc); 1722 return -ENOENT; 1723 } 1724 } 1725 1726 idx = (hisi_hba->n_phy * HISI_SAS_PHY_INT_NR) + hisi_hba->queue_count; 1727 for (i = 0; i < HISI_SAS_FATAL_INT_NR; i++, idx++) { 1728 irq = platform_get_irq(pdev, idx); 1729 if (!irq) { 1730 dev_err(dev, "irq init: could not map fatal interrupt %d\n", 1731 idx); 1732 return -ENOENT; 1733 } 1734 1735 rc = devm_request_irq(dev, irq, fatal_interrupts[i], 0, 1736 DRV_NAME " fatal", hisi_hba); 1737 if (rc) { 1738 dev_err(dev, "irq init: could not request fatal interrupt %d, rc=%d\n", 1739 irq, rc); 1740 return -ENOENT; 1741 } 1742 } 1743 1744 hisi_hba->cq_nvecs = hisi_hba->queue_count; 1745 1746 return 0; 1747 } 1748 1749 static int interrupt_openall_v1_hw(struct hisi_hba *hisi_hba) 1750 { 1751 int i; 1752 u32 val; 1753 1754 for (i = 0; i < hisi_hba->n_phy; i++) { 1755 /* Clear interrupt status */ 1756 val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT0); 1757 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, val); 1758 val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT1); 1759 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, val); 1760 val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT2); 1761 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, val); 1762 1763 /* Unmask interrupt */ 1764 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0_MSK, 0x3ce3ee); 1765 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0x17fff); 1766 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8000012a); 1767 1768 /* bypass chip bug mask abnormal intr */ 1769 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0_MSK, 1770 0x3fffff & ~CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK); 1771 } 1772 1773 return 0; 1774 } 1775 1776 static int hisi_sas_v1_init(struct hisi_hba *hisi_hba) 1777 { 1778 int rc; 1779 1780 rc = hw_init_v1_hw(hisi_hba); 1781 if (rc) 1782 return rc; 1783 1784 rc = interrupt_init_v1_hw(hisi_hba); 1785 if (rc) 1786 return rc; 1787 1788 rc = interrupt_openall_v1_hw(hisi_hba); 1789 if (rc) 1790 return rc; 1791 1792 return 0; 1793 } 1794 1795 static struct device_attribute *host_attrs_v1_hw[] = { 1796 &dev_attr_phy_event_threshold, 1797 NULL 1798 }; 1799 1800 static struct scsi_host_template sht_v1_hw = { 1801 .name = DRV_NAME, 1802 .module = THIS_MODULE, 1803 .queuecommand = sas_queuecommand, 1804 .target_alloc = sas_target_alloc, 1805 .slave_configure = hisi_sas_slave_configure, 1806 .scan_finished = hisi_sas_scan_finished, 1807 .scan_start = hisi_sas_scan_start, 1808 .change_queue_depth = sas_change_queue_depth, 1809 .bios_param = sas_bios_param, 1810 .this_id = -1, 1811 .sg_tablesize = HISI_SAS_SGE_PAGE_CNT, 1812 .max_sectors = SCSI_DEFAULT_MAX_SECTORS, 1813 .eh_device_reset_handler = sas_eh_device_reset_handler, 1814 .eh_target_reset_handler = sas_eh_target_reset_handler, 1815 .target_destroy = sas_target_destroy, 1816 .ioctl = sas_ioctl, 1817 .shost_attrs = host_attrs_v1_hw, 1818 .host_reset = hisi_sas_host_reset, 1819 }; 1820 1821 static const struct hisi_sas_hw hisi_sas_v1_hw = { 1822 .hw_init = hisi_sas_v1_init, 1823 .setup_itct = setup_itct_v1_hw, 1824 .sl_notify_ssp = sl_notify_ssp_v1_hw, 1825 .clear_itct = clear_itct_v1_hw, 1826 .prep_smp = prep_smp_v1_hw, 1827 .prep_ssp = prep_ssp_v1_hw, 1828 .get_free_slot = get_free_slot_v1_hw, 1829 .start_delivery = start_delivery_v1_hw, 1830 .slot_complete = slot_complete_v1_hw, 1831 .phys_init = phys_init_v1_hw, 1832 .phy_start = start_phy_v1_hw, 1833 .phy_disable = disable_phy_v1_hw, 1834 .phy_hard_reset = phy_hard_reset_v1_hw, 1835 .phy_set_linkrate = phy_set_linkrate_v1_hw, 1836 .phy_get_max_linkrate = phy_get_max_linkrate_v1_hw, 1837 .get_wideport_bitmap = get_wideport_bitmap_v1_hw, 1838 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V1_HW, 1839 .complete_hdr_size = sizeof(struct hisi_sas_complete_v1_hdr), 1840 .sht = &sht_v1_hw, 1841 }; 1842 1843 static int hisi_sas_v1_probe(struct platform_device *pdev) 1844 { 1845 return hisi_sas_probe(pdev, &hisi_sas_v1_hw); 1846 } 1847 1848 static int hisi_sas_v1_remove(struct platform_device *pdev) 1849 { 1850 return hisi_sas_remove(pdev); 1851 } 1852 1853 static const struct of_device_id sas_v1_of_match[] = { 1854 { .compatible = "hisilicon,hip05-sas-v1",}, 1855 {}, 1856 }; 1857 MODULE_DEVICE_TABLE(of, sas_v1_of_match); 1858 1859 static const struct acpi_device_id sas_v1_acpi_match[] = { 1860 { "HISI0161", 0 }, 1861 { } 1862 }; 1863 1864 MODULE_DEVICE_TABLE(acpi, sas_v1_acpi_match); 1865 1866 static struct platform_driver hisi_sas_v1_driver = { 1867 .probe = hisi_sas_v1_probe, 1868 .remove = hisi_sas_v1_remove, 1869 .driver = { 1870 .name = DRV_NAME, 1871 .of_match_table = sas_v1_of_match, 1872 .acpi_match_table = ACPI_PTR(sas_v1_acpi_match), 1873 }, 1874 }; 1875 1876 module_platform_driver(hisi_sas_v1_driver); 1877 1878 MODULE_LICENSE("GPL"); 1879 MODULE_AUTHOR("John Garry <john.garry@huawei.com>"); 1880 MODULE_DESCRIPTION("HISILICON SAS controller v1 hw driver"); 1881 MODULE_ALIAS("platform:" DRV_NAME); 1882