1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) 2015 Linaro Ltd. 4 * Copyright (c) 2015 Hisilicon Limited. 5 */ 6 7 #include "hisi_sas.h" 8 #define DRV_NAME "hisi_sas_v1_hw" 9 10 /* global registers need init*/ 11 #define DLVRY_QUEUE_ENABLE 0x0 12 #define IOST_BASE_ADDR_LO 0x8 13 #define IOST_BASE_ADDR_HI 0xc 14 #define ITCT_BASE_ADDR_LO 0x10 15 #define ITCT_BASE_ADDR_HI 0x14 16 #define BROKEN_MSG_ADDR_LO 0x18 17 #define BROKEN_MSG_ADDR_HI 0x1c 18 #define PHY_CONTEXT 0x20 19 #define PHY_STATE 0x24 20 #define PHY_PORT_NUM_MA 0x28 21 #define PORT_STATE 0x2c 22 #define PHY_CONN_RATE 0x30 23 #define HGC_TRANS_TASK_CNT_LIMIT 0x38 24 #define AXI_AHB_CLK_CFG 0x3c 25 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x84 26 #define HGC_GET_ITV_TIME 0x90 27 #define DEVICE_MSG_WORK_MODE 0x94 28 #define I_T_NEXUS_LOSS_TIME 0xa0 29 #define BUS_INACTIVE_LIMIT_TIME 0xa8 30 #define REJECT_TO_OPEN_LIMIT_TIME 0xac 31 #define CFG_AGING_TIME 0xbc 32 #define CFG_AGING_TIME_ITCT_REL_OFF 0 33 #define CFG_AGING_TIME_ITCT_REL_MSK (0x1 << CFG_AGING_TIME_ITCT_REL_OFF) 34 #define HGC_DFX_CFG2 0xc0 35 #define FIS_LIST_BADDR_L 0xc4 36 #define CFG_1US_TIMER_TRSH 0xcc 37 #define CFG_SAS_CONFIG 0xd4 38 #define HGC_IOST_ECC_ADDR 0x140 39 #define HGC_IOST_ECC_ADDR_BAD_OFF 16 40 #define HGC_IOST_ECC_ADDR_BAD_MSK (0x3ff << HGC_IOST_ECC_ADDR_BAD_OFF) 41 #define HGC_DQ_ECC_ADDR 0x144 42 #define HGC_DQ_ECC_ADDR_BAD_OFF 16 43 #define HGC_DQ_ECC_ADDR_BAD_MSK (0xfff << HGC_DQ_ECC_ADDR_BAD_OFF) 44 #define HGC_INVLD_DQE_INFO 0x148 45 #define HGC_INVLD_DQE_INFO_DQ_OFF 0 46 #define HGC_INVLD_DQE_INFO_DQ_MSK (0xffff << HGC_INVLD_DQE_INFO_DQ_OFF) 47 #define HGC_INVLD_DQE_INFO_TYPE_OFF 16 48 #define HGC_INVLD_DQE_INFO_TYPE_MSK (0x1 << HGC_INVLD_DQE_INFO_TYPE_OFF) 49 #define HGC_INVLD_DQE_INFO_FORCE_OFF 17 50 #define HGC_INVLD_DQE_INFO_FORCE_MSK (0x1 << HGC_INVLD_DQE_INFO_FORCE_OFF) 51 #define HGC_INVLD_DQE_INFO_PHY_OFF 18 52 #define HGC_INVLD_DQE_INFO_PHY_MSK (0x1 << HGC_INVLD_DQE_INFO_PHY_OFF) 53 #define HGC_INVLD_DQE_INFO_ABORT_OFF 19 54 #define HGC_INVLD_DQE_INFO_ABORT_MSK (0x1 << HGC_INVLD_DQE_INFO_ABORT_OFF) 55 #define HGC_INVLD_DQE_INFO_IPTT_OF_OFF 20 56 #define HGC_INVLD_DQE_INFO_IPTT_OF_MSK (0x1 << HGC_INVLD_DQE_INFO_IPTT_OF_OFF) 57 #define HGC_INVLD_DQE_INFO_SSP_ERR_OFF 21 58 #define HGC_INVLD_DQE_INFO_SSP_ERR_MSK (0x1 << HGC_INVLD_DQE_INFO_SSP_ERR_OFF) 59 #define HGC_INVLD_DQE_INFO_OFL_OFF 22 60 #define HGC_INVLD_DQE_INFO_OFL_MSK (0x1 << HGC_INVLD_DQE_INFO_OFL_OFF) 61 #define HGC_ITCT_ECC_ADDR 0x150 62 #define HGC_ITCT_ECC_ADDR_BAD_OFF 16 63 #define HGC_ITCT_ECC_ADDR_BAD_MSK (0x3ff << HGC_ITCT_ECC_ADDR_BAD_OFF) 64 #define HGC_AXI_FIFO_ERR_INFO 0x154 65 #define INT_COAL_EN 0x1bc 66 #define OQ_INT_COAL_TIME 0x1c0 67 #define OQ_INT_COAL_CNT 0x1c4 68 #define ENT_INT_COAL_TIME 0x1c8 69 #define ENT_INT_COAL_CNT 0x1cc 70 #define OQ_INT_SRC 0x1d0 71 #define OQ_INT_SRC_MSK 0x1d4 72 #define ENT_INT_SRC1 0x1d8 73 #define ENT_INT_SRC2 0x1dc 74 #define ENT_INT_SRC2_DQ_CFG_ERR_OFF 25 75 #define ENT_INT_SRC2_DQ_CFG_ERR_MSK (0x1 << ENT_INT_SRC2_DQ_CFG_ERR_OFF) 76 #define ENT_INT_SRC2_CQ_CFG_ERR_OFF 27 77 #define ENT_INT_SRC2_CQ_CFG_ERR_MSK (0x1 << ENT_INT_SRC2_CQ_CFG_ERR_OFF) 78 #define ENT_INT_SRC2_AXI_WRONG_INT_OFF 28 79 #define ENT_INT_SRC2_AXI_WRONG_INT_MSK (0x1 << ENT_INT_SRC2_AXI_WRONG_INT_OFF) 80 #define ENT_INT_SRC2_AXI_OVERLF_INT_OFF 29 81 #define ENT_INT_SRC2_AXI_OVERLF_INT_MSK (0x1 << ENT_INT_SRC2_AXI_OVERLF_INT_OFF) 82 #define ENT_INT_SRC_MSK1 0x1e0 83 #define ENT_INT_SRC_MSK2 0x1e4 84 #define SAS_ECC_INTR 0x1e8 85 #define SAS_ECC_INTR_DQ_ECC1B_OFF 0 86 #define SAS_ECC_INTR_DQ_ECC1B_MSK (0x1 << SAS_ECC_INTR_DQ_ECC1B_OFF) 87 #define SAS_ECC_INTR_DQ_ECCBAD_OFF 1 88 #define SAS_ECC_INTR_DQ_ECCBAD_MSK (0x1 << SAS_ECC_INTR_DQ_ECCBAD_OFF) 89 #define SAS_ECC_INTR_IOST_ECC1B_OFF 2 90 #define SAS_ECC_INTR_IOST_ECC1B_MSK (0x1 << SAS_ECC_INTR_IOST_ECC1B_OFF) 91 #define SAS_ECC_INTR_IOST_ECCBAD_OFF 3 92 #define SAS_ECC_INTR_IOST_ECCBAD_MSK (0x1 << SAS_ECC_INTR_IOST_ECCBAD_OFF) 93 #define SAS_ECC_INTR_ITCT_ECC1B_OFF 4 94 #define SAS_ECC_INTR_ITCT_ECC1B_MSK (0x1 << SAS_ECC_INTR_ITCT_ECC1B_OFF) 95 #define SAS_ECC_INTR_ITCT_ECCBAD_OFF 5 96 #define SAS_ECC_INTR_ITCT_ECCBAD_MSK (0x1 << SAS_ECC_INTR_ITCT_ECCBAD_OFF) 97 #define SAS_ECC_INTR_MSK 0x1ec 98 #define HGC_ERR_STAT_EN 0x238 99 #define DLVRY_Q_0_BASE_ADDR_LO 0x260 100 #define DLVRY_Q_0_BASE_ADDR_HI 0x264 101 #define DLVRY_Q_0_DEPTH 0x268 102 #define DLVRY_Q_0_WR_PTR 0x26c 103 #define DLVRY_Q_0_RD_PTR 0x270 104 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0 105 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4 106 #define COMPL_Q_0_DEPTH 0x4e8 107 #define COMPL_Q_0_WR_PTR 0x4ec 108 #define COMPL_Q_0_RD_PTR 0x4f0 109 #define HGC_ECC_ERR 0x7d0 110 111 /* phy registers need init */ 112 #define PORT_BASE (0x800) 113 114 #define PHY_CFG (PORT_BASE + 0x0) 115 #define PHY_CFG_ENA_OFF 0 116 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF) 117 #define PHY_CFG_DC_OPT_OFF 2 118 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF) 119 #define PROG_PHY_LINK_RATE (PORT_BASE + 0xc) 120 #define PROG_PHY_LINK_RATE_MAX_OFF 0 121 #define PROG_PHY_LINK_RATE_MAX_MSK (0xf << PROG_PHY_LINK_RATE_MAX_OFF) 122 #define PROG_PHY_LINK_RATE_MIN_OFF 4 123 #define PROG_PHY_LINK_RATE_MIN_MSK (0xf << PROG_PHY_LINK_RATE_MIN_OFF) 124 #define PROG_PHY_LINK_RATE_OOB_OFF 8 125 #define PROG_PHY_LINK_RATE_OOB_MSK (0xf << PROG_PHY_LINK_RATE_OOB_OFF) 126 #define PHY_CTRL (PORT_BASE + 0x14) 127 #define PHY_CTRL_RESET_OFF 0 128 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF) 129 #define PHY_RATE_NEGO (PORT_BASE + 0x30) 130 #define PHY_PCN (PORT_BASE + 0x44) 131 #define SL_TOUT_CFG (PORT_BASE + 0x8c) 132 #define SL_CONTROL (PORT_BASE + 0x94) 133 #define SL_CONTROL_NOTIFY_EN_OFF 0 134 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF) 135 #define TX_ID_DWORD0 (PORT_BASE + 0x9c) 136 #define TX_ID_DWORD1 (PORT_BASE + 0xa0) 137 #define TX_ID_DWORD2 (PORT_BASE + 0xa4) 138 #define TX_ID_DWORD3 (PORT_BASE + 0xa8) 139 #define TX_ID_DWORD4 (PORT_BASE + 0xaC) 140 #define TX_ID_DWORD5 (PORT_BASE + 0xb0) 141 #define TX_ID_DWORD6 (PORT_BASE + 0xb4) 142 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4) 143 #define RX_IDAF_DWORD1 (PORT_BASE + 0xc8) 144 #define RX_IDAF_DWORD2 (PORT_BASE + 0xcc) 145 #define RX_IDAF_DWORD3 (PORT_BASE + 0xd0) 146 #define RX_IDAF_DWORD4 (PORT_BASE + 0xd4) 147 #define RX_IDAF_DWORD5 (PORT_BASE + 0xd8) 148 #define RX_IDAF_DWORD6 (PORT_BASE + 0xdc) 149 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) 150 #define DONE_RECEIVED_TIME (PORT_BASE + 0x12c) 151 #define CON_CFG_DRIVER (PORT_BASE + 0x130) 152 #define PHY_CONFIG2 (PORT_BASE + 0x1a8) 153 #define PHY_CONFIG2_FORCE_TXDEEMPH_OFF 3 154 #define PHY_CONFIG2_FORCE_TXDEEMPH_MSK (0x1 << PHY_CONFIG2_FORCE_TXDEEMPH_OFF) 155 #define PHY_CONFIG2_TX_TRAIN_COMP_OFF 24 156 #define PHY_CONFIG2_TX_TRAIN_COMP_MSK (0x1 << PHY_CONFIG2_TX_TRAIN_COMP_OFF) 157 #define CHL_INT0 (PORT_BASE + 0x1b0) 158 #define CHL_INT0_PHYCTRL_NOTRDY_OFF 0 159 #define CHL_INT0_PHYCTRL_NOTRDY_MSK (0x1 << CHL_INT0_PHYCTRL_NOTRDY_OFF) 160 #define CHL_INT0_SN_FAIL_NGR_OFF 2 161 #define CHL_INT0_SN_FAIL_NGR_MSK (0x1 << CHL_INT0_SN_FAIL_NGR_OFF) 162 #define CHL_INT0_DWS_LOST_OFF 4 163 #define CHL_INT0_DWS_LOST_MSK (0x1 << CHL_INT0_DWS_LOST_OFF) 164 #define CHL_INT0_SL_IDAF_FAIL_OFF 10 165 #define CHL_INT0_SL_IDAF_FAIL_MSK (0x1 << CHL_INT0_SL_IDAF_FAIL_OFF) 166 #define CHL_INT0_ID_TIMEOUT_OFF 11 167 #define CHL_INT0_ID_TIMEOUT_MSK (0x1 << CHL_INT0_ID_TIMEOUT_OFF) 168 #define CHL_INT0_SL_OPAF_FAIL_OFF 12 169 #define CHL_INT0_SL_OPAF_FAIL_MSK (0x1 << CHL_INT0_SL_OPAF_FAIL_OFF) 170 #define CHL_INT0_SL_PS_FAIL_OFF 21 171 #define CHL_INT0_SL_PS_FAIL_MSK (0x1 << CHL_INT0_SL_PS_FAIL_OFF) 172 #define CHL_INT1 (PORT_BASE + 0x1b4) 173 #define CHL_INT2 (PORT_BASE + 0x1b8) 174 #define CHL_INT2_SL_RX_BC_ACK_OFF 2 175 #define CHL_INT2_SL_RX_BC_ACK_MSK (0x1 << CHL_INT2_SL_RX_BC_ACK_OFF) 176 #define CHL_INT2_SL_PHY_ENA_OFF 6 177 #define CHL_INT2_SL_PHY_ENA_MSK (0x1 << CHL_INT2_SL_PHY_ENA_OFF) 178 #define CHL_INT0_MSK (PORT_BASE + 0x1bc) 179 #define CHL_INT0_MSK_PHYCTRL_NOTRDY_OFF 0 180 #define CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK (0x1 << CHL_INT0_MSK_PHYCTRL_NOTRDY_OFF) 181 #define CHL_INT1_MSK (PORT_BASE + 0x1c0) 182 #define CHL_INT2_MSK (PORT_BASE + 0x1c4) 183 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0) 184 #define DMA_TX_STATUS (PORT_BASE + 0x2d0) 185 #define DMA_TX_STATUS_BUSY_OFF 0 186 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF) 187 #define DMA_RX_STATUS (PORT_BASE + 0x2e8) 188 #define DMA_RX_STATUS_BUSY_OFF 0 189 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF) 190 191 #define AXI_CFG 0x5100 192 #define RESET_VALUE 0x7ffff 193 194 /* HW dma structures */ 195 /* Delivery queue header */ 196 /* dw0 */ 197 #define CMD_HDR_RESP_REPORT_OFF 5 198 #define CMD_HDR_RESP_REPORT_MSK 0x20 199 #define CMD_HDR_TLR_CTRL_OFF 6 200 #define CMD_HDR_TLR_CTRL_MSK 0xc0 201 #define CMD_HDR_PORT_OFF 17 202 #define CMD_HDR_PORT_MSK 0xe0000 203 #define CMD_HDR_PRIORITY_OFF 27 204 #define CMD_HDR_PRIORITY_MSK 0x8000000 205 #define CMD_HDR_MODE_OFF 28 206 #define CMD_HDR_MODE_MSK 0x10000000 207 #define CMD_HDR_CMD_OFF 29 208 #define CMD_HDR_CMD_MSK 0xe0000000 209 /* dw1 */ 210 #define CMD_HDR_VERIFY_DTL_OFF 10 211 #define CMD_HDR_VERIFY_DTL_MSK 0x400 212 #define CMD_HDR_SSP_FRAME_TYPE_OFF 13 213 #define CMD_HDR_SSP_FRAME_TYPE_MSK 0xe000 214 #define CMD_HDR_DEVICE_ID_OFF 16 215 #define CMD_HDR_DEVICE_ID_MSK 0xffff0000 216 /* dw2 */ 217 #define CMD_HDR_CFL_OFF 0 218 #define CMD_HDR_CFL_MSK 0x1ff 219 #define CMD_HDR_MRFL_OFF 15 220 #define CMD_HDR_MRFL_MSK 0xff8000 221 #define CMD_HDR_FIRST_BURST_OFF 25 222 #define CMD_HDR_FIRST_BURST_MSK 0x2000000 223 /* dw3 */ 224 #define CMD_HDR_IPTT_OFF 0 225 #define CMD_HDR_IPTT_MSK 0xffff 226 /* dw6 */ 227 #define CMD_HDR_DATA_SGL_LEN_OFF 16 228 #define CMD_HDR_DATA_SGL_LEN_MSK 0xffff0000 229 230 /* Completion header */ 231 #define CMPLT_HDR_IPTT_OFF 0 232 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF) 233 #define CMPLT_HDR_CMD_CMPLT_OFF 17 234 #define CMPLT_HDR_CMD_CMPLT_MSK (0x1 << CMPLT_HDR_CMD_CMPLT_OFF) 235 #define CMPLT_HDR_ERR_RCRD_XFRD_OFF 18 236 #define CMPLT_HDR_ERR_RCRD_XFRD_MSK (0x1 << CMPLT_HDR_ERR_RCRD_XFRD_OFF) 237 #define CMPLT_HDR_RSPNS_XFRD_OFF 19 238 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF) 239 #define CMPLT_HDR_IO_CFG_ERR_OFF 27 240 #define CMPLT_HDR_IO_CFG_ERR_MSK (0x1 << CMPLT_HDR_IO_CFG_ERR_OFF) 241 242 /* ITCT header */ 243 /* qw0 */ 244 #define ITCT_HDR_DEV_TYPE_OFF 0 245 #define ITCT_HDR_DEV_TYPE_MSK (0x3ULL << ITCT_HDR_DEV_TYPE_OFF) 246 #define ITCT_HDR_VALID_OFF 2 247 #define ITCT_HDR_VALID_MSK (0x1ULL << ITCT_HDR_VALID_OFF) 248 #define ITCT_HDR_AWT_CONTROL_OFF 4 249 #define ITCT_HDR_AWT_CONTROL_MSK (0x1ULL << ITCT_HDR_AWT_CONTROL_OFF) 250 #define ITCT_HDR_MAX_CONN_RATE_OFF 5 251 #define ITCT_HDR_MAX_CONN_RATE_MSK (0xfULL << ITCT_HDR_MAX_CONN_RATE_OFF) 252 #define ITCT_HDR_VALID_LINK_NUM_OFF 9 253 #define ITCT_HDR_VALID_LINK_NUM_MSK (0xfULL << ITCT_HDR_VALID_LINK_NUM_OFF) 254 #define ITCT_HDR_PORT_ID_OFF 13 255 #define ITCT_HDR_PORT_ID_MSK (0x7ULL << ITCT_HDR_PORT_ID_OFF) 256 #define ITCT_HDR_SMP_TIMEOUT_OFF 16 257 #define ITCT_HDR_SMP_TIMEOUT_MSK (0xffffULL << ITCT_HDR_SMP_TIMEOUT_OFF) 258 /* qw1 */ 259 #define ITCT_HDR_MAX_SAS_ADDR_OFF 0 260 #define ITCT_HDR_MAX_SAS_ADDR_MSK (0xffffffffffffffff << \ 261 ITCT_HDR_MAX_SAS_ADDR_OFF) 262 /* qw2 */ 263 #define ITCT_HDR_IT_NEXUS_LOSS_TL_OFF 0 264 #define ITCT_HDR_IT_NEXUS_LOSS_TL_MSK (0xffffULL << \ 265 ITCT_HDR_IT_NEXUS_LOSS_TL_OFF) 266 #define ITCT_HDR_BUS_INACTIVE_TL_OFF 16 267 #define ITCT_HDR_BUS_INACTIVE_TL_MSK (0xffffULL << \ 268 ITCT_HDR_BUS_INACTIVE_TL_OFF) 269 #define ITCT_HDR_MAX_CONN_TL_OFF 32 270 #define ITCT_HDR_MAX_CONN_TL_MSK (0xffffULL << \ 271 ITCT_HDR_MAX_CONN_TL_OFF) 272 #define ITCT_HDR_REJ_OPEN_TL_OFF 48 273 #define ITCT_HDR_REJ_OPEN_TL_MSK (0xffffULL << \ 274 ITCT_HDR_REJ_OPEN_TL_OFF) 275 276 /* Err record header */ 277 #define ERR_HDR_DMA_TX_ERR_TYPE_OFF 0 278 #define ERR_HDR_DMA_TX_ERR_TYPE_MSK (0xffff << ERR_HDR_DMA_TX_ERR_TYPE_OFF) 279 #define ERR_HDR_DMA_RX_ERR_TYPE_OFF 16 280 #define ERR_HDR_DMA_RX_ERR_TYPE_MSK (0xffff << ERR_HDR_DMA_RX_ERR_TYPE_OFF) 281 282 struct hisi_sas_complete_v1_hdr { 283 __le32 data; 284 }; 285 286 struct hisi_sas_err_record_v1 { 287 /* dw0 */ 288 __le32 dma_err_type; 289 290 /* dw1 */ 291 __le32 trans_tx_fail_type; 292 293 /* dw2 */ 294 __le32 trans_rx_fail_type; 295 296 /* dw3 */ 297 u32 rsvd; 298 }; 299 300 enum { 301 HISI_SAS_PHY_BCAST_ACK = 0, 302 HISI_SAS_PHY_SL_PHY_ENABLED, 303 HISI_SAS_PHY_INT_ABNORMAL, 304 HISI_SAS_PHY_INT_NR 305 }; 306 307 enum { 308 DMA_TX_ERR_BASE = 0x0, 309 DMA_RX_ERR_BASE = 0x100, 310 TRANS_TX_FAIL_BASE = 0x200, 311 TRANS_RX_FAIL_BASE = 0x300, 312 313 /* dma tx */ 314 DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x0 */ 315 DMA_TX_DIF_APP_ERR, /* 0x1 */ 316 DMA_TX_DIF_RPP_ERR, /* 0x2 */ 317 DMA_TX_AXI_BUS_ERR, /* 0x3 */ 318 DMA_TX_DATA_SGL_OVERFLOW_ERR, /* 0x4 */ 319 DMA_TX_DIF_SGL_OVERFLOW_ERR, /* 0x5 */ 320 DMA_TX_UNEXP_XFER_RDY_ERR, /* 0x6 */ 321 DMA_TX_XFER_RDY_OFFSET_ERR, /* 0x7 */ 322 DMA_TX_DATA_UNDERFLOW_ERR, /* 0x8 */ 323 DMA_TX_XFER_RDY_LENGTH_OVERFLOW_ERR, /* 0x9 */ 324 325 /* dma rx */ 326 DMA_RX_BUFFER_ECC_ERR = DMA_RX_ERR_BASE, /* 0x100 */ 327 DMA_RX_DIF_CRC_ERR, /* 0x101 */ 328 DMA_RX_DIF_APP_ERR, /* 0x102 */ 329 DMA_RX_DIF_RPP_ERR, /* 0x103 */ 330 DMA_RX_RESP_BUFFER_OVERFLOW_ERR, /* 0x104 */ 331 DMA_RX_AXI_BUS_ERR, /* 0x105 */ 332 DMA_RX_DATA_SGL_OVERFLOW_ERR, /* 0x106 */ 333 DMA_RX_DIF_SGL_OVERFLOW_ERR, /* 0x107 */ 334 DMA_RX_DATA_OFFSET_ERR, /* 0x108 */ 335 DMA_RX_UNEXP_RX_DATA_ERR, /* 0x109 */ 336 DMA_RX_DATA_OVERFLOW_ERR, /* 0x10a */ 337 DMA_RX_DATA_UNDERFLOW_ERR, /* 0x10b */ 338 DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x10c */ 339 340 /* trans tx */ 341 TRANS_TX_RSVD0_ERR = TRANS_TX_FAIL_BASE, /* 0x200 */ 342 TRANS_TX_PHY_NOT_ENABLE_ERR, /* 0x201 */ 343 TRANS_TX_OPEN_REJCT_WRONG_DEST_ERR, /* 0x202 */ 344 TRANS_TX_OPEN_REJCT_ZONE_VIOLATION_ERR, /* 0x203 */ 345 TRANS_TX_OPEN_REJCT_BY_OTHER_ERR, /* 0x204 */ 346 TRANS_TX_RSVD1_ERR, /* 0x205 */ 347 TRANS_TX_OPEN_REJCT_AIP_TIMEOUT_ERR, /* 0x206 */ 348 TRANS_TX_OPEN_REJCT_STP_BUSY_ERR, /* 0x207 */ 349 TRANS_TX_OPEN_REJCT_PROTOCOL_NOT_SUPPORT_ERR, /* 0x208 */ 350 TRANS_TX_OPEN_REJCT_RATE_NOT_SUPPORT_ERR, /* 0x209 */ 351 TRANS_TX_OPEN_REJCT_BAD_DEST_ERR, /* 0x20a */ 352 TRANS_TX_OPEN_BREAK_RECEIVE_ERR, /* 0x20b */ 353 TRANS_TX_LOW_PHY_POWER_ERR, /* 0x20c */ 354 TRANS_TX_OPEN_REJCT_PATHWAY_BLOCKED_ERR, /* 0x20d */ 355 TRANS_TX_OPEN_TIMEOUT_ERR, /* 0x20e */ 356 TRANS_TX_OPEN_REJCT_NO_DEST_ERR, /* 0x20f */ 357 TRANS_TX_OPEN_RETRY_ERR, /* 0x210 */ 358 TRANS_TX_RSVD2_ERR, /* 0x211 */ 359 TRANS_TX_BREAK_TIMEOUT_ERR, /* 0x212 */ 360 TRANS_TX_BREAK_REQUEST_ERR, /* 0x213 */ 361 TRANS_TX_BREAK_RECEIVE_ERR, /* 0x214 */ 362 TRANS_TX_CLOSE_TIMEOUT_ERR, /* 0x215 */ 363 TRANS_TX_CLOSE_NORMAL_ERR, /* 0x216 */ 364 TRANS_TX_CLOSE_PHYRESET_ERR, /* 0x217 */ 365 TRANS_TX_WITH_CLOSE_DWS_TIMEOUT_ERR, /* 0x218 */ 366 TRANS_TX_WITH_CLOSE_COMINIT_ERR, /* 0x219 */ 367 TRANS_TX_NAK_RECEIVE_ERR, /* 0x21a */ 368 TRANS_TX_ACK_NAK_TIMEOUT_ERR, /* 0x21b */ 369 TRANS_TX_CREDIT_TIMEOUT_ERR, /* 0x21c */ 370 TRANS_TX_IPTT_CONFLICT_ERR, /* 0x21d */ 371 TRANS_TX_TXFRM_TYPE_ERR, /* 0x21e */ 372 TRANS_TX_TXSMP_LENGTH_ERR, /* 0x21f */ 373 374 /* trans rx */ 375 TRANS_RX_FRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x300 */ 376 TRANS_RX_FRAME_DONE_ERR, /* 0x301 */ 377 TRANS_RX_FRAME_ERRPRM_ERR, /* 0x302 */ 378 TRANS_RX_FRAME_NO_CREDIT_ERR, /* 0x303 */ 379 TRANS_RX_RSVD0_ERR, /* 0x304 */ 380 TRANS_RX_FRAME_OVERRUN_ERR, /* 0x305 */ 381 TRANS_RX_FRAME_NO_EOF_ERR, /* 0x306 */ 382 TRANS_RX_LINK_BUF_OVERRUN_ERR, /* 0x307 */ 383 TRANS_RX_BREAK_TIMEOUT_ERR, /* 0x308 */ 384 TRANS_RX_BREAK_REQUEST_ERR, /* 0x309 */ 385 TRANS_RX_BREAK_RECEIVE_ERR, /* 0x30a */ 386 TRANS_RX_CLOSE_TIMEOUT_ERR, /* 0x30b */ 387 TRANS_RX_CLOSE_NORMAL_ERR, /* 0x30c */ 388 TRANS_RX_CLOSE_PHYRESET_ERR, /* 0x30d */ 389 TRANS_RX_WITH_CLOSE_DWS_TIMEOUT_ERR, /* 0x30e */ 390 TRANS_RX_WITH_CLOSE_COMINIT_ERR, /* 0x30f */ 391 TRANS_RX_DATA_LENGTH0_ERR, /* 0x310 */ 392 TRANS_RX_BAD_HASH_ERR, /* 0x311 */ 393 TRANS_RX_XRDY_ZERO_ERR, /* 0x312 */ 394 TRANS_RX_SSP_FRAME_LEN_ERR, /* 0x313 */ 395 TRANS_RX_TRANS_RX_RSVD1_ERR, /* 0x314 */ 396 TRANS_RX_NO_BALANCE_ERR, /* 0x315 */ 397 TRANS_RX_TRANS_RX_RSVD2_ERR, /* 0x316 */ 398 TRANS_RX_TRANS_RX_RSVD3_ERR, /* 0x317 */ 399 TRANS_RX_BAD_FRAME_TYPE_ERR, /* 0x318 */ 400 TRANS_RX_SMP_FRAME_LEN_ERR, /* 0x319 */ 401 TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x31a */ 402 }; 403 404 #define HISI_SAS_COMMAND_ENTRIES_V1_HW 8192 405 406 #define HISI_SAS_PHY_MAX_INT_NR (HISI_SAS_PHY_INT_NR * HISI_SAS_MAX_PHYS) 407 #define HISI_SAS_CQ_MAX_INT_NR (HISI_SAS_MAX_QUEUES) 408 #define HISI_SAS_FATAL_INT_NR (2) 409 410 #define HISI_SAS_MAX_INT_NR \ 411 (HISI_SAS_PHY_MAX_INT_NR + HISI_SAS_CQ_MAX_INT_NR +\ 412 HISI_SAS_FATAL_INT_NR) 413 414 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) 415 { 416 void __iomem *regs = hisi_hba->regs + off; 417 418 return readl(regs); 419 } 420 421 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off) 422 { 423 void __iomem *regs = hisi_hba->regs + off; 424 425 return readl_relaxed(regs); 426 } 427 428 static void hisi_sas_write32(struct hisi_hba *hisi_hba, 429 u32 off, u32 val) 430 { 431 void __iomem *regs = hisi_hba->regs + off; 432 433 writel(val, regs); 434 } 435 436 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, 437 int phy_no, u32 off, u32 val) 438 { 439 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 440 441 writel(val, regs); 442 } 443 444 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba, 445 int phy_no, u32 off) 446 { 447 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; 448 449 return readl(regs); 450 } 451 452 static void config_phy_opt_mode_v1_hw(struct hisi_hba *hisi_hba, int phy_no) 453 { 454 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 455 456 cfg &= ~PHY_CFG_DC_OPT_MSK; 457 cfg |= 1 << PHY_CFG_DC_OPT_OFF; 458 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 459 } 460 461 static void config_tx_tfe_autoneg_v1_hw(struct hisi_hba *hisi_hba, int phy_no) 462 { 463 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CONFIG2); 464 465 cfg &= ~PHY_CONFIG2_FORCE_TXDEEMPH_MSK; 466 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CONFIG2, cfg); 467 } 468 469 static void config_id_frame_v1_hw(struct hisi_hba *hisi_hba, int phy_no) 470 { 471 struct sas_identify_frame identify_frame; 472 u32 *identify_buffer; 473 474 memset(&identify_frame, 0, sizeof(identify_frame)); 475 identify_frame.dev_type = SAS_END_DEVICE; 476 identify_frame.frame_type = 0; 477 identify_frame._un1 = 1; 478 identify_frame.initiator_bits = SAS_PROTOCOL_ALL; 479 identify_frame.target_bits = SAS_PROTOCOL_NONE; 480 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 481 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); 482 identify_frame.phy_id = phy_no; 483 identify_buffer = (u32 *)(&identify_frame); 484 485 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0, 486 __swab32(identify_buffer[0])); 487 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1, 488 __swab32(identify_buffer[1])); 489 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2, 490 __swab32(identify_buffer[2])); 491 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3, 492 __swab32(identify_buffer[3])); 493 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4, 494 __swab32(identify_buffer[4])); 495 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5, 496 __swab32(identify_buffer[5])); 497 } 498 499 static void setup_itct_v1_hw(struct hisi_hba *hisi_hba, 500 struct hisi_sas_device *sas_dev) 501 { 502 struct domain_device *device = sas_dev->sas_device; 503 struct device *dev = hisi_hba->dev; 504 u64 qw0, device_id = sas_dev->device_id; 505 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id]; 506 struct asd_sas_port *sas_port = device->port; 507 struct hisi_sas_port *port = to_hisi_sas_port(sas_port); 508 u64 sas_addr; 509 510 memset(itct, 0, sizeof(*itct)); 511 512 /* qw0 */ 513 qw0 = 0; 514 switch (sas_dev->dev_type) { 515 case SAS_END_DEVICE: 516 case SAS_EDGE_EXPANDER_DEVICE: 517 case SAS_FANOUT_EXPANDER_DEVICE: 518 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF; 519 break; 520 default: 521 dev_warn(dev, "setup itct: unsupported dev type (%d)\n", 522 sas_dev->dev_type); 523 } 524 525 qw0 |= ((1 << ITCT_HDR_VALID_OFF) | 526 (1 << ITCT_HDR_AWT_CONTROL_OFF) | 527 (device->max_linkrate << ITCT_HDR_MAX_CONN_RATE_OFF) | 528 (1 << ITCT_HDR_VALID_LINK_NUM_OFF) | 529 (port->id << ITCT_HDR_PORT_ID_OFF)); 530 itct->qw0 = cpu_to_le64(qw0); 531 532 /* qw1 */ 533 memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE); 534 itct->sas_addr = cpu_to_le64(__swab64(sas_addr)); 535 536 /* qw2 */ 537 itct->qw2 = cpu_to_le64((500ULL << ITCT_HDR_IT_NEXUS_LOSS_TL_OFF) | 538 (0xff00ULL << ITCT_HDR_BUS_INACTIVE_TL_OFF) | 539 (0xff00ULL << ITCT_HDR_MAX_CONN_TL_OFF) | 540 (0xff00ULL << ITCT_HDR_REJ_OPEN_TL_OFF)); 541 } 542 543 static void clear_itct_v1_hw(struct hisi_hba *hisi_hba, 544 struct hisi_sas_device *sas_dev) 545 { 546 u64 dev_id = sas_dev->device_id; 547 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id]; 548 u64 qw0; 549 u32 reg_val = hisi_sas_read32(hisi_hba, CFG_AGING_TIME); 550 551 reg_val |= CFG_AGING_TIME_ITCT_REL_MSK; 552 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, reg_val); 553 554 /* free itct */ 555 udelay(1); 556 reg_val = hisi_sas_read32(hisi_hba, CFG_AGING_TIME); 557 reg_val &= ~CFG_AGING_TIME_ITCT_REL_MSK; 558 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, reg_val); 559 560 qw0 = le64_to_cpu(itct->qw0); 561 qw0 &= ~ITCT_HDR_VALID_MSK; 562 itct->qw0 = cpu_to_le64(qw0); 563 } 564 565 static int reset_hw_v1_hw(struct hisi_hba *hisi_hba) 566 { 567 int i; 568 unsigned long end_time; 569 u32 val; 570 struct device *dev = hisi_hba->dev; 571 572 for (i = 0; i < hisi_hba->n_phy; i++) { 573 u32 phy_ctrl = hisi_sas_phy_read32(hisi_hba, i, PHY_CTRL); 574 575 phy_ctrl |= PHY_CTRL_RESET_MSK; 576 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, phy_ctrl); 577 } 578 msleep(1); /* It is safe to wait for 50us */ 579 580 /* Ensure DMA tx & rx idle */ 581 for (i = 0; i < hisi_hba->n_phy; i++) { 582 u32 dma_tx_status, dma_rx_status; 583 584 end_time = jiffies + msecs_to_jiffies(1000); 585 586 while (1) { 587 dma_tx_status = hisi_sas_phy_read32(hisi_hba, i, 588 DMA_TX_STATUS); 589 dma_rx_status = hisi_sas_phy_read32(hisi_hba, i, 590 DMA_RX_STATUS); 591 592 if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) && 593 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK)) 594 break; 595 596 msleep(20); 597 if (time_after(jiffies, end_time)) 598 return -EIO; 599 } 600 } 601 602 /* Ensure axi bus idle */ 603 end_time = jiffies + msecs_to_jiffies(1000); 604 while (1) { 605 u32 axi_status = 606 hisi_sas_read32(hisi_hba, AXI_CFG); 607 608 if (axi_status == 0) 609 break; 610 611 msleep(20); 612 if (time_after(jiffies, end_time)) 613 return -EIO; 614 } 615 616 if (ACPI_HANDLE(dev)) { 617 acpi_status s; 618 619 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL); 620 if (ACPI_FAILURE(s)) { 621 dev_err(dev, "Reset failed\n"); 622 return -EIO; 623 } 624 } else if (hisi_hba->ctrl) { 625 /* Apply reset and disable clock */ 626 /* clk disable reg is offset by +4 bytes from clk enable reg */ 627 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg, 628 RESET_VALUE); 629 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4, 630 RESET_VALUE); 631 msleep(1); 632 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val); 633 if (RESET_VALUE != (val & RESET_VALUE)) { 634 dev_err(dev, "Reset failed\n"); 635 return -EIO; 636 } 637 638 /* De-reset and enable clock */ 639 /* deassert rst reg is offset by +4 bytes from assert reg */ 640 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4, 641 RESET_VALUE); 642 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg, 643 RESET_VALUE); 644 msleep(1); 645 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val); 646 if (val & RESET_VALUE) { 647 dev_err(dev, "De-reset failed\n"); 648 return -EIO; 649 } 650 } else { 651 dev_warn(dev, "no reset method\n"); 652 return -EINVAL; 653 } 654 655 return 0; 656 } 657 658 static void init_reg_v1_hw(struct hisi_hba *hisi_hba) 659 { 660 int i; 661 662 /* Global registers init*/ 663 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 664 (u32)((1ULL << hisi_hba->queue_count) - 1)); 665 hisi_sas_write32(hisi_hba, HGC_TRANS_TASK_CNT_LIMIT, 0x11); 666 hisi_sas_write32(hisi_hba, DEVICE_MSG_WORK_MODE, 0x1); 667 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x1ff); 668 hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x401); 669 hisi_sas_write32(hisi_hba, CFG_1US_TIMER_TRSH, 0x64); 670 hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1); 671 hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x64); 672 hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x2710); 673 hisi_sas_write32(hisi_hba, REJECT_TO_OPEN_LIMIT_TIME, 0x1); 674 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x7a12); 675 hisi_sas_write32(hisi_hba, HGC_DFX_CFG2, 0x9c40); 676 hisi_sas_write32(hisi_hba, FIS_LIST_BADDR_L, 0x2); 677 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0xc); 678 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x186a0); 679 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 1); 680 hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1); 681 hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1); 682 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffffffff); 683 hisi_sas_write32(hisi_hba, OQ_INT_SRC_MSK, 0); 684 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff); 685 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0); 686 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff); 687 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0); 688 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0); 689 hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 0x2); 690 hisi_sas_write32(hisi_hba, CFG_SAS_CONFIG, 0x22000000); 691 692 for (i = 0; i < hisi_hba->n_phy; i++) { 693 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x88a); 694 hisi_sas_phy_write32(hisi_hba, i, PHY_CONFIG2, 0x7c080); 695 hisi_sas_phy_write32(hisi_hba, i, PHY_RATE_NEGO, 0x415ee00); 696 hisi_sas_phy_write32(hisi_hba, i, PHY_PCN, 0x80a80000); 697 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d); 698 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x0); 699 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000); 700 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0); 701 hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x13f0a); 702 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 3); 703 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 8); 704 } 705 706 for (i = 0; i < hisi_hba->queue_count; i++) { 707 /* Delivery queue */ 708 hisi_sas_write32(hisi_hba, 709 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14), 710 upper_32_bits(hisi_hba->cmd_hdr_dma[i])); 711 712 hisi_sas_write32(hisi_hba, 713 DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14), 714 lower_32_bits(hisi_hba->cmd_hdr_dma[i])); 715 716 hisi_sas_write32(hisi_hba, 717 DLVRY_Q_0_DEPTH + (i * 0x14), 718 HISI_SAS_QUEUE_SLOTS); 719 720 /* Completion queue */ 721 hisi_sas_write32(hisi_hba, 722 COMPL_Q_0_BASE_ADDR_HI + (i * 0x14), 723 upper_32_bits(hisi_hba->complete_hdr_dma[i])); 724 725 hisi_sas_write32(hisi_hba, 726 COMPL_Q_0_BASE_ADDR_LO + (i * 0x14), 727 lower_32_bits(hisi_hba->complete_hdr_dma[i])); 728 729 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14), 730 HISI_SAS_QUEUE_SLOTS); 731 } 732 733 /* itct */ 734 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO, 735 lower_32_bits(hisi_hba->itct_dma)); 736 737 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI, 738 upper_32_bits(hisi_hba->itct_dma)); 739 740 /* iost */ 741 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO, 742 lower_32_bits(hisi_hba->iost_dma)); 743 744 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI, 745 upper_32_bits(hisi_hba->iost_dma)); 746 747 /* breakpoint */ 748 hisi_sas_write32(hisi_hba, BROKEN_MSG_ADDR_LO, 749 lower_32_bits(hisi_hba->breakpoint_dma)); 750 751 hisi_sas_write32(hisi_hba, BROKEN_MSG_ADDR_HI, 752 upper_32_bits(hisi_hba->breakpoint_dma)); 753 } 754 755 static int hw_init_v1_hw(struct hisi_hba *hisi_hba) 756 { 757 struct device *dev = hisi_hba->dev; 758 int rc; 759 760 rc = reset_hw_v1_hw(hisi_hba); 761 if (rc) { 762 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc); 763 return rc; 764 } 765 766 msleep(100); 767 init_reg_v1_hw(hisi_hba); 768 769 return 0; 770 } 771 772 static void enable_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no) 773 { 774 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 775 776 cfg |= PHY_CFG_ENA_MSK; 777 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 778 } 779 780 static void disable_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no) 781 { 782 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); 783 784 cfg &= ~PHY_CFG_ENA_MSK; 785 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); 786 } 787 788 static void start_phy_v1_hw(struct hisi_hba *hisi_hba, int phy_no) 789 { 790 config_id_frame_v1_hw(hisi_hba, phy_no); 791 config_phy_opt_mode_v1_hw(hisi_hba, phy_no); 792 config_tx_tfe_autoneg_v1_hw(hisi_hba, phy_no); 793 enable_phy_v1_hw(hisi_hba, phy_no); 794 } 795 796 static void phy_hard_reset_v1_hw(struct hisi_hba *hisi_hba, int phy_no) 797 { 798 hisi_sas_phy_enable(hisi_hba, phy_no, 0); 799 msleep(100); 800 hisi_sas_phy_enable(hisi_hba, phy_no, 1); 801 } 802 803 static void start_phys_v1_hw(struct timer_list *t) 804 { 805 struct hisi_hba *hisi_hba = from_timer(hisi_hba, t, timer); 806 int i; 807 808 for (i = 0; i < hisi_hba->n_phy; i++) { 809 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x12a); 810 hisi_sas_phy_enable(hisi_hba, i, 1); 811 } 812 } 813 814 static void phys_init_v1_hw(struct hisi_hba *hisi_hba) 815 { 816 int i; 817 struct timer_list *timer = &hisi_hba->timer; 818 819 for (i = 0; i < hisi_hba->n_phy; i++) { 820 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x6a); 821 hisi_sas_phy_read32(hisi_hba, i, CHL_INT2_MSK); 822 } 823 824 timer_setup(timer, start_phys_v1_hw, 0); 825 mod_timer(timer, jiffies + HZ); 826 } 827 828 static void sl_notify_ssp_v1_hw(struct hisi_hba *hisi_hba, int phy_no) 829 { 830 u32 sl_control; 831 832 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 833 sl_control |= SL_CONTROL_NOTIFY_EN_MSK; 834 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 835 msleep(1); 836 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); 837 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK; 838 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); 839 } 840 841 static enum sas_linkrate phy_get_max_linkrate_v1_hw(void) 842 { 843 return SAS_LINK_RATE_6_0_GBPS; 844 } 845 846 static void phy_set_linkrate_v1_hw(struct hisi_hba *hisi_hba, int phy_no, 847 struct sas_phy_linkrates *r) 848 { 849 enum sas_linkrate max = r->maximum_linkrate; 850 u32 prog_phy_link_rate = 0x800; 851 852 prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max); 853 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, 854 prog_phy_link_rate); 855 } 856 857 static int get_wideport_bitmap_v1_hw(struct hisi_hba *hisi_hba, int port_id) 858 { 859 int i, bitmap = 0; 860 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); 861 862 for (i = 0; i < hisi_hba->n_phy; i++) 863 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id) 864 bitmap |= 1 << i; 865 866 return bitmap; 867 } 868 869 /* 870 * The callpath to this function and upto writing the write 871 * queue pointer should be safe from interruption. 872 */ 873 static int 874 get_free_slot_v1_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq) 875 { 876 struct device *dev = hisi_hba->dev; 877 int queue = dq->id; 878 u32 r, w; 879 880 w = dq->wr_point; 881 r = hisi_sas_read32_relaxed(hisi_hba, 882 DLVRY_Q_0_RD_PTR + (queue * 0x14)); 883 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) { 884 dev_warn(dev, "could not find free slot\n"); 885 return -EAGAIN; 886 } 887 888 dq->wr_point = (dq->wr_point + 1) % HISI_SAS_QUEUE_SLOTS; 889 890 return w; 891 } 892 893 /* DQ lock must be taken here */ 894 static void start_delivery_v1_hw(struct hisi_sas_dq *dq) 895 { 896 struct hisi_hba *hisi_hba = dq->hisi_hba; 897 struct hisi_sas_slot *s, *s1, *s2 = NULL; 898 int dlvry_queue = dq->id; 899 int wp; 900 901 list_for_each_entry_safe(s, s1, &dq->list, delivery) { 902 if (!s->ready) 903 break; 904 s2 = s; 905 list_del(&s->delivery); 906 } 907 908 if (!s2) 909 return; 910 911 /* 912 * Ensure that memories for slots built on other CPUs is observed. 913 */ 914 smp_rmb(); 915 wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS; 916 917 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp); 918 } 919 920 static void prep_prd_sge_v1_hw(struct hisi_hba *hisi_hba, 921 struct hisi_sas_slot *slot, 922 struct hisi_sas_cmd_hdr *hdr, 923 struct scatterlist *scatter, 924 int n_elem) 925 { 926 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot); 927 struct scatterlist *sg; 928 int i; 929 930 for_each_sg(scatter, sg, n_elem, i) { 931 struct hisi_sas_sge *entry = &sge_page->sge[i]; 932 933 entry->addr = cpu_to_le64(sg_dma_address(sg)); 934 entry->page_ctrl_0 = entry->page_ctrl_1 = 0; 935 entry->data_len = cpu_to_le32(sg_dma_len(sg)); 936 entry->data_off = 0; 937 } 938 939 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot)); 940 941 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF); 942 } 943 944 static void prep_smp_v1_hw(struct hisi_hba *hisi_hba, 945 struct hisi_sas_slot *slot) 946 { 947 struct sas_task *task = slot->task; 948 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 949 struct domain_device *device = task->dev; 950 struct hisi_sas_port *port = slot->port; 951 struct scatterlist *sg_req; 952 struct hisi_sas_device *sas_dev = device->lldd_dev; 953 dma_addr_t req_dma_addr; 954 unsigned int req_len; 955 956 /* req */ 957 sg_req = &task->smp_task.smp_req; 958 req_len = sg_dma_len(sg_req); 959 req_dma_addr = sg_dma_address(sg_req); 960 961 /* create header */ 962 /* dw0 */ 963 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) | 964 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */ 965 (1 << CMD_HDR_MODE_OFF) | /* ini mode */ 966 (2 << CMD_HDR_CMD_OFF)); /* smp */ 967 968 /* map itct entry */ 969 hdr->dw1 = cpu_to_le32(sas_dev->device_id << CMD_HDR_DEVICE_ID_OFF); 970 971 /* dw2 */ 972 hdr->dw2 = cpu_to_le32((((req_len-4)/4) << CMD_HDR_CFL_OFF) | 973 (HISI_SAS_MAX_SMP_RESP_SZ/4 << 974 CMD_HDR_MRFL_OFF)); 975 976 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF); 977 978 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr); 979 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 980 } 981 982 static void prep_ssp_v1_hw(struct hisi_hba *hisi_hba, 983 struct hisi_sas_slot *slot) 984 { 985 struct sas_task *task = slot->task; 986 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; 987 struct domain_device *device = task->dev; 988 struct hisi_sas_device *sas_dev = device->lldd_dev; 989 struct hisi_sas_port *port = slot->port; 990 struct sas_ssp_task *ssp_task = &task->ssp_task; 991 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd; 992 struct hisi_sas_tmf_task *tmf = slot->tmf; 993 int has_data = 0, priority = !!tmf; 994 u8 *buf_cmd, fburst = 0; 995 u32 dw1, dw2; 996 997 /* create header */ 998 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) | 999 (0x2 << CMD_HDR_TLR_CTRL_OFF) | 1000 (port->id << CMD_HDR_PORT_OFF) | 1001 (priority << CMD_HDR_PRIORITY_OFF) | 1002 (1 << CMD_HDR_MODE_OFF) | /* ini mode */ 1003 (1 << CMD_HDR_CMD_OFF)); /* ssp */ 1004 1005 dw1 = 1 << CMD_HDR_VERIFY_DTL_OFF; 1006 1007 if (tmf) { 1008 dw1 |= 3 << CMD_HDR_SSP_FRAME_TYPE_OFF; 1009 } else { 1010 switch (scsi_cmnd->sc_data_direction) { 1011 case DMA_TO_DEVICE: 1012 dw1 |= 2 << CMD_HDR_SSP_FRAME_TYPE_OFF; 1013 has_data = 1; 1014 break; 1015 case DMA_FROM_DEVICE: 1016 dw1 |= 1 << CMD_HDR_SSP_FRAME_TYPE_OFF; 1017 has_data = 1; 1018 break; 1019 default: 1020 dw1 |= 0 << CMD_HDR_SSP_FRAME_TYPE_OFF; 1021 } 1022 } 1023 1024 /* map itct entry */ 1025 dw1 |= sas_dev->device_id << CMD_HDR_DEVICE_ID_OFF; 1026 hdr->dw1 = cpu_to_le32(dw1); 1027 1028 if (tmf) { 1029 dw2 = ((sizeof(struct ssp_tmf_iu) + 1030 sizeof(struct ssp_frame_hdr)+3)/4) << 1031 CMD_HDR_CFL_OFF; 1032 } else { 1033 dw2 = ((sizeof(struct ssp_command_iu) + 1034 sizeof(struct ssp_frame_hdr)+3)/4) << 1035 CMD_HDR_CFL_OFF; 1036 } 1037 1038 dw2 |= (HISI_SAS_MAX_SSP_RESP_SZ/4) << CMD_HDR_MRFL_OFF; 1039 1040 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF); 1041 1042 if (has_data) 1043 prep_prd_sge_v1_hw(hisi_hba, slot, hdr, task->scatter, 1044 slot->n_elem); 1045 1046 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); 1047 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); 1048 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); 1049 1050 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) + 1051 sizeof(struct ssp_frame_hdr); 1052 if (task->ssp_task.enable_first_burst) { 1053 fburst = (1 << 7); 1054 dw2 |= 1 << CMD_HDR_FIRST_BURST_OFF; 1055 } 1056 hdr->dw2 = cpu_to_le32(dw2); 1057 1058 memcpy(buf_cmd, &task->ssp_task.LUN, 8); 1059 if (!tmf) { 1060 buf_cmd[9] = fburst | task->ssp_task.task_attr | 1061 (task->ssp_task.task_prio << 3); 1062 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd, 1063 task->ssp_task.cmd->cmd_len); 1064 } else { 1065 buf_cmd[10] = tmf->tmf; 1066 switch (tmf->tmf) { 1067 case TMF_ABORT_TASK: 1068 case TMF_QUERY_TASK: 1069 buf_cmd[12] = 1070 (tmf->tag_of_task_to_be_managed >> 8) & 0xff; 1071 buf_cmd[13] = 1072 tmf->tag_of_task_to_be_managed & 0xff; 1073 break; 1074 default: 1075 break; 1076 } 1077 } 1078 } 1079 1080 /* by default, task resp is complete */ 1081 static void slot_err_v1_hw(struct hisi_hba *hisi_hba, 1082 struct sas_task *task, 1083 struct hisi_sas_slot *slot) 1084 { 1085 struct task_status_struct *ts = &task->task_status; 1086 struct hisi_sas_err_record_v1 *err_record = 1087 hisi_sas_status_buf_addr_mem(slot); 1088 struct device *dev = hisi_hba->dev; 1089 1090 switch (task->task_proto) { 1091 case SAS_PROTOCOL_SSP: 1092 { 1093 int error = -1; 1094 u32 dma_err_type = le32_to_cpu(err_record->dma_err_type); 1095 u32 dma_tx_err_type = ((dma_err_type & 1096 ERR_HDR_DMA_TX_ERR_TYPE_MSK)) >> 1097 ERR_HDR_DMA_TX_ERR_TYPE_OFF; 1098 u32 dma_rx_err_type = ((dma_err_type & 1099 ERR_HDR_DMA_RX_ERR_TYPE_MSK)) >> 1100 ERR_HDR_DMA_RX_ERR_TYPE_OFF; 1101 u32 trans_tx_fail_type = 1102 le32_to_cpu(err_record->trans_tx_fail_type); 1103 u32 trans_rx_fail_type = 1104 le32_to_cpu(err_record->trans_rx_fail_type); 1105 1106 if (dma_tx_err_type) { 1107 /* dma tx err */ 1108 error = ffs(dma_tx_err_type) 1109 - 1 + DMA_TX_ERR_BASE; 1110 } else if (dma_rx_err_type) { 1111 /* dma rx err */ 1112 error = ffs(dma_rx_err_type) 1113 - 1 + DMA_RX_ERR_BASE; 1114 } else if (trans_tx_fail_type) { 1115 /* trans tx err */ 1116 error = ffs(trans_tx_fail_type) 1117 - 1 + TRANS_TX_FAIL_BASE; 1118 } else if (trans_rx_fail_type) { 1119 /* trans rx err */ 1120 error = ffs(trans_rx_fail_type) 1121 - 1 + TRANS_RX_FAIL_BASE; 1122 } 1123 1124 switch (error) { 1125 case DMA_TX_DATA_UNDERFLOW_ERR: 1126 case DMA_RX_DATA_UNDERFLOW_ERR: 1127 { 1128 ts->residual = 0; 1129 ts->stat = SAS_DATA_UNDERRUN; 1130 break; 1131 } 1132 case DMA_TX_DATA_SGL_OVERFLOW_ERR: 1133 case DMA_TX_DIF_SGL_OVERFLOW_ERR: 1134 case DMA_TX_XFER_RDY_LENGTH_OVERFLOW_ERR: 1135 case DMA_RX_DATA_OVERFLOW_ERR: 1136 case TRANS_RX_FRAME_OVERRUN_ERR: 1137 case TRANS_RX_LINK_BUF_OVERRUN_ERR: 1138 { 1139 ts->stat = SAS_DATA_OVERRUN; 1140 ts->residual = 0; 1141 break; 1142 } 1143 case TRANS_TX_PHY_NOT_ENABLE_ERR: 1144 { 1145 ts->stat = SAS_PHY_DOWN; 1146 break; 1147 } 1148 case TRANS_TX_OPEN_REJCT_WRONG_DEST_ERR: 1149 case TRANS_TX_OPEN_REJCT_ZONE_VIOLATION_ERR: 1150 case TRANS_TX_OPEN_REJCT_BY_OTHER_ERR: 1151 case TRANS_TX_OPEN_REJCT_AIP_TIMEOUT_ERR: 1152 case TRANS_TX_OPEN_REJCT_STP_BUSY_ERR: 1153 case TRANS_TX_OPEN_REJCT_PROTOCOL_NOT_SUPPORT_ERR: 1154 case TRANS_TX_OPEN_REJCT_RATE_NOT_SUPPORT_ERR: 1155 case TRANS_TX_OPEN_REJCT_BAD_DEST_ERR: 1156 case TRANS_TX_OPEN_BREAK_RECEIVE_ERR: 1157 case TRANS_TX_OPEN_REJCT_PATHWAY_BLOCKED_ERR: 1158 case TRANS_TX_OPEN_REJCT_NO_DEST_ERR: 1159 case TRANS_TX_OPEN_RETRY_ERR: 1160 { 1161 ts->stat = SAS_OPEN_REJECT; 1162 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1163 break; 1164 } 1165 case TRANS_TX_OPEN_TIMEOUT_ERR: 1166 { 1167 ts->stat = SAS_OPEN_TO; 1168 break; 1169 } 1170 case TRANS_TX_NAK_RECEIVE_ERR: 1171 case TRANS_TX_ACK_NAK_TIMEOUT_ERR: 1172 { 1173 ts->stat = SAS_NAK_R_ERR; 1174 break; 1175 } 1176 case TRANS_TX_CREDIT_TIMEOUT_ERR: 1177 case TRANS_TX_CLOSE_NORMAL_ERR: 1178 { 1179 /* This will request a retry */ 1180 ts->stat = SAS_QUEUE_FULL; 1181 slot->abort = 1; 1182 break; 1183 } 1184 default: 1185 { 1186 ts->stat = SAM_STAT_CHECK_CONDITION; 1187 break; 1188 } 1189 } 1190 } 1191 break; 1192 case SAS_PROTOCOL_SMP: 1193 ts->stat = SAM_STAT_CHECK_CONDITION; 1194 break; 1195 1196 case SAS_PROTOCOL_SATA: 1197 case SAS_PROTOCOL_STP: 1198 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 1199 { 1200 dev_err(dev, "slot err: SATA/STP not supported"); 1201 } 1202 break; 1203 default: 1204 break; 1205 } 1206 1207 } 1208 1209 static int slot_complete_v1_hw(struct hisi_hba *hisi_hba, 1210 struct hisi_sas_slot *slot) 1211 { 1212 struct sas_task *task = slot->task; 1213 struct hisi_sas_device *sas_dev; 1214 struct device *dev = hisi_hba->dev; 1215 struct task_status_struct *ts; 1216 struct domain_device *device; 1217 enum exec_status sts; 1218 struct hisi_sas_complete_v1_hdr *complete_queue = 1219 hisi_hba->complete_hdr[slot->cmplt_queue]; 1220 struct hisi_sas_complete_v1_hdr *complete_hdr; 1221 unsigned long flags; 1222 u32 cmplt_hdr_data; 1223 1224 complete_hdr = &complete_queue[slot->cmplt_queue_slot]; 1225 cmplt_hdr_data = le32_to_cpu(complete_hdr->data); 1226 1227 if (unlikely(!task || !task->lldd_task || !task->dev)) 1228 return -EINVAL; 1229 1230 ts = &task->task_status; 1231 device = task->dev; 1232 sas_dev = device->lldd_dev; 1233 1234 spin_lock_irqsave(&task->task_state_lock, flags); 1235 task->task_state_flags &= 1236 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR); 1237 task->task_state_flags |= SAS_TASK_STATE_DONE; 1238 spin_unlock_irqrestore(&task->task_state_lock, flags); 1239 1240 memset(ts, 0, sizeof(*ts)); 1241 ts->resp = SAS_TASK_COMPLETE; 1242 1243 if (unlikely(!sas_dev)) { 1244 dev_dbg(dev, "slot complete: port has no device\n"); 1245 ts->stat = SAS_PHY_DOWN; 1246 goto out; 1247 } 1248 1249 if (cmplt_hdr_data & CMPLT_HDR_IO_CFG_ERR_MSK) { 1250 u32 info_reg = hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO); 1251 1252 if (info_reg & HGC_INVLD_DQE_INFO_DQ_MSK) 1253 dev_err(dev, "slot complete: [%d:%d] has dq IPTT err", 1254 slot->cmplt_queue, slot->cmplt_queue_slot); 1255 1256 if (info_reg & HGC_INVLD_DQE_INFO_TYPE_MSK) 1257 dev_err(dev, "slot complete: [%d:%d] has dq type err", 1258 slot->cmplt_queue, slot->cmplt_queue_slot); 1259 1260 if (info_reg & HGC_INVLD_DQE_INFO_FORCE_MSK) 1261 dev_err(dev, "slot complete: [%d:%d] has dq force phy err", 1262 slot->cmplt_queue, slot->cmplt_queue_slot); 1263 1264 if (info_reg & HGC_INVLD_DQE_INFO_PHY_MSK) 1265 dev_err(dev, "slot complete: [%d:%d] has dq phy id err", 1266 slot->cmplt_queue, slot->cmplt_queue_slot); 1267 1268 if (info_reg & HGC_INVLD_DQE_INFO_ABORT_MSK) 1269 dev_err(dev, "slot complete: [%d:%d] has dq abort flag err", 1270 slot->cmplt_queue, slot->cmplt_queue_slot); 1271 1272 if (info_reg & HGC_INVLD_DQE_INFO_IPTT_OF_MSK) 1273 dev_err(dev, "slot complete: [%d:%d] has dq IPTT or ICT err", 1274 slot->cmplt_queue, slot->cmplt_queue_slot); 1275 1276 if (info_reg & HGC_INVLD_DQE_INFO_SSP_ERR_MSK) 1277 dev_err(dev, "slot complete: [%d:%d] has dq SSP frame type err", 1278 slot->cmplt_queue, slot->cmplt_queue_slot); 1279 1280 if (info_reg & HGC_INVLD_DQE_INFO_OFL_MSK) 1281 dev_err(dev, "slot complete: [%d:%d] has dq order frame len err", 1282 slot->cmplt_queue, slot->cmplt_queue_slot); 1283 1284 ts->stat = SAS_OPEN_REJECT; 1285 ts->open_rej_reason = SAS_OREJ_UNKNOWN; 1286 goto out; 1287 } 1288 1289 if (cmplt_hdr_data & CMPLT_HDR_ERR_RCRD_XFRD_MSK && 1290 !(cmplt_hdr_data & CMPLT_HDR_RSPNS_XFRD_MSK)) { 1291 1292 slot_err_v1_hw(hisi_hba, task, slot); 1293 if (unlikely(slot->abort)) 1294 return ts->stat; 1295 goto out; 1296 } 1297 1298 switch (task->task_proto) { 1299 case SAS_PROTOCOL_SSP: 1300 { 1301 struct hisi_sas_status_buffer *status_buffer = 1302 hisi_sas_status_buf_addr_mem(slot); 1303 struct ssp_response_iu *iu = (struct ssp_response_iu *) 1304 &status_buffer->iu[0]; 1305 1306 sas_ssp_task_response(dev, task, iu); 1307 break; 1308 } 1309 case SAS_PROTOCOL_SMP: 1310 { 1311 void *to; 1312 struct scatterlist *sg_resp = &task->smp_task.smp_resp; 1313 1314 ts->stat = SAM_STAT_GOOD; 1315 to = kmap_atomic(sg_page(sg_resp)); 1316 1317 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1, 1318 DMA_FROM_DEVICE); 1319 dma_unmap_sg(dev, &task->smp_task.smp_req, 1, 1320 DMA_TO_DEVICE); 1321 memcpy(to + sg_resp->offset, 1322 hisi_sas_status_buf_addr_mem(slot) + 1323 sizeof(struct hisi_sas_err_record), 1324 sg_dma_len(sg_resp)); 1325 kunmap_atomic(to); 1326 break; 1327 } 1328 case SAS_PROTOCOL_SATA: 1329 case SAS_PROTOCOL_STP: 1330 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: 1331 dev_err(dev, "slot complete: SATA/STP not supported"); 1332 break; 1333 1334 default: 1335 ts->stat = SAM_STAT_CHECK_CONDITION; 1336 break; 1337 } 1338 1339 if (!slot->port->port_attached) { 1340 dev_err(dev, "slot complete: port %d has removed\n", 1341 slot->port->sas_port.id); 1342 ts->stat = SAS_PHY_DOWN; 1343 } 1344 1345 out: 1346 hisi_sas_slot_task_free(hisi_hba, task, slot); 1347 sts = ts->stat; 1348 1349 if (task->task_done) 1350 task->task_done(task); 1351 1352 return sts; 1353 } 1354 1355 /* Interrupts */ 1356 static irqreturn_t int_phyup_v1_hw(int irq_no, void *p) 1357 { 1358 struct hisi_sas_phy *phy = p; 1359 struct hisi_hba *hisi_hba = phy->hisi_hba; 1360 struct device *dev = hisi_hba->dev; 1361 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1362 int i, phy_no = sas_phy->id; 1363 u32 irq_value, context, port_id, link_rate; 1364 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd; 1365 struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd; 1366 irqreturn_t res = IRQ_HANDLED; 1367 unsigned long flags; 1368 1369 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2); 1370 if (!(irq_value & CHL_INT2_SL_PHY_ENA_MSK)) { 1371 dev_dbg(dev, "phyup: irq_value = %x not set enable bit\n", 1372 irq_value); 1373 res = IRQ_NONE; 1374 goto end; 1375 } 1376 1377 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT); 1378 if (context & 1 << phy_no) { 1379 dev_err(dev, "phyup: phy%d SATA attached equipment\n", 1380 phy_no); 1381 goto end; 1382 } 1383 1384 port_id = (hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA) >> (4 * phy_no)) 1385 & 0xf; 1386 if (port_id == 0xf) { 1387 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no); 1388 res = IRQ_NONE; 1389 goto end; 1390 } 1391 1392 for (i = 0; i < 6; i++) { 1393 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no, 1394 RX_IDAF_DWORD0 + (i * 4)); 1395 frame_rcvd[i] = __swab32(idaf); 1396 } 1397 1398 /* Get the linkrate */ 1399 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); 1400 link_rate = (link_rate >> (phy_no * 4)) & 0xf; 1401 sas_phy->linkrate = link_rate; 1402 sas_phy->oob_mode = SAS_OOB_MODE; 1403 memcpy(sas_phy->attached_sas_addr, 1404 &id->sas_addr, SAS_ADDR_SIZE); 1405 dev_info(dev, "phyup: phy%d link_rate=%d\n", 1406 phy_no, link_rate); 1407 phy->port_id = port_id; 1408 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); 1409 phy->phy_type |= PORT_TYPE_SAS; 1410 phy->phy_attached = 1; 1411 phy->identify.device_type = id->dev_type; 1412 phy->frame_rcvd_size = sizeof(struct sas_identify_frame); 1413 if (phy->identify.device_type == SAS_END_DEVICE) 1414 phy->identify.target_port_protocols = 1415 SAS_PROTOCOL_SSP; 1416 else if (phy->identify.device_type != SAS_PHY_UNUSED) 1417 phy->identify.target_port_protocols = 1418 SAS_PROTOCOL_SMP; 1419 hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP); 1420 1421 spin_lock_irqsave(&phy->lock, flags); 1422 if (phy->reset_completion) { 1423 phy->in_reset = 0; 1424 complete(phy->reset_completion); 1425 } 1426 spin_unlock_irqrestore(&phy->lock, flags); 1427 1428 end: 1429 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, 1430 CHL_INT2_SL_PHY_ENA_MSK); 1431 1432 if (irq_value & CHL_INT2_SL_PHY_ENA_MSK) { 1433 u32 chl_int0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0); 1434 1435 chl_int0 &= ~CHL_INT0_PHYCTRL_NOTRDY_MSK; 1436 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, chl_int0); 1437 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, 0x3ce3ee); 1438 } 1439 1440 return res; 1441 } 1442 1443 static irqreturn_t int_bcast_v1_hw(int irq, void *p) 1444 { 1445 struct hisi_sas_phy *phy = p; 1446 struct hisi_hba *hisi_hba = phy->hisi_hba; 1447 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1448 struct sas_ha_struct *sha = &hisi_hba->sha; 1449 struct device *dev = hisi_hba->dev; 1450 int phy_no = sas_phy->id; 1451 u32 irq_value; 1452 irqreturn_t res = IRQ_HANDLED; 1453 1454 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2); 1455 1456 if (!(irq_value & CHL_INT2_SL_RX_BC_ACK_MSK)) { 1457 dev_err(dev, "bcast: irq_value = %x not set enable bit", 1458 irq_value); 1459 res = IRQ_NONE; 1460 goto end; 1461 } 1462 1463 if (!test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)) 1464 sha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); 1465 1466 end: 1467 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, 1468 CHL_INT2_SL_RX_BC_ACK_MSK); 1469 1470 return res; 1471 } 1472 1473 static irqreturn_t int_abnormal_v1_hw(int irq, void *p) 1474 { 1475 struct hisi_sas_phy *phy = p; 1476 struct hisi_hba *hisi_hba = phy->hisi_hba; 1477 struct device *dev = hisi_hba->dev; 1478 struct asd_sas_phy *sas_phy = &phy->sas_phy; 1479 u32 irq_value, irq_mask_old; 1480 int phy_no = sas_phy->id; 1481 1482 /* mask_int0 */ 1483 irq_mask_old = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0_MSK); 1484 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, 0x3fffff); 1485 1486 /* read int0 */ 1487 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0); 1488 1489 if (irq_value & CHL_INT0_PHYCTRL_NOTRDY_MSK) { 1490 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); 1491 1492 hisi_sas_phy_down(hisi_hba, phy_no, 1493 (phy_state & 1 << phy_no) ? 1 : 0); 1494 } 1495 1496 if (irq_value & CHL_INT0_ID_TIMEOUT_MSK) 1497 dev_dbg(dev, "abnormal: ID_TIMEOUT phy%d identify timeout\n", 1498 phy_no); 1499 1500 if (irq_value & CHL_INT0_DWS_LOST_MSK) 1501 dev_dbg(dev, "abnormal: DWS_LOST phy%d dws lost\n", phy_no); 1502 1503 if (irq_value & CHL_INT0_SN_FAIL_NGR_MSK) 1504 dev_dbg(dev, "abnormal: SN_FAIL_NGR phy%d sn fail ngr\n", 1505 phy_no); 1506 1507 if (irq_value & CHL_INT0_SL_IDAF_FAIL_MSK || 1508 irq_value & CHL_INT0_SL_OPAF_FAIL_MSK) 1509 dev_dbg(dev, "abnormal: SL_ID/OPAF_FAIL phy%d check adr frm err\n", 1510 phy_no); 1511 1512 if (irq_value & CHL_INT0_SL_PS_FAIL_OFF) 1513 dev_dbg(dev, "abnormal: SL_PS_FAIL phy%d fail\n", phy_no); 1514 1515 /* write to zero */ 1516 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, irq_value); 1517 1518 if (irq_value & CHL_INT0_PHYCTRL_NOTRDY_MSK) 1519 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, 1520 0x3fffff & ~CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK); 1521 else 1522 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0_MSK, 1523 irq_mask_old); 1524 1525 return IRQ_HANDLED; 1526 } 1527 1528 static irqreturn_t cq_interrupt_v1_hw(int irq, void *p) 1529 { 1530 struct hisi_sas_cq *cq = p; 1531 struct hisi_hba *hisi_hba = cq->hisi_hba; 1532 struct hisi_sas_slot *slot; 1533 int queue = cq->id; 1534 struct hisi_sas_complete_v1_hdr *complete_queue = 1535 (struct hisi_sas_complete_v1_hdr *) 1536 hisi_hba->complete_hdr[queue]; 1537 u32 irq_value, rd_point = cq->rd_point, wr_point; 1538 1539 spin_lock(&hisi_hba->lock); 1540 irq_value = hisi_sas_read32(hisi_hba, OQ_INT_SRC); 1541 1542 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue); 1543 wr_point = hisi_sas_read32(hisi_hba, 1544 COMPL_Q_0_WR_PTR + (0x14 * queue)); 1545 1546 while (rd_point != wr_point) { 1547 struct hisi_sas_complete_v1_hdr *complete_hdr; 1548 int idx; 1549 u32 cmplt_hdr_data; 1550 1551 complete_hdr = &complete_queue[rd_point]; 1552 cmplt_hdr_data = le32_to_cpu(complete_hdr->data); 1553 idx = (cmplt_hdr_data & CMPLT_HDR_IPTT_MSK) >> 1554 CMPLT_HDR_IPTT_OFF; 1555 slot = &hisi_hba->slot_info[idx]; 1556 1557 /* The completion queue and queue slot index are not 1558 * necessarily the same as the delivery queue and 1559 * queue slot index. 1560 */ 1561 slot->cmplt_queue_slot = rd_point; 1562 slot->cmplt_queue = queue; 1563 slot_complete_v1_hw(hisi_hba, slot); 1564 1565 if (++rd_point >= HISI_SAS_QUEUE_SLOTS) 1566 rd_point = 0; 1567 } 1568 1569 /* update rd_point */ 1570 cq->rd_point = rd_point; 1571 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point); 1572 spin_unlock(&hisi_hba->lock); 1573 1574 return IRQ_HANDLED; 1575 } 1576 1577 static irqreturn_t fatal_ecc_int_v1_hw(int irq, void *p) 1578 { 1579 struct hisi_hba *hisi_hba = p; 1580 struct device *dev = hisi_hba->dev; 1581 u32 ecc_int = hisi_sas_read32(hisi_hba, SAS_ECC_INTR); 1582 1583 if (ecc_int & SAS_ECC_INTR_DQ_ECC1B_MSK) { 1584 u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR); 1585 1586 panic("%s: Fatal DQ 1b ECC interrupt (0x%x)\n", 1587 dev_name(dev), ecc_err); 1588 } 1589 1590 if (ecc_int & SAS_ECC_INTR_DQ_ECCBAD_MSK) { 1591 u32 addr = (hisi_sas_read32(hisi_hba, HGC_DQ_ECC_ADDR) & 1592 HGC_DQ_ECC_ADDR_BAD_MSK) >> 1593 HGC_DQ_ECC_ADDR_BAD_OFF; 1594 1595 panic("%s: Fatal DQ RAM ECC interrupt @ 0x%08x\n", 1596 dev_name(dev), addr); 1597 } 1598 1599 if (ecc_int & SAS_ECC_INTR_IOST_ECC1B_MSK) { 1600 u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR); 1601 1602 panic("%s: Fatal IOST 1b ECC interrupt (0x%x)\n", 1603 dev_name(dev), ecc_err); 1604 } 1605 1606 if (ecc_int & SAS_ECC_INTR_IOST_ECCBAD_MSK) { 1607 u32 addr = (hisi_sas_read32(hisi_hba, HGC_IOST_ECC_ADDR) & 1608 HGC_IOST_ECC_ADDR_BAD_MSK) >> 1609 HGC_IOST_ECC_ADDR_BAD_OFF; 1610 1611 panic("%s: Fatal IOST RAM ECC interrupt @ 0x%08x\n", 1612 dev_name(dev), addr); 1613 } 1614 1615 if (ecc_int & SAS_ECC_INTR_ITCT_ECCBAD_MSK) { 1616 u32 addr = (hisi_sas_read32(hisi_hba, HGC_ITCT_ECC_ADDR) & 1617 HGC_ITCT_ECC_ADDR_BAD_MSK) >> 1618 HGC_ITCT_ECC_ADDR_BAD_OFF; 1619 1620 panic("%s: Fatal TCT RAM ECC interrupt @ 0x%08x\n", 1621 dev_name(dev), addr); 1622 } 1623 1624 if (ecc_int & SAS_ECC_INTR_ITCT_ECC1B_MSK) { 1625 u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR); 1626 1627 panic("%s: Fatal ITCT 1b ECC interrupt (0x%x)\n", 1628 dev_name(dev), ecc_err); 1629 } 1630 1631 hisi_sas_write32(hisi_hba, SAS_ECC_INTR, ecc_int | 0x3f); 1632 1633 return IRQ_HANDLED; 1634 } 1635 1636 static irqreturn_t fatal_axi_int_v1_hw(int irq, void *p) 1637 { 1638 struct hisi_hba *hisi_hba = p; 1639 struct device *dev = hisi_hba->dev; 1640 u32 axi_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC2); 1641 u32 axi_info = hisi_sas_read32(hisi_hba, HGC_AXI_FIFO_ERR_INFO); 1642 1643 if (axi_int & ENT_INT_SRC2_DQ_CFG_ERR_MSK) 1644 panic("%s: Fatal DQ_CFG_ERR interrupt (0x%x)\n", 1645 dev_name(dev), axi_info); 1646 1647 if (axi_int & ENT_INT_SRC2_CQ_CFG_ERR_MSK) 1648 panic("%s: Fatal CQ_CFG_ERR interrupt (0x%x)\n", 1649 dev_name(dev), axi_info); 1650 1651 if (axi_int & ENT_INT_SRC2_AXI_WRONG_INT_MSK) 1652 panic("%s: Fatal AXI_WRONG_INT interrupt (0x%x)\n", 1653 dev_name(dev), axi_info); 1654 1655 if (axi_int & ENT_INT_SRC2_AXI_OVERLF_INT_MSK) 1656 panic("%s: Fatal AXI_OVERLF_INT incorrect interrupt (0x%x)\n", 1657 dev_name(dev), axi_info); 1658 1659 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, axi_int | 0x30000000); 1660 1661 return IRQ_HANDLED; 1662 } 1663 1664 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = { 1665 int_bcast_v1_hw, 1666 int_phyup_v1_hw, 1667 int_abnormal_v1_hw 1668 }; 1669 1670 static irq_handler_t fatal_interrupts[HISI_SAS_MAX_QUEUES] = { 1671 fatal_ecc_int_v1_hw, 1672 fatal_axi_int_v1_hw 1673 }; 1674 1675 static int interrupt_init_v1_hw(struct hisi_hba *hisi_hba) 1676 { 1677 struct platform_device *pdev = hisi_hba->platform_dev; 1678 struct device *dev = &pdev->dev; 1679 int i, j, irq, rc, idx; 1680 1681 for (i = 0; i < hisi_hba->n_phy; i++) { 1682 struct hisi_sas_phy *phy = &hisi_hba->phy[i]; 1683 1684 idx = i * HISI_SAS_PHY_INT_NR; 1685 for (j = 0; j < HISI_SAS_PHY_INT_NR; j++, idx++) { 1686 irq = platform_get_irq(pdev, idx); 1687 if (!irq) { 1688 dev_err(dev, "irq init: fail map phy interrupt %d\n", 1689 idx); 1690 return -ENOENT; 1691 } 1692 1693 rc = devm_request_irq(dev, irq, phy_interrupts[j], 0, 1694 DRV_NAME " phy", phy); 1695 if (rc) { 1696 dev_err(dev, "irq init: could not request phy interrupt %d, rc=%d\n", 1697 irq, rc); 1698 return -ENOENT; 1699 } 1700 } 1701 } 1702 1703 idx = hisi_hba->n_phy * HISI_SAS_PHY_INT_NR; 1704 for (i = 0; i < hisi_hba->queue_count; i++, idx++) { 1705 irq = platform_get_irq(pdev, idx); 1706 if (!irq) { 1707 dev_err(dev, "irq init: could not map cq interrupt %d\n", 1708 idx); 1709 return -ENOENT; 1710 } 1711 1712 rc = devm_request_irq(dev, irq, cq_interrupt_v1_hw, 0, 1713 DRV_NAME " cq", &hisi_hba->cq[i]); 1714 if (rc) { 1715 dev_err(dev, "irq init: could not request cq interrupt %d, rc=%d\n", 1716 irq, rc); 1717 return -ENOENT; 1718 } 1719 } 1720 1721 idx = (hisi_hba->n_phy * HISI_SAS_PHY_INT_NR) + hisi_hba->queue_count; 1722 for (i = 0; i < HISI_SAS_FATAL_INT_NR; i++, idx++) { 1723 irq = platform_get_irq(pdev, idx); 1724 if (!irq) { 1725 dev_err(dev, "irq init: could not map fatal interrupt %d\n", 1726 idx); 1727 return -ENOENT; 1728 } 1729 1730 rc = devm_request_irq(dev, irq, fatal_interrupts[i], 0, 1731 DRV_NAME " fatal", hisi_hba); 1732 if (rc) { 1733 dev_err(dev, "irq init: could not request fatal interrupt %d, rc=%d\n", 1734 irq, rc); 1735 return -ENOENT; 1736 } 1737 } 1738 1739 hisi_hba->cq_nvecs = hisi_hba->queue_count; 1740 1741 return 0; 1742 } 1743 1744 static int interrupt_openall_v1_hw(struct hisi_hba *hisi_hba) 1745 { 1746 int i; 1747 u32 val; 1748 1749 for (i = 0; i < hisi_hba->n_phy; i++) { 1750 /* Clear interrupt status */ 1751 val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT0); 1752 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, val); 1753 val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT1); 1754 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, val); 1755 val = hisi_sas_phy_read32(hisi_hba, i, CHL_INT2); 1756 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, val); 1757 1758 /* Unmask interrupt */ 1759 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0_MSK, 0x3ce3ee); 1760 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0x17fff); 1761 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8000012a); 1762 1763 /* bypass chip bug mask abnormal intr */ 1764 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0_MSK, 1765 0x3fffff & ~CHL_INT0_MSK_PHYCTRL_NOTRDY_MSK); 1766 } 1767 1768 return 0; 1769 } 1770 1771 static int hisi_sas_v1_init(struct hisi_hba *hisi_hba) 1772 { 1773 int rc; 1774 1775 rc = hw_init_v1_hw(hisi_hba); 1776 if (rc) 1777 return rc; 1778 1779 rc = interrupt_init_v1_hw(hisi_hba); 1780 if (rc) 1781 return rc; 1782 1783 rc = interrupt_openall_v1_hw(hisi_hba); 1784 if (rc) 1785 return rc; 1786 1787 return 0; 1788 } 1789 1790 static struct device_attribute *host_attrs_v1_hw[] = { 1791 &dev_attr_phy_event_threshold, 1792 NULL 1793 }; 1794 1795 static struct scsi_host_template sht_v1_hw = { 1796 .name = DRV_NAME, 1797 .module = THIS_MODULE, 1798 .queuecommand = sas_queuecommand, 1799 .target_alloc = sas_target_alloc, 1800 .slave_configure = hisi_sas_slave_configure, 1801 .scan_finished = hisi_sas_scan_finished, 1802 .scan_start = hisi_sas_scan_start, 1803 .change_queue_depth = sas_change_queue_depth, 1804 .bios_param = sas_bios_param, 1805 .this_id = -1, 1806 .sg_tablesize = HISI_SAS_SGE_PAGE_CNT, 1807 .max_sectors = SCSI_DEFAULT_MAX_SECTORS, 1808 .eh_device_reset_handler = sas_eh_device_reset_handler, 1809 .eh_target_reset_handler = sas_eh_target_reset_handler, 1810 .target_destroy = sas_target_destroy, 1811 .ioctl = sas_ioctl, 1812 .shost_attrs = host_attrs_v1_hw, 1813 .host_reset = hisi_sas_host_reset, 1814 }; 1815 1816 static const struct hisi_sas_hw hisi_sas_v1_hw = { 1817 .hw_init = hisi_sas_v1_init, 1818 .setup_itct = setup_itct_v1_hw, 1819 .sl_notify_ssp = sl_notify_ssp_v1_hw, 1820 .clear_itct = clear_itct_v1_hw, 1821 .prep_smp = prep_smp_v1_hw, 1822 .prep_ssp = prep_ssp_v1_hw, 1823 .get_free_slot = get_free_slot_v1_hw, 1824 .start_delivery = start_delivery_v1_hw, 1825 .slot_complete = slot_complete_v1_hw, 1826 .phys_init = phys_init_v1_hw, 1827 .phy_start = start_phy_v1_hw, 1828 .phy_disable = disable_phy_v1_hw, 1829 .phy_hard_reset = phy_hard_reset_v1_hw, 1830 .phy_set_linkrate = phy_set_linkrate_v1_hw, 1831 .phy_get_max_linkrate = phy_get_max_linkrate_v1_hw, 1832 .get_wideport_bitmap = get_wideport_bitmap_v1_hw, 1833 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V1_HW, 1834 .complete_hdr_size = sizeof(struct hisi_sas_complete_v1_hdr), 1835 .sht = &sht_v1_hw, 1836 }; 1837 1838 static int hisi_sas_v1_probe(struct platform_device *pdev) 1839 { 1840 return hisi_sas_probe(pdev, &hisi_sas_v1_hw); 1841 } 1842 1843 static int hisi_sas_v1_remove(struct platform_device *pdev) 1844 { 1845 return hisi_sas_remove(pdev); 1846 } 1847 1848 static const struct of_device_id sas_v1_of_match[] = { 1849 { .compatible = "hisilicon,hip05-sas-v1",}, 1850 {}, 1851 }; 1852 MODULE_DEVICE_TABLE(of, sas_v1_of_match); 1853 1854 static const struct acpi_device_id sas_v1_acpi_match[] = { 1855 { "HISI0161", 0 }, 1856 { } 1857 }; 1858 1859 MODULE_DEVICE_TABLE(acpi, sas_v1_acpi_match); 1860 1861 static struct platform_driver hisi_sas_v1_driver = { 1862 .probe = hisi_sas_v1_probe, 1863 .remove = hisi_sas_v1_remove, 1864 .driver = { 1865 .name = DRV_NAME, 1866 .of_match_table = sas_v1_of_match, 1867 .acpi_match_table = ACPI_PTR(sas_v1_acpi_match), 1868 }, 1869 }; 1870 1871 module_platform_driver(hisi_sas_v1_driver); 1872 1873 MODULE_LICENSE("GPL"); 1874 MODULE_AUTHOR("John Garry <john.garry@huawei.com>"); 1875 MODULE_DESCRIPTION("HISILICON SAS controller v1 hw driver"); 1876 MODULE_ALIAS("platform:" DRV_NAME); 1877