1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (c) 2015 Linaro Ltd. 4 * Copyright (c) 2015 Hisilicon Limited. 5 */ 6 7 #ifndef _HISI_SAS_H_ 8 #define _HISI_SAS_H_ 9 10 #include <linux/acpi.h> 11 #include <linux/blk-mq.h> 12 #include <linux/blk-mq-pci.h> 13 #include <linux/clk.h> 14 #include <linux/debugfs.h> 15 #include <linux/dmapool.h> 16 #include <linux/iopoll.h> 17 #include <linux/irq.h> 18 #include <linux/lcm.h> 19 #include <linux/libata.h> 20 #include <linux/mfd/syscon.h> 21 #include <linux/module.h> 22 #include <linux/of_address.h> 23 #include <linux/pci.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/property.h> 27 #include <linux/regmap.h> 28 #include <linux/timer.h> 29 #include <scsi/sas_ata.h> 30 #include <scsi/libsas.h> 31 32 #define HISI_SAS_MAX_PHYS 9 33 #define HISI_SAS_MAX_QUEUES 32 34 #define HISI_SAS_QUEUE_SLOTS 4096 35 #define HISI_SAS_MAX_ITCT_ENTRIES 1024 36 #define HISI_SAS_MAX_DEVICES HISI_SAS_MAX_ITCT_ENTRIES 37 #define HISI_SAS_RESETTING_BIT 0 38 #define HISI_SAS_REJECT_CMD_BIT 1 39 #define HISI_SAS_PM_BIT 2 40 #define HISI_SAS_HW_FAULT_BIT 3 41 #define HISI_SAS_MAX_COMMANDS (HISI_SAS_QUEUE_SLOTS) 42 #define HISI_SAS_RESERVED_IPTT 96 43 #define HISI_SAS_UNRESERVED_IPTT \ 44 (HISI_SAS_MAX_COMMANDS - HISI_SAS_RESERVED_IPTT) 45 46 #define HISI_SAS_IOST_ITCT_CACHE_NUM 64 47 #define HISI_SAS_IOST_ITCT_CACHE_DW_SZ 10 48 #define HISI_SAS_FIFO_DATA_DW_SIZE 32 49 50 #define HISI_SAS_STATUS_BUF_SZ (sizeof(struct hisi_sas_status_buffer)) 51 #define HISI_SAS_COMMAND_TABLE_SZ (sizeof(union hisi_sas_command_table)) 52 53 #define hisi_sas_status_buf_addr(buf) \ 54 ((buf) + offsetof(struct hisi_sas_slot_buf_table, status_buffer)) 55 #define hisi_sas_status_buf_addr_mem(slot) hisi_sas_status_buf_addr((slot)->buf) 56 #define hisi_sas_status_buf_addr_dma(slot) \ 57 hisi_sas_status_buf_addr((slot)->buf_dma) 58 59 #define hisi_sas_cmd_hdr_addr(buf) \ 60 ((buf) + offsetof(struct hisi_sas_slot_buf_table, command_header)) 61 #define hisi_sas_cmd_hdr_addr_mem(slot) hisi_sas_cmd_hdr_addr((slot)->buf) 62 #define hisi_sas_cmd_hdr_addr_dma(slot) hisi_sas_cmd_hdr_addr((slot)->buf_dma) 63 64 #define hisi_sas_sge_addr(buf) \ 65 ((buf) + offsetof(struct hisi_sas_slot_buf_table, sge_page)) 66 #define hisi_sas_sge_addr_mem(slot) hisi_sas_sge_addr((slot)->buf) 67 #define hisi_sas_sge_addr_dma(slot) hisi_sas_sge_addr((slot)->buf_dma) 68 69 #define hisi_sas_sge_dif_addr(buf) \ 70 ((buf) + offsetof(struct hisi_sas_slot_dif_buf_table, sge_dif_page)) 71 #define hisi_sas_sge_dif_addr_mem(slot) hisi_sas_sge_dif_addr((slot)->buf) 72 #define hisi_sas_sge_dif_addr_dma(slot) hisi_sas_sge_dif_addr((slot)->buf_dma) 73 74 #define HISI_SAS_MAX_SSP_RESP_SZ (sizeof(struct ssp_frame_hdr) + 1024) 75 #define HISI_SAS_MAX_SMP_RESP_SZ 1028 76 #define HISI_SAS_MAX_STP_RESP_SZ 28 77 78 #define HISI_SAS_SATA_PROTOCOL_NONDATA 0x1 79 #define HISI_SAS_SATA_PROTOCOL_PIO 0x2 80 #define HISI_SAS_SATA_PROTOCOL_DMA 0x4 81 #define HISI_SAS_SATA_PROTOCOL_FPDMA 0x8 82 #define HISI_SAS_SATA_PROTOCOL_ATAPI 0x10 83 84 #define HISI_SAS_DIF_PROT_MASK (SHOST_DIF_TYPE1_PROTECTION | \ 85 SHOST_DIF_TYPE2_PROTECTION | \ 86 SHOST_DIF_TYPE3_PROTECTION) 87 88 #define HISI_SAS_DIX_PROT_MASK (SHOST_DIX_TYPE1_PROTECTION | \ 89 SHOST_DIX_TYPE2_PROTECTION | \ 90 SHOST_DIX_TYPE3_PROTECTION) 91 92 #define HISI_SAS_PROT_MASK (HISI_SAS_DIF_PROT_MASK | HISI_SAS_DIX_PROT_MASK) 93 94 #define HISI_SAS_WAIT_PHYUP_TIMEOUT (20 * HZ) 95 #define HISI_SAS_CLEAR_ITCT_TIMEOUT (20 * HZ) 96 97 struct hisi_hba; 98 99 enum { 100 PORT_TYPE_SAS = (1U << 1), 101 PORT_TYPE_SATA = (1U << 0), 102 }; 103 104 enum dev_status { 105 HISI_SAS_DEV_INIT, 106 HISI_SAS_DEV_NORMAL, 107 }; 108 109 enum { 110 HISI_SAS_INT_ABT_CMD = 0, 111 HISI_SAS_INT_ABT_DEV = 1, 112 }; 113 114 enum hisi_sas_dev_type { 115 HISI_SAS_DEV_TYPE_STP = 0, 116 HISI_SAS_DEV_TYPE_SSP, 117 HISI_SAS_DEV_TYPE_SATA, 118 }; 119 120 struct hisi_sas_hw_error { 121 u32 irq_msk; 122 u32 msk; 123 int shift; 124 const char *msg; 125 int reg; 126 const struct hisi_sas_hw_error *sub; 127 }; 128 129 struct hisi_sas_rst { 130 struct hisi_hba *hisi_hba; 131 struct completion *completion; 132 struct work_struct work; 133 bool done; 134 }; 135 136 struct hisi_sas_internal_abort { 137 unsigned int flag; 138 unsigned int tag; 139 }; 140 141 #define HISI_SAS_RST_WORK_INIT(r, c) \ 142 { .hisi_hba = hisi_hba, \ 143 .completion = &c, \ 144 .work = __WORK_INITIALIZER(r.work, \ 145 hisi_sas_sync_rst_work_handler), \ 146 .done = false, \ 147 } 148 149 #define HISI_SAS_DECLARE_RST_WORK_ON_STACK(r) \ 150 DECLARE_COMPLETION_ONSTACK(c); \ 151 struct hisi_sas_rst r = HISI_SAS_RST_WORK_INIT(r, c) 152 153 enum hisi_sas_bit_err_type { 154 HISI_SAS_ERR_SINGLE_BIT_ECC = 0x0, 155 HISI_SAS_ERR_MULTI_BIT_ECC = 0x1, 156 }; 157 158 enum hisi_sas_phy_event { 159 HISI_PHYE_PHY_UP = 0U, 160 HISI_PHYE_LINK_RESET, 161 HISI_PHYE_PHY_UP_PM, 162 HISI_PHYES_NUM, 163 }; 164 165 struct hisi_sas_debugfs_fifo { 166 u32 signal_sel; 167 u32 dump_msk; 168 u32 dump_mode; 169 u32 trigger; 170 u32 trigger_msk; 171 u32 trigger_mode; 172 u32 rd_data[HISI_SAS_FIFO_DATA_DW_SIZE]; 173 }; 174 175 struct hisi_sas_phy { 176 struct work_struct works[HISI_PHYES_NUM]; 177 struct hisi_hba *hisi_hba; 178 struct hisi_sas_port *port; 179 struct asd_sas_phy sas_phy; 180 struct sas_identify identify; 181 struct completion *reset_completion; 182 struct timer_list timer; 183 spinlock_t lock; 184 u64 port_id; /* from hw */ 185 u64 frame_rcvd_size; 186 u8 frame_rcvd[32]; 187 u8 phy_attached; 188 u8 in_reset; 189 u8 reserved[2]; 190 u32 phy_type; 191 u32 code_violation_err_count; 192 enum sas_linkrate minimum_linkrate; 193 enum sas_linkrate maximum_linkrate; 194 int enable; 195 int wait_phyup_cnt; 196 atomic_t down_cnt; 197 198 /* Trace FIFO */ 199 struct hisi_sas_debugfs_fifo fifo; 200 }; 201 202 struct hisi_sas_port { 203 struct asd_sas_port sas_port; 204 u8 port_attached; 205 u8 id; /* from hw */ 206 }; 207 208 struct hisi_sas_cq { 209 struct hisi_hba *hisi_hba; 210 const struct cpumask *irq_mask; 211 int rd_point; 212 int id; 213 int irq_no; 214 }; 215 216 struct hisi_sas_dq { 217 struct hisi_hba *hisi_hba; 218 struct list_head list; 219 spinlock_t lock; 220 int wr_point; 221 int id; 222 }; 223 224 struct hisi_sas_device { 225 struct hisi_hba *hisi_hba; 226 struct domain_device *sas_device; 227 struct completion *completion; 228 struct hisi_sas_dq *dq; 229 struct list_head list; 230 enum sas_device_type dev_type; 231 enum dev_status dev_status; 232 int device_id; 233 int sata_idx; 234 spinlock_t lock; /* For protecting slots */ 235 }; 236 237 struct hisi_sas_tmf_task { 238 int force_phy; 239 int phy_id; 240 u8 tmf; 241 u16 tag_of_task_to_be_managed; 242 }; 243 244 struct hisi_sas_slot { 245 struct list_head entry; 246 struct list_head delivery; 247 struct sas_task *task; 248 struct hisi_sas_port *port; 249 u64 n_elem; 250 u64 n_elem_dif; 251 int dlvry_queue; 252 int dlvry_queue_slot; 253 int cmplt_queue; 254 int cmplt_queue_slot; 255 int abort; 256 int ready; 257 int device_id; 258 void *cmd_hdr; 259 dma_addr_t cmd_hdr_dma; 260 struct timer_list internal_abort_timer; 261 bool is_internal; 262 struct hisi_sas_tmf_task *tmf; 263 /* Do not reorder/change members after here */ 264 void *buf; 265 dma_addr_t buf_dma; 266 u16 idx; 267 }; 268 269 struct hisi_sas_iost_itct_cache { 270 u32 data[HISI_SAS_IOST_ITCT_CACHE_DW_SZ]; 271 }; 272 273 enum hisi_sas_debugfs_reg_array_member { 274 DEBUGFS_GLOBAL = 0, 275 DEBUGFS_AXI, 276 DEBUGFS_RAS, 277 DEBUGFS_REGS_NUM 278 }; 279 280 enum hisi_sas_debugfs_cache_type { 281 HISI_SAS_ITCT_CACHE, 282 HISI_SAS_IOST_CACHE, 283 }; 284 285 enum hisi_sas_debugfs_bist_ffe_cfg { 286 FFE_SAS_1_5_GBPS, 287 FFE_SAS_3_0_GBPS, 288 FFE_SAS_6_0_GBPS, 289 FFE_SAS_12_0_GBPS, 290 FFE_RESV, 291 FFE_SATA_1_5_GBPS, 292 FFE_SATA_3_0_GBPS, 293 FFE_SATA_6_0_GBPS, 294 FFE_CFG_MAX 295 }; 296 297 enum hisi_sas_debugfs_bist_fixed_code { 298 FIXED_CODE, 299 FIXED_CODE_1, 300 FIXED_CODE_MAX 301 }; 302 303 enum { 304 HISI_SAS_BIST_CODE_MODE_PRBS7, 305 HISI_SAS_BIST_CODE_MODE_PRBS23, 306 HISI_SAS_BIST_CODE_MODE_PRBS31, 307 HISI_SAS_BIST_CODE_MODE_JTPAT, 308 HISI_SAS_BIST_CODE_MODE_CJTPAT, 309 HISI_SAS_BIST_CODE_MODE_SCRAMBED_0, 310 HISI_SAS_BIST_CODE_MODE_TRAIN, 311 HISI_SAS_BIST_CODE_MODE_TRAIN_DONE, 312 HISI_SAS_BIST_CODE_MODE_HFTP, 313 HISI_SAS_BIST_CODE_MODE_MFTP, 314 HISI_SAS_BIST_CODE_MODE_LFTP, 315 HISI_SAS_BIST_CODE_MODE_FIXED_DATA, 316 }; 317 318 struct hisi_sas_hw { 319 int (*hw_init)(struct hisi_hba *hisi_hba); 320 int (*interrupt_preinit)(struct hisi_hba *hisi_hba); 321 void (*setup_itct)(struct hisi_hba *hisi_hba, 322 struct hisi_sas_device *device); 323 int (*slot_index_alloc)(struct hisi_hba *hisi_hba, 324 struct domain_device *device); 325 struct hisi_sas_device *(*alloc_dev)(struct domain_device *device); 326 void (*sl_notify_ssp)(struct hisi_hba *hisi_hba, int phy_no); 327 void (*start_delivery)(struct hisi_sas_dq *dq); 328 void (*prep_ssp)(struct hisi_hba *hisi_hba, 329 struct hisi_sas_slot *slot); 330 void (*prep_smp)(struct hisi_hba *hisi_hba, 331 struct hisi_sas_slot *slot); 332 void (*prep_stp)(struct hisi_hba *hisi_hba, 333 struct hisi_sas_slot *slot); 334 void (*prep_abort)(struct hisi_hba *hisi_hba, 335 struct hisi_sas_slot *slot, 336 int device_id, int abort_flag, int tag_to_abort); 337 void (*phys_init)(struct hisi_hba *hisi_hba); 338 void (*phy_start)(struct hisi_hba *hisi_hba, int phy_no); 339 void (*phy_disable)(struct hisi_hba *hisi_hba, int phy_no); 340 void (*phy_hard_reset)(struct hisi_hba *hisi_hba, int phy_no); 341 void (*get_events)(struct hisi_hba *hisi_hba, int phy_no); 342 void (*phy_set_linkrate)(struct hisi_hba *hisi_hba, int phy_no, 343 struct sas_phy_linkrates *linkrates); 344 enum sas_linkrate (*phy_get_max_linkrate)(void); 345 int (*clear_itct)(struct hisi_hba *hisi_hba, 346 struct hisi_sas_device *dev); 347 void (*free_device)(struct hisi_sas_device *sas_dev); 348 int (*get_wideport_bitmap)(struct hisi_hba *hisi_hba, int port_id); 349 void (*dereg_device)(struct hisi_hba *hisi_hba, 350 struct domain_device *device); 351 int (*soft_reset)(struct hisi_hba *hisi_hba); 352 u32 (*get_phys_state)(struct hisi_hba *hisi_hba); 353 int (*write_gpio)(struct hisi_hba *hisi_hba, u8 reg_type, 354 u8 reg_index, u8 reg_count, u8 *write_data); 355 void (*wait_cmds_complete_timeout)(struct hisi_hba *hisi_hba, 356 int delay_ms, int timeout_ms); 357 void (*debugfs_snapshot_regs)(struct hisi_hba *hisi_hba); 358 int complete_hdr_size; 359 struct scsi_host_template *sht; 360 }; 361 362 #define HISI_SAS_MAX_DEBUGFS_DUMP (50) 363 364 struct hisi_sas_debugfs_cq { 365 struct hisi_sas_cq *cq; 366 void *complete_hdr; 367 }; 368 369 struct hisi_sas_debugfs_dq { 370 struct hisi_sas_dq *dq; 371 struct hisi_sas_cmd_hdr *hdr; 372 }; 373 374 struct hisi_sas_debugfs_regs { 375 struct hisi_hba *hisi_hba; 376 u32 *data; 377 }; 378 379 struct hisi_sas_debugfs_port { 380 struct hisi_sas_phy *phy; 381 u32 *data; 382 }; 383 384 struct hisi_sas_debugfs_iost { 385 struct hisi_sas_iost *iost; 386 }; 387 388 struct hisi_sas_debugfs_itct { 389 struct hisi_sas_itct *itct; 390 }; 391 392 struct hisi_sas_debugfs_iost_cache { 393 struct hisi_sas_iost_itct_cache *cache; 394 }; 395 396 struct hisi_sas_debugfs_itct_cache { 397 struct hisi_sas_iost_itct_cache *cache; 398 }; 399 400 struct hisi_hba { 401 /* This must be the first element, used by SHOST_TO_SAS_HA */ 402 struct sas_ha_struct *p; 403 404 struct platform_device *platform_dev; 405 struct pci_dev *pci_dev; 406 struct device *dev; 407 408 int prot_mask; 409 410 void __iomem *regs; 411 void __iomem *sgpio_regs; 412 struct regmap *ctrl; 413 u32 ctrl_reset_reg; 414 u32 ctrl_reset_sts_reg; 415 u32 ctrl_clock_ena_reg; 416 u32 refclk_frequency_mhz; 417 u8 sas_addr[SAS_ADDR_SIZE]; 418 419 int *irq_map; /* v2 hw */ 420 421 int n_phy; 422 spinlock_t lock; 423 struct semaphore sem; 424 425 struct timer_list timer; 426 struct workqueue_struct *wq; 427 428 int slot_index_count; 429 int last_slot_index; 430 int last_dev_id; 431 unsigned long *slot_index_tags; 432 unsigned long reject_stp_links_msk; 433 434 /* SCSI/SAS glue */ 435 struct sas_ha_struct sha; 436 struct Scsi_Host *shost; 437 438 struct hisi_sas_cq cq[HISI_SAS_MAX_QUEUES]; 439 struct hisi_sas_dq dq[HISI_SAS_MAX_QUEUES]; 440 struct hisi_sas_phy phy[HISI_SAS_MAX_PHYS]; 441 struct hisi_sas_port port[HISI_SAS_MAX_PHYS]; 442 443 int queue_count; 444 445 struct hisi_sas_device devices[HISI_SAS_MAX_DEVICES]; 446 struct hisi_sas_cmd_hdr *cmd_hdr[HISI_SAS_MAX_QUEUES]; 447 dma_addr_t cmd_hdr_dma[HISI_SAS_MAX_QUEUES]; 448 void *complete_hdr[HISI_SAS_MAX_QUEUES]; 449 dma_addr_t complete_hdr_dma[HISI_SAS_MAX_QUEUES]; 450 struct hisi_sas_initial_fis *initial_fis; 451 dma_addr_t initial_fis_dma; 452 struct hisi_sas_itct *itct; 453 dma_addr_t itct_dma; 454 struct hisi_sas_iost *iost; 455 dma_addr_t iost_dma; 456 struct hisi_sas_breakpoint *breakpoint; 457 dma_addr_t breakpoint_dma; 458 struct hisi_sas_breakpoint *sata_breakpoint; 459 dma_addr_t sata_breakpoint_dma; 460 struct hisi_sas_slot *slot_info; 461 unsigned long flags; 462 const struct hisi_sas_hw *hw; /* Low level hw interface */ 463 unsigned long sata_dev_bitmap[BITS_TO_LONGS(HISI_SAS_MAX_DEVICES)]; 464 struct work_struct rst_work; 465 struct work_struct debugfs_work; 466 u32 phy_state; 467 u32 intr_coal_ticks; /* Time of interrupt coalesce in us */ 468 u32 intr_coal_count; /* Interrupt count to coalesce */ 469 470 int cq_nvecs; 471 472 /* bist */ 473 enum sas_linkrate debugfs_bist_linkrate; 474 int debugfs_bist_code_mode; 475 int debugfs_bist_phy_no; 476 int debugfs_bist_mode; 477 u32 debugfs_bist_cnt; 478 int debugfs_bist_enable; 479 u32 debugfs_bist_ffe[HISI_SAS_MAX_PHYS][FFE_CFG_MAX]; 480 u32 debugfs_bist_fixed_code[FIXED_CODE_MAX]; 481 482 /* debugfs memories */ 483 /* Put Global AXI and RAS Register into register array */ 484 struct hisi_sas_debugfs_regs debugfs_regs[HISI_SAS_MAX_DEBUGFS_DUMP][DEBUGFS_REGS_NUM]; 485 struct hisi_sas_debugfs_port debugfs_port_reg[HISI_SAS_MAX_DEBUGFS_DUMP][HISI_SAS_MAX_PHYS]; 486 struct hisi_sas_debugfs_cq debugfs_cq[HISI_SAS_MAX_DEBUGFS_DUMP][HISI_SAS_MAX_QUEUES]; 487 struct hisi_sas_debugfs_dq debugfs_dq[HISI_SAS_MAX_DEBUGFS_DUMP][HISI_SAS_MAX_QUEUES]; 488 struct hisi_sas_debugfs_iost debugfs_iost[HISI_SAS_MAX_DEBUGFS_DUMP]; 489 struct hisi_sas_debugfs_itct debugfs_itct[HISI_SAS_MAX_DEBUGFS_DUMP]; 490 struct hisi_sas_debugfs_iost_cache debugfs_iost_cache[HISI_SAS_MAX_DEBUGFS_DUMP]; 491 struct hisi_sas_debugfs_itct_cache debugfs_itct_cache[HISI_SAS_MAX_DEBUGFS_DUMP]; 492 493 u64 debugfs_timestamp[HISI_SAS_MAX_DEBUGFS_DUMP]; 494 int debugfs_dump_index; 495 struct dentry *debugfs_dir; 496 struct dentry *debugfs_dump_dentry; 497 struct dentry *debugfs_bist_dentry; 498 struct dentry *debugfs_fifo_dentry; 499 }; 500 501 /* Generic HW DMA host memory structures */ 502 /* Delivery queue header */ 503 struct hisi_sas_cmd_hdr { 504 /* dw0 */ 505 __le32 dw0; 506 507 /* dw1 */ 508 __le32 dw1; 509 510 /* dw2 */ 511 __le32 dw2; 512 513 /* dw3 */ 514 __le32 transfer_tags; 515 516 /* dw4 */ 517 __le32 data_transfer_len; 518 519 /* dw5 */ 520 __le32 first_burst_num; 521 522 /* dw6 */ 523 __le32 sg_len; 524 525 /* dw7 */ 526 __le32 dw7; 527 528 /* dw8-9 */ 529 __le64 cmd_table_addr; 530 531 /* dw10-11 */ 532 __le64 sts_buffer_addr; 533 534 /* dw12-13 */ 535 __le64 prd_table_addr; 536 537 /* dw14-15 */ 538 __le64 dif_prd_table_addr; 539 }; 540 541 struct hisi_sas_itct { 542 __le64 qw0; 543 __le64 sas_addr; 544 __le64 qw2; 545 __le64 qw3; 546 __le64 qw4_15[12]; 547 }; 548 549 struct hisi_sas_iost { 550 __le64 qw0; 551 __le64 qw1; 552 __le64 qw2; 553 __le64 qw3; 554 }; 555 556 struct hisi_sas_err_record { 557 u32 data[4]; 558 }; 559 560 struct hisi_sas_initial_fis { 561 struct hisi_sas_err_record err_record; 562 struct dev_to_host_fis fis; 563 u32 rsvd[3]; 564 }; 565 566 struct hisi_sas_breakpoint { 567 u8 data[128]; 568 }; 569 570 struct hisi_sas_sata_breakpoint { 571 struct hisi_sas_breakpoint tag[32]; 572 }; 573 574 struct hisi_sas_sge { 575 __le64 addr; 576 __le32 page_ctrl_0; 577 __le32 page_ctrl_1; 578 __le32 data_len; 579 __le32 data_off; 580 }; 581 582 struct hisi_sas_command_table_smp { 583 u8 bytes[44]; 584 }; 585 586 struct hisi_sas_command_table_stp { 587 struct host_to_dev_fis command_fis; 588 u8 dummy[12]; 589 u8 atapi_cdb[ATAPI_CDB_LEN]; 590 }; 591 592 #define HISI_SAS_SGE_PAGE_CNT (124) 593 struct hisi_sas_sge_page { 594 struct hisi_sas_sge sge[HISI_SAS_SGE_PAGE_CNT]; 595 } __aligned(16); 596 597 #define HISI_SAS_SGE_DIF_PAGE_CNT HISI_SAS_SGE_PAGE_CNT 598 struct hisi_sas_sge_dif_page { 599 struct hisi_sas_sge sge[HISI_SAS_SGE_DIF_PAGE_CNT]; 600 } __aligned(16); 601 602 struct hisi_sas_command_table_ssp { 603 struct ssp_frame_hdr hdr; 604 union { 605 struct { 606 struct ssp_command_iu task; 607 u32 prot[7]; 608 }; 609 struct ssp_tmf_iu ssp_task; 610 struct xfer_rdy_iu xfer_rdy; 611 struct ssp_response_iu ssp_res; 612 } u; 613 }; 614 615 union hisi_sas_command_table { 616 struct hisi_sas_command_table_ssp ssp; 617 struct hisi_sas_command_table_smp smp; 618 struct hisi_sas_command_table_stp stp; 619 } __aligned(16); 620 621 struct hisi_sas_status_buffer { 622 struct hisi_sas_err_record err; 623 u8 iu[1024]; 624 } __aligned(16); 625 626 struct hisi_sas_slot_buf_table { 627 struct hisi_sas_status_buffer status_buffer; 628 union hisi_sas_command_table command_header; 629 struct hisi_sas_sge_page sge_page; 630 }; 631 632 struct hisi_sas_slot_dif_buf_table { 633 struct hisi_sas_slot_buf_table slot_buf; 634 struct hisi_sas_sge_dif_page sge_dif_page; 635 }; 636 637 extern struct scsi_transport_template *hisi_sas_stt; 638 639 extern bool hisi_sas_debugfs_enable; 640 extern u32 hisi_sas_debugfs_dump_count; 641 extern struct dentry *hisi_sas_debugfs_dir; 642 643 extern void hisi_sas_stop_phys(struct hisi_hba *hisi_hba); 644 extern int hisi_sas_alloc(struct hisi_hba *hisi_hba); 645 extern void hisi_sas_free(struct hisi_hba *hisi_hba); 646 extern u8 hisi_sas_get_ata_protocol(struct host_to_dev_fis *fis, 647 int direction); 648 extern struct hisi_sas_port *to_hisi_sas_port(struct asd_sas_port *sas_port); 649 extern void hisi_sas_sata_done(struct sas_task *task, 650 struct hisi_sas_slot *slot); 651 extern int hisi_sas_get_fw_info(struct hisi_hba *hisi_hba); 652 extern int hisi_sas_probe(struct platform_device *pdev, 653 const struct hisi_sas_hw *ops); 654 extern int hisi_sas_remove(struct platform_device *pdev); 655 656 extern int hisi_sas_slave_configure(struct scsi_device *sdev); 657 extern int hisi_sas_slave_alloc(struct scsi_device *sdev); 658 extern int hisi_sas_scan_finished(struct Scsi_Host *shost, unsigned long time); 659 extern void hisi_sas_scan_start(struct Scsi_Host *shost); 660 extern int hisi_sas_host_reset(struct Scsi_Host *shost, int reset_type); 661 extern void hisi_sas_phy_enable(struct hisi_hba *hisi_hba, int phy_no, 662 int enable); 663 extern void hisi_sas_phy_down(struct hisi_hba *hisi_hba, int phy_no, int rdy, 664 gfp_t gfp_flags); 665 extern void hisi_sas_slot_task_free(struct hisi_hba *hisi_hba, 666 struct sas_task *task, 667 struct hisi_sas_slot *slot); 668 extern void hisi_sas_init_mem(struct hisi_hba *hisi_hba); 669 extern void hisi_sas_rst_work_handler(struct work_struct *work); 670 extern void hisi_sas_sync_rst_work_handler(struct work_struct *work); 671 extern void hisi_sas_sync_irqs(struct hisi_hba *hisi_hba); 672 extern void hisi_sas_phy_oob_ready(struct hisi_hba *hisi_hba, int phy_no); 673 extern bool hisi_sas_notify_phy_event(struct hisi_sas_phy *phy, 674 enum hisi_sas_phy_event event); 675 extern void hisi_sas_release_tasks(struct hisi_hba *hisi_hba); 676 extern u8 hisi_sas_get_prog_phy_linkrate_mask(enum sas_linkrate max); 677 extern void hisi_sas_controller_reset_prepare(struct hisi_hba *hisi_hba); 678 extern void hisi_sas_controller_reset_done(struct hisi_hba *hisi_hba); 679 #endif 680