1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (c) 2015 Linaro Ltd. 4 * Copyright (c) 2015 Hisilicon Limited. 5 */ 6 7 #ifndef _HISI_SAS_H_ 8 #define _HISI_SAS_H_ 9 10 #include <linux/acpi.h> 11 #include <linux/blk-mq.h> 12 #include <linux/blk-mq-pci.h> 13 #include <linux/clk.h> 14 #include <linux/debugfs.h> 15 #include <linux/dmapool.h> 16 #include <linux/iopoll.h> 17 #include <linux/irq.h> 18 #include <linux/lcm.h> 19 #include <linux/libata.h> 20 #include <linux/mfd/syscon.h> 21 #include <linux/module.h> 22 #include <linux/of_address.h> 23 #include <linux/pci.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/property.h> 27 #include <linux/regmap.h> 28 #include <linux/timer.h> 29 #include <scsi/sas_ata.h> 30 #include <scsi/libsas.h> 31 32 #define HISI_SAS_MAX_PHYS 9 33 #define HISI_SAS_MAX_QUEUES 32 34 #define HISI_SAS_QUEUE_SLOTS 4096 35 #define HISI_SAS_MAX_ITCT_ENTRIES 1024 36 #define HISI_SAS_MAX_DEVICES HISI_SAS_MAX_ITCT_ENTRIES 37 #define HISI_SAS_RESETTING_BIT 0 38 #define HISI_SAS_REJECT_CMD_BIT 1 39 #define HISI_SAS_PM_BIT 2 40 #define HISI_SAS_HW_FAULT_BIT 3 41 #define HISI_SAS_MAX_COMMANDS (HISI_SAS_QUEUE_SLOTS) 42 #define HISI_SAS_RESERVED_IPTT 96 43 #define HISI_SAS_UNRESERVED_IPTT \ 44 (HISI_SAS_MAX_COMMANDS - HISI_SAS_RESERVED_IPTT) 45 46 #define HISI_SAS_IOST_ITCT_CACHE_NUM 64 47 #define HISI_SAS_IOST_ITCT_CACHE_DW_SZ 10 48 #define HISI_SAS_FIFO_DATA_DW_SIZE 32 49 50 #define HISI_SAS_STATUS_BUF_SZ (sizeof(struct hisi_sas_status_buffer)) 51 #define HISI_SAS_COMMAND_TABLE_SZ (sizeof(union hisi_sas_command_table)) 52 53 #define hisi_sas_status_buf_addr(buf) \ 54 ((buf) + offsetof(struct hisi_sas_slot_buf_table, status_buffer)) 55 #define hisi_sas_status_buf_addr_mem(slot) hisi_sas_status_buf_addr((slot)->buf) 56 #define hisi_sas_status_buf_addr_dma(slot) \ 57 hisi_sas_status_buf_addr((slot)->buf_dma) 58 59 #define hisi_sas_cmd_hdr_addr(buf) \ 60 ((buf) + offsetof(struct hisi_sas_slot_buf_table, command_header)) 61 #define hisi_sas_cmd_hdr_addr_mem(slot) hisi_sas_cmd_hdr_addr((slot)->buf) 62 #define hisi_sas_cmd_hdr_addr_dma(slot) hisi_sas_cmd_hdr_addr((slot)->buf_dma) 63 64 #define hisi_sas_sge_addr(buf) \ 65 ((buf) + offsetof(struct hisi_sas_slot_buf_table, sge_page)) 66 #define hisi_sas_sge_addr_mem(slot) hisi_sas_sge_addr((slot)->buf) 67 #define hisi_sas_sge_addr_dma(slot) hisi_sas_sge_addr((slot)->buf_dma) 68 69 #define hisi_sas_sge_dif_addr(buf) \ 70 ((buf) + offsetof(struct hisi_sas_slot_dif_buf_table, sge_dif_page)) 71 #define hisi_sas_sge_dif_addr_mem(slot) hisi_sas_sge_dif_addr((slot)->buf) 72 #define hisi_sas_sge_dif_addr_dma(slot) hisi_sas_sge_dif_addr((slot)->buf_dma) 73 74 #define HISI_SAS_MAX_SSP_RESP_SZ (sizeof(struct ssp_frame_hdr) + 1024) 75 #define HISI_SAS_MAX_SMP_RESP_SZ 1028 76 #define HISI_SAS_MAX_STP_RESP_SZ 28 77 78 #define HISI_SAS_SATA_PROTOCOL_NONDATA 0x1 79 #define HISI_SAS_SATA_PROTOCOL_PIO 0x2 80 #define HISI_SAS_SATA_PROTOCOL_DMA 0x4 81 #define HISI_SAS_SATA_PROTOCOL_FPDMA 0x8 82 #define HISI_SAS_SATA_PROTOCOL_ATAPI 0x10 83 84 #define HISI_SAS_DIF_PROT_MASK (SHOST_DIF_TYPE1_PROTECTION | \ 85 SHOST_DIF_TYPE2_PROTECTION | \ 86 SHOST_DIF_TYPE3_PROTECTION) 87 88 #define HISI_SAS_DIX_PROT_MASK (SHOST_DIX_TYPE1_PROTECTION | \ 89 SHOST_DIX_TYPE2_PROTECTION | \ 90 SHOST_DIX_TYPE3_PROTECTION) 91 92 #define HISI_SAS_PROT_MASK (HISI_SAS_DIF_PROT_MASK | HISI_SAS_DIX_PROT_MASK) 93 94 #define HISI_SAS_WAIT_PHYUP_TIMEOUT (30 * HZ) 95 #define HISI_SAS_CLEAR_ITCT_TIMEOUT (20 * HZ) 96 97 struct hisi_hba; 98 99 enum { 100 PORT_TYPE_SAS = (1U << 1), 101 PORT_TYPE_SATA = (1U << 0), 102 }; 103 104 enum dev_status { 105 HISI_SAS_DEV_INIT, 106 HISI_SAS_DEV_NORMAL, 107 HISI_SAS_DEV_NCQ_ERR, 108 }; 109 110 enum { 111 HISI_SAS_INT_ABT_CMD = 0, 112 HISI_SAS_INT_ABT_DEV = 1, 113 }; 114 115 enum hisi_sas_dev_type { 116 HISI_SAS_DEV_TYPE_STP = 0, 117 HISI_SAS_DEV_TYPE_SSP, 118 HISI_SAS_DEV_TYPE_SATA, 119 }; 120 121 struct hisi_sas_hw_error { 122 u32 irq_msk; 123 u32 msk; 124 int shift; 125 const char *msg; 126 int reg; 127 const struct hisi_sas_hw_error *sub; 128 }; 129 130 struct hisi_sas_rst { 131 struct hisi_hba *hisi_hba; 132 struct completion *completion; 133 struct work_struct work; 134 bool done; 135 }; 136 137 #define HISI_SAS_RST_WORK_INIT(r, c) \ 138 { .hisi_hba = hisi_hba, \ 139 .completion = &c, \ 140 .work = __WORK_INITIALIZER(r.work, \ 141 hisi_sas_sync_rst_work_handler), \ 142 .done = false, \ 143 } 144 145 #define HISI_SAS_DECLARE_RST_WORK_ON_STACK(r) \ 146 DECLARE_COMPLETION_ONSTACK(c); \ 147 struct hisi_sas_rst r = HISI_SAS_RST_WORK_INIT(r, c) 148 149 enum hisi_sas_bit_err_type { 150 HISI_SAS_ERR_SINGLE_BIT_ECC = 0x0, 151 HISI_SAS_ERR_MULTI_BIT_ECC = 0x1, 152 }; 153 154 enum hisi_sas_phy_event { 155 HISI_PHYE_PHY_UP = 0U, 156 HISI_PHYE_LINK_RESET, 157 HISI_PHYE_PHY_UP_PM, 158 HISI_PHYES_NUM, 159 }; 160 161 struct hisi_sas_debugfs_fifo { 162 u32 signal_sel; 163 u32 dump_msk; 164 u32 dump_mode; 165 u32 trigger; 166 u32 trigger_msk; 167 u32 trigger_mode; 168 u32 rd_data[HISI_SAS_FIFO_DATA_DW_SIZE]; 169 }; 170 171 struct hisi_sas_phy { 172 struct work_struct works[HISI_PHYES_NUM]; 173 struct hisi_hba *hisi_hba; 174 struct hisi_sas_port *port; 175 struct asd_sas_phy sas_phy; 176 struct sas_identify identify; 177 struct completion *reset_completion; 178 struct timer_list timer; 179 spinlock_t lock; 180 u64 port_id; /* from hw */ 181 u64 frame_rcvd_size; 182 u8 frame_rcvd[32]; 183 u8 phy_attached; 184 u8 in_reset; 185 u8 reserved[2]; 186 u32 phy_type; 187 u32 code_violation_err_count; 188 enum sas_linkrate minimum_linkrate; 189 enum sas_linkrate maximum_linkrate; 190 int enable; 191 int wait_phyup_cnt; 192 atomic_t down_cnt; 193 194 /* Trace FIFO */ 195 struct hisi_sas_debugfs_fifo fifo; 196 }; 197 198 struct hisi_sas_port { 199 struct asd_sas_port sas_port; 200 u8 port_attached; 201 u8 id; /* from hw */ 202 }; 203 204 struct hisi_sas_cq { 205 struct hisi_hba *hisi_hba; 206 const struct cpumask *irq_mask; 207 int rd_point; 208 int id; 209 int irq_no; 210 }; 211 212 struct hisi_sas_dq { 213 struct hisi_hba *hisi_hba; 214 struct list_head list; 215 spinlock_t lock; 216 int wr_point; 217 int id; 218 }; 219 220 struct hisi_sas_device { 221 struct hisi_hba *hisi_hba; 222 struct domain_device *sas_device; 223 struct completion *completion; 224 struct hisi_sas_dq *dq; 225 struct list_head list; 226 enum sas_device_type dev_type; 227 enum dev_status dev_status; 228 int device_id; 229 int sata_idx; 230 spinlock_t lock; /* For protecting slots */ 231 }; 232 233 struct hisi_sas_slot { 234 struct list_head entry; 235 struct list_head delivery; 236 struct sas_task *task; 237 struct hisi_sas_port *port; 238 u64 n_elem; 239 u64 n_elem_dif; 240 int dlvry_queue; 241 int dlvry_queue_slot; 242 int cmplt_queue; 243 int cmplt_queue_slot; 244 int abort; 245 int ready; 246 int device_id; 247 void *cmd_hdr; 248 dma_addr_t cmd_hdr_dma; 249 struct timer_list internal_abort_timer; 250 bool is_internal; 251 struct sas_tmf_task *tmf; 252 /* Do not reorder/change members after here */ 253 void *buf; 254 dma_addr_t buf_dma; 255 u16 idx; 256 }; 257 258 struct hisi_sas_iost_itct_cache { 259 u32 data[HISI_SAS_IOST_ITCT_CACHE_DW_SZ]; 260 }; 261 262 enum hisi_sas_debugfs_reg_array_member { 263 DEBUGFS_GLOBAL = 0, 264 DEBUGFS_AXI, 265 DEBUGFS_RAS, 266 DEBUGFS_REGS_NUM 267 }; 268 269 enum hisi_sas_debugfs_cache_type { 270 HISI_SAS_ITCT_CACHE, 271 HISI_SAS_IOST_CACHE, 272 }; 273 274 enum hisi_sas_debugfs_bist_ffe_cfg { 275 FFE_SAS_1_5_GBPS, 276 FFE_SAS_3_0_GBPS, 277 FFE_SAS_6_0_GBPS, 278 FFE_SAS_12_0_GBPS, 279 FFE_RESV, 280 FFE_SATA_1_5_GBPS, 281 FFE_SATA_3_0_GBPS, 282 FFE_SATA_6_0_GBPS, 283 FFE_CFG_MAX 284 }; 285 286 enum hisi_sas_debugfs_bist_fixed_code { 287 FIXED_CODE, 288 FIXED_CODE_1, 289 FIXED_CODE_MAX 290 }; 291 292 enum { 293 HISI_SAS_BIST_CODE_MODE_PRBS7, 294 HISI_SAS_BIST_CODE_MODE_PRBS23, 295 HISI_SAS_BIST_CODE_MODE_PRBS31, 296 HISI_SAS_BIST_CODE_MODE_JTPAT, 297 HISI_SAS_BIST_CODE_MODE_CJTPAT, 298 HISI_SAS_BIST_CODE_MODE_SCRAMBED_0, 299 HISI_SAS_BIST_CODE_MODE_TRAIN, 300 HISI_SAS_BIST_CODE_MODE_TRAIN_DONE, 301 HISI_SAS_BIST_CODE_MODE_HFTP, 302 HISI_SAS_BIST_CODE_MODE_MFTP, 303 HISI_SAS_BIST_CODE_MODE_LFTP, 304 HISI_SAS_BIST_CODE_MODE_FIXED_DATA, 305 }; 306 307 struct hisi_sas_hw { 308 int (*hw_init)(struct hisi_hba *hisi_hba); 309 int (*interrupt_preinit)(struct hisi_hba *hisi_hba); 310 void (*setup_itct)(struct hisi_hba *hisi_hba, 311 struct hisi_sas_device *device); 312 int (*slot_index_alloc)(struct hisi_hba *hisi_hba, 313 struct domain_device *device); 314 struct hisi_sas_device *(*alloc_dev)(struct domain_device *device); 315 void (*sl_notify_ssp)(struct hisi_hba *hisi_hba, int phy_no); 316 void (*start_delivery)(struct hisi_sas_dq *dq); 317 void (*prep_ssp)(struct hisi_hba *hisi_hba, 318 struct hisi_sas_slot *slot); 319 void (*prep_smp)(struct hisi_hba *hisi_hba, 320 struct hisi_sas_slot *slot); 321 void (*prep_stp)(struct hisi_hba *hisi_hba, 322 struct hisi_sas_slot *slot); 323 void (*prep_abort)(struct hisi_hba *hisi_hba, 324 struct hisi_sas_slot *slot); 325 void (*phys_init)(struct hisi_hba *hisi_hba); 326 void (*phy_start)(struct hisi_hba *hisi_hba, int phy_no); 327 void (*phy_disable)(struct hisi_hba *hisi_hba, int phy_no); 328 void (*phy_hard_reset)(struct hisi_hba *hisi_hba, int phy_no); 329 void (*get_events)(struct hisi_hba *hisi_hba, int phy_no); 330 void (*phy_set_linkrate)(struct hisi_hba *hisi_hba, int phy_no, 331 struct sas_phy_linkrates *linkrates); 332 enum sas_linkrate (*phy_get_max_linkrate)(void); 333 int (*clear_itct)(struct hisi_hba *hisi_hba, 334 struct hisi_sas_device *dev); 335 void (*free_device)(struct hisi_sas_device *sas_dev); 336 int (*get_wideport_bitmap)(struct hisi_hba *hisi_hba, int port_id); 337 void (*dereg_device)(struct hisi_hba *hisi_hba, 338 struct domain_device *device); 339 int (*soft_reset)(struct hisi_hba *hisi_hba); 340 u32 (*get_phys_state)(struct hisi_hba *hisi_hba); 341 int (*write_gpio)(struct hisi_hba *hisi_hba, u8 reg_type, 342 u8 reg_index, u8 reg_count, u8 *write_data); 343 void (*wait_cmds_complete_timeout)(struct hisi_hba *hisi_hba, 344 int delay_ms, int timeout_ms); 345 void (*debugfs_snapshot_regs)(struct hisi_hba *hisi_hba); 346 int complete_hdr_size; 347 struct scsi_host_template *sht; 348 }; 349 350 #define HISI_SAS_MAX_DEBUGFS_DUMP (50) 351 352 struct hisi_sas_debugfs_cq { 353 struct hisi_sas_cq *cq; 354 void *complete_hdr; 355 }; 356 357 struct hisi_sas_debugfs_dq { 358 struct hisi_sas_dq *dq; 359 struct hisi_sas_cmd_hdr *hdr; 360 }; 361 362 struct hisi_sas_debugfs_regs { 363 struct hisi_hba *hisi_hba; 364 u32 *data; 365 }; 366 367 struct hisi_sas_debugfs_port { 368 struct hisi_sas_phy *phy; 369 u32 *data; 370 }; 371 372 struct hisi_sas_debugfs_iost { 373 struct hisi_sas_iost *iost; 374 }; 375 376 struct hisi_sas_debugfs_itct { 377 struct hisi_sas_itct *itct; 378 }; 379 380 struct hisi_sas_debugfs_iost_cache { 381 struct hisi_sas_iost_itct_cache *cache; 382 }; 383 384 struct hisi_sas_debugfs_itct_cache { 385 struct hisi_sas_iost_itct_cache *cache; 386 }; 387 388 struct hisi_hba { 389 /* This must be the first element, used by SHOST_TO_SAS_HA */ 390 struct sas_ha_struct *p; 391 392 struct platform_device *platform_dev; 393 struct pci_dev *pci_dev; 394 struct device *dev; 395 396 int prot_mask; 397 398 void __iomem *regs; 399 void __iomem *sgpio_regs; 400 struct regmap *ctrl; 401 u32 ctrl_reset_reg; 402 u32 ctrl_reset_sts_reg; 403 u32 ctrl_clock_ena_reg; 404 u32 refclk_frequency_mhz; 405 u8 sas_addr[SAS_ADDR_SIZE]; 406 407 int *irq_map; /* v2 hw */ 408 409 int n_phy; 410 spinlock_t lock; 411 struct semaphore sem; 412 413 struct timer_list timer; 414 struct workqueue_struct *wq; 415 416 int slot_index_count; 417 int last_slot_index; 418 int last_dev_id; 419 unsigned long *slot_index_tags; 420 unsigned long reject_stp_links_msk; 421 422 /* SCSI/SAS glue */ 423 struct sas_ha_struct sha; 424 struct Scsi_Host *shost; 425 426 struct hisi_sas_cq cq[HISI_SAS_MAX_QUEUES]; 427 struct hisi_sas_dq dq[HISI_SAS_MAX_QUEUES]; 428 struct hisi_sas_phy phy[HISI_SAS_MAX_PHYS]; 429 struct hisi_sas_port port[HISI_SAS_MAX_PHYS]; 430 431 int queue_count; 432 433 struct hisi_sas_device devices[HISI_SAS_MAX_DEVICES]; 434 struct hisi_sas_cmd_hdr *cmd_hdr[HISI_SAS_MAX_QUEUES]; 435 dma_addr_t cmd_hdr_dma[HISI_SAS_MAX_QUEUES]; 436 void *complete_hdr[HISI_SAS_MAX_QUEUES]; 437 dma_addr_t complete_hdr_dma[HISI_SAS_MAX_QUEUES]; 438 struct hisi_sas_initial_fis *initial_fis; 439 dma_addr_t initial_fis_dma; 440 struct hisi_sas_itct *itct; 441 dma_addr_t itct_dma; 442 struct hisi_sas_iost *iost; 443 dma_addr_t iost_dma; 444 struct hisi_sas_breakpoint *breakpoint; 445 dma_addr_t breakpoint_dma; 446 struct hisi_sas_breakpoint *sata_breakpoint; 447 dma_addr_t sata_breakpoint_dma; 448 struct hisi_sas_slot *slot_info; 449 unsigned long flags; 450 const struct hisi_sas_hw *hw; /* Low level hw interface */ 451 unsigned long sata_dev_bitmap[BITS_TO_LONGS(HISI_SAS_MAX_DEVICES)]; 452 struct work_struct rst_work; 453 struct work_struct debugfs_work; 454 u32 phy_state; 455 u32 intr_coal_ticks; /* Time of interrupt coalesce in us */ 456 u32 intr_coal_count; /* Interrupt count to coalesce */ 457 458 int cq_nvecs; 459 460 /* bist */ 461 enum sas_linkrate debugfs_bist_linkrate; 462 int debugfs_bist_code_mode; 463 int debugfs_bist_phy_no; 464 int debugfs_bist_mode; 465 u32 debugfs_bist_cnt; 466 int debugfs_bist_enable; 467 u32 debugfs_bist_ffe[HISI_SAS_MAX_PHYS][FFE_CFG_MAX]; 468 u32 debugfs_bist_fixed_code[FIXED_CODE_MAX]; 469 470 /* debugfs memories */ 471 /* Put Global AXI and RAS Register into register array */ 472 struct hisi_sas_debugfs_regs debugfs_regs[HISI_SAS_MAX_DEBUGFS_DUMP][DEBUGFS_REGS_NUM]; 473 struct hisi_sas_debugfs_port debugfs_port_reg[HISI_SAS_MAX_DEBUGFS_DUMP][HISI_SAS_MAX_PHYS]; 474 struct hisi_sas_debugfs_cq debugfs_cq[HISI_SAS_MAX_DEBUGFS_DUMP][HISI_SAS_MAX_QUEUES]; 475 struct hisi_sas_debugfs_dq debugfs_dq[HISI_SAS_MAX_DEBUGFS_DUMP][HISI_SAS_MAX_QUEUES]; 476 struct hisi_sas_debugfs_iost debugfs_iost[HISI_SAS_MAX_DEBUGFS_DUMP]; 477 struct hisi_sas_debugfs_itct debugfs_itct[HISI_SAS_MAX_DEBUGFS_DUMP]; 478 struct hisi_sas_debugfs_iost_cache debugfs_iost_cache[HISI_SAS_MAX_DEBUGFS_DUMP]; 479 struct hisi_sas_debugfs_itct_cache debugfs_itct_cache[HISI_SAS_MAX_DEBUGFS_DUMP]; 480 481 u64 debugfs_timestamp[HISI_SAS_MAX_DEBUGFS_DUMP]; 482 int debugfs_dump_index; 483 struct dentry *debugfs_dir; 484 struct dentry *debugfs_dump_dentry; 485 struct dentry *debugfs_bist_dentry; 486 struct dentry *debugfs_fifo_dentry; 487 }; 488 489 /* Generic HW DMA host memory structures */ 490 /* Delivery queue header */ 491 struct hisi_sas_cmd_hdr { 492 /* dw0 */ 493 __le32 dw0; 494 495 /* dw1 */ 496 __le32 dw1; 497 498 /* dw2 */ 499 __le32 dw2; 500 501 /* dw3 */ 502 __le32 transfer_tags; 503 504 /* dw4 */ 505 __le32 data_transfer_len; 506 507 /* dw5 */ 508 __le32 first_burst_num; 509 510 /* dw6 */ 511 __le32 sg_len; 512 513 /* dw7 */ 514 __le32 dw7; 515 516 /* dw8-9 */ 517 __le64 cmd_table_addr; 518 519 /* dw10-11 */ 520 __le64 sts_buffer_addr; 521 522 /* dw12-13 */ 523 __le64 prd_table_addr; 524 525 /* dw14-15 */ 526 __le64 dif_prd_table_addr; 527 }; 528 529 struct hisi_sas_itct { 530 __le64 qw0; 531 __le64 sas_addr; 532 __le64 qw2; 533 __le64 qw3; 534 __le64 qw4_15[12]; 535 }; 536 537 struct hisi_sas_iost { 538 __le64 qw0; 539 __le64 qw1; 540 __le64 qw2; 541 __le64 qw3; 542 }; 543 544 struct hisi_sas_err_record { 545 u32 data[4]; 546 }; 547 548 struct hisi_sas_initial_fis { 549 struct hisi_sas_err_record err_record; 550 struct dev_to_host_fis fis; 551 u32 rsvd[3]; 552 }; 553 554 struct hisi_sas_breakpoint { 555 u8 data[128]; 556 }; 557 558 struct hisi_sas_sata_breakpoint { 559 struct hisi_sas_breakpoint tag[32]; 560 }; 561 562 struct hisi_sas_sge { 563 __le64 addr; 564 __le32 page_ctrl_0; 565 __le32 page_ctrl_1; 566 __le32 data_len; 567 __le32 data_off; 568 }; 569 570 struct hisi_sas_command_table_smp { 571 u8 bytes[44]; 572 }; 573 574 struct hisi_sas_command_table_stp { 575 struct host_to_dev_fis command_fis; 576 u8 dummy[12]; 577 u8 atapi_cdb[ATAPI_CDB_LEN]; 578 }; 579 580 #define HISI_SAS_SGE_PAGE_CNT (124) 581 struct hisi_sas_sge_page { 582 struct hisi_sas_sge sge[HISI_SAS_SGE_PAGE_CNT]; 583 } __aligned(16); 584 585 #define HISI_SAS_SGE_DIF_PAGE_CNT HISI_SAS_SGE_PAGE_CNT 586 struct hisi_sas_sge_dif_page { 587 struct hisi_sas_sge sge[HISI_SAS_SGE_DIF_PAGE_CNT]; 588 } __aligned(16); 589 590 struct hisi_sas_command_table_ssp { 591 struct ssp_frame_hdr hdr; 592 union { 593 struct { 594 struct ssp_command_iu task; 595 u32 prot[7]; 596 }; 597 struct ssp_tmf_iu ssp_task; 598 struct xfer_rdy_iu xfer_rdy; 599 struct ssp_response_iu ssp_res; 600 } u; 601 }; 602 603 union hisi_sas_command_table { 604 struct hisi_sas_command_table_ssp ssp; 605 struct hisi_sas_command_table_smp smp; 606 struct hisi_sas_command_table_stp stp; 607 } __aligned(16); 608 609 struct hisi_sas_status_buffer { 610 struct hisi_sas_err_record err; 611 u8 iu[1024]; 612 } __aligned(16); 613 614 struct hisi_sas_slot_buf_table { 615 struct hisi_sas_status_buffer status_buffer; 616 union hisi_sas_command_table command_header; 617 struct hisi_sas_sge_page sge_page; 618 }; 619 620 struct hisi_sas_slot_dif_buf_table { 621 struct hisi_sas_slot_buf_table slot_buf; 622 struct hisi_sas_sge_dif_page sge_dif_page; 623 }; 624 625 extern struct scsi_transport_template *hisi_sas_stt; 626 627 extern bool hisi_sas_debugfs_enable; 628 extern u32 hisi_sas_debugfs_dump_count; 629 extern struct dentry *hisi_sas_debugfs_dir; 630 631 extern void hisi_sas_stop_phys(struct hisi_hba *hisi_hba); 632 extern int hisi_sas_alloc(struct hisi_hba *hisi_hba); 633 extern void hisi_sas_free(struct hisi_hba *hisi_hba); 634 extern u8 hisi_sas_get_ata_protocol(struct host_to_dev_fis *fis, 635 int direction); 636 extern struct hisi_sas_port *to_hisi_sas_port(struct asd_sas_port *sas_port); 637 extern void hisi_sas_sata_done(struct sas_task *task, 638 struct hisi_sas_slot *slot); 639 extern int hisi_sas_get_fw_info(struct hisi_hba *hisi_hba); 640 extern int hisi_sas_probe(struct platform_device *pdev, 641 const struct hisi_sas_hw *ops); 642 extern int hisi_sas_remove(struct platform_device *pdev); 643 644 extern int hisi_sas_slave_configure(struct scsi_device *sdev); 645 extern int hisi_sas_slave_alloc(struct scsi_device *sdev); 646 extern int hisi_sas_scan_finished(struct Scsi_Host *shost, unsigned long time); 647 extern void hisi_sas_scan_start(struct Scsi_Host *shost); 648 extern int hisi_sas_host_reset(struct Scsi_Host *shost, int reset_type); 649 extern void hisi_sas_phy_enable(struct hisi_hba *hisi_hba, int phy_no, 650 int enable); 651 extern void hisi_sas_phy_down(struct hisi_hba *hisi_hba, int phy_no, int rdy, 652 gfp_t gfp_flags); 653 extern void hisi_sas_phy_bcast(struct hisi_sas_phy *phy); 654 extern void hisi_sas_slot_task_free(struct hisi_hba *hisi_hba, 655 struct sas_task *task, 656 struct hisi_sas_slot *slot); 657 extern void hisi_sas_init_mem(struct hisi_hba *hisi_hba); 658 extern void hisi_sas_rst_work_handler(struct work_struct *work); 659 extern void hisi_sas_sync_rst_work_handler(struct work_struct *work); 660 extern void hisi_sas_sync_irqs(struct hisi_hba *hisi_hba); 661 extern void hisi_sas_phy_oob_ready(struct hisi_hba *hisi_hba, int phy_no); 662 extern bool hisi_sas_notify_phy_event(struct hisi_sas_phy *phy, 663 enum hisi_sas_phy_event event); 664 extern void hisi_sas_release_tasks(struct hisi_hba *hisi_hba); 665 extern u8 hisi_sas_get_prog_phy_linkrate_mask(enum sas_linkrate max); 666 extern void hisi_sas_controller_reset_prepare(struct hisi_hba *hisi_hba); 667 extern void hisi_sas_controller_reset_done(struct hisi_hba *hisi_hba); 668 #endif 669