1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (c) 2015 Linaro Ltd. 4 * Copyright (c) 2015 Hisilicon Limited. 5 */ 6 7 #ifndef _HISI_SAS_H_ 8 #define _HISI_SAS_H_ 9 10 #include <linux/acpi.h> 11 #include <linux/blk-mq.h> 12 #include <linux/blk-mq-pci.h> 13 #include <linux/clk.h> 14 #include <linux/debugfs.h> 15 #include <linux/dmapool.h> 16 #include <linux/iopoll.h> 17 #include <linux/irq.h> 18 #include <linux/lcm.h> 19 #include <linux/libata.h> 20 #include <linux/mfd/syscon.h> 21 #include <linux/module.h> 22 #include <linux/of_address.h> 23 #include <linux/pci.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/property.h> 27 #include <linux/regmap.h> 28 #include <linux/timer.h> 29 #include <scsi/sas_ata.h> 30 #include <scsi/libsas.h> 31 32 #define HISI_SAS_MAX_PHYS 9 33 #define HISI_SAS_MAX_QUEUES 32 34 #define HISI_SAS_QUEUE_SLOTS 4096 35 #define HISI_SAS_MAX_ITCT_ENTRIES 1024 36 #define HISI_SAS_MAX_DEVICES HISI_SAS_MAX_ITCT_ENTRIES 37 #define HISI_SAS_RESETTING_BIT 0 38 #define HISI_SAS_REJECT_CMD_BIT 1 39 #define HISI_SAS_PM_BIT 2 40 #define HISI_SAS_HW_FAULT_BIT 3 41 #define HISI_SAS_MAX_COMMANDS (HISI_SAS_QUEUE_SLOTS) 42 #define HISI_SAS_RESERVED_IPTT 96 43 #define HISI_SAS_UNRESERVED_IPTT \ 44 (HISI_SAS_MAX_COMMANDS - HISI_SAS_RESERVED_IPTT) 45 46 #define HISI_SAS_IOST_ITCT_CACHE_NUM 64 47 #define HISI_SAS_IOST_ITCT_CACHE_DW_SZ 10 48 #define HISI_SAS_FIFO_DATA_DW_SIZE 32 49 50 #define HISI_SAS_STATUS_BUF_SZ (sizeof(struct hisi_sas_status_buffer)) 51 #define HISI_SAS_COMMAND_TABLE_SZ (sizeof(union hisi_sas_command_table)) 52 53 #define hisi_sas_status_buf_addr(buf) \ 54 ((buf) + offsetof(struct hisi_sas_slot_buf_table, status_buffer)) 55 #define hisi_sas_status_buf_addr_mem(slot) hisi_sas_status_buf_addr((slot)->buf) 56 #define hisi_sas_status_buf_addr_dma(slot) \ 57 hisi_sas_status_buf_addr((slot)->buf_dma) 58 59 #define hisi_sas_cmd_hdr_addr(buf) \ 60 ((buf) + offsetof(struct hisi_sas_slot_buf_table, command_header)) 61 #define hisi_sas_cmd_hdr_addr_mem(slot) hisi_sas_cmd_hdr_addr((slot)->buf) 62 #define hisi_sas_cmd_hdr_addr_dma(slot) hisi_sas_cmd_hdr_addr((slot)->buf_dma) 63 64 #define hisi_sas_sge_addr(buf) \ 65 ((buf) + offsetof(struct hisi_sas_slot_buf_table, sge_page)) 66 #define hisi_sas_sge_addr_mem(slot) hisi_sas_sge_addr((slot)->buf) 67 #define hisi_sas_sge_addr_dma(slot) hisi_sas_sge_addr((slot)->buf_dma) 68 69 #define hisi_sas_sge_dif_addr(buf) \ 70 ((buf) + offsetof(struct hisi_sas_slot_dif_buf_table, sge_dif_page)) 71 #define hisi_sas_sge_dif_addr_mem(slot) hisi_sas_sge_dif_addr((slot)->buf) 72 #define hisi_sas_sge_dif_addr_dma(slot) hisi_sas_sge_dif_addr((slot)->buf_dma) 73 74 #define HISI_SAS_MAX_SSP_RESP_SZ (sizeof(struct ssp_frame_hdr) + 1024) 75 #define HISI_SAS_MAX_SMP_RESP_SZ 1028 76 #define HISI_SAS_MAX_STP_RESP_SZ 28 77 78 #define HISI_SAS_SATA_PROTOCOL_NONDATA 0x1 79 #define HISI_SAS_SATA_PROTOCOL_PIO 0x2 80 #define HISI_SAS_SATA_PROTOCOL_DMA 0x4 81 #define HISI_SAS_SATA_PROTOCOL_FPDMA 0x8 82 #define HISI_SAS_SATA_PROTOCOL_ATAPI 0x10 83 84 #define HISI_SAS_DIF_PROT_MASK (SHOST_DIF_TYPE1_PROTECTION | \ 85 SHOST_DIF_TYPE2_PROTECTION | \ 86 SHOST_DIF_TYPE3_PROTECTION) 87 88 #define HISI_SAS_DIX_PROT_MASK (SHOST_DIX_TYPE1_PROTECTION | \ 89 SHOST_DIX_TYPE2_PROTECTION | \ 90 SHOST_DIX_TYPE3_PROTECTION) 91 92 #define HISI_SAS_PROT_MASK (HISI_SAS_DIF_PROT_MASK | HISI_SAS_DIX_PROT_MASK) 93 94 #define HISI_SAS_WAIT_PHYUP_TIMEOUT (30 * HZ) 95 #define HISI_SAS_CLEAR_ITCT_TIMEOUT (20 * HZ) 96 97 struct hisi_hba; 98 99 enum { 100 PORT_TYPE_SAS = (1U << 1), 101 PORT_TYPE_SATA = (1U << 0), 102 }; 103 104 enum dev_status { 105 HISI_SAS_DEV_INIT, 106 HISI_SAS_DEV_NORMAL, 107 }; 108 109 enum { 110 HISI_SAS_INT_ABT_CMD = 0, 111 HISI_SAS_INT_ABT_DEV = 1, 112 }; 113 114 enum hisi_sas_dev_type { 115 HISI_SAS_DEV_TYPE_STP = 0, 116 HISI_SAS_DEV_TYPE_SSP, 117 HISI_SAS_DEV_TYPE_SATA, 118 }; 119 120 struct hisi_sas_hw_error { 121 u32 irq_msk; 122 u32 msk; 123 int shift; 124 const char *msg; 125 int reg; 126 const struct hisi_sas_hw_error *sub; 127 }; 128 129 struct hisi_sas_rst { 130 struct hisi_hba *hisi_hba; 131 struct completion *completion; 132 struct work_struct work; 133 bool done; 134 }; 135 136 #define HISI_SAS_RST_WORK_INIT(r, c) \ 137 { .hisi_hba = hisi_hba, \ 138 .completion = &c, \ 139 .work = __WORK_INITIALIZER(r.work, \ 140 hisi_sas_sync_rst_work_handler), \ 141 .done = false, \ 142 } 143 144 #define HISI_SAS_DECLARE_RST_WORK_ON_STACK(r) \ 145 DECLARE_COMPLETION_ONSTACK(c); \ 146 struct hisi_sas_rst r = HISI_SAS_RST_WORK_INIT(r, c) 147 148 enum hisi_sas_bit_err_type { 149 HISI_SAS_ERR_SINGLE_BIT_ECC = 0x0, 150 HISI_SAS_ERR_MULTI_BIT_ECC = 0x1, 151 }; 152 153 enum hisi_sas_phy_event { 154 HISI_PHYE_PHY_UP = 0U, 155 HISI_PHYE_LINK_RESET, 156 HISI_PHYE_PHY_UP_PM, 157 HISI_PHYES_NUM, 158 }; 159 160 struct hisi_sas_debugfs_fifo { 161 u32 signal_sel; 162 u32 dump_msk; 163 u32 dump_mode; 164 u32 trigger; 165 u32 trigger_msk; 166 u32 trigger_mode; 167 u32 rd_data[HISI_SAS_FIFO_DATA_DW_SIZE]; 168 }; 169 170 struct hisi_sas_phy { 171 struct work_struct works[HISI_PHYES_NUM]; 172 struct hisi_hba *hisi_hba; 173 struct hisi_sas_port *port; 174 struct asd_sas_phy sas_phy; 175 struct sas_identify identify; 176 struct completion *reset_completion; 177 struct timer_list timer; 178 spinlock_t lock; 179 u64 port_id; /* from hw */ 180 u64 frame_rcvd_size; 181 u8 frame_rcvd[32]; 182 u8 phy_attached; 183 u8 in_reset; 184 u8 reserved[2]; 185 u32 phy_type; 186 u32 code_violation_err_count; 187 enum sas_linkrate minimum_linkrate; 188 enum sas_linkrate maximum_linkrate; 189 int enable; 190 int wait_phyup_cnt; 191 atomic_t down_cnt; 192 193 /* Trace FIFO */ 194 struct hisi_sas_debugfs_fifo fifo; 195 }; 196 197 struct hisi_sas_port { 198 struct asd_sas_port sas_port; 199 u8 port_attached; 200 u8 id; /* from hw */ 201 }; 202 203 struct hisi_sas_cq { 204 struct hisi_hba *hisi_hba; 205 const struct cpumask *irq_mask; 206 int rd_point; 207 int id; 208 int irq_no; 209 }; 210 211 struct hisi_sas_dq { 212 struct hisi_hba *hisi_hba; 213 struct list_head list; 214 spinlock_t lock; 215 int wr_point; 216 int id; 217 }; 218 219 struct hisi_sas_device { 220 struct hisi_hba *hisi_hba; 221 struct domain_device *sas_device; 222 struct completion *completion; 223 struct hisi_sas_dq *dq; 224 struct list_head list; 225 enum sas_device_type dev_type; 226 enum dev_status dev_status; 227 int device_id; 228 int sata_idx; 229 spinlock_t lock; /* For protecting slots */ 230 }; 231 232 struct hisi_sas_slot { 233 struct list_head entry; 234 struct list_head delivery; 235 struct sas_task *task; 236 struct hisi_sas_port *port; 237 u64 n_elem; 238 u64 n_elem_dif; 239 int dlvry_queue; 240 int dlvry_queue_slot; 241 int cmplt_queue; 242 int cmplt_queue_slot; 243 int abort; 244 int ready; 245 int device_id; 246 void *cmd_hdr; 247 dma_addr_t cmd_hdr_dma; 248 struct timer_list internal_abort_timer; 249 bool is_internal; 250 struct sas_tmf_task *tmf; 251 /* Do not reorder/change members after here */ 252 void *buf; 253 dma_addr_t buf_dma; 254 u16 idx; 255 }; 256 257 struct hisi_sas_iost_itct_cache { 258 u32 data[HISI_SAS_IOST_ITCT_CACHE_DW_SZ]; 259 }; 260 261 enum hisi_sas_debugfs_reg_array_member { 262 DEBUGFS_GLOBAL = 0, 263 DEBUGFS_AXI, 264 DEBUGFS_RAS, 265 DEBUGFS_REGS_NUM 266 }; 267 268 enum hisi_sas_debugfs_cache_type { 269 HISI_SAS_ITCT_CACHE, 270 HISI_SAS_IOST_CACHE, 271 }; 272 273 enum hisi_sas_debugfs_bist_ffe_cfg { 274 FFE_SAS_1_5_GBPS, 275 FFE_SAS_3_0_GBPS, 276 FFE_SAS_6_0_GBPS, 277 FFE_SAS_12_0_GBPS, 278 FFE_RESV, 279 FFE_SATA_1_5_GBPS, 280 FFE_SATA_3_0_GBPS, 281 FFE_SATA_6_0_GBPS, 282 FFE_CFG_MAX 283 }; 284 285 enum hisi_sas_debugfs_bist_fixed_code { 286 FIXED_CODE, 287 FIXED_CODE_1, 288 FIXED_CODE_MAX 289 }; 290 291 enum { 292 HISI_SAS_BIST_CODE_MODE_PRBS7, 293 HISI_SAS_BIST_CODE_MODE_PRBS23, 294 HISI_SAS_BIST_CODE_MODE_PRBS31, 295 HISI_SAS_BIST_CODE_MODE_JTPAT, 296 HISI_SAS_BIST_CODE_MODE_CJTPAT, 297 HISI_SAS_BIST_CODE_MODE_SCRAMBED_0, 298 HISI_SAS_BIST_CODE_MODE_TRAIN, 299 HISI_SAS_BIST_CODE_MODE_TRAIN_DONE, 300 HISI_SAS_BIST_CODE_MODE_HFTP, 301 HISI_SAS_BIST_CODE_MODE_MFTP, 302 HISI_SAS_BIST_CODE_MODE_LFTP, 303 HISI_SAS_BIST_CODE_MODE_FIXED_DATA, 304 }; 305 306 struct hisi_sas_hw { 307 int (*hw_init)(struct hisi_hba *hisi_hba); 308 int (*interrupt_preinit)(struct hisi_hba *hisi_hba); 309 void (*setup_itct)(struct hisi_hba *hisi_hba, 310 struct hisi_sas_device *device); 311 int (*slot_index_alloc)(struct hisi_hba *hisi_hba, 312 struct domain_device *device); 313 struct hisi_sas_device *(*alloc_dev)(struct domain_device *device); 314 void (*sl_notify_ssp)(struct hisi_hba *hisi_hba, int phy_no); 315 void (*start_delivery)(struct hisi_sas_dq *dq); 316 void (*prep_ssp)(struct hisi_hba *hisi_hba, 317 struct hisi_sas_slot *slot); 318 void (*prep_smp)(struct hisi_hba *hisi_hba, 319 struct hisi_sas_slot *slot); 320 void (*prep_stp)(struct hisi_hba *hisi_hba, 321 struct hisi_sas_slot *slot); 322 void (*prep_abort)(struct hisi_hba *hisi_hba, 323 struct hisi_sas_slot *slot); 324 void (*phys_init)(struct hisi_hba *hisi_hba); 325 void (*phy_start)(struct hisi_hba *hisi_hba, int phy_no); 326 void (*phy_disable)(struct hisi_hba *hisi_hba, int phy_no); 327 void (*phy_hard_reset)(struct hisi_hba *hisi_hba, int phy_no); 328 void (*get_events)(struct hisi_hba *hisi_hba, int phy_no); 329 void (*phy_set_linkrate)(struct hisi_hba *hisi_hba, int phy_no, 330 struct sas_phy_linkrates *linkrates); 331 enum sas_linkrate (*phy_get_max_linkrate)(void); 332 int (*clear_itct)(struct hisi_hba *hisi_hba, 333 struct hisi_sas_device *dev); 334 void (*free_device)(struct hisi_sas_device *sas_dev); 335 int (*get_wideport_bitmap)(struct hisi_hba *hisi_hba, int port_id); 336 void (*dereg_device)(struct hisi_hba *hisi_hba, 337 struct domain_device *device); 338 int (*soft_reset)(struct hisi_hba *hisi_hba); 339 u32 (*get_phys_state)(struct hisi_hba *hisi_hba); 340 int (*write_gpio)(struct hisi_hba *hisi_hba, u8 reg_type, 341 u8 reg_index, u8 reg_count, u8 *write_data); 342 void (*wait_cmds_complete_timeout)(struct hisi_hba *hisi_hba, 343 int delay_ms, int timeout_ms); 344 void (*debugfs_snapshot_regs)(struct hisi_hba *hisi_hba); 345 int complete_hdr_size; 346 struct scsi_host_template *sht; 347 }; 348 349 #define HISI_SAS_MAX_DEBUGFS_DUMP (50) 350 351 struct hisi_sas_debugfs_cq { 352 struct hisi_sas_cq *cq; 353 void *complete_hdr; 354 }; 355 356 struct hisi_sas_debugfs_dq { 357 struct hisi_sas_dq *dq; 358 struct hisi_sas_cmd_hdr *hdr; 359 }; 360 361 struct hisi_sas_debugfs_regs { 362 struct hisi_hba *hisi_hba; 363 u32 *data; 364 }; 365 366 struct hisi_sas_debugfs_port { 367 struct hisi_sas_phy *phy; 368 u32 *data; 369 }; 370 371 struct hisi_sas_debugfs_iost { 372 struct hisi_sas_iost *iost; 373 }; 374 375 struct hisi_sas_debugfs_itct { 376 struct hisi_sas_itct *itct; 377 }; 378 379 struct hisi_sas_debugfs_iost_cache { 380 struct hisi_sas_iost_itct_cache *cache; 381 }; 382 383 struct hisi_sas_debugfs_itct_cache { 384 struct hisi_sas_iost_itct_cache *cache; 385 }; 386 387 struct hisi_hba { 388 /* This must be the first element, used by SHOST_TO_SAS_HA */ 389 struct sas_ha_struct *p; 390 391 struct platform_device *platform_dev; 392 struct pci_dev *pci_dev; 393 struct device *dev; 394 395 int prot_mask; 396 397 void __iomem *regs; 398 void __iomem *sgpio_regs; 399 struct regmap *ctrl; 400 u32 ctrl_reset_reg; 401 u32 ctrl_reset_sts_reg; 402 u32 ctrl_clock_ena_reg; 403 u32 refclk_frequency_mhz; 404 u8 sas_addr[SAS_ADDR_SIZE]; 405 406 int *irq_map; /* v2 hw */ 407 408 int n_phy; 409 spinlock_t lock; 410 struct semaphore sem; 411 412 struct timer_list timer; 413 struct workqueue_struct *wq; 414 415 int slot_index_count; 416 int last_slot_index; 417 int last_dev_id; 418 unsigned long *slot_index_tags; 419 unsigned long reject_stp_links_msk; 420 421 /* SCSI/SAS glue */ 422 struct sas_ha_struct sha; 423 struct Scsi_Host *shost; 424 425 struct hisi_sas_cq cq[HISI_SAS_MAX_QUEUES]; 426 struct hisi_sas_dq dq[HISI_SAS_MAX_QUEUES]; 427 struct hisi_sas_phy phy[HISI_SAS_MAX_PHYS]; 428 struct hisi_sas_port port[HISI_SAS_MAX_PHYS]; 429 430 int queue_count; 431 432 struct hisi_sas_device devices[HISI_SAS_MAX_DEVICES]; 433 struct hisi_sas_cmd_hdr *cmd_hdr[HISI_SAS_MAX_QUEUES]; 434 dma_addr_t cmd_hdr_dma[HISI_SAS_MAX_QUEUES]; 435 void *complete_hdr[HISI_SAS_MAX_QUEUES]; 436 dma_addr_t complete_hdr_dma[HISI_SAS_MAX_QUEUES]; 437 struct hisi_sas_initial_fis *initial_fis; 438 dma_addr_t initial_fis_dma; 439 struct hisi_sas_itct *itct; 440 dma_addr_t itct_dma; 441 struct hisi_sas_iost *iost; 442 dma_addr_t iost_dma; 443 struct hisi_sas_breakpoint *breakpoint; 444 dma_addr_t breakpoint_dma; 445 struct hisi_sas_breakpoint *sata_breakpoint; 446 dma_addr_t sata_breakpoint_dma; 447 struct hisi_sas_slot *slot_info; 448 unsigned long flags; 449 const struct hisi_sas_hw *hw; /* Low level hw interface */ 450 unsigned long sata_dev_bitmap[BITS_TO_LONGS(HISI_SAS_MAX_DEVICES)]; 451 struct work_struct rst_work; 452 struct work_struct debugfs_work; 453 u32 phy_state; 454 u32 intr_coal_ticks; /* Time of interrupt coalesce in us */ 455 u32 intr_coal_count; /* Interrupt count to coalesce */ 456 457 int cq_nvecs; 458 459 /* bist */ 460 enum sas_linkrate debugfs_bist_linkrate; 461 int debugfs_bist_code_mode; 462 int debugfs_bist_phy_no; 463 int debugfs_bist_mode; 464 u32 debugfs_bist_cnt; 465 int debugfs_bist_enable; 466 u32 debugfs_bist_ffe[HISI_SAS_MAX_PHYS][FFE_CFG_MAX]; 467 u32 debugfs_bist_fixed_code[FIXED_CODE_MAX]; 468 469 /* debugfs memories */ 470 /* Put Global AXI and RAS Register into register array */ 471 struct hisi_sas_debugfs_regs debugfs_regs[HISI_SAS_MAX_DEBUGFS_DUMP][DEBUGFS_REGS_NUM]; 472 struct hisi_sas_debugfs_port debugfs_port_reg[HISI_SAS_MAX_DEBUGFS_DUMP][HISI_SAS_MAX_PHYS]; 473 struct hisi_sas_debugfs_cq debugfs_cq[HISI_SAS_MAX_DEBUGFS_DUMP][HISI_SAS_MAX_QUEUES]; 474 struct hisi_sas_debugfs_dq debugfs_dq[HISI_SAS_MAX_DEBUGFS_DUMP][HISI_SAS_MAX_QUEUES]; 475 struct hisi_sas_debugfs_iost debugfs_iost[HISI_SAS_MAX_DEBUGFS_DUMP]; 476 struct hisi_sas_debugfs_itct debugfs_itct[HISI_SAS_MAX_DEBUGFS_DUMP]; 477 struct hisi_sas_debugfs_iost_cache debugfs_iost_cache[HISI_SAS_MAX_DEBUGFS_DUMP]; 478 struct hisi_sas_debugfs_itct_cache debugfs_itct_cache[HISI_SAS_MAX_DEBUGFS_DUMP]; 479 480 u64 debugfs_timestamp[HISI_SAS_MAX_DEBUGFS_DUMP]; 481 int debugfs_dump_index; 482 struct dentry *debugfs_dir; 483 struct dentry *debugfs_dump_dentry; 484 struct dentry *debugfs_bist_dentry; 485 struct dentry *debugfs_fifo_dentry; 486 }; 487 488 /* Generic HW DMA host memory structures */ 489 /* Delivery queue header */ 490 struct hisi_sas_cmd_hdr { 491 /* dw0 */ 492 __le32 dw0; 493 494 /* dw1 */ 495 __le32 dw1; 496 497 /* dw2 */ 498 __le32 dw2; 499 500 /* dw3 */ 501 __le32 transfer_tags; 502 503 /* dw4 */ 504 __le32 data_transfer_len; 505 506 /* dw5 */ 507 __le32 first_burst_num; 508 509 /* dw6 */ 510 __le32 sg_len; 511 512 /* dw7 */ 513 __le32 dw7; 514 515 /* dw8-9 */ 516 __le64 cmd_table_addr; 517 518 /* dw10-11 */ 519 __le64 sts_buffer_addr; 520 521 /* dw12-13 */ 522 __le64 prd_table_addr; 523 524 /* dw14-15 */ 525 __le64 dif_prd_table_addr; 526 }; 527 528 struct hisi_sas_itct { 529 __le64 qw0; 530 __le64 sas_addr; 531 __le64 qw2; 532 __le64 qw3; 533 __le64 qw4_15[12]; 534 }; 535 536 struct hisi_sas_iost { 537 __le64 qw0; 538 __le64 qw1; 539 __le64 qw2; 540 __le64 qw3; 541 }; 542 543 struct hisi_sas_err_record { 544 u32 data[4]; 545 }; 546 547 struct hisi_sas_initial_fis { 548 struct hisi_sas_err_record err_record; 549 struct dev_to_host_fis fis; 550 u32 rsvd[3]; 551 }; 552 553 struct hisi_sas_breakpoint { 554 u8 data[128]; 555 }; 556 557 struct hisi_sas_sata_breakpoint { 558 struct hisi_sas_breakpoint tag[32]; 559 }; 560 561 struct hisi_sas_sge { 562 __le64 addr; 563 __le32 page_ctrl_0; 564 __le32 page_ctrl_1; 565 __le32 data_len; 566 __le32 data_off; 567 }; 568 569 struct hisi_sas_command_table_smp { 570 u8 bytes[44]; 571 }; 572 573 struct hisi_sas_command_table_stp { 574 struct host_to_dev_fis command_fis; 575 u8 dummy[12]; 576 u8 atapi_cdb[ATAPI_CDB_LEN]; 577 }; 578 579 #define HISI_SAS_SGE_PAGE_CNT (124) 580 struct hisi_sas_sge_page { 581 struct hisi_sas_sge sge[HISI_SAS_SGE_PAGE_CNT]; 582 } __aligned(16); 583 584 #define HISI_SAS_SGE_DIF_PAGE_CNT HISI_SAS_SGE_PAGE_CNT 585 struct hisi_sas_sge_dif_page { 586 struct hisi_sas_sge sge[HISI_SAS_SGE_DIF_PAGE_CNT]; 587 } __aligned(16); 588 589 struct hisi_sas_command_table_ssp { 590 struct ssp_frame_hdr hdr; 591 union { 592 struct { 593 struct ssp_command_iu task; 594 u32 prot[7]; 595 }; 596 struct ssp_tmf_iu ssp_task; 597 struct xfer_rdy_iu xfer_rdy; 598 struct ssp_response_iu ssp_res; 599 } u; 600 }; 601 602 union hisi_sas_command_table { 603 struct hisi_sas_command_table_ssp ssp; 604 struct hisi_sas_command_table_smp smp; 605 struct hisi_sas_command_table_stp stp; 606 } __aligned(16); 607 608 struct hisi_sas_status_buffer { 609 struct hisi_sas_err_record err; 610 u8 iu[1024]; 611 } __aligned(16); 612 613 struct hisi_sas_slot_buf_table { 614 struct hisi_sas_status_buffer status_buffer; 615 union hisi_sas_command_table command_header; 616 struct hisi_sas_sge_page sge_page; 617 }; 618 619 struct hisi_sas_slot_dif_buf_table { 620 struct hisi_sas_slot_buf_table slot_buf; 621 struct hisi_sas_sge_dif_page sge_dif_page; 622 }; 623 624 extern struct scsi_transport_template *hisi_sas_stt; 625 626 extern bool hisi_sas_debugfs_enable; 627 extern u32 hisi_sas_debugfs_dump_count; 628 extern struct dentry *hisi_sas_debugfs_dir; 629 630 extern void hisi_sas_stop_phys(struct hisi_hba *hisi_hba); 631 extern int hisi_sas_alloc(struct hisi_hba *hisi_hba); 632 extern void hisi_sas_free(struct hisi_hba *hisi_hba); 633 extern u8 hisi_sas_get_ata_protocol(struct host_to_dev_fis *fis, 634 int direction); 635 extern struct hisi_sas_port *to_hisi_sas_port(struct asd_sas_port *sas_port); 636 extern void hisi_sas_sata_done(struct sas_task *task, 637 struct hisi_sas_slot *slot); 638 extern int hisi_sas_get_fw_info(struct hisi_hba *hisi_hba); 639 extern int hisi_sas_probe(struct platform_device *pdev, 640 const struct hisi_sas_hw *ops); 641 extern int hisi_sas_remove(struct platform_device *pdev); 642 643 extern int hisi_sas_slave_configure(struct scsi_device *sdev); 644 extern int hisi_sas_slave_alloc(struct scsi_device *sdev); 645 extern int hisi_sas_scan_finished(struct Scsi_Host *shost, unsigned long time); 646 extern void hisi_sas_scan_start(struct Scsi_Host *shost); 647 extern int hisi_sas_host_reset(struct Scsi_Host *shost, int reset_type); 648 extern void hisi_sas_phy_enable(struct hisi_hba *hisi_hba, int phy_no, 649 int enable); 650 extern void hisi_sas_phy_down(struct hisi_hba *hisi_hba, int phy_no, int rdy, 651 gfp_t gfp_flags); 652 extern void hisi_sas_slot_task_free(struct hisi_hba *hisi_hba, 653 struct sas_task *task, 654 struct hisi_sas_slot *slot); 655 extern void hisi_sas_init_mem(struct hisi_hba *hisi_hba); 656 extern void hisi_sas_rst_work_handler(struct work_struct *work); 657 extern void hisi_sas_sync_rst_work_handler(struct work_struct *work); 658 extern void hisi_sas_sync_irqs(struct hisi_hba *hisi_hba); 659 extern void hisi_sas_phy_oob_ready(struct hisi_hba *hisi_hba, int phy_no); 660 extern bool hisi_sas_notify_phy_event(struct hisi_sas_phy *phy, 661 enum hisi_sas_phy_event event); 662 extern void hisi_sas_release_tasks(struct hisi_hba *hisi_hba); 663 extern u8 hisi_sas_get_prog_phy_linkrate_mask(enum sas_linkrate max); 664 extern void hisi_sas_controller_reset_prepare(struct hisi_hba *hisi_hba); 665 extern void hisi_sas_controller_reset_done(struct hisi_hba *hisi_hba); 666 #endif 667