1 /* esp_scsi.h: Defines and structures for the ESP drier. 2 * 3 * Copyright (C) 2007 David S. Miller (davem@davemloft.net) 4 */ 5 6 #ifndef _ESP_SCSI_H 7 #define _ESP_SCSI_H 8 9 /* Access Description Offset */ 10 #define ESP_TCLOW 0x00UL /* rw Low bits transfer count 0x00 */ 11 #define ESP_TCMED 0x01UL /* rw Mid bits transfer count 0x04 */ 12 #define ESP_FDATA 0x02UL /* rw FIFO data bits 0x08 */ 13 #define ESP_CMD 0x03UL /* rw SCSI command bits 0x0c */ 14 #define ESP_STATUS 0x04UL /* ro ESP status register 0x10 */ 15 #define ESP_BUSID ESP_STATUS /* wo BusID for sel/resel 0x10 */ 16 #define ESP_INTRPT 0x05UL /* ro Kind of interrupt 0x14 */ 17 #define ESP_TIMEO ESP_INTRPT /* wo Timeout for sel/resel 0x14 */ 18 #define ESP_SSTEP 0x06UL /* ro Sequence step register 0x18 */ 19 #define ESP_STP ESP_SSTEP /* wo Transfer period/sync 0x18 */ 20 #define ESP_FFLAGS 0x07UL /* ro Bits current FIFO info 0x1c */ 21 #define ESP_SOFF ESP_FFLAGS /* wo Sync offset 0x1c */ 22 #define ESP_CFG1 0x08UL /* rw First cfg register 0x20 */ 23 #define ESP_CFACT 0x09UL /* wo Clock conv factor 0x24 */ 24 #define ESP_STATUS2 ESP_CFACT /* ro HME status2 register 0x24 */ 25 #define ESP_CTEST 0x0aUL /* wo Chip test register 0x28 */ 26 #define ESP_CFG2 0x0bUL /* rw Second cfg register 0x2c */ 27 #define ESP_CFG3 0x0cUL /* rw Third cfg register 0x30 */ 28 #define ESP_TCHI 0x0eUL /* rw High bits transf count 0x38 */ 29 #define ESP_UID ESP_TCHI /* ro Unique ID code 0x38 */ 30 #define FAS_RLO ESP_TCHI /* rw HME extended counter 0x38 */ 31 #define ESP_FGRND 0x0fUL /* rw Data base for fifo 0x3c */ 32 #define FAS_RHI ESP_FGRND /* rw HME extended counter 0x3c */ 33 34 #define SBUS_ESP_REG_SIZE 0x40UL 35 36 /* Bitfield meanings for the above registers. */ 37 38 /* ESP config reg 1, read-write, found on all ESP chips */ 39 #define ESP_CONFIG1_ID 0x07 /* My BUS ID bits */ 40 #define ESP_CONFIG1_CHTEST 0x08 /* Enable ESP chip tests */ 41 #define ESP_CONFIG1_PENABLE 0x10 /* Enable parity checks */ 42 #define ESP_CONFIG1_PARTEST 0x20 /* Parity test mode enabled? */ 43 #define ESP_CONFIG1_SRRDISAB 0x40 /* Disable SCSI reset reports */ 44 #define ESP_CONFIG1_SLCABLE 0x80 /* Enable slow cable mode */ 45 46 /* ESP config reg 2, read-write, found only on esp100a+esp200+esp236 chips */ 47 #define ESP_CONFIG2_DMAPARITY 0x01 /* enable DMA Parity (200,236) */ 48 #define ESP_CONFIG2_REGPARITY 0x02 /* enable reg Parity (200,236) */ 49 #define ESP_CONFIG2_BADPARITY 0x04 /* Bad parity target abort */ 50 #define ESP_CONFIG2_SCSI2ENAB 0x08 /* Enable SCSI-2 features (tgtmode) */ 51 #define ESP_CONFIG2_HI 0x10 /* High Impedance DREQ ??? */ 52 #define ESP_CONFIG2_HMEFENAB 0x10 /* HME features enable */ 53 #define ESP_CONFIG2_BCM 0x20 /* Enable byte-ctrl (236) */ 54 #define ESP_CONFIG2_DISPINT 0x20 /* Disable pause irq (hme) */ 55 #define ESP_CONFIG2_FENAB 0x40 /* Enable features (fas100,216) */ 56 #define ESP_CONFIG2_SPL 0x40 /* Enable status-phase latch (236) */ 57 #define ESP_CONFIG2_MKDONE 0x40 /* HME magic feature */ 58 #define ESP_CONFIG2_HME32 0x80 /* HME 32 extended */ 59 #define ESP_CONFIG2_MAGIC 0xe0 /* Invalid bits... */ 60 61 /* ESP config register 3 read-write, found only esp236+fas236+fas100a+hme chips */ 62 #define ESP_CONFIG3_FCLOCK 0x01 /* FAST SCSI clock rate (esp100a/hme) */ 63 #define ESP_CONFIG3_TEM 0x01 /* Enable thresh-8 mode (esp/fas236) */ 64 #define ESP_CONFIG3_FAST 0x02 /* Enable FAST SCSI (esp100a/hme) */ 65 #define ESP_CONFIG3_ADMA 0x02 /* Enable alternate-dma (esp/fas236) */ 66 #define ESP_CONFIG3_TENB 0x04 /* group2 SCSI2 support (esp100a/hme) */ 67 #define ESP_CONFIG3_SRB 0x04 /* Save residual byte (esp/fas236) */ 68 #define ESP_CONFIG3_TMS 0x08 /* Three-byte msg's ok (esp100a/hme) */ 69 #define ESP_CONFIG3_FCLK 0x08 /* Fast SCSI clock rate (esp/fas236) */ 70 #define ESP_CONFIG3_IDMSG 0x10 /* ID message checking (esp100a/hme) */ 71 #define ESP_CONFIG3_FSCSI 0x10 /* Enable FAST SCSI (esp/fas236) */ 72 #define ESP_CONFIG3_GTM 0x20 /* group2 SCSI2 support (esp/fas236) */ 73 #define ESP_CONFIG3_IDBIT3 0x20 /* Bit 3 of HME SCSI-ID (hme) */ 74 #define ESP_CONFIG3_TBMS 0x40 /* Three-byte msg's ok (esp/fas236) */ 75 #define ESP_CONFIG3_EWIDE 0x40 /* Enable Wide-SCSI (hme) */ 76 #define ESP_CONFIG3_IMS 0x80 /* ID msg chk'ng (esp/fas236) */ 77 #define ESP_CONFIG3_OBPUSH 0x80 /* Push odd-byte to dma (hme) */ 78 79 /* ESP command register read-write */ 80 /* Group 1 commands: These may be sent at any point in time to the ESP 81 * chip. None of them can generate interrupts 'cept 82 * the "SCSI bus reset" command if you have not disabled 83 * SCSI reset interrupts in the config1 ESP register. 84 */ 85 #define ESP_CMD_NULL 0x00 /* Null command, ie. a nop */ 86 #define ESP_CMD_FLUSH 0x01 /* FIFO Flush */ 87 #define ESP_CMD_RC 0x02 /* Chip reset */ 88 #define ESP_CMD_RS 0x03 /* SCSI bus reset */ 89 90 /* Group 2 commands: ESP must be an initiator and connected to a target 91 * for these commands to work. 92 */ 93 #define ESP_CMD_TI 0x10 /* Transfer Information */ 94 #define ESP_CMD_ICCSEQ 0x11 /* Initiator cmd complete sequence */ 95 #define ESP_CMD_MOK 0x12 /* Message okie-dokie */ 96 #define ESP_CMD_TPAD 0x18 /* Transfer Pad */ 97 #define ESP_CMD_SATN 0x1a /* Set ATN */ 98 #define ESP_CMD_RATN 0x1b /* De-assert ATN */ 99 100 /* Group 3 commands: ESP must be in the MSGOUT or MSGIN state and be connected 101 * to a target as the initiator for these commands to work. 102 */ 103 #define ESP_CMD_SMSG 0x20 /* Send message */ 104 #define ESP_CMD_SSTAT 0x21 /* Send status */ 105 #define ESP_CMD_SDATA 0x22 /* Send data */ 106 #define ESP_CMD_DSEQ 0x23 /* Discontinue Sequence */ 107 #define ESP_CMD_TSEQ 0x24 /* Terminate Sequence */ 108 #define ESP_CMD_TCCSEQ 0x25 /* Target cmd cmplt sequence */ 109 #define ESP_CMD_DCNCT 0x27 /* Disconnect */ 110 #define ESP_CMD_RMSG 0x28 /* Receive Message */ 111 #define ESP_CMD_RCMD 0x29 /* Receive Command */ 112 #define ESP_CMD_RDATA 0x2a /* Receive Data */ 113 #define ESP_CMD_RCSEQ 0x2b /* Receive cmd sequence */ 114 115 /* Group 4 commands: The ESP must be in the disconnected state and must 116 * not be connected to any targets as initiator for 117 * these commands to work. 118 */ 119 #define ESP_CMD_RSEL 0x40 /* Reselect */ 120 #define ESP_CMD_SEL 0x41 /* Select w/o ATN */ 121 #define ESP_CMD_SELA 0x42 /* Select w/ATN */ 122 #define ESP_CMD_SELAS 0x43 /* Select w/ATN & STOP */ 123 #define ESP_CMD_ESEL 0x44 /* Enable selection */ 124 #define ESP_CMD_DSEL 0x45 /* Disable selections */ 125 #define ESP_CMD_SA3 0x46 /* Select w/ATN3 */ 126 #define ESP_CMD_RSEL3 0x47 /* Reselect3 */ 127 128 /* This bit enables the ESP's DMA on the SBus */ 129 #define ESP_CMD_DMA 0x80 /* Do DMA? */ 130 131 /* ESP status register read-only */ 132 #define ESP_STAT_PIO 0x01 /* IO phase bit */ 133 #define ESP_STAT_PCD 0x02 /* CD phase bit */ 134 #define ESP_STAT_PMSG 0x04 /* MSG phase bit */ 135 #define ESP_STAT_PMASK 0x07 /* Mask of phase bits */ 136 #define ESP_STAT_TDONE 0x08 /* Transfer Completed */ 137 #define ESP_STAT_TCNT 0x10 /* Transfer Counter Is Zero */ 138 #define ESP_STAT_PERR 0x20 /* Parity error */ 139 #define ESP_STAT_SPAM 0x40 /* Real bad error */ 140 /* This indicates the 'interrupt pending' condition on esp236, it is a reserved 141 * bit on other revs of the ESP. 142 */ 143 #define ESP_STAT_INTR 0x80 /* Interrupt */ 144 145 /* The status register can be masked with ESP_STAT_PMASK and compared 146 * with the following values to determine the current phase the ESP 147 * (at least thinks it) is in. For our purposes we also add our own 148 * software 'done' bit for our phase management engine. 149 */ 150 #define ESP_DOP (0) /* Data Out */ 151 #define ESP_DIP (ESP_STAT_PIO) /* Data In */ 152 #define ESP_CMDP (ESP_STAT_PCD) /* Command */ 153 #define ESP_STATP (ESP_STAT_PCD|ESP_STAT_PIO) /* Status */ 154 #define ESP_MOP (ESP_STAT_PMSG|ESP_STAT_PCD) /* Message Out */ 155 #define ESP_MIP (ESP_STAT_PMSG|ESP_STAT_PCD|ESP_STAT_PIO) /* Message In */ 156 157 /* HME only: status 2 register */ 158 #define ESP_STAT2_SCHBIT 0x01 /* Upper bits 3-7 of sstep enabled */ 159 #define ESP_STAT2_FFLAGS 0x02 /* The fifo flags are now latched */ 160 #define ESP_STAT2_XCNT 0x04 /* The transfer counter is latched */ 161 #define ESP_STAT2_CREGA 0x08 /* The command reg is active now */ 162 #define ESP_STAT2_WIDE 0x10 /* Interface on this adapter is wide */ 163 #define ESP_STAT2_F1BYTE 0x20 /* There is one byte at top of fifo */ 164 #define ESP_STAT2_FMSB 0x40 /* Next byte in fifo is most significant */ 165 #define ESP_STAT2_FEMPTY 0x80 /* FIFO is empty */ 166 167 /* ESP interrupt register read-only */ 168 #define ESP_INTR_S 0x01 /* Select w/o ATN */ 169 #define ESP_INTR_SATN 0x02 /* Select w/ATN */ 170 #define ESP_INTR_RSEL 0x04 /* Reselected */ 171 #define ESP_INTR_FDONE 0x08 /* Function done */ 172 #define ESP_INTR_BSERV 0x10 /* Bus service */ 173 #define ESP_INTR_DC 0x20 /* Disconnect */ 174 #define ESP_INTR_IC 0x40 /* Illegal command given */ 175 #define ESP_INTR_SR 0x80 /* SCSI bus reset detected */ 176 177 /* ESP sequence step register read-only */ 178 #define ESP_STEP_VBITS 0x07 /* Valid bits */ 179 #define ESP_STEP_ASEL 0x00 /* Selection&Arbitrate cmplt */ 180 #define ESP_STEP_SID 0x01 /* One msg byte sent */ 181 #define ESP_STEP_NCMD 0x02 /* Was not in command phase */ 182 #define ESP_STEP_PPC 0x03 /* Early phase chg caused cmnd 183 * bytes to be lost 184 */ 185 #define ESP_STEP_FINI4 0x04 /* Command was sent ok */ 186 187 /* Ho hum, some ESP's set the step register to this as well... */ 188 #define ESP_STEP_FINI5 0x05 189 #define ESP_STEP_FINI6 0x06 190 #define ESP_STEP_FINI7 0x07 191 192 /* ESP chip-test register read-write */ 193 #define ESP_TEST_TARG 0x01 /* Target test mode */ 194 #define ESP_TEST_INI 0x02 /* Initiator test mode */ 195 #define ESP_TEST_TS 0x04 /* Tristate test mode */ 196 197 /* ESP unique ID register read-only, found on fas236+fas100a only */ 198 #define ESP_UID_F100A 0x00 /* ESP FAS100A */ 199 #define ESP_UID_F236 0x02 /* ESP FAS236 */ 200 #define ESP_UID_REV 0x07 /* ESP revision */ 201 #define ESP_UID_FAM 0xf8 /* ESP family */ 202 203 /* ESP fifo flags register read-only */ 204 /* Note that the following implies a 16 byte FIFO on the ESP. */ 205 #define ESP_FF_FBYTES 0x1f /* Num bytes in FIFO */ 206 #define ESP_FF_ONOTZERO 0x20 /* offset ctr not zero (esp100) */ 207 #define ESP_FF_SSTEP 0xe0 /* Sequence step */ 208 209 /* ESP clock conversion factor register write-only */ 210 #define ESP_CCF_F0 0x00 /* 35.01MHz - 40MHz */ 211 #define ESP_CCF_NEVER 0x01 /* Set it to this and die */ 212 #define ESP_CCF_F2 0x02 /* 10MHz */ 213 #define ESP_CCF_F3 0x03 /* 10.01MHz - 15MHz */ 214 #define ESP_CCF_F4 0x04 /* 15.01MHz - 20MHz */ 215 #define ESP_CCF_F5 0x05 /* 20.01MHz - 25MHz */ 216 #define ESP_CCF_F6 0x06 /* 25.01MHz - 30MHz */ 217 #define ESP_CCF_F7 0x07 /* 30.01MHz - 35MHz */ 218 219 /* HME only... */ 220 #define ESP_BUSID_RESELID 0x10 221 #define ESP_BUSID_CTR32BIT 0x40 222 223 #define ESP_BUS_TIMEOUT 250 /* In milli-seconds */ 224 #define ESP_TIMEO_CONST 8192 225 #define ESP_NEG_DEFP(mhz, cfact) \ 226 ((ESP_BUS_TIMEOUT * ((mhz) / 1000)) / (8192 * (cfact))) 227 #define ESP_HZ_TO_CYCLE(hertz) ((1000000000) / ((hertz) / 1000)) 228 #define ESP_TICK(ccf, cycle) ((7682 * (ccf) * (cycle) / 1000)) 229 230 /* For slow to medium speed input clock rates we shoot for 5mb/s, but for high 231 * input clock rates we try to do 10mb/s although I don't think a transfer can 232 * even run that fast with an ESP even with DMA2 scatter gather pipelining. 233 */ 234 #define SYNC_DEFP_SLOW 0x32 /* 5mb/s */ 235 #define SYNC_DEFP_FAST 0x19 /* 10mb/s */ 236 237 struct esp_cmd_priv { 238 union { 239 dma_addr_t dma_addr; 240 int num_sg; 241 } u; 242 243 int cur_residue; 244 struct scatterlist *cur_sg; 245 int tot_residue; 246 }; 247 #define ESP_CMD_PRIV(CMD) ((struct esp_cmd_priv *)(&(CMD)->SCp)) 248 249 enum esp_rev { 250 ESP100 = 0x00, /* NCR53C90 - very broken */ 251 ESP100A = 0x01, /* NCR53C90A */ 252 ESP236 = 0x02, 253 FAS236 = 0x03, 254 FAS100A = 0x04, 255 FAST = 0x05, 256 FASHME = 0x06, 257 }; 258 259 struct esp_cmd_entry { 260 struct list_head list; 261 262 struct scsi_cmnd *cmd; 263 264 unsigned int saved_cur_residue; 265 struct scatterlist *saved_cur_sg; 266 unsigned int saved_tot_residue; 267 268 u8 flags; 269 #define ESP_CMD_FLAG_WRITE 0x01 /* DMA is a write */ 270 #define ESP_CMD_FLAG_ABORT 0x02 /* being aborted */ 271 #define ESP_CMD_FLAG_AUTOSENSE 0x04 /* Doing automatic REQUEST_SENSE */ 272 273 u8 tag[2]; 274 275 u8 status; 276 u8 message; 277 278 unsigned char *sense_ptr; 279 unsigned char *saved_sense_ptr; 280 dma_addr_t sense_dma; 281 282 struct completion *eh_done; 283 }; 284 285 /* XXX make this configurable somehow XXX */ 286 #define ESP_DEFAULT_TAGS 16 287 288 #define ESP_MAX_TARGET 16 289 #define ESP_MAX_LUN 8 290 #define ESP_MAX_TAG 256 291 292 struct esp_lun_data { 293 struct esp_cmd_entry *non_tagged_cmd; 294 int num_tagged; 295 int hold; 296 struct esp_cmd_entry *tagged_cmds[ESP_MAX_TAG]; 297 }; 298 299 struct esp_target_data { 300 /* These are the ESP_STP, ESP_SOFF, and ESP_CFG3 register values which 301 * match the currently negotiated settings for this target. The SCSI 302 * protocol values are maintained in spi_{offset,period,wide}(starget). 303 */ 304 u8 esp_period; 305 u8 esp_offset; 306 u8 esp_config3; 307 308 u8 flags; 309 #define ESP_TGT_WIDE 0x01 310 #define ESP_TGT_DISCONNECT 0x02 311 #define ESP_TGT_NEGO_WIDE 0x04 312 #define ESP_TGT_NEGO_SYNC 0x08 313 #define ESP_TGT_CHECK_NEGO 0x40 314 #define ESP_TGT_BROKEN 0x80 315 316 /* When ESP_TGT_CHECK_NEGO is set, on the next scsi command to this 317 * device we will try to negotiate the following parameters. 318 */ 319 u8 nego_goal_period; 320 u8 nego_goal_offset; 321 u8 nego_goal_width; 322 u8 nego_goal_tags; 323 324 struct scsi_target *starget; 325 }; 326 327 struct esp_event_ent { 328 u8 type; 329 #define ESP_EVENT_TYPE_EVENT 0x01 330 #define ESP_EVENT_TYPE_CMD 0x02 331 u8 val; 332 333 u8 sreg; 334 u8 seqreg; 335 u8 sreg2; 336 u8 ireg; 337 u8 select_state; 338 u8 event; 339 u8 __pad; 340 }; 341 342 struct esp; 343 struct esp_driver_ops { 344 /* Read and write the ESP 8-bit registers. On some 345 * applications of the ESP chip the registers are at 4-byte 346 * instead of 1-byte intervals. 347 */ 348 void (*esp_write8)(struct esp *esp, u8 val, unsigned long reg); 349 u8 (*esp_read8)(struct esp *esp, unsigned long reg); 350 351 /* Map and unmap DMA memory. Eventually the driver will be 352 * converted to the generic DMA API as soon as SBUS is able to 353 * cope with that. At such time we can remove this. 354 */ 355 dma_addr_t (*map_single)(struct esp *esp, void *buf, 356 size_t sz, int dir); 357 int (*map_sg)(struct esp *esp, struct scatterlist *sg, 358 int num_sg, int dir); 359 void (*unmap_single)(struct esp *esp, dma_addr_t addr, 360 size_t sz, int dir); 361 void (*unmap_sg)(struct esp *esp, struct scatterlist *sg, 362 int num_sg, int dir); 363 364 /* Return non-zero if there is an IRQ pending. Usually this 365 * status bit lives in the DMA controller sitting in front of 366 * the ESP. This has to be accurate or else the ESP interrupt 367 * handler will not run. 368 */ 369 int (*irq_pending)(struct esp *esp); 370 371 /* Return the maximum allowable size of a DMA transfer for a 372 * given buffer. 373 */ 374 u32 (*dma_length_limit)(struct esp *esp, u32 dma_addr, 375 u32 dma_len); 376 377 /* Reset the DMA engine entirely. On return, ESP interrupts 378 * should be enabled. Often the interrupt enabling is 379 * controlled in the DMA engine. 380 */ 381 void (*reset_dma)(struct esp *esp); 382 383 /* Drain any pending DMA in the DMA engine after a transfer. 384 * This is for writes to memory. 385 */ 386 void (*dma_drain)(struct esp *esp); 387 388 /* Invalidate the DMA engine after a DMA transfer. */ 389 void (*dma_invalidate)(struct esp *esp); 390 391 /* Setup an ESP command that will use a DMA transfer. 392 * The 'esp_count' specifies what transfer length should be 393 * programmed into the ESP transfer counter registers, whereas 394 * the 'dma_count' is the length that should be programmed into 395 * the DMA controller. Usually they are the same. If 'write' 396 * is non-zero, this transfer is a write into memory. 'cmd' 397 * holds the ESP command that should be issued by calling 398 * scsi_esp_cmd() at the appropriate time while programming 399 * the DMA hardware. 400 */ 401 void (*send_dma_cmd)(struct esp *esp, u32 dma_addr, u32 esp_count, 402 u32 dma_count, int write, u8 cmd); 403 404 /* Return non-zero if the DMA engine is reporting an error 405 * currently. 406 */ 407 int (*dma_error)(struct esp *esp); 408 }; 409 410 #define ESP_MAX_MSG_SZ 8 411 #define ESP_EVENT_LOG_SZ 32 412 413 #define ESP_QUICKIRQ_LIMIT 100 414 #define ESP_RESELECT_TAG_LIMIT 2500 415 416 struct esp { 417 void __iomem *regs; 418 void __iomem *dma_regs; 419 420 const struct esp_driver_ops *ops; 421 422 struct Scsi_Host *host; 423 void *dev; 424 425 struct esp_cmd_entry *active_cmd; 426 427 struct list_head queued_cmds; 428 struct list_head active_cmds; 429 430 u8 *command_block; 431 dma_addr_t command_block_dma; 432 433 unsigned int data_dma_len; 434 435 /* The following are used to determine the cause of an IRQ. Upon every 436 * IRQ entry we synchronize these with the hardware registers. 437 */ 438 u8 sreg; 439 u8 seqreg; 440 u8 sreg2; 441 u8 ireg; 442 443 u32 prev_hme_dmacsr; 444 u8 prev_soff; 445 u8 prev_stp; 446 u8 prev_cfg3; 447 u8 __pad; 448 449 struct list_head esp_cmd_pool; 450 451 struct esp_target_data target[ESP_MAX_TARGET]; 452 453 int fifo_cnt; 454 u8 fifo[16]; 455 456 struct esp_event_ent esp_event_log[ESP_EVENT_LOG_SZ]; 457 int esp_event_cur; 458 459 u8 msg_out[ESP_MAX_MSG_SZ]; 460 int msg_out_len; 461 462 u8 msg_in[ESP_MAX_MSG_SZ]; 463 int msg_in_len; 464 465 u8 bursts; 466 u8 config1; 467 u8 config2; 468 469 u8 scsi_id; 470 u32 scsi_id_mask; 471 472 enum esp_rev rev; 473 474 u32 flags; 475 #define ESP_FLAG_DIFFERENTIAL 0x00000001 476 #define ESP_FLAG_RESETTING 0x00000002 477 #define ESP_FLAG_DOING_SLOWCMD 0x00000004 478 #define ESP_FLAG_WIDE_CAPABLE 0x00000008 479 #define ESP_FLAG_QUICKIRQ_CHECK 0x00000010 480 #define ESP_FLAG_DISABLE_SYNC 0x00000020 481 482 u8 select_state; 483 #define ESP_SELECT_NONE 0x00 /* Not selecting */ 484 #define ESP_SELECT_BASIC 0x01 /* Select w/o MSGOUT phase */ 485 #define ESP_SELECT_MSGOUT 0x02 /* Select with MSGOUT */ 486 487 /* When we are not selecting, we are expecting an event. */ 488 u8 event; 489 #define ESP_EVENT_NONE 0x00 490 #define ESP_EVENT_CMD_START 0x01 491 #define ESP_EVENT_CMD_DONE 0x02 492 #define ESP_EVENT_DATA_IN 0x03 493 #define ESP_EVENT_DATA_OUT 0x04 494 #define ESP_EVENT_DATA_DONE 0x05 495 #define ESP_EVENT_MSGIN 0x06 496 #define ESP_EVENT_MSGIN_MORE 0x07 497 #define ESP_EVENT_MSGIN_DONE 0x08 498 #define ESP_EVENT_MSGOUT 0x09 499 #define ESP_EVENT_MSGOUT_DONE 0x0a 500 #define ESP_EVENT_STATUS 0x0b 501 #define ESP_EVENT_FREE_BUS 0x0c 502 #define ESP_EVENT_CHECK_PHASE 0x0d 503 #define ESP_EVENT_RESET 0x10 504 505 /* Probed in esp_get_clock_params() */ 506 u32 cfact; 507 u32 cfreq; 508 u32 ccycle; 509 u32 ctick; 510 u32 neg_defp; 511 u32 sync_defp; 512 513 /* Computed in esp_reset_esp() */ 514 u32 max_period; 515 u32 min_period; 516 u32 radelay; 517 518 /* Slow command state. */ 519 u8 *cmd_bytes_ptr; 520 int cmd_bytes_left; 521 522 struct completion *eh_reset; 523 524 void *dma; 525 int dmarev; 526 }; 527 528 /* A front-end driver for the ESP chip should do the following in 529 * it's device probe routine: 530 * 1) Allocate the host and private area using scsi_host_alloc() 531 * with size 'sizeof(struct esp)'. The first argument to 532 * scsi_host_alloc() should be &scsi_esp_template. 533 * 2) Set host->max_id as appropriate. 534 * 3) Set esp->host to the scsi_host itself, and esp->dev 535 * to the device object pointer. 536 * 4) Hook up esp->ops to the front-end implementation. 537 * 5) If the ESP chip supports wide transfers, set ESP_FLAG_WIDE_CAPABLE 538 * in esp->flags. 539 * 6) Map the DMA and ESP chip registers. 540 * 7) DMA map the ESP command block, store the DMA address 541 * in esp->command_block_dma. 542 * 8) Register the scsi_esp_intr() interrupt handler. 543 * 9) Probe for and provide the following chip properties: 544 * esp->scsi_id (assign to esp->host->this_id too) 545 * esp->scsi_id_mask 546 * If ESP bus is differential, set ESP_FLAG_DIFFERENTIAL 547 * esp->cfreq 548 * DMA burst bit mask in esp->bursts, if necessary 549 * 10) Perform any actions necessary before the ESP device can 550 * be programmed for the first time. On some configs, for 551 * example, the DMA engine has to be reset before ESP can 552 * be programmed. 553 * 11) If necessary, call dev_set_drvdata() as needed. 554 * 12) Call scsi_esp_register() with prepared 'esp' structure 555 * and a device pointer if possible. 556 * 13) Check scsi_esp_register() return value, release all resources 557 * if an error was returned. 558 */ 559 extern struct scsi_host_template scsi_esp_template; 560 extern int scsi_esp_register(struct esp *, struct device *); 561 562 extern void scsi_esp_unregister(struct esp *); 563 extern irqreturn_t scsi_esp_intr(int, void *); 564 extern void scsi_esp_cmd(struct esp *, u8); 565 566 #endif /* !(_ESP_SCSI_H) */ 567