1*4df84e84SJames Smart /* SPDX-License-Identifier: GPL-2.0 */ 2*4df84e84SJames Smart /* 3*4df84e84SJames Smart * Copyright (C) 2021 Broadcom. All Rights Reserved. The term 4*4df84e84SJames Smart * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. 5*4df84e84SJames Smart */ 6*4df84e84SJames Smart 7*4df84e84SJames Smart #if !defined(__EFCT_DRIVER_H__) 8*4df84e84SJames Smart #define __EFCT_DRIVER_H__ 9*4df84e84SJames Smart 10*4df84e84SJames Smart /*************************************************************************** 11*4df84e84SJames Smart * OS specific includes 12*4df84e84SJames Smart */ 13*4df84e84SJames Smart #include <stdarg.h> 14*4df84e84SJames Smart #include <linux/module.h> 15*4df84e84SJames Smart #include <linux/debugfs.h> 16*4df84e84SJames Smart #include <linux/firmware.h> 17*4df84e84SJames Smart #include "../include/efc_common.h" 18*4df84e84SJames Smart #include "../libefc/efclib.h" 19*4df84e84SJames Smart #include "efct_hw.h" 20*4df84e84SJames Smart #include "efct_io.h" 21*4df84e84SJames Smart #include "efct_xport.h" 22*4df84e84SJames Smart 23*4df84e84SJames Smart #define EFCT_DRIVER_NAME "efct" 24*4df84e84SJames Smart #define EFCT_DRIVER_VERSION "1.0.0.0" 25*4df84e84SJames Smart 26*4df84e84SJames Smart /* EFCT_DEFAULT_FILTER- 27*4df84e84SJames Smart * MRQ filter to segregate the IO flow. 28*4df84e84SJames Smart */ 29*4df84e84SJames Smart #define EFCT_DEFAULT_FILTER "0x01ff22ff,0,0,0" 30*4df84e84SJames Smart 31*4df84e84SJames Smart /* EFCT_OS_MAX_ISR_TIME_MSEC - 32*4df84e84SJames Smart * maximum time driver code should spend in an interrupt 33*4df84e84SJames Smart * or kernel thread context without yielding 34*4df84e84SJames Smart */ 35*4df84e84SJames Smart #define EFCT_OS_MAX_ISR_TIME_MSEC 1000 36*4df84e84SJames Smart 37*4df84e84SJames Smart #define EFCT_FC_MAX_SGL 64 38*4df84e84SJames Smart #define EFCT_FC_DIF_SEED 0 39*4df84e84SJames Smart 40*4df84e84SJames Smart /* Watermark */ 41*4df84e84SJames Smart #define EFCT_WATERMARK_HIGH_PCT 90 42*4df84e84SJames Smart #define EFCT_WATERMARK_LOW_PCT 80 43*4df84e84SJames Smart #define EFCT_IO_WATERMARK_PER_INITIATOR 8 44*4df84e84SJames Smart 45*4df84e84SJames Smart #define EFCT_PCI_MAX_REGS 6 46*4df84e84SJames Smart #define MAX_PCI_INTERRUPTS 16 47*4df84e84SJames Smart 48*4df84e84SJames Smart struct efct_intr_context { 49*4df84e84SJames Smart struct efct *efct; 50*4df84e84SJames Smart u32 index; 51*4df84e84SJames Smart }; 52*4df84e84SJames Smart 53*4df84e84SJames Smart struct efct { 54*4df84e84SJames Smart struct pci_dev *pci; 55*4df84e84SJames Smart void __iomem *reg[EFCT_PCI_MAX_REGS]; 56*4df84e84SJames Smart 57*4df84e84SJames Smart u32 n_msix_vec; 58*4df84e84SJames Smart bool attached; 59*4df84e84SJames Smart bool soft_wwn_enable; 60*4df84e84SJames Smart u8 efct_req_fw_upgrade; 61*4df84e84SJames Smart struct efct_intr_context intr_context[MAX_PCI_INTERRUPTS]; 62*4df84e84SJames Smart u32 numa_node; 63*4df84e84SJames Smart 64*4df84e84SJames Smart char name[EFC_NAME_LENGTH]; 65*4df84e84SJames Smart u32 instance_index; 66*4df84e84SJames Smart struct list_head list_entry; 67*4df84e84SJames Smart struct efct_scsi_tgt tgt_efct; 68*4df84e84SJames Smart struct efct_xport *xport; 69*4df84e84SJames Smart struct efc *efcport; 70*4df84e84SJames Smart struct Scsi_Host *shost; 71*4df84e84SJames Smart int logmask; 72*4df84e84SJames Smart u32 max_isr_time_msec; 73*4df84e84SJames Smart 74*4df84e84SJames Smart const char *desc; 75*4df84e84SJames Smart 76*4df84e84SJames Smart const char *model; 77*4df84e84SJames Smart 78*4df84e84SJames Smart struct efct_hw hw; 79*4df84e84SJames Smart 80*4df84e84SJames Smart u32 rq_selection_policy; 81*4df84e84SJames Smart char *filter_def; 82*4df84e84SJames Smart int topology; 83*4df84e84SJames Smart 84*4df84e84SJames Smart /* Look up for target node */ 85*4df84e84SJames Smart struct xarray lookup; 86*4df84e84SJames Smart 87*4df84e84SJames Smart /* 88*4df84e84SJames Smart * Target IO timer value: 89*4df84e84SJames Smart * Zero: target command timeout disabled. 90*4df84e84SJames Smart * Non-zero: Timeout value, in seconds, for target commands 91*4df84e84SJames Smart */ 92*4df84e84SJames Smart u32 target_io_timer_sec; 93*4df84e84SJames Smart 94*4df84e84SJames Smart int speed; 95*4df84e84SJames Smart struct dentry *sess_debugfs_dir; 96*4df84e84SJames Smart }; 97*4df84e84SJames Smart 98*4df84e84SJames Smart #define FW_WRITE_BUFSIZE (64 * 1024) 99*4df84e84SJames Smart 100*4df84e84SJames Smart struct efct_fw_write_result { 101*4df84e84SJames Smart struct completion done; 102*4df84e84SJames Smart int status; 103*4df84e84SJames Smart u32 actual_xfer; 104*4df84e84SJames Smart u32 change_status; 105*4df84e84SJames Smart }; 106*4df84e84SJames Smart 107*4df84e84SJames Smart extern struct list_head efct_devices; 108*4df84e84SJames Smart 109*4df84e84SJames Smart #endif /* __EFCT_DRIVER_H__ */ 110