1 /* 2 * CXL Flash Device Driver 3 * 4 * Written by: Manoj N. Kumar <manoj@linux.vnet.ibm.com>, IBM Corporation 5 * Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation 6 * 7 * Copyright (C) 2015 IBM Corporation 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 */ 14 15 #ifndef _CXLFLASH_COMMON_H 16 #define _CXLFLASH_COMMON_H 17 18 #include <linux/async.h> 19 #include <linux/cdev.h> 20 #include <linux/irq_poll.h> 21 #include <linux/list.h> 22 #include <linux/rwsem.h> 23 #include <linux/types.h> 24 #include <scsi/scsi.h> 25 #include <scsi/scsi_cmnd.h> 26 #include <scsi/scsi_device.h> 27 28 extern const struct file_operations cxlflash_cxl_fops; 29 30 #define MAX_CONTEXT CXLFLASH_MAX_CONTEXT /* num contexts per afu */ 31 #define MAX_FC_PORTS CXLFLASH_MAX_FC_PORTS /* max ports per AFU */ 32 #define LEGACY_FC_PORTS 2 /* legacy ports per AFU */ 33 34 #define CHAN2PORTBANK(_x) ((_x) >> ilog2(CXLFLASH_NUM_FC_PORTS_PER_BANK)) 35 #define CHAN2BANKPORT(_x) ((_x) & (CXLFLASH_NUM_FC_PORTS_PER_BANK - 1)) 36 37 #define CHAN2PORTMASK(_x) (1 << (_x)) /* channel to port mask */ 38 #define PORTMASK2CHAN(_x) (ilog2((_x))) /* port mask to channel */ 39 #define PORTNUM2CHAN(_x) ((_x) - 1) /* port number to channel */ 40 41 #define CXLFLASH_BLOCK_SIZE 4096 /* 4K blocks */ 42 #define CXLFLASH_MAX_XFER_SIZE 16777216 /* 16MB transfer */ 43 #define CXLFLASH_MAX_SECTORS (CXLFLASH_MAX_XFER_SIZE/512) /* SCSI wants 44 * max_sectors 45 * in units of 46 * 512 byte 47 * sectors 48 */ 49 50 #define MAX_RHT_PER_CONTEXT (PAGE_SIZE / sizeof(struct sisl_rht_entry)) 51 52 /* AFU command retry limit */ 53 #define MC_RETRY_CNT 5 /* Sufficient for SCSI and certain AFU errors */ 54 55 /* Command management definitions */ 56 #define CXLFLASH_MAX_CMDS 256 57 #define CXLFLASH_MAX_CMDS_PER_LUN CXLFLASH_MAX_CMDS 58 59 /* RRQ for master issued cmds */ 60 #define NUM_RRQ_ENTRY CXLFLASH_MAX_CMDS 61 62 /* SQ for master issued cmds */ 63 #define NUM_SQ_ENTRY CXLFLASH_MAX_CMDS 64 65 /* Hardware queue definitions */ 66 #define CXLFLASH_DEF_HWQS 1 67 #define CXLFLASH_MAX_HWQS 8 68 #define PRIMARY_HWQ 0 69 70 71 static inline void check_sizes(void) 72 { 73 BUILD_BUG_ON_NOT_POWER_OF_2(CXLFLASH_NUM_FC_PORTS_PER_BANK); 74 BUILD_BUG_ON_NOT_POWER_OF_2(CXLFLASH_MAX_CMDS); 75 } 76 77 /* AFU defines a fixed size of 4K for command buffers (borrow 4K page define) */ 78 #define CMD_BUFSIZE SIZE_4K 79 80 enum cxlflash_lr_state { 81 LINK_RESET_INVALID, 82 LINK_RESET_REQUIRED, 83 LINK_RESET_COMPLETE 84 }; 85 86 enum cxlflash_init_state { 87 INIT_STATE_NONE, 88 INIT_STATE_PCI, 89 INIT_STATE_AFU, 90 INIT_STATE_SCSI, 91 INIT_STATE_CDEV 92 }; 93 94 enum cxlflash_state { 95 STATE_PROBING, /* Initial state during probe */ 96 STATE_PROBED, /* Temporary state, probe completed but EEH occurred */ 97 STATE_NORMAL, /* Normal running state, everything good */ 98 STATE_RESET, /* Reset state, trying to reset/recover */ 99 STATE_FAILTERM /* Failed/terminating state, error out users/threads */ 100 }; 101 102 enum cxlflash_hwq_mode { 103 HWQ_MODE_RR, /* Roundrobin (default) */ 104 HWQ_MODE_TAG, /* Distribute based on block MQ tag */ 105 HWQ_MODE_CPU, /* CPU affinity */ 106 MAX_HWQ_MODE 107 }; 108 109 /* 110 * Each context has its own set of resource handles that is visible 111 * only from that context. 112 */ 113 114 struct cxlflash_cfg { 115 struct afu *afu; 116 117 struct pci_dev *dev; 118 struct pci_device_id *dev_id; 119 struct Scsi_Host *host; 120 int num_fc_ports; 121 struct cdev cdev; 122 struct device *chardev; 123 124 ulong cxlflash_regs_pci; 125 126 struct work_struct work_q; 127 enum cxlflash_init_state init_state; 128 enum cxlflash_lr_state lr_state; 129 int lr_port; 130 atomic_t scan_host_needed; 131 132 struct cxl_afu *cxl_afu; 133 134 atomic_t recovery_threads; 135 struct mutex ctx_recovery_mutex; 136 struct mutex ctx_tbl_list_mutex; 137 struct rw_semaphore ioctl_rwsem; 138 struct ctx_info *ctx_tbl[MAX_CONTEXT]; 139 struct list_head ctx_err_recovery; /* contexts w/ recovery pending */ 140 struct file_operations cxl_fops; 141 142 /* Parameters that are LUN table related */ 143 int last_lun_index[MAX_FC_PORTS]; 144 int promote_lun_index; 145 struct list_head lluns; /* list of llun_info structs */ 146 147 wait_queue_head_t tmf_waitq; 148 spinlock_t tmf_slock; 149 bool tmf_active; 150 bool ws_unmap; /* Write-same unmap supported */ 151 wait_queue_head_t reset_waitq; 152 enum cxlflash_state state; 153 async_cookie_t async_reset_cookie; 154 }; 155 156 struct afu_cmd { 157 struct sisl_ioarcb rcb; /* IOARCB (cache line aligned) */ 158 struct sisl_ioasa sa; /* IOASA must follow IOARCB */ 159 struct afu *parent; 160 struct scsi_cmnd *scp; 161 struct completion cevent; 162 struct list_head queue; 163 u32 hwq_index; 164 165 u8 cmd_tmf:1, 166 cmd_aborted:1; 167 168 struct list_head list; /* Pending commands link */ 169 170 /* As per the SISLITE spec the IOARCB EA has to be 16-byte aligned. 171 * However for performance reasons the IOARCB/IOASA should be 172 * cache line aligned. 173 */ 174 } __aligned(cache_line_size()); 175 176 static inline struct afu_cmd *sc_to_afuc(struct scsi_cmnd *sc) 177 { 178 return PTR_ALIGN(scsi_cmd_priv(sc), __alignof__(struct afu_cmd)); 179 } 180 181 static inline struct afu_cmd *sc_to_afuci(struct scsi_cmnd *sc) 182 { 183 struct afu_cmd *afuc = sc_to_afuc(sc); 184 185 INIT_LIST_HEAD(&afuc->queue); 186 return afuc; 187 } 188 189 static inline struct afu_cmd *sc_to_afucz(struct scsi_cmnd *sc) 190 { 191 struct afu_cmd *afuc = sc_to_afuc(sc); 192 193 memset(afuc, 0, sizeof(*afuc)); 194 return sc_to_afuci(sc); 195 } 196 197 struct hwq { 198 /* Stuff requiring alignment go first. */ 199 struct sisl_ioarcb sq[NUM_SQ_ENTRY]; /* 16K SQ */ 200 u64 rrq_entry[NUM_RRQ_ENTRY]; /* 2K RRQ */ 201 202 /* Beware of alignment till here. Preferably introduce new 203 * fields after this point 204 */ 205 struct afu *afu; 206 struct cxl_context *ctx; 207 struct cxl_ioctl_start_work work; 208 struct sisl_host_map __iomem *host_map; /* MC host map */ 209 struct sisl_ctrl_map __iomem *ctrl_map; /* MC control map */ 210 ctx_hndl_t ctx_hndl; /* master's context handle */ 211 u32 index; /* Index of this hwq */ 212 struct list_head pending_cmds; /* Commands pending completion */ 213 214 atomic_t hsq_credits; 215 spinlock_t hsq_slock; /* Hardware send queue lock */ 216 struct sisl_ioarcb *hsq_start; 217 struct sisl_ioarcb *hsq_end; 218 struct sisl_ioarcb *hsq_curr; 219 spinlock_t hrrq_slock; 220 u64 *hrrq_start; 221 u64 *hrrq_end; 222 u64 *hrrq_curr; 223 bool toggle; 224 225 s64 room; 226 227 struct irq_poll irqpoll; 228 } __aligned(cache_line_size()); 229 230 struct afu { 231 struct hwq hwqs[CXLFLASH_MAX_HWQS]; 232 int (*send_cmd)(struct afu *, struct afu_cmd *); 233 int (*context_reset)(struct hwq *); 234 235 /* AFU HW */ 236 struct cxlflash_afu_map __iomem *afu_map; /* entire MMIO map */ 237 238 atomic_t cmds_active; /* Number of currently active AFU commands */ 239 u64 hb; 240 u32 internal_lun; /* User-desired LUN mode for this AFU */ 241 242 u32 num_hwqs; /* Number of hardware queues */ 243 u32 desired_hwqs; /* Desired h/w queues, effective on AFU reset */ 244 enum cxlflash_hwq_mode hwq_mode; /* Steering mode for h/w queues */ 245 u32 hwq_rr_count; /* Count to distribute traffic for roundrobin */ 246 247 char version[16]; 248 u64 interface_version; 249 250 u32 irqpoll_weight; 251 struct cxlflash_cfg *parent; /* Pointer back to parent cxlflash_cfg */ 252 }; 253 254 static inline struct hwq *get_hwq(struct afu *afu, u32 index) 255 { 256 WARN_ON(index >= CXLFLASH_MAX_HWQS); 257 258 return &afu->hwqs[index]; 259 } 260 261 static inline bool afu_is_irqpoll_enabled(struct afu *afu) 262 { 263 return !!afu->irqpoll_weight; 264 } 265 266 static inline bool afu_has_cap(struct afu *afu, u64 cap) 267 { 268 u64 afu_cap = afu->interface_version >> SISL_INTVER_CAP_SHIFT; 269 270 return afu_cap & cap; 271 } 272 273 static inline bool afu_is_afu_debug(struct afu *afu) 274 { 275 return afu_has_cap(afu, SISL_INTVER_CAP_AFU_DEBUG); 276 } 277 278 static inline bool afu_is_lun_provision(struct afu *afu) 279 { 280 return afu_has_cap(afu, SISL_INTVER_CAP_LUN_PROVISION); 281 } 282 283 static inline bool afu_is_sq_cmd_mode(struct afu *afu) 284 { 285 return afu_has_cap(afu, SISL_INTVER_CAP_SQ_CMD_MODE); 286 } 287 288 static inline bool afu_is_ioarrin_cmd_mode(struct afu *afu) 289 { 290 return afu_has_cap(afu, SISL_INTVER_CAP_IOARRIN_CMD_MODE); 291 } 292 293 static inline u64 lun_to_lunid(u64 lun) 294 { 295 __be64 lun_id; 296 297 int_to_scsilun(lun, (struct scsi_lun *)&lun_id); 298 return be64_to_cpu(lun_id); 299 } 300 301 static inline struct fc_port_bank __iomem *get_fc_port_bank( 302 struct cxlflash_cfg *cfg, int i) 303 { 304 struct afu *afu = cfg->afu; 305 306 return &afu->afu_map->global.bank[CHAN2PORTBANK(i)]; 307 } 308 309 static inline __be64 __iomem *get_fc_port_regs(struct cxlflash_cfg *cfg, int i) 310 { 311 struct fc_port_bank __iomem *fcpb = get_fc_port_bank(cfg, i); 312 313 return &fcpb->fc_port_regs[CHAN2BANKPORT(i)][0]; 314 } 315 316 static inline __be64 __iomem *get_fc_port_luns(struct cxlflash_cfg *cfg, int i) 317 { 318 struct fc_port_bank __iomem *fcpb = get_fc_port_bank(cfg, i); 319 320 return &fcpb->fc_port_luns[CHAN2BANKPORT(i)][0]; 321 } 322 323 int cxlflash_afu_sync(struct afu *afu, ctx_hndl_t c, res_hndl_t r, u8 mode); 324 void cxlflash_list_init(void); 325 void cxlflash_term_global_luns(void); 326 void cxlflash_free_errpage(void); 327 int cxlflash_ioctl(struct scsi_device *sdev, int cmd, void __user *arg); 328 void cxlflash_stop_term_user_contexts(struct cxlflash_cfg *cfg); 329 int cxlflash_mark_contexts_error(struct cxlflash_cfg *cfg); 330 void cxlflash_term_local_luns(struct cxlflash_cfg *cfg); 331 void cxlflash_restore_luntable(struct cxlflash_cfg *cfg); 332 333 #endif /* ifndef _CXLFLASH_COMMON_H */ 334