1 /* 2 * CXL Flash Device Driver 3 * 4 * Written by: Manoj N. Kumar <manoj@linux.vnet.ibm.com>, IBM Corporation 5 * Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation 6 * 7 * Copyright (C) 2015 IBM Corporation 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License 11 * as published by the Free Software Foundation; either version 12 * 2 of the License, or (at your option) any later version. 13 */ 14 15 #ifndef _CXLFLASH_COMMON_H 16 #define _CXLFLASH_COMMON_H 17 18 #include <linux/irq_poll.h> 19 #include <linux/list.h> 20 #include <linux/rwsem.h> 21 #include <linux/types.h> 22 #include <scsi/scsi.h> 23 #include <scsi/scsi_cmnd.h> 24 #include <scsi/scsi_device.h> 25 26 extern const struct file_operations cxlflash_cxl_fops; 27 28 #define MAX_CONTEXT CXLFLASH_MAX_CONTEXT /* num contexts per afu */ 29 #define MAX_FC_PORTS CXLFLASH_MAX_FC_PORTS /* max ports per AFU */ 30 #define LEGACY_FC_PORTS 2 /* legacy ports per AFU */ 31 32 #define CHAN2PORTBANK(_x) ((_x) >> ilog2(CXLFLASH_NUM_FC_PORTS_PER_BANK)) 33 #define CHAN2BANKPORT(_x) ((_x) & (CXLFLASH_NUM_FC_PORTS_PER_BANK - 1)) 34 35 #define CHAN2PORTMASK(_x) (1 << (_x)) /* channel to port mask */ 36 #define PORTMASK2CHAN(_x) (ilog2((_x))) /* port mask to channel */ 37 #define PORTNUM2CHAN(_x) ((_x) - 1) /* port number to channel */ 38 39 #define CXLFLASH_BLOCK_SIZE 4096 /* 4K blocks */ 40 #define CXLFLASH_MAX_XFER_SIZE 16777216 /* 16MB transfer */ 41 #define CXLFLASH_MAX_SECTORS (CXLFLASH_MAX_XFER_SIZE/512) /* SCSI wants 42 * max_sectors 43 * in units of 44 * 512 byte 45 * sectors 46 */ 47 48 #define MAX_RHT_PER_CONTEXT (PAGE_SIZE / sizeof(struct sisl_rht_entry)) 49 50 /* AFU command retry limit */ 51 #define MC_RETRY_CNT 5 /* Sufficient for SCSI and certain AFU errors */ 52 53 /* Command management definitions */ 54 #define CXLFLASH_MAX_CMDS 256 55 #define CXLFLASH_MAX_CMDS_PER_LUN CXLFLASH_MAX_CMDS 56 57 /* RRQ for master issued cmds */ 58 #define NUM_RRQ_ENTRY CXLFLASH_MAX_CMDS 59 60 /* SQ for master issued cmds */ 61 #define NUM_SQ_ENTRY CXLFLASH_MAX_CMDS 62 63 /* Hardware queue definitions */ 64 #define CXLFLASH_DEF_HWQS 1 65 #define CXLFLASH_MAX_HWQS 8 66 #define PRIMARY_HWQ 0 67 68 69 static inline void check_sizes(void) 70 { 71 BUILD_BUG_ON_NOT_POWER_OF_2(CXLFLASH_NUM_FC_PORTS_PER_BANK); 72 BUILD_BUG_ON_NOT_POWER_OF_2(CXLFLASH_MAX_CMDS); 73 } 74 75 /* AFU defines a fixed size of 4K for command buffers (borrow 4K page define) */ 76 #define CMD_BUFSIZE SIZE_4K 77 78 enum cxlflash_lr_state { 79 LINK_RESET_INVALID, 80 LINK_RESET_REQUIRED, 81 LINK_RESET_COMPLETE 82 }; 83 84 enum cxlflash_init_state { 85 INIT_STATE_NONE, 86 INIT_STATE_PCI, 87 INIT_STATE_AFU, 88 INIT_STATE_SCSI 89 }; 90 91 enum cxlflash_state { 92 STATE_PROBING, /* Initial state during probe */ 93 STATE_PROBED, /* Temporary state, probe completed but EEH occurred */ 94 STATE_NORMAL, /* Normal running state, everything good */ 95 STATE_RESET, /* Reset state, trying to reset/recover */ 96 STATE_FAILTERM /* Failed/terminating state, error out users/threads */ 97 }; 98 99 enum cxlflash_hwq_mode { 100 HWQ_MODE_RR, /* Roundrobin (default) */ 101 HWQ_MODE_TAG, /* Distribute based on block MQ tag */ 102 HWQ_MODE_CPU, /* CPU affinity */ 103 MAX_HWQ_MODE 104 }; 105 106 /* 107 * Each context has its own set of resource handles that is visible 108 * only from that context. 109 */ 110 111 struct cxlflash_cfg { 112 struct afu *afu; 113 114 struct pci_dev *dev; 115 struct pci_device_id *dev_id; 116 struct Scsi_Host *host; 117 int num_fc_ports; 118 119 ulong cxlflash_regs_pci; 120 121 struct work_struct work_q; 122 enum cxlflash_init_state init_state; 123 enum cxlflash_lr_state lr_state; 124 int lr_port; 125 atomic_t scan_host_needed; 126 127 struct cxl_afu *cxl_afu; 128 129 atomic_t recovery_threads; 130 struct mutex ctx_recovery_mutex; 131 struct mutex ctx_tbl_list_mutex; 132 struct rw_semaphore ioctl_rwsem; 133 struct ctx_info *ctx_tbl[MAX_CONTEXT]; 134 struct list_head ctx_err_recovery; /* contexts w/ recovery pending */ 135 struct file_operations cxl_fops; 136 137 /* Parameters that are LUN table related */ 138 int last_lun_index[MAX_FC_PORTS]; 139 int promote_lun_index; 140 struct list_head lluns; /* list of llun_info structs */ 141 142 wait_queue_head_t tmf_waitq; 143 spinlock_t tmf_slock; 144 bool tmf_active; 145 wait_queue_head_t reset_waitq; 146 enum cxlflash_state state; 147 }; 148 149 struct afu_cmd { 150 struct sisl_ioarcb rcb; /* IOARCB (cache line aligned) */ 151 struct sisl_ioasa sa; /* IOASA must follow IOARCB */ 152 struct afu *parent; 153 struct scsi_cmnd *scp; 154 struct completion cevent; 155 struct list_head queue; 156 u32 hwq_index; 157 158 u8 cmd_tmf:1; 159 160 /* As per the SISLITE spec the IOARCB EA has to be 16-byte aligned. 161 * However for performance reasons the IOARCB/IOASA should be 162 * cache line aligned. 163 */ 164 } __aligned(cache_line_size()); 165 166 static inline struct afu_cmd *sc_to_afuc(struct scsi_cmnd *sc) 167 { 168 return PTR_ALIGN(scsi_cmd_priv(sc), __alignof__(struct afu_cmd)); 169 } 170 171 static inline struct afu_cmd *sc_to_afucz(struct scsi_cmnd *sc) 172 { 173 struct afu_cmd *afuc = sc_to_afuc(sc); 174 175 memset(afuc, 0, sizeof(*afuc)); 176 return afuc; 177 } 178 179 struct hwq { 180 /* Stuff requiring alignment go first. */ 181 struct sisl_ioarcb sq[NUM_SQ_ENTRY]; /* 16K SQ */ 182 u64 rrq_entry[NUM_RRQ_ENTRY]; /* 2K RRQ */ 183 184 /* Beware of alignment till here. Preferably introduce new 185 * fields after this point 186 */ 187 struct afu *afu; 188 struct cxl_context *ctx; 189 struct cxl_ioctl_start_work work; 190 struct sisl_host_map __iomem *host_map; /* MC host map */ 191 struct sisl_ctrl_map __iomem *ctrl_map; /* MC control map */ 192 ctx_hndl_t ctx_hndl; /* master's context handle */ 193 u32 index; /* Index of this hwq */ 194 195 atomic_t hsq_credits; 196 spinlock_t hsq_slock; 197 struct sisl_ioarcb *hsq_start; 198 struct sisl_ioarcb *hsq_end; 199 struct sisl_ioarcb *hsq_curr; 200 spinlock_t hrrq_slock; 201 u64 *hrrq_start; 202 u64 *hrrq_end; 203 u64 *hrrq_curr; 204 bool toggle; 205 206 s64 room; 207 spinlock_t rrin_slock; /* Lock to rrin queuing and cmd_room updates */ 208 209 struct irq_poll irqpoll; 210 } __aligned(cache_line_size()); 211 212 struct afu { 213 struct hwq hwqs[CXLFLASH_MAX_HWQS]; 214 int (*send_cmd)(struct afu *, struct afu_cmd *); 215 void (*context_reset)(struct afu_cmd *); 216 217 /* AFU HW */ 218 struct cxlflash_afu_map __iomem *afu_map; /* entire MMIO map */ 219 220 atomic_t cmds_active; /* Number of currently active AFU commands */ 221 u64 hb; 222 u32 internal_lun; /* User-desired LUN mode for this AFU */ 223 224 u32 num_hwqs; /* Number of hardware queues */ 225 u32 desired_hwqs; /* Desired h/w queues, effective on AFU reset */ 226 enum cxlflash_hwq_mode hwq_mode; /* Steering mode for h/w queues */ 227 u32 hwq_rr_count; /* Count to distribute traffic for roundrobin */ 228 229 char version[16]; 230 u64 interface_version; 231 232 u32 irqpoll_weight; 233 struct cxlflash_cfg *parent; /* Pointer back to parent cxlflash_cfg */ 234 }; 235 236 static inline struct hwq *get_hwq(struct afu *afu, u32 index) 237 { 238 WARN_ON(index >= CXLFLASH_MAX_HWQS); 239 240 return &afu->hwqs[index]; 241 } 242 243 static inline bool afu_is_irqpoll_enabled(struct afu *afu) 244 { 245 return !!afu->irqpoll_weight; 246 } 247 248 static inline bool afu_is_cmd_mode(struct afu *afu, u64 cmd_mode) 249 { 250 u64 afu_cap = afu->interface_version >> SISL_INTVER_CAP_SHIFT; 251 252 return afu_cap & cmd_mode; 253 } 254 255 static inline bool afu_is_sq_cmd_mode(struct afu *afu) 256 { 257 return afu_is_cmd_mode(afu, SISL_INTVER_CAP_SQ_CMD_MODE); 258 } 259 260 static inline bool afu_is_ioarrin_cmd_mode(struct afu *afu) 261 { 262 return afu_is_cmd_mode(afu, SISL_INTVER_CAP_IOARRIN_CMD_MODE); 263 } 264 265 static inline u64 lun_to_lunid(u64 lun) 266 { 267 __be64 lun_id; 268 269 int_to_scsilun(lun, (struct scsi_lun *)&lun_id); 270 return be64_to_cpu(lun_id); 271 } 272 273 static inline struct fc_port_bank __iomem *get_fc_port_bank( 274 struct cxlflash_cfg *cfg, int i) 275 { 276 struct afu *afu = cfg->afu; 277 278 return &afu->afu_map->global.bank[CHAN2PORTBANK(i)]; 279 } 280 281 static inline __be64 __iomem *get_fc_port_regs(struct cxlflash_cfg *cfg, int i) 282 { 283 struct fc_port_bank __iomem *fcpb = get_fc_port_bank(cfg, i); 284 285 return &fcpb->fc_port_regs[CHAN2BANKPORT(i)][0]; 286 } 287 288 static inline __be64 __iomem *get_fc_port_luns(struct cxlflash_cfg *cfg, int i) 289 { 290 struct fc_port_bank __iomem *fcpb = get_fc_port_bank(cfg, i); 291 292 return &fcpb->fc_port_luns[CHAN2BANKPORT(i)][0]; 293 } 294 295 int cxlflash_afu_sync(struct afu *afu, ctx_hndl_t c, res_hndl_t r, u8 mode); 296 void cxlflash_list_init(void); 297 void cxlflash_term_global_luns(void); 298 void cxlflash_free_errpage(void); 299 int cxlflash_ioctl(struct scsi_device *sdev, int cmd, void __user *arg); 300 void cxlflash_stop_term_user_contexts(struct cxlflash_cfg *cfg); 301 int cxlflash_mark_contexts_error(struct cxlflash_cfg *cfg); 302 void cxlflash_term_local_luns(struct cxlflash_cfg *cfg); 303 void cxlflash_restore_luntable(struct cxlflash_cfg *cfg); 304 305 #endif /* ifndef _CXLFLASH_COMMON_H */ 306