1 /* 2 * This file is part of the Chelsio FCoE driver for Linux. 3 * 4 * Copyright (c) 2008-2013 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include "csio_hw.h" 35 #include "csio_init.h" 36 37 static int 38 csio_t5_set_mem_win(struct csio_hw *hw, uint32_t win) 39 { 40 u32 mem_win_base; 41 /* 42 * Truncation intentional: we only read the bottom 32-bits of the 43 * 64-bit BAR0/BAR1 ... We use the hardware backdoor mechanism to 44 * read BAR0 instead of using pci_resource_start() because we could be 45 * operating from within a Virtual Machine which is trapping our 46 * accesses to our Configuration Space and we need to set up the PCI-E 47 * Memory Window decoders with the actual addresses which will be 48 * coming across the PCI-E link. 49 */ 50 51 /* For T5, only relative offset inside the PCIe BAR is passed */ 52 mem_win_base = MEMWIN_BASE; 53 54 /* 55 * Set up memory window for accessing adapter memory ranges. (Read 56 * back MA register to ensure that changes propagate before we attempt 57 * to use the new values.) 58 */ 59 csio_wr_reg32(hw, mem_win_base | BIR_V(0) | 60 WINDOW_V(ilog2(MEMWIN_APERTURE) - 10), 61 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win)); 62 csio_rd_reg32(hw, 63 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win)); 64 65 return 0; 66 } 67 68 /* 69 * Interrupt handler for the PCIE module. 70 */ 71 static void 72 csio_t5_pcie_intr_handler(struct csio_hw *hw) 73 { 74 static struct intr_info sysbus_intr_info[] = { 75 { RNPP_F, "RXNP array parity error", -1, 1 }, 76 { RPCP_F, "RXPC array parity error", -1, 1 }, 77 { RCIP_F, "RXCIF array parity error", -1, 1 }, 78 { RCCP_F, "Rx completions control array parity error", -1, 1 }, 79 { RFTP_F, "RXFT array parity error", -1, 1 }, 80 { 0, NULL, 0, 0 } 81 }; 82 static struct intr_info pcie_port_intr_info[] = { 83 { TPCP_F, "TXPC array parity error", -1, 1 }, 84 { TNPP_F, "TXNP array parity error", -1, 1 }, 85 { TFTP_F, "TXFT array parity error", -1, 1 }, 86 { TCAP_F, "TXCA array parity error", -1, 1 }, 87 { TCIP_F, "TXCIF array parity error", -1, 1 }, 88 { RCAP_F, "RXCA array parity error", -1, 1 }, 89 { OTDD_F, "outbound request TLP discarded", -1, 1 }, 90 { RDPE_F, "Rx data parity error", -1, 1 }, 91 { TDUE_F, "Tx uncorrectable data error", -1, 1 }, 92 { 0, NULL, 0, 0 } 93 }; 94 95 static struct intr_info pcie_intr_info[] = { 96 { MSTGRPPERR_F, "Master Response Read Queue parity error", 97 -1, 1 }, 98 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 }, 99 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 }, 100 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 }, 101 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 }, 102 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 }, 103 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 }, 104 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error", 105 -1, 1 }, 106 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error", 107 -1, 1 }, 108 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 }, 109 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 }, 110 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 }, 111 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 }, 112 { DREQWRPERR_F, "PCI DMA channel write request parity error", 113 -1, 1 }, 114 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 }, 115 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 }, 116 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 }, 117 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 }, 118 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 }, 119 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 }, 120 { FIDPERR_F, "PCI FID parity error", -1, 1 }, 121 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 }, 122 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 }, 123 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 }, 124 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error", 125 -1, 1 }, 126 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error", 127 -1, 1 }, 128 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 }, 129 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 }, 130 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 }, 131 { READRSPERR_F, "Outbound read error", -1, 0 }, 132 { 0, NULL, 0, 0 } 133 }; 134 135 int fat; 136 fat = csio_handle_intr_status(hw, 137 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A, 138 sysbus_intr_info) + 139 csio_handle_intr_status(hw, 140 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A, 141 pcie_port_intr_info) + 142 csio_handle_intr_status(hw, PCIE_INT_CAUSE_A, pcie_intr_info); 143 if (fat) 144 csio_hw_fatal_err(hw); 145 } 146 147 /* 148 * csio_t5_flash_cfg_addr - return the address of the flash configuration file 149 * @hw: the HW module 150 * 151 * Return the address within the flash where the Firmware Configuration 152 * File is stored. 153 */ 154 static unsigned int 155 csio_t5_flash_cfg_addr(struct csio_hw *hw) 156 { 157 return FLASH_CFG_START; 158 } 159 160 /* 161 * csio_t5_mc_read - read from MC through backdoor accesses 162 * @hw: the hw module 163 * @idx: index to the register 164 * @addr: address of first byte requested 165 * @data: 64 bytes of data containing the requested address 166 * @ecc: where to store the corresponding 64-bit ECC word 167 * 168 * Read 64 bytes of data from MC starting at a 64-byte-aligned address 169 * that covers the requested address @addr. If @parity is not %NULL it 170 * is assigned the 64-bit ECC word for the read data. 171 */ 172 static int 173 csio_t5_mc_read(struct csio_hw *hw, int idx, uint32_t addr, __be32 *data, 174 uint64_t *ecc) 175 { 176 int i; 177 uint32_t mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg; 178 uint32_t mc_bist_status_rdata_reg, mc_bist_data_pattern_reg; 179 180 mc_bist_cmd_reg = MC_REG(MC_P_BIST_CMD_A, idx); 181 mc_bist_cmd_addr_reg = MC_REG(MC_P_BIST_CMD_ADDR_A, idx); 182 mc_bist_cmd_len_reg = MC_REG(MC_P_BIST_CMD_LEN_A, idx); 183 mc_bist_status_rdata_reg = MC_REG(MC_P_BIST_STATUS_RDATA_A, idx); 184 mc_bist_data_pattern_reg = MC_REG(MC_P_BIST_DATA_PATTERN_A, idx); 185 186 if (csio_rd_reg32(hw, mc_bist_cmd_reg) & START_BIST_F) 187 return -EBUSY; 188 csio_wr_reg32(hw, addr & ~0x3fU, mc_bist_cmd_addr_reg); 189 csio_wr_reg32(hw, 64, mc_bist_cmd_len_reg); 190 csio_wr_reg32(hw, 0xc, mc_bist_data_pattern_reg); 191 csio_wr_reg32(hw, BIST_OPCODE_V(1) | START_BIST_F | BIST_CMD_GAP_V(1), 192 mc_bist_cmd_reg); 193 i = csio_hw_wait_op_done_val(hw, mc_bist_cmd_reg, START_BIST_F, 194 0, 10, 1, NULL); 195 if (i) 196 return i; 197 198 #define MC_DATA(i) MC_BIST_STATUS_REG(MC_BIST_STATUS_RDATA_A, i) 199 200 for (i = 15; i >= 0; i--) 201 *data++ = htonl(csio_rd_reg32(hw, MC_DATA(i))); 202 if (ecc) 203 *ecc = csio_rd_reg64(hw, MC_DATA(16)); 204 #undef MC_DATA 205 return 0; 206 } 207 208 /* 209 * csio_t5_edc_read - read from EDC through backdoor accesses 210 * @hw: the hw module 211 * @idx: which EDC to access 212 * @addr: address of first byte requested 213 * @data: 64 bytes of data containing the requested address 214 * @ecc: where to store the corresponding 64-bit ECC word 215 * 216 * Read 64 bytes of data from EDC starting at a 64-byte-aligned address 217 * that covers the requested address @addr. If @parity is not %NULL it 218 * is assigned the 64-bit ECC word for the read data. 219 */ 220 static int 221 csio_t5_edc_read(struct csio_hw *hw, int idx, uint32_t addr, __be32 *data, 222 uint64_t *ecc) 223 { 224 int i; 225 uint32_t edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg; 226 uint32_t edc_bist_cmd_data_pattern, edc_bist_status_rdata_reg; 227 228 /* 229 * These macro are missing in t4_regs.h file. 230 */ 231 #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR) 232 #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx) 233 234 edc_bist_cmd_reg = EDC_REG_T5(EDC_H_BIST_CMD_A, idx); 235 edc_bist_cmd_addr_reg = EDC_REG_T5(EDC_H_BIST_CMD_ADDR_A, idx); 236 edc_bist_cmd_len_reg = EDC_REG_T5(EDC_H_BIST_CMD_LEN_A, idx); 237 edc_bist_cmd_data_pattern = EDC_REG_T5(EDC_H_BIST_DATA_PATTERN_A, idx); 238 edc_bist_status_rdata_reg = EDC_REG_T5(EDC_H_BIST_STATUS_RDATA_A, idx); 239 #undef EDC_REG_T5 240 #undef EDC_STRIDE_T5 241 242 if (csio_rd_reg32(hw, edc_bist_cmd_reg) & START_BIST_F) 243 return -EBUSY; 244 csio_wr_reg32(hw, addr & ~0x3fU, edc_bist_cmd_addr_reg); 245 csio_wr_reg32(hw, 64, edc_bist_cmd_len_reg); 246 csio_wr_reg32(hw, 0xc, edc_bist_cmd_data_pattern); 247 csio_wr_reg32(hw, BIST_OPCODE_V(1) | START_BIST_F | BIST_CMD_GAP_V(1), 248 edc_bist_cmd_reg); 249 i = csio_hw_wait_op_done_val(hw, edc_bist_cmd_reg, START_BIST_F, 250 0, 10, 1, NULL); 251 if (i) 252 return i; 253 254 #define EDC_DATA(i) (EDC_BIST_STATUS_REG(EDC_BIST_STATUS_RDATA_A, i) + idx) 255 256 for (i = 15; i >= 0; i--) 257 *data++ = htonl(csio_rd_reg32(hw, EDC_DATA(i))); 258 if (ecc) 259 *ecc = csio_rd_reg64(hw, EDC_DATA(16)); 260 #undef EDC_DATA 261 return 0; 262 } 263 264 /* 265 * csio_t5_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window 266 * @hw: the csio_hw 267 * @win: PCI-E memory Window to use 268 * @mtype: memory type: MEM_EDC0, MEM_EDC1, MEM_MC0 (or MEM_MC) or MEM_MC1 269 * @addr: address within indicated memory type 270 * @len: amount of memory to transfer 271 * @buf: host memory buffer 272 * @dir: direction of transfer 1 => read, 0 => write 273 * 274 * Reads/writes an [almost] arbitrary memory region in the firmware: the 275 * firmware memory address, length and host buffer must be aligned on 276 * 32-bit boudaries. The memory is transferred as a raw byte sequence 277 * from/to the firmware's memory. If this memory contains data 278 * structures which contain multi-byte integers, it's the callers 279 * responsibility to perform appropriate byte order conversions. 280 */ 281 static int 282 csio_t5_memory_rw(struct csio_hw *hw, u32 win, int mtype, u32 addr, 283 u32 len, uint32_t *buf, int dir) 284 { 285 u32 pos, start, offset, memoffset; 286 u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base; 287 288 /* 289 * Argument sanity checks ... 290 */ 291 if ((addr & 0x3) || (len & 0x3)) 292 return -EINVAL; 293 294 /* Offset into the region of memory which is being accessed 295 * MEM_EDC0 = 0 296 * MEM_EDC1 = 1 297 * MEM_MC = 2 -- T4 298 * MEM_MC0 = 2 -- For T5 299 * MEM_MC1 = 3 -- For T5 300 */ 301 edc_size = EDRAM0_SIZE_G(csio_rd_reg32(hw, MA_EDRAM0_BAR_A)); 302 if (mtype != MEM_MC1) 303 memoffset = (mtype * (edc_size * 1024 * 1024)); 304 else { 305 mc_size = EXT_MEM_SIZE_G(csio_rd_reg32(hw, 306 MA_EXT_MEMORY_BAR_A)); 307 memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024; 308 } 309 310 /* Determine the PCIE_MEM_ACCESS_OFFSET */ 311 addr = addr + memoffset; 312 313 /* 314 * Each PCI-E Memory Window is programmed with a window size -- or 315 * "aperture" -- which controls the granularity of its mapping onto 316 * adapter memory. We need to grab that aperture in order to know 317 * how to use the specified window. The window is also programmed 318 * with the base address of the Memory Window in BAR0's address 319 * space. For T4 this is an absolute PCI-E Bus Address. For T5 320 * the address is relative to BAR0. 321 */ 322 mem_reg = csio_rd_reg32(hw, 323 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win)); 324 mem_aperture = 1 << (WINDOW_V(mem_reg) + 10); 325 mem_base = PCIEOFST_G(mem_reg) << 10; 326 327 start = addr & ~(mem_aperture-1); 328 offset = addr - start; 329 win_pf = PFNUM_V(hw->pfn); 330 331 csio_dbg(hw, "csio_t5_memory_rw: mem_reg: 0x%x, mem_aperture: 0x%x\n", 332 mem_reg, mem_aperture); 333 csio_dbg(hw, "csio_t5_memory_rw: mem_base: 0x%x, mem_offset: 0x%x\n", 334 mem_base, memoffset); 335 csio_dbg(hw, "csio_t5_memory_rw: start:0x%x, offset:0x%x, win_pf:%d\n", 336 start, offset, win_pf); 337 csio_dbg(hw, "csio_t5_memory_rw: mtype: %d, addr: 0x%x, len: %d\n", 338 mtype, addr, len); 339 340 for (pos = start; len > 0; pos += mem_aperture, offset = 0) { 341 /* 342 * Move PCI-E Memory Window to our current transfer 343 * position. Read it back to ensure that changes propagate 344 * before we attempt to use the new value. 345 */ 346 csio_wr_reg32(hw, pos | win_pf, 347 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win)); 348 csio_rd_reg32(hw, 349 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win)); 350 351 while (offset < mem_aperture && len > 0) { 352 if (dir) 353 *buf++ = csio_rd_reg32(hw, mem_base + offset); 354 else 355 csio_wr_reg32(hw, *buf++, mem_base + offset); 356 357 offset += sizeof(__be32); 358 len -= sizeof(__be32); 359 } 360 } 361 return 0; 362 } 363 364 /* 365 * csio_t5_dfs_create_ext_mem - setup debugfs for MC0 or MC1 to read the values 366 * @hw: the csio_hw 367 * 368 * This function creates files in the debugfs with external memory region 369 * MC0 & MC1. 370 */ 371 static void 372 csio_t5_dfs_create_ext_mem(struct csio_hw *hw) 373 { 374 u32 size; 375 int i = csio_rd_reg32(hw, MA_TARGET_MEM_ENABLE_A); 376 377 if (i & EXT_MEM_ENABLE_F) { 378 size = csio_rd_reg32(hw, MA_EXT_MEMORY_BAR_A); 379 csio_add_debugfs_mem(hw, "mc0", MEM_MC0, 380 EXT_MEM_SIZE_G(size)); 381 } 382 if (i & EXT_MEM1_ENABLE_F) { 383 size = csio_rd_reg32(hw, MA_EXT_MEMORY1_BAR_A); 384 csio_add_debugfs_mem(hw, "mc1", MEM_MC1, 385 EXT_MEM_SIZE_G(size)); 386 } 387 } 388 389 /* T5 adapter specific function */ 390 struct csio_hw_chip_ops t5_ops = { 391 .chip_set_mem_win = csio_t5_set_mem_win, 392 .chip_pcie_intr_handler = csio_t5_pcie_intr_handler, 393 .chip_flash_cfg_addr = csio_t5_flash_cfg_addr, 394 .chip_mc_read = csio_t5_mc_read, 395 .chip_edc_read = csio_t5_edc_read, 396 .chip_memory_rw = csio_t5_memory_rw, 397 .chip_dfs_create_ext_mem = csio_t5_dfs_create_ext_mem, 398 }; 399