1 /* 57xx_hsi_bnx2fc.h: QLogic Linux FCoE offload driver. 2 * Handles operations such as session offload/upload etc, and manages 3 * session resources such as connection id and qp resources. 4 * 5 * Copyright (c) 2008-2013 Broadcom Corporation 6 * Copyright (c) 2014-2015 QLogic Corporation 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation. 11 * 12 */ 13 14 #ifndef __57XX_FCOE_HSI_LINUX_LE__ 15 #define __57XX_FCOE_HSI_LINUX_LE__ 16 17 /* 18 * common data for all protocols 19 */ 20 struct b577xx_doorbell_hdr { 21 u8 header; 22 #define B577XX_DOORBELL_HDR_RX (0x1<<0) 23 #define B577XX_DOORBELL_HDR_RX_SHIFT 0 24 #define B577XX_DOORBELL_HDR_DB_TYPE (0x1<<1) 25 #define B577XX_DOORBELL_HDR_DB_TYPE_SHIFT 1 26 #define B577XX_DOORBELL_HDR_DPM_SIZE (0x3<<2) 27 #define B577XX_DOORBELL_HDR_DPM_SIZE_SHIFT 2 28 #define B577XX_DOORBELL_HDR_CONN_TYPE (0xF<<4) 29 #define B577XX_DOORBELL_HDR_CONN_TYPE_SHIFT 4 30 }; 31 32 /* 33 * doorbell message sent to the chip 34 */ 35 struct b577xx_doorbell { 36 #if defined(__BIG_ENDIAN) 37 u16 zero_fill2; 38 u8 zero_fill1; 39 struct b577xx_doorbell_hdr header; 40 #elif defined(__LITTLE_ENDIAN) 41 struct b577xx_doorbell_hdr header; 42 u8 zero_fill1; 43 u16 zero_fill2; 44 #endif 45 }; 46 47 48 49 /* 50 * doorbell message sent to the chip 51 */ 52 struct b577xx_doorbell_set_prod { 53 #if defined(__BIG_ENDIAN) 54 u16 prod; 55 u8 zero_fill1; 56 struct b577xx_doorbell_hdr header; 57 #elif defined(__LITTLE_ENDIAN) 58 struct b577xx_doorbell_hdr header; 59 u8 zero_fill1; 60 u16 prod; 61 #endif 62 }; 63 64 65 struct regpair { 66 __le32 lo; 67 __le32 hi; 68 }; 69 70 71 /* 72 * ABTS info $$KEEP_ENDIANNESS$$ 73 */ 74 struct fcoe_abts_info { 75 __le16 aborted_task_id; 76 __le16 reserved0; 77 __le32 reserved1; 78 }; 79 80 81 /* 82 * Fixed size structure in order to plant it in Union structure 83 * $$KEEP_ENDIANNESS$$ 84 */ 85 struct fcoe_abts_rsp_union { 86 u8 r_ctl; 87 u8 rsrv[3]; 88 __le32 abts_rsp_payload[7]; 89 }; 90 91 92 /* 93 * 4 regs size $$KEEP_ENDIANNESS$$ 94 */ 95 struct fcoe_bd_ctx { 96 __le32 buf_addr_hi; 97 __le32 buf_addr_lo; 98 __le16 buf_len; 99 __le16 rsrv0; 100 __le16 flags; 101 __le16 rsrv1; 102 }; 103 104 105 /* 106 * FCoE cached sges context $$KEEP_ENDIANNESS$$ 107 */ 108 struct fcoe_cached_sge_ctx { 109 struct regpair cur_buf_addr; 110 __le16 cur_buf_rem; 111 __le16 second_buf_rem; 112 struct regpair second_buf_addr; 113 }; 114 115 116 /* 117 * Cleanup info $$KEEP_ENDIANNESS$$ 118 */ 119 struct fcoe_cleanup_info { 120 __le16 cleaned_task_id; 121 __le16 rolled_tx_seq_cnt; 122 __le32 rolled_tx_data_offset; 123 }; 124 125 126 /* 127 * Fcp RSP flags $$KEEP_ENDIANNESS$$ 128 */ 129 struct fcoe_fcp_rsp_flags { 130 u8 flags; 131 #define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID (0x1<<0) 132 #define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID_SHIFT 0 133 #define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID (0x1<<1) 134 #define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID_SHIFT 1 135 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER (0x1<<2) 136 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER_SHIFT 2 137 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER (0x1<<3) 138 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER_SHIFT 3 139 #define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ (0x1<<4) 140 #define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ_SHIFT 4 141 #define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS (0x7<<5) 142 #define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS_SHIFT 5 143 }; 144 145 /* 146 * Fcp RSP payload $$KEEP_ENDIANNESS$$ 147 */ 148 struct fcoe_fcp_rsp_payload { 149 struct regpair reserved0; 150 __le32 fcp_resid; 151 u8 scsi_status_code; 152 struct fcoe_fcp_rsp_flags fcp_flags; 153 __le16 retry_delay_timer; 154 __le32 fcp_rsp_len; 155 __le32 fcp_sns_len; 156 }; 157 158 /* 159 * Fixed size structure in order to plant it in Union structure 160 * $$KEEP_ENDIANNESS$$ 161 */ 162 struct fcoe_fcp_rsp_union { 163 struct fcoe_fcp_rsp_payload payload; 164 struct regpair reserved0; 165 }; 166 167 /* 168 * FC header $$KEEP_ENDIANNESS$$ 169 */ 170 struct fcoe_fc_hdr { 171 u8 s_id[3]; 172 u8 cs_ctl; 173 u8 d_id[3]; 174 u8 r_ctl; 175 __le16 seq_cnt; 176 u8 df_ctl; 177 u8 seq_id; 178 u8 f_ctl[3]; 179 u8 type; 180 __le32 parameters; 181 __le16 rx_id; 182 __le16 ox_id; 183 }; 184 185 /* 186 * FC header union $$KEEP_ENDIANNESS$$ 187 */ 188 struct fcoe_mp_rsp_union { 189 struct fcoe_fc_hdr fc_hdr; 190 __le32 mp_payload_len; 191 __le32 rsrv; 192 }; 193 194 /* 195 * Completion information $$KEEP_ENDIANNESS$$ 196 */ 197 union fcoe_comp_flow_info { 198 struct fcoe_fcp_rsp_union fcp_rsp; 199 struct fcoe_abts_rsp_union abts_rsp; 200 struct fcoe_mp_rsp_union mp_rsp; 201 __le32 opaque[8]; 202 }; 203 204 205 /* 206 * External ABTS info $$KEEP_ENDIANNESS$$ 207 */ 208 struct fcoe_ext_abts_info { 209 __le32 rsrv0[6]; 210 struct fcoe_abts_info ctx; 211 }; 212 213 214 /* 215 * External cleanup info $$KEEP_ENDIANNESS$$ 216 */ 217 struct fcoe_ext_cleanup_info { 218 __le32 rsrv0[6]; 219 struct fcoe_cleanup_info ctx; 220 }; 221 222 223 /* 224 * Fcoe FW Tx sequence context $$KEEP_ENDIANNESS$$ 225 */ 226 struct fcoe_fw_tx_seq_ctx { 227 __le32 data_offset; 228 __le16 seq_cnt; 229 __le16 rsrv0; 230 }; 231 232 /* 233 * Fcoe external FW Tx sequence context $$KEEP_ENDIANNESS$$ 234 */ 235 struct fcoe_ext_fw_tx_seq_ctx { 236 __le32 rsrv0[6]; 237 struct fcoe_fw_tx_seq_ctx ctx; 238 }; 239 240 241 /* 242 * FCoE multiple sges context $$KEEP_ENDIANNESS$$ 243 */ 244 struct fcoe_mul_sges_ctx { 245 struct regpair cur_sge_addr; 246 __le16 cur_sge_off; 247 u8 cur_sge_idx; 248 u8 sgl_size; 249 }; 250 251 /* 252 * FCoE external multiple sges context $$KEEP_ENDIANNESS$$ 253 */ 254 struct fcoe_ext_mul_sges_ctx { 255 struct fcoe_mul_sges_ctx mul_sgl; 256 struct regpair rsrv0; 257 }; 258 259 260 /* 261 * FCP CMD payload $$KEEP_ENDIANNESS$$ 262 */ 263 struct fcoe_fcp_cmd_payload { 264 __le32 opaque[8]; 265 }; 266 267 268 269 270 271 /* 272 * Fcp xfr rdy payload $$KEEP_ENDIANNESS$$ 273 */ 274 struct fcoe_fcp_xfr_rdy_payload { 275 __le32 burst_len; 276 __le32 data_ro; 277 }; 278 279 280 /* 281 * FC frame $$KEEP_ENDIANNESS$$ 282 */ 283 struct fcoe_fc_frame { 284 struct fcoe_fc_hdr fc_hdr; 285 __le32 reserved0[2]; 286 }; 287 288 289 290 291 /* 292 * FCoE KCQ CQE parameters $$KEEP_ENDIANNESS$$ 293 */ 294 union fcoe_kcqe_params { 295 __le32 reserved0[4]; 296 }; 297 298 /* 299 * FCoE KCQ CQE $$KEEP_ENDIANNESS$$ 300 */ 301 struct fcoe_kcqe { 302 __le32 fcoe_conn_id; 303 __le32 completion_status; 304 __le32 fcoe_conn_context_id; 305 union fcoe_kcqe_params params; 306 __le16 qe_self_seq; 307 u8 op_code; 308 u8 flags; 309 #define FCOE_KCQE_RESERVED0 (0x7<<0) 310 #define FCOE_KCQE_RESERVED0_SHIFT 0 311 #define FCOE_KCQE_RAMROD_COMPLETION (0x1<<3) 312 #define FCOE_KCQE_RAMROD_COMPLETION_SHIFT 3 313 #define FCOE_KCQE_LAYER_CODE (0x7<<4) 314 #define FCOE_KCQE_LAYER_CODE_SHIFT 4 315 #define FCOE_KCQE_LINKED_WITH_NEXT (0x1<<7) 316 #define FCOE_KCQE_LINKED_WITH_NEXT_SHIFT 7 317 }; 318 319 320 321 /* 322 * FCoE KWQE header $$KEEP_ENDIANNESS$$ 323 */ 324 struct fcoe_kwqe_header { 325 u8 op_code; 326 u8 flags; 327 #define FCOE_KWQE_HEADER_RESERVED0 (0xF<<0) 328 #define FCOE_KWQE_HEADER_RESERVED0_SHIFT 0 329 #define FCOE_KWQE_HEADER_LAYER_CODE (0x7<<4) 330 #define FCOE_KWQE_HEADER_LAYER_CODE_SHIFT 4 331 #define FCOE_KWQE_HEADER_RESERVED1 (0x1<<7) 332 #define FCOE_KWQE_HEADER_RESERVED1_SHIFT 7 333 }; 334 335 /* 336 * FCoE firmware init request 1 $$KEEP_ENDIANNESS$$ 337 */ 338 struct fcoe_kwqe_init1 { 339 __le16 num_tasks; 340 struct fcoe_kwqe_header hdr; 341 __le32 task_list_pbl_addr_lo; 342 __le32 task_list_pbl_addr_hi; 343 __le32 dummy_buffer_addr_lo; 344 __le32 dummy_buffer_addr_hi; 345 __le16 sq_num_wqes; 346 __le16 rq_num_wqes; 347 __le16 rq_buffer_log_size; 348 __le16 cq_num_wqes; 349 __le16 mtu; 350 u8 num_sessions_log; 351 u8 flags; 352 #define FCOE_KWQE_INIT1_LOG_PAGE_SIZE (0xF<<0) 353 #define FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT 0 354 #define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC (0x7<<4) 355 #define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC_SHIFT 4 356 #define FCOE_KWQE_INIT1_RESERVED1 (0x1<<7) 357 #define FCOE_KWQE_INIT1_RESERVED1_SHIFT 7 358 }; 359 360 /* 361 * FCoE firmware init request 2 $$KEEP_ENDIANNESS$$ 362 */ 363 struct fcoe_kwqe_init2 { 364 u8 hsi_major_version; 365 u8 hsi_minor_version; 366 struct fcoe_kwqe_header hdr; 367 __le32 hash_tbl_pbl_addr_lo; 368 __le32 hash_tbl_pbl_addr_hi; 369 __le32 t2_hash_tbl_addr_lo; 370 __le32 t2_hash_tbl_addr_hi; 371 __le32 t2_ptr_hash_tbl_addr_lo; 372 __le32 t2_ptr_hash_tbl_addr_hi; 373 __le32 free_list_count; 374 }; 375 376 /* 377 * FCoE firmware init request 3 $$KEEP_ENDIANNESS$$ 378 */ 379 struct fcoe_kwqe_init3 { 380 __le16 reserved0; 381 struct fcoe_kwqe_header hdr; 382 __le32 error_bit_map_lo; 383 __le32 error_bit_map_hi; 384 u8 perf_config; 385 u8 reserved21[3]; 386 __le32 reserved2[4]; 387 }; 388 389 /* 390 * FCoE connection offload request 1 $$KEEP_ENDIANNESS$$ 391 */ 392 struct fcoe_kwqe_conn_offload1 { 393 __le16 fcoe_conn_id; 394 struct fcoe_kwqe_header hdr; 395 __le32 sq_addr_lo; 396 __le32 sq_addr_hi; 397 __le32 rq_pbl_addr_lo; 398 __le32 rq_pbl_addr_hi; 399 __le32 rq_first_pbe_addr_lo; 400 __le32 rq_first_pbe_addr_hi; 401 __le16 rq_prod; 402 __le16 reserved0; 403 }; 404 405 /* 406 * FCoE connection offload request 2 $$KEEP_ENDIANNESS$$ 407 */ 408 struct fcoe_kwqe_conn_offload2 { 409 __le16 tx_max_fc_pay_len; 410 struct fcoe_kwqe_header hdr; 411 __le32 cq_addr_lo; 412 __le32 cq_addr_hi; 413 __le32 xferq_addr_lo; 414 __le32 xferq_addr_hi; 415 __le32 conn_db_addr_lo; 416 __le32 conn_db_addr_hi; 417 __le32 reserved1; 418 }; 419 420 /* 421 * FCoE connection offload request 3 $$KEEP_ENDIANNESS$$ 422 */ 423 struct fcoe_kwqe_conn_offload3 { 424 __le16 vlan_tag; 425 #define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID (0xFFF<<0) 426 #define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT 0 427 #define FCOE_KWQE_CONN_OFFLOAD3_CFI (0x1<<12) 428 #define FCOE_KWQE_CONN_OFFLOAD3_CFI_SHIFT 12 429 #define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY (0x7<<13) 430 #define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT 13 431 struct fcoe_kwqe_header hdr; 432 u8 s_id[3]; 433 u8 tx_max_conc_seqs_c3; 434 u8 d_id[3]; 435 u8 flags; 436 #define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS (0x1<<0) 437 #define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT 0 438 #define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES (0x1<<1) 439 #define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT 1 440 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT (0x1<<2) 441 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT 2 442 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ (0x1<<3) 443 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT 3 444 #define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID (0x1<<4) 445 #define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT 4 446 #define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID (0x1<<5) 447 #define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID_SHIFT 5 448 #define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0 (0x1<<6) 449 #define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0_SHIFT 6 450 #define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG (0x1<<7) 451 #define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT 7 452 __le32 reserved; 453 __le32 confq_first_pbe_addr_lo; 454 __le32 confq_first_pbe_addr_hi; 455 __le16 tx_total_conc_seqs; 456 __le16 rx_max_fc_pay_len; 457 __le16 rx_total_conc_seqs; 458 u8 rx_max_conc_seqs_c3; 459 u8 rx_open_seqs_exch_c3; 460 }; 461 462 /* 463 * FCoE connection offload request 4 $$KEEP_ENDIANNESS$$ 464 */ 465 struct fcoe_kwqe_conn_offload4 { 466 u8 e_d_tov_timer_val; 467 u8 reserved2; 468 struct fcoe_kwqe_header hdr; 469 u8 src_mac_addr_lo[2]; 470 u8 src_mac_addr_mid[2]; 471 u8 src_mac_addr_hi[2]; 472 u8 dst_mac_addr_hi[2]; 473 u8 dst_mac_addr_lo[2]; 474 u8 dst_mac_addr_mid[2]; 475 __le32 lcq_addr_lo; 476 __le32 lcq_addr_hi; 477 __le32 confq_pbl_base_addr_lo; 478 __le32 confq_pbl_base_addr_hi; 479 }; 480 481 /* 482 * FCoE connection enable request $$KEEP_ENDIANNESS$$ 483 */ 484 struct fcoe_kwqe_conn_enable_disable { 485 __le16 reserved0; 486 struct fcoe_kwqe_header hdr; 487 u8 src_mac_addr_lo[2]; 488 u8 src_mac_addr_mid[2]; 489 u8 src_mac_addr_hi[2]; 490 u16 vlan_tag; 491 #define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID (0xFFF<<0) 492 #define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT 0 493 #define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI (0x1<<12) 494 #define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI_SHIFT 12 495 #define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY (0x7<<13) 496 #define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT 13 497 u8 dst_mac_addr_lo[2]; 498 u8 dst_mac_addr_mid[2]; 499 u8 dst_mac_addr_hi[2]; 500 __le16 reserved1; 501 u8 s_id[3]; 502 u8 vlan_flag; 503 u8 d_id[3]; 504 u8 reserved3; 505 __le32 context_id; 506 __le32 conn_id; 507 __le32 reserved4; 508 }; 509 510 /* 511 * FCoE connection destroy request $$KEEP_ENDIANNESS$$ 512 */ 513 struct fcoe_kwqe_conn_destroy { 514 __le16 reserved0; 515 struct fcoe_kwqe_header hdr; 516 __le32 context_id; 517 __le32 conn_id; 518 __le32 reserved1[5]; 519 }; 520 521 /* 522 * FCoe destroy request $$KEEP_ENDIANNESS$$ 523 */ 524 struct fcoe_kwqe_destroy { 525 __le16 reserved0; 526 struct fcoe_kwqe_header hdr; 527 __le32 reserved1[7]; 528 }; 529 530 /* 531 * FCoe statistics request $$KEEP_ENDIANNESS$$ 532 */ 533 struct fcoe_kwqe_stat { 534 __le16 reserved0; 535 struct fcoe_kwqe_header hdr; 536 __le32 stat_params_addr_lo; 537 __le32 stat_params_addr_hi; 538 __le32 reserved1[5]; 539 }; 540 541 /* 542 * FCoE KWQ WQE $$KEEP_ENDIANNESS$$ 543 */ 544 union fcoe_kwqe { 545 struct fcoe_kwqe_init1 init1; 546 struct fcoe_kwqe_init2 init2; 547 struct fcoe_kwqe_init3 init3; 548 struct fcoe_kwqe_conn_offload1 conn_offload1; 549 struct fcoe_kwqe_conn_offload2 conn_offload2; 550 struct fcoe_kwqe_conn_offload3 conn_offload3; 551 struct fcoe_kwqe_conn_offload4 conn_offload4; 552 struct fcoe_kwqe_conn_enable_disable conn_enable_disable; 553 struct fcoe_kwqe_conn_destroy conn_destroy; 554 struct fcoe_kwqe_destroy destroy; 555 struct fcoe_kwqe_stat statistics; 556 }; 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 /* 574 * TX SGL context $$KEEP_ENDIANNESS$$ 575 */ 576 union fcoe_sgl_union_ctx { 577 struct fcoe_cached_sge_ctx cached_sge; 578 struct fcoe_ext_mul_sges_ctx sgl; 579 __le32 opaque[5]; 580 }; 581 582 /* 583 * Data-In/ELS/BLS information $$KEEP_ENDIANNESS$$ 584 */ 585 struct fcoe_read_flow_info { 586 union fcoe_sgl_union_ctx sgl_ctx; 587 __le32 rsrv0[3]; 588 }; 589 590 591 /* 592 * Fcoe stat context $$KEEP_ENDIANNESS$$ 593 */ 594 struct fcoe_s_stat_ctx { 595 u8 flags; 596 #define FCOE_S_STAT_CTX_ACTIVE (0x1<<0) 597 #define FCOE_S_STAT_CTX_ACTIVE_SHIFT 0 598 #define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND (0x1<<1) 599 #define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND_SHIFT 1 600 #define FCOE_S_STAT_CTX_ABTS_PERFORMED (0x1<<2) 601 #define FCOE_S_STAT_CTX_ABTS_PERFORMED_SHIFT 2 602 #define FCOE_S_STAT_CTX_SEQ_TIMEOUT (0x1<<3) 603 #define FCOE_S_STAT_CTX_SEQ_TIMEOUT_SHIFT 3 604 #define FCOE_S_STAT_CTX_P_RJT (0x1<<4) 605 #define FCOE_S_STAT_CTX_P_RJT_SHIFT 4 606 #define FCOE_S_STAT_CTX_ACK_EOFT (0x1<<5) 607 #define FCOE_S_STAT_CTX_ACK_EOFT_SHIFT 5 608 #define FCOE_S_STAT_CTX_RSRV1 (0x3<<6) 609 #define FCOE_S_STAT_CTX_RSRV1_SHIFT 6 610 }; 611 612 /* 613 * Fcoe rx seq context $$KEEP_ENDIANNESS$$ 614 */ 615 struct fcoe_rx_seq_ctx { 616 u8 seq_id; 617 struct fcoe_s_stat_ctx s_stat; 618 __le16 seq_cnt; 619 __le32 low_exp_ro; 620 __le32 high_exp_ro; 621 }; 622 623 624 /* 625 * Fcoe rx_wr union context $$KEEP_ENDIANNESS$$ 626 */ 627 union fcoe_rx_wr_union_ctx { 628 struct fcoe_read_flow_info read_info; 629 union fcoe_comp_flow_info comp_info; 630 __le32 opaque[8]; 631 }; 632 633 634 635 /* 636 * FCoE SQ element $$KEEP_ENDIANNESS$$ 637 */ 638 struct fcoe_sqe { 639 __le16 wqe; 640 #define FCOE_SQE_TASK_ID (0x7FFF<<0) 641 #define FCOE_SQE_TASK_ID_SHIFT 0 642 #define FCOE_SQE_TOGGLE_BIT (0x1<<15) 643 #define FCOE_SQE_TOGGLE_BIT_SHIFT 15 644 }; 645 646 647 648 /* 649 * 14 regs $$KEEP_ENDIANNESS$$ 650 */ 651 struct fcoe_tce_tx_only { 652 union fcoe_sgl_union_ctx sgl_ctx; 653 __le32 rsrv0; 654 }; 655 656 /* 657 * 32 bytes (8 regs) used for TX only purposes $$KEEP_ENDIANNESS$$ 658 */ 659 union fcoe_tx_wr_rx_rd_union_ctx { 660 struct fcoe_fc_frame tx_frame; 661 struct fcoe_fcp_cmd_payload fcp_cmd; 662 struct fcoe_ext_cleanup_info cleanup; 663 struct fcoe_ext_abts_info abts; 664 struct fcoe_ext_fw_tx_seq_ctx tx_seq; 665 __le32 opaque[8]; 666 }; 667 668 /* 669 * tce_tx_wr_rx_rd_const $$KEEP_ENDIANNESS$$ 670 */ 671 struct fcoe_tce_tx_wr_rx_rd_const { 672 u8 init_flags; 673 #define FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE (0x7<<0) 674 #define FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT 0 675 #define FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE (0x1<<3) 676 #define FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT 3 677 #define FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE (0x1<<4) 678 #define FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT 4 679 #define FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE (0x3<<5) 680 #define FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT 5 681 #define FCOE_TCE_TX_WR_RX_RD_CONST_SUPPORT_REC_TOV (0x1<<7) 682 #define FCOE_TCE_TX_WR_RX_RD_CONST_SUPPORT_REC_TOV_SHIFT 7 683 u8 tx_flags; 684 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_VALID (0x1<<0) 685 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_VALID_SHIFT 0 686 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE (0xF<<1) 687 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT 1 688 #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV1 (0x1<<5) 689 #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV1_SHIFT 5 690 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_SEQ_INIT (0x1<<6) 691 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_SEQ_INIT_SHIFT 6 692 #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV2 (0x1<<7) 693 #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV2_SHIFT 7 694 __le16 rsrv3; 695 __le32 verify_tx_seq; 696 }; 697 698 /* 699 * tce_tx_wr_rx_rd $$KEEP_ENDIANNESS$$ 700 */ 701 struct fcoe_tce_tx_wr_rx_rd { 702 union fcoe_tx_wr_rx_rd_union_ctx union_ctx; 703 struct fcoe_tce_tx_wr_rx_rd_const const_ctx; 704 }; 705 706 /* 707 * tce_rx_wr_tx_rd_const $$KEEP_ENDIANNESS$$ 708 */ 709 struct fcoe_tce_rx_wr_tx_rd_const { 710 __le32 data_2_trns; 711 __le32 init_flags; 712 #define FCOE_TCE_RX_WR_TX_RD_CONST_CID (0xFFFFFF<<0) 713 #define FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT 0 714 #define FCOE_TCE_RX_WR_TX_RD_CONST_RSRV0 (0xFF<<24) 715 #define FCOE_TCE_RX_WR_TX_RD_CONST_RSRV0_SHIFT 24 716 }; 717 718 /* 719 * tce_rx_wr_tx_rd_var $$KEEP_ENDIANNESS$$ 720 */ 721 struct fcoe_tce_rx_wr_tx_rd_var { 722 __le16 rx_flags; 723 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV1 (0xF<<0) 724 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV1_SHIFT 0 725 #define FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE (0x7<<4) 726 #define FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE_SHIFT 4 727 #define FCOE_TCE_RX_WR_TX_RD_VAR_CONF_REQ (0x1<<7) 728 #define FCOE_TCE_RX_WR_TX_RD_VAR_CONF_REQ_SHIFT 7 729 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE (0xF<<8) 730 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE_SHIFT 8 731 #define FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME (0x1<<12) 732 #define FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT 12 733 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_SEQ_INIT (0x1<<13) 734 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_SEQ_INIT_SHIFT 13 735 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV2 (0x1<<14) 736 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV2_SHIFT 14 737 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_VALID (0x1<<15) 738 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_VALID_SHIFT 15 739 __le16 rx_id; 740 struct fcoe_fcp_xfr_rdy_payload fcp_xfr_rdy; 741 }; 742 743 /* 744 * tce_rx_wr_tx_rd $$KEEP_ENDIANNESS$$ 745 */ 746 struct fcoe_tce_rx_wr_tx_rd { 747 struct fcoe_tce_rx_wr_tx_rd_const const_ctx; 748 struct fcoe_tce_rx_wr_tx_rd_var var_ctx; 749 }; 750 751 /* 752 * tce_rx_only $$KEEP_ENDIANNESS$$ 753 */ 754 struct fcoe_tce_rx_only { 755 struct fcoe_rx_seq_ctx rx_seq_ctx; 756 union fcoe_rx_wr_union_ctx union_ctx; 757 }; 758 759 /* 760 * task_ctx_entry $$KEEP_ENDIANNESS$$ 761 */ 762 struct fcoe_task_ctx_entry { 763 struct fcoe_tce_tx_only txwr_only; 764 struct fcoe_tce_tx_wr_rx_rd txwr_rxrd; 765 struct fcoe_tce_rx_wr_tx_rd rxwr_txrd; 766 struct fcoe_tce_rx_only rxwr_only; 767 }; 768 769 770 771 772 773 774 775 776 777 778 /* 779 * FCoE XFRQ element $$KEEP_ENDIANNESS$$ 780 */ 781 struct fcoe_xfrqe { 782 __le16 wqe; 783 #define FCOE_XFRQE_TASK_ID (0x7FFF<<0) 784 #define FCOE_XFRQE_TASK_ID_SHIFT 0 785 #define FCOE_XFRQE_TOGGLE_BIT (0x1<<15) 786 #define FCOE_XFRQE_TOGGLE_BIT_SHIFT 15 787 }; 788 789 790 /* 791 * fcoe rx doorbell message sent to the chip $$KEEP_ENDIANNESS$$ 792 */ 793 struct b577xx_fcoe_rx_doorbell { 794 struct b577xx_doorbell_hdr hdr; 795 u8 params; 796 #define B577XX_FCOE_RX_DOORBELL_NEGATIVE_ARM (0x1F<<0) 797 #define B577XX_FCOE_RX_DOORBELL_NEGATIVE_ARM_SHIFT 0 798 #define B577XX_FCOE_RX_DOORBELL_OPCODE (0x7<<5) 799 #define B577XX_FCOE_RX_DOORBELL_OPCODE_SHIFT 5 800 __le16 doorbell_cq_cons; 801 }; 802 803 804 /* 805 * FCoE CONFQ element $$KEEP_ENDIANNESS$$ 806 */ 807 struct fcoe_confqe { 808 __le16 ox_id; 809 __le16 rx_id; 810 __le32 param; 811 }; 812 813 814 /* 815 * FCoE conection data base 816 */ 817 struct fcoe_conn_db { 818 #if defined(__BIG_ENDIAN) 819 u16 rsrv0; 820 u16 rq_prod; 821 #elif defined(__LITTLE_ENDIAN) 822 u16 rq_prod; 823 u16 rsrv0; 824 #endif 825 u32 rsrv1; 826 struct regpair cq_arm; 827 }; 828 829 830 /* 831 * FCoE CQ element $$KEEP_ENDIANNESS$$ 832 */ 833 struct fcoe_cqe { 834 __le16 wqe; 835 #define FCOE_CQE_CQE_INFO (0x3FFF<<0) 836 #define FCOE_CQE_CQE_INFO_SHIFT 0 837 #define FCOE_CQE_CQE_TYPE (0x1<<14) 838 #define FCOE_CQE_CQE_TYPE_SHIFT 14 839 #define FCOE_CQE_TOGGLE_BIT (0x1<<15) 840 #define FCOE_CQE_TOGGLE_BIT_SHIFT 15 841 }; 842 843 844 /* 845 * FCoE error/warning reporting entry $$KEEP_ENDIANNESS$$ 846 */ 847 struct fcoe_partial_err_report_entry { 848 __le32 err_warn_bitmap_lo; 849 __le32 err_warn_bitmap_hi; 850 __le32 tx_buf_off; 851 __le32 rx_buf_off; 852 }; 853 854 /* 855 * FCoE error/warning reporting entry $$KEEP_ENDIANNESS$$ 856 */ 857 struct fcoe_err_report_entry { 858 struct fcoe_partial_err_report_entry data; 859 struct fcoe_fc_hdr fc_hdr; 860 }; 861 862 863 /* 864 * FCoE hash table entry (32 bytes) $$KEEP_ENDIANNESS$$ 865 */ 866 struct fcoe_hash_table_entry { 867 u8 s_id_0; 868 u8 s_id_1; 869 u8 s_id_2; 870 u8 d_id_0; 871 u8 d_id_1; 872 u8 d_id_2; 873 __le16 dst_mac_addr_hi; 874 __le16 dst_mac_addr_mid; 875 __le16 dst_mac_addr_lo; 876 __le16 src_mac_addr_hi; 877 __le16 vlan_id; 878 __le16 src_mac_addr_lo; 879 __le16 src_mac_addr_mid; 880 u8 vlan_flag; 881 u8 reserved0; 882 __le16 reserved1; 883 __le32 reserved2; 884 __le32 field_id; 885 #define FCOE_HASH_TABLE_ENTRY_CID (0xFFFFFF<<0) 886 #define FCOE_HASH_TABLE_ENTRY_CID_SHIFT 0 887 #define FCOE_HASH_TABLE_ENTRY_RESERVED3 (0x7F<<24) 888 #define FCOE_HASH_TABLE_ENTRY_RESERVED3_SHIFT 24 889 #define FCOE_HASH_TABLE_ENTRY_VALID (0x1<<31) 890 #define FCOE_HASH_TABLE_ENTRY_VALID_SHIFT 31 891 }; 892 893 894 /* 895 * FCoE LCQ element $$KEEP_ENDIANNESS$$ 896 */ 897 struct fcoe_lcqe { 898 __le32 wqe; 899 #define FCOE_LCQE_TASK_ID (0xFFFF<<0) 900 #define FCOE_LCQE_TASK_ID_SHIFT 0 901 #define FCOE_LCQE_LCQE_TYPE (0xFF<<16) 902 #define FCOE_LCQE_LCQE_TYPE_SHIFT 16 903 #define FCOE_LCQE_RESERVED (0xFF<<24) 904 #define FCOE_LCQE_RESERVED_SHIFT 24 905 }; 906 907 908 909 /* 910 * FCoE pending work request CQE $$KEEP_ENDIANNESS$$ 911 */ 912 struct fcoe_pend_wq_cqe { 913 __le16 wqe; 914 #define FCOE_PEND_WQ_CQE_TASK_ID (0x3FFF<<0) 915 #define FCOE_PEND_WQ_CQE_TASK_ID_SHIFT 0 916 #define FCOE_PEND_WQ_CQE_CQE_TYPE (0x1<<14) 917 #define FCOE_PEND_WQ_CQE_CQE_TYPE_SHIFT 14 918 #define FCOE_PEND_WQ_CQE_TOGGLE_BIT (0x1<<15) 919 #define FCOE_PEND_WQ_CQE_TOGGLE_BIT_SHIFT 15 920 }; 921 922 923 /* 924 * FCoE RX statistics parameters section#0 $$KEEP_ENDIANNESS$$ 925 */ 926 struct fcoe_rx_stat_params_section0 { 927 __le32 fcoe_rx_pkt_cnt; 928 __le32 fcoe_rx_byte_cnt; 929 }; 930 931 932 /* 933 * FCoE RX statistics parameters section#1 $$KEEP_ENDIANNESS$$ 934 */ 935 struct fcoe_rx_stat_params_section1 { 936 __le32 fcoe_ver_cnt; 937 __le32 fcoe_rx_drop_pkt_cnt; 938 }; 939 940 941 /* 942 * FCoE RX statistics parameters section#2 $$KEEP_ENDIANNESS$$ 943 */ 944 struct fcoe_rx_stat_params_section2 { 945 __le32 fc_crc_cnt; 946 __le32 eofa_del_cnt; 947 __le32 miss_frame_cnt; 948 __le32 seq_timeout_cnt; 949 __le32 drop_seq_cnt; 950 __le32 fcoe_rx_drop_pkt_cnt; 951 __le32 fcp_rx_pkt_cnt; 952 __le32 reserved0; 953 }; 954 955 956 /* 957 * FCoE TX statistics parameters $$KEEP_ENDIANNESS$$ 958 */ 959 struct fcoe_tx_stat_params { 960 __le32 fcoe_tx_pkt_cnt; 961 __le32 fcoe_tx_byte_cnt; 962 __le32 fcp_tx_pkt_cnt; 963 __le32 reserved0; 964 }; 965 966 /* 967 * FCoE statistics parameters $$KEEP_ENDIANNESS$$ 968 */ 969 struct fcoe_statistics_params { 970 struct fcoe_tx_stat_params tx_stat; 971 struct fcoe_rx_stat_params_section0 rx_stat0; 972 struct fcoe_rx_stat_params_section1 rx_stat1; 973 struct fcoe_rx_stat_params_section2 rx_stat2; 974 }; 975 976 977 /* 978 * FCoE t2 hash table entry (64 bytes) $$KEEP_ENDIANNESS$$ 979 */ 980 struct fcoe_t2_hash_table_entry { 981 struct fcoe_hash_table_entry data; 982 struct regpair next; 983 struct regpair reserved0[3]; 984 }; 985 986 987 988 /* 989 * FCoE unsolicited CQE $$KEEP_ENDIANNESS$$ 990 */ 991 struct fcoe_unsolicited_cqe { 992 __le16 wqe; 993 #define FCOE_UNSOLICITED_CQE_SUBTYPE (0x3<<0) 994 #define FCOE_UNSOLICITED_CQE_SUBTYPE_SHIFT 0 995 #define FCOE_UNSOLICITED_CQE_PKT_LEN (0xFFF<<2) 996 #define FCOE_UNSOLICITED_CQE_PKT_LEN_SHIFT 2 997 #define FCOE_UNSOLICITED_CQE_CQE_TYPE (0x1<<14) 998 #define FCOE_UNSOLICITED_CQE_CQE_TYPE_SHIFT 14 999 #define FCOE_UNSOLICITED_CQE_TOGGLE_BIT (0x1<<15) 1000 #define FCOE_UNSOLICITED_CQE_TOGGLE_BIT_SHIFT 15 1001 }; 1002 1003 #endif /* __57XX_FCOE_HSI_LINUX_LE__ */ 1004