1 /* 2 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc. 3 * All rights reserved 4 * www.brocade.com 5 * 6 * Linux driver for Brocade Fibre Channel Host Bus Adapter. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License (GPL) Version 2 as 10 * published by the Free Software Foundation 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 */ 17 18 #ifndef __BFI_H__ 19 #define __BFI_H__ 20 21 #include "bfa_defs.h" 22 #include "bfa_defs_svc.h" 23 24 #pragma pack(1) 25 26 /* Per dma segment max size */ 27 #define BFI_MEM_DMA_SEG_SZ (131072) 28 29 /* Get number of dma segments required */ 30 #define BFI_MEM_DMA_NSEGS(_num_reqs, _req_sz) \ 31 ((u16)(((((_num_reqs) * (_req_sz)) + BFI_MEM_DMA_SEG_SZ - 1) & \ 32 ~(BFI_MEM_DMA_SEG_SZ - 1)) / BFI_MEM_DMA_SEG_SZ)) 33 34 /* Get num dma reqs - that fit in a segment */ 35 #define BFI_MEM_NREQS_SEG(_rqsz) (BFI_MEM_DMA_SEG_SZ / (_rqsz)) 36 37 /* Get segment num from tag */ 38 #define BFI_MEM_SEG_FROM_TAG(_tag, _rqsz) ((_tag) / BFI_MEM_NREQS_SEG(_rqsz)) 39 40 /* Get dma req offset in a segment */ 41 #define BFI_MEM_SEG_REQ_OFFSET(_tag, _sz) \ 42 ((_tag) - (BFI_MEM_SEG_FROM_TAG(_tag, _sz) * BFI_MEM_NREQS_SEG(_sz))) 43 44 /* 45 * BFI FW image type 46 */ 47 #define BFI_FLASH_CHUNK_SZ 256 /* Flash chunk size */ 48 #define BFI_FLASH_CHUNK_SZ_WORDS (BFI_FLASH_CHUNK_SZ/sizeof(u32)) 49 #define BFI_FLASH_IMAGE_SZ 0x100000 50 51 /* 52 * Msg header common to all msgs 53 */ 54 struct bfi_mhdr_s { 55 u8 msg_class; /* @ref bfi_mclass_t */ 56 u8 msg_id; /* msg opcode with in the class */ 57 union { 58 struct { 59 u8 qid; 60 u8 fn_lpu; /* msg destination */ 61 } h2i; 62 u16 i2htok; /* token in msgs to host */ 63 } mtag; 64 }; 65 66 #define bfi_fn_lpu(__fn, __lpu) ((__fn) << 1 | (__lpu)) 67 #define bfi_mhdr_2_fn(_mh) ((_mh)->mtag.h2i.fn_lpu >> 1) 68 69 #define bfi_h2i_set(_mh, _mc, _op, _fn_lpu) do { \ 70 (_mh).msg_class = (_mc); \ 71 (_mh).msg_id = (_op); \ 72 (_mh).mtag.h2i.fn_lpu = (_fn_lpu); \ 73 } while (0) 74 75 #define bfi_i2h_set(_mh, _mc, _op, _i2htok) do { \ 76 (_mh).msg_class = (_mc); \ 77 (_mh).msg_id = (_op); \ 78 (_mh).mtag.i2htok = (_i2htok); \ 79 } while (0) 80 81 /* 82 * Message opcodes: 0-127 to firmware, 128-255 to host 83 */ 84 #define BFI_I2H_OPCODE_BASE 128 85 #define BFA_I2HM(_x) ((_x) + BFI_I2H_OPCODE_BASE) 86 87 /* 88 **************************************************************************** 89 * 90 * Scatter Gather Element and Page definition 91 * 92 **************************************************************************** 93 */ 94 95 #define BFI_SGE_INLINE 1 96 #define BFI_SGE_INLINE_MAX (BFI_SGE_INLINE + 1) 97 98 /* 99 * SG Flags 100 */ 101 enum { 102 BFI_SGE_DATA = 0, /* data address, not last */ 103 BFI_SGE_DATA_CPL = 1, /* data addr, last in current page */ 104 BFI_SGE_DATA_LAST = 3, /* data address, last */ 105 BFI_SGE_LINK = 2, /* link address */ 106 BFI_SGE_PGDLEN = 2, /* cumulative data length for page */ 107 }; 108 109 /* 110 * DMA addresses 111 */ 112 union bfi_addr_u { 113 struct { 114 __be32 addr_lo; 115 __be32 addr_hi; 116 } a32; 117 }; 118 119 /* 120 * Scatter Gather Element used for fast-path IO requests 121 */ 122 struct bfi_sge_s { 123 #ifdef __BIG_ENDIAN 124 u32 flags:2, 125 rsvd:2, 126 sg_len:28; 127 #else 128 u32 sg_len:28, 129 rsvd:2, 130 flags:2; 131 #endif 132 union bfi_addr_u sga; 133 }; 134 135 /** 136 * Generic DMA addr-len pair. 137 */ 138 struct bfi_alen_s { 139 union bfi_addr_u al_addr; /* DMA addr of buffer */ 140 u32 al_len; /* length of buffer */ 141 }; 142 143 /* 144 * Scatter Gather Page 145 */ 146 #define BFI_SGPG_DATA_SGES 7 147 #define BFI_SGPG_SGES_MAX (BFI_SGPG_DATA_SGES + 1) 148 #define BFI_SGPG_RSVD_WD_LEN 8 149 struct bfi_sgpg_s { 150 struct bfi_sge_s sges[BFI_SGPG_SGES_MAX]; 151 u32 rsvd[BFI_SGPG_RSVD_WD_LEN]; 152 }; 153 154 /* FCP module definitions */ 155 #define BFI_IO_MAX (2000) 156 #define BFI_IOIM_SNSLEN (256) 157 #define BFI_IOIM_SNSBUF_SEGS \ 158 BFI_MEM_DMA_NSEGS(BFI_IO_MAX, BFI_IOIM_SNSLEN) 159 160 /* 161 * Large Message structure - 128 Bytes size Msgs 162 */ 163 #define BFI_LMSG_SZ 128 164 #define BFI_LMSG_PL_WSZ \ 165 ((BFI_LMSG_SZ - sizeof(struct bfi_mhdr_s)) / 4) 166 167 struct bfi_msg_s { 168 struct bfi_mhdr_s mhdr; 169 u32 pl[BFI_LMSG_PL_WSZ]; 170 }; 171 172 /* 173 * Mailbox message structure 174 */ 175 #define BFI_MBMSG_SZ 7 176 struct bfi_mbmsg_s { 177 struct bfi_mhdr_s mh; 178 u32 pl[BFI_MBMSG_SZ]; 179 }; 180 181 /* 182 * Supported PCI function class codes (personality) 183 */ 184 enum bfi_pcifn_class { 185 BFI_PCIFN_CLASS_FC = 0x0c04, 186 BFI_PCIFN_CLASS_ETH = 0x0200, 187 }; 188 189 /* 190 * Message Classes 191 */ 192 enum bfi_mclass { 193 BFI_MC_IOC = 1, /* IO Controller (IOC) */ 194 BFI_MC_DIAG = 2, /* Diagnostic Msgs */ 195 BFI_MC_FLASH = 3, /* Flash message class */ 196 BFI_MC_CEE = 4, /* CEE */ 197 BFI_MC_FCPORT = 5, /* FC port */ 198 BFI_MC_IOCFC = 6, /* FC - IO Controller (IOC) */ 199 BFI_MC_ABLK = 7, /* ASIC block configuration */ 200 BFI_MC_UF = 8, /* Unsolicited frame receive */ 201 BFI_MC_FCXP = 9, /* FC Transport */ 202 BFI_MC_LPS = 10, /* lport fc login services */ 203 BFI_MC_RPORT = 11, /* Remote port */ 204 BFI_MC_ITN = 12, /* I-T nexus (Initiator mode) */ 205 BFI_MC_IOIM_READ = 13, /* read IO (Initiator mode) */ 206 BFI_MC_IOIM_WRITE = 14, /* write IO (Initiator mode) */ 207 BFI_MC_IOIM_IO = 15, /* IO (Initiator mode) */ 208 BFI_MC_IOIM = 16, /* IO (Initiator mode) */ 209 BFI_MC_IOIM_IOCOM = 17, /* good IO completion */ 210 BFI_MC_TSKIM = 18, /* Initiator Task management */ 211 BFI_MC_PORT = 21, /* Physical port */ 212 BFI_MC_SFP = 22, /* SFP module */ 213 BFI_MC_PHY = 25, /* External PHY message class */ 214 BFI_MC_FRU = 34, 215 BFI_MC_MAX = 35 216 }; 217 218 #define BFI_IOC_MAX_CQS 4 219 #define BFI_IOC_MAX_CQS_ASIC 8 220 #define BFI_IOC_MSGLEN_MAX 32 /* 32 bytes */ 221 222 /* 223 *---------------------------------------------------------------------- 224 * IOC 225 *---------------------------------------------------------------------- 226 */ 227 228 /* 229 * Different asic generations 230 */ 231 enum bfi_asic_gen { 232 BFI_ASIC_GEN_CB = 1, /* crossbow 8G FC */ 233 BFI_ASIC_GEN_CT = 2, /* catapult 8G FC or 10G CNA */ 234 BFI_ASIC_GEN_CT2 = 3, /* catapult-2 16G FC or 10G CNA */ 235 }; 236 237 enum bfi_asic_mode { 238 BFI_ASIC_MODE_FC = 1, /* FC upto 8G speed */ 239 BFI_ASIC_MODE_FC16 = 2, /* FC upto 16G speed */ 240 BFI_ASIC_MODE_ETH = 3, /* Ethernet ports */ 241 BFI_ASIC_MODE_COMBO = 4, /* FC 16G and Ethernet 10G port */ 242 }; 243 244 enum bfi_ioc_h2i_msgs { 245 BFI_IOC_H2I_ENABLE_REQ = 1, 246 BFI_IOC_H2I_DISABLE_REQ = 2, 247 BFI_IOC_H2I_GETATTR_REQ = 3, 248 BFI_IOC_H2I_DBG_SYNC = 4, 249 BFI_IOC_H2I_DBG_DUMP = 5, 250 }; 251 252 enum bfi_ioc_i2h_msgs { 253 BFI_IOC_I2H_ENABLE_REPLY = BFA_I2HM(1), 254 BFI_IOC_I2H_DISABLE_REPLY = BFA_I2HM(2), 255 BFI_IOC_I2H_GETATTR_REPLY = BFA_I2HM(3), 256 BFI_IOC_I2H_HBEAT = BFA_I2HM(4), 257 BFI_IOC_I2H_ACQ_ADDR_REPLY = BFA_I2HM(5), 258 }; 259 260 /* 261 * BFI_IOC_H2I_GETATTR_REQ message 262 */ 263 struct bfi_ioc_getattr_req_s { 264 struct bfi_mhdr_s mh; 265 union bfi_addr_u attr_addr; 266 }; 267 268 #define BFI_IOC_ATTR_UUID_SZ 16 269 struct bfi_ioc_attr_s { 270 wwn_t mfg_pwwn; /* Mfg port wwn */ 271 wwn_t mfg_nwwn; /* Mfg node wwn */ 272 mac_t mfg_mac; /* Mfg mac */ 273 u8 port_mode; /* bfi_port_mode */ 274 u8 rsvd_a; 275 wwn_t pwwn; 276 wwn_t nwwn; 277 mac_t mac; /* PBC or Mfg mac */ 278 u16 rsvd_b; 279 mac_t fcoe_mac; 280 u16 rsvd_c; 281 char brcd_serialnum[STRSZ(BFA_MFG_SERIALNUM_SIZE)]; 282 u8 pcie_gen; 283 u8 pcie_lanes_orig; 284 u8 pcie_lanes; 285 u8 rx_bbcredit; /* receive buffer credits */ 286 u32 adapter_prop; /* adapter properties */ 287 u16 maxfrsize; /* max receive frame size */ 288 char asic_rev; 289 u8 rsvd_d; 290 char fw_version[BFA_VERSION_LEN]; 291 char optrom_version[BFA_VERSION_LEN]; 292 struct bfa_mfg_vpd_s vpd; 293 u32 card_type; /* card type */ 294 u8 mfg_day; /* manufacturing day */ 295 u8 mfg_month; /* manufacturing month */ 296 u16 mfg_year; /* manufacturing year */ 297 u8 uuid[BFI_IOC_ATTR_UUID_SZ]; /*!< chinook uuid */ 298 }; 299 300 /* 301 * BFI_IOC_I2H_GETATTR_REPLY message 302 */ 303 struct bfi_ioc_getattr_reply_s { 304 struct bfi_mhdr_s mh; /* Common msg header */ 305 u8 status; /* cfg reply status */ 306 u8 rsvd[3]; 307 }; 308 309 /* 310 * Firmware memory page offsets 311 */ 312 #define BFI_IOC_SMEM_PG0_CB (0x40) 313 #define BFI_IOC_SMEM_PG0_CT (0x180) 314 315 /* 316 * Firmware statistic offset 317 */ 318 #define BFI_IOC_FWSTATS_OFF (0x6B40) 319 #define BFI_IOC_FWSTATS_SZ (4096) 320 321 /* 322 * Firmware trace offset 323 */ 324 #define BFI_IOC_TRC_OFF (0x4b00) 325 #define BFI_IOC_TRC_ENTS 256 326 327 #define BFI_IOC_FW_SIGNATURE (0xbfadbfad) 328 #define BFA_IOC_FW_INV_SIGN (0xdeaddead) 329 #define BFI_IOC_MD5SUM_SZ 4 330 331 struct bfi_ioc_fwver_s { 332 #ifdef __BIG_ENDIAN 333 uint8_t patch; 334 uint8_t maint; 335 uint8_t minor; 336 uint8_t major; 337 uint8_t rsvd[2]; 338 uint8_t build; 339 uint8_t phase; 340 #else 341 uint8_t major; 342 uint8_t minor; 343 uint8_t maint; 344 uint8_t patch; 345 uint8_t phase; 346 uint8_t build; 347 uint8_t rsvd[2]; 348 #endif 349 }; 350 351 struct bfi_ioc_image_hdr_s { 352 u32 signature; /* constant signature */ 353 u8 asic_gen; /* asic generation */ 354 u8 asic_mode; 355 u8 port0_mode; /* device mode for port 0 */ 356 u8 port1_mode; /* device mode for port 1 */ 357 u32 exec; /* exec vector */ 358 u32 bootenv; /* fimware boot env */ 359 u32 rsvd_b[2]; 360 struct bfi_ioc_fwver_s fwver; 361 u32 md5sum[BFI_IOC_MD5SUM_SZ]; 362 }; 363 364 enum bfi_ioc_img_ver_cmp_e { 365 BFI_IOC_IMG_VER_INCOMP, 366 BFI_IOC_IMG_VER_OLD, 367 BFI_IOC_IMG_VER_SAME, 368 BFI_IOC_IMG_VER_BETTER 369 }; 370 371 #define BFI_FWBOOT_DEVMODE_OFF 4 372 #define BFI_FWBOOT_TYPE_OFF 8 373 #define BFI_FWBOOT_ENV_OFF 12 374 #define BFI_FWBOOT_DEVMODE(__asic_gen, __asic_mode, __p0_mode, __p1_mode) \ 375 (((u32)(__asic_gen)) << 24 | \ 376 ((u32)(__asic_mode)) << 16 | \ 377 ((u32)(__p0_mode)) << 8 | \ 378 ((u32)(__p1_mode))) 379 380 enum bfi_fwboot_type { 381 BFI_FWBOOT_TYPE_NORMAL = 0, 382 BFI_FWBOOT_TYPE_FLASH = 1, 383 BFI_FWBOOT_TYPE_MEMTEST = 2, 384 }; 385 386 #define BFI_FWBOOT_TYPE_NORMAL 0 387 #define BFI_FWBOOT_TYPE_MEMTEST 2 388 #define BFI_FWBOOT_ENV_OS 0 389 390 enum bfi_port_mode { 391 BFI_PORT_MODE_FC = 1, 392 BFI_PORT_MODE_ETH = 2, 393 }; 394 395 struct bfi_ioc_hbeat_s { 396 struct bfi_mhdr_s mh; /* common msg header */ 397 u32 hb_count; /* current heart beat count */ 398 }; 399 400 /* 401 * IOC hardware/firmware state 402 */ 403 enum bfi_ioc_state { 404 BFI_IOC_UNINIT = 0, /* not initialized */ 405 BFI_IOC_INITING = 1, /* h/w is being initialized */ 406 BFI_IOC_HWINIT = 2, /* h/w is initialized */ 407 BFI_IOC_CFG = 3, /* IOC configuration in progress */ 408 BFI_IOC_OP = 4, /* IOC is operational */ 409 BFI_IOC_DISABLING = 5, /* IOC is being disabled */ 410 BFI_IOC_DISABLED = 6, /* IOC is disabled */ 411 BFI_IOC_CFG_DISABLED = 7, /* IOC is being disabled;transient */ 412 BFI_IOC_FAIL = 8, /* IOC heart-beat failure */ 413 BFI_IOC_MEMTEST = 9, /* IOC is doing memtest */ 414 }; 415 416 #define BFA_IOC_CB_JOIN_SH 16 417 #define BFA_IOC_CB_FWSTATE_MASK 0x0000ffff 418 #define BFA_IOC_CB_JOIN_MASK 0xffff0000 419 420 #define BFI_IOC_ENDIAN_SIG 0x12345678 421 422 enum { 423 BFI_ADAPTER_TYPE_FC = 0x01, /* FC adapters */ 424 BFI_ADAPTER_TYPE_MK = 0x0f0000, /* adapter type mask */ 425 BFI_ADAPTER_TYPE_SH = 16, /* adapter type shift */ 426 BFI_ADAPTER_NPORTS_MK = 0xff00, /* number of ports mask */ 427 BFI_ADAPTER_NPORTS_SH = 8, /* number of ports shift */ 428 BFI_ADAPTER_SPEED_MK = 0xff, /* adapter speed mask */ 429 BFI_ADAPTER_SPEED_SH = 0, /* adapter speed shift */ 430 BFI_ADAPTER_PROTO = 0x100000, /* prototype adapaters */ 431 BFI_ADAPTER_TTV = 0x200000, /* TTV debug capable */ 432 BFI_ADAPTER_UNSUPP = 0x400000, /* unknown adapter type */ 433 }; 434 435 #define BFI_ADAPTER_GETP(__prop, __adap_prop) \ 436 (((__adap_prop) & BFI_ADAPTER_ ## __prop ## _MK) >> \ 437 BFI_ADAPTER_ ## __prop ## _SH) 438 #define BFI_ADAPTER_SETP(__prop, __val) \ 439 ((__val) << BFI_ADAPTER_ ## __prop ## _SH) 440 #define BFI_ADAPTER_IS_PROTO(__adap_type) \ 441 ((__adap_type) & BFI_ADAPTER_PROTO) 442 #define BFI_ADAPTER_IS_TTV(__adap_type) \ 443 ((__adap_type) & BFI_ADAPTER_TTV) 444 #define BFI_ADAPTER_IS_UNSUPP(__adap_type) \ 445 ((__adap_type) & BFI_ADAPTER_UNSUPP) 446 #define BFI_ADAPTER_IS_SPECIAL(__adap_type) \ 447 ((__adap_type) & (BFI_ADAPTER_TTV | BFI_ADAPTER_PROTO | \ 448 BFI_ADAPTER_UNSUPP)) 449 450 /* 451 * BFI_IOC_H2I_ENABLE_REQ & BFI_IOC_H2I_DISABLE_REQ messages 452 */ 453 struct bfi_ioc_ctrl_req_s { 454 struct bfi_mhdr_s mh; 455 u16 clscode; 456 u16 rsvd; 457 u32 tv_sec; 458 }; 459 #define bfi_ioc_enable_req_t struct bfi_ioc_ctrl_req_s; 460 #define bfi_ioc_disable_req_t struct bfi_ioc_ctrl_req_s; 461 462 /* 463 * BFI_IOC_I2H_ENABLE_REPLY & BFI_IOC_I2H_DISABLE_REPLY messages 464 */ 465 struct bfi_ioc_ctrl_reply_s { 466 struct bfi_mhdr_s mh; /* Common msg header */ 467 u8 status; /* enable/disable status */ 468 u8 port_mode; /* bfa_mode_s */ 469 u8 cap_bm; /* capability bit mask */ 470 u8 rsvd; 471 }; 472 #define bfi_ioc_enable_reply_t struct bfi_ioc_ctrl_reply_s; 473 #define bfi_ioc_disable_reply_t struct bfi_ioc_ctrl_reply_s; 474 475 #define BFI_IOC_MSGSZ 8 476 /* 477 * H2I Messages 478 */ 479 union bfi_ioc_h2i_msg_u { 480 struct bfi_mhdr_s mh; 481 struct bfi_ioc_ctrl_req_s enable_req; 482 struct bfi_ioc_ctrl_req_s disable_req; 483 struct bfi_ioc_getattr_req_s getattr_req; 484 u32 mboxmsg[BFI_IOC_MSGSZ]; 485 }; 486 487 /* 488 * I2H Messages 489 */ 490 union bfi_ioc_i2h_msg_u { 491 struct bfi_mhdr_s mh; 492 struct bfi_ioc_ctrl_reply_s fw_event; 493 u32 mboxmsg[BFI_IOC_MSGSZ]; 494 }; 495 496 497 /* 498 *---------------------------------------------------------------------- 499 * PBC 500 *---------------------------------------------------------------------- 501 */ 502 503 #define BFI_PBC_MAX_BLUNS 8 504 #define BFI_PBC_MAX_VPORTS 16 505 #define BFI_PBC_PORT_DISABLED 2 506 507 /* 508 * PBC boot lun configuration 509 */ 510 struct bfi_pbc_blun_s { 511 wwn_t tgt_pwwn; 512 struct scsi_lun tgt_lun; 513 }; 514 515 /* 516 * PBC virtual port configuration 517 */ 518 struct bfi_pbc_vport_s { 519 wwn_t vp_pwwn; 520 wwn_t vp_nwwn; 521 }; 522 523 /* 524 * BFI pre-boot configuration information 525 */ 526 struct bfi_pbc_s { 527 u8 port_enabled; 528 u8 boot_enabled; 529 u8 nbluns; 530 u8 nvports; 531 u8 port_speed; 532 u8 rsvd_a; 533 u16 hss; 534 wwn_t pbc_pwwn; 535 wwn_t pbc_nwwn; 536 struct bfi_pbc_blun_s blun[BFI_PBC_MAX_BLUNS]; 537 struct bfi_pbc_vport_s vport[BFI_PBC_MAX_VPORTS]; 538 }; 539 540 /* 541 *---------------------------------------------------------------------- 542 * MSGQ 543 *---------------------------------------------------------------------- 544 */ 545 #define BFI_MSGQ_FULL(_q) (((_q->pi + 1) % _q->q_depth) == _q->ci) 546 #define BFI_MSGQ_EMPTY(_q) (_q->pi == _q->ci) 547 #define BFI_MSGQ_UPDATE_CI(_q) (_q->ci = (_q->ci + 1) % _q->q_depth) 548 #define BFI_MSGQ_UPDATE_PI(_q) (_q->pi = (_q->pi + 1) % _q->q_depth) 549 550 /* q_depth must be power of 2 */ 551 #define BFI_MSGQ_FREE_CNT(_q) ((_q->ci - _q->pi - 1) & (_q->q_depth - 1)) 552 553 enum bfi_msgq_h2i_msgs_e { 554 BFI_MSGQ_H2I_INIT_REQ = 1, 555 BFI_MSGQ_H2I_DOORBELL = 2, 556 BFI_MSGQ_H2I_SHUTDOWN = 3, 557 }; 558 559 enum bfi_msgq_i2h_msgs_e { 560 BFI_MSGQ_I2H_INIT_RSP = 1, 561 BFI_MSGQ_I2H_DOORBELL = 2, 562 }; 563 564 565 /* Messages(commands/responsed/AENS will have the following header */ 566 struct bfi_msgq_mhdr_s { 567 u8 msg_class; 568 u8 msg_id; 569 u16 msg_token; 570 u16 num_entries; 571 u8 enet_id; 572 u8 rsvd[1]; 573 }; 574 575 #define bfi_msgq_mhdr_set(_mh, _mc, _mid, _tok, _enet_id) do { \ 576 (_mh).msg_class = (_mc); \ 577 (_mh).msg_id = (_mid); \ 578 (_mh).msg_token = (_tok); \ 579 (_mh).enet_id = (_enet_id); \ 580 } while (0) 581 582 /* 583 * Mailbox for messaging interface 584 * 585 */ 586 #define BFI_MSGQ_CMD_ENTRY_SIZE (64) /* TBD */ 587 #define BFI_MSGQ_RSP_ENTRY_SIZE (64) /* TBD */ 588 #define BFI_MSGQ_MSG_SIZE_MAX (2048) /* TBD */ 589 590 struct bfi_msgq_s { 591 union bfi_addr_u addr; 592 u16 q_depth; /* Total num of entries in the queue */ 593 u8 rsvd[2]; 594 }; 595 596 /* BFI_ENET_MSGQ_CFG_REQ TBD init or cfg? */ 597 struct bfi_msgq_cfg_req_s { 598 struct bfi_mhdr_s mh; 599 struct bfi_msgq_s cmdq; 600 struct bfi_msgq_s rspq; 601 }; 602 603 /* BFI_ENET_MSGQ_CFG_RSP */ 604 struct bfi_msgq_cfg_rsp_s { 605 struct bfi_mhdr_s mh; 606 u8 cmd_status; 607 u8 rsvd[3]; 608 }; 609 610 611 /* BFI_MSGQ_H2I_DOORBELL */ 612 struct bfi_msgq_h2i_db_s { 613 struct bfi_mhdr_s mh; 614 u16 cmdq_pi; 615 u16 rspq_ci; 616 }; 617 618 /* BFI_MSGQ_I2H_DOORBELL */ 619 struct bfi_msgq_i2h_db_s { 620 struct bfi_mhdr_s mh; 621 u16 rspq_pi; 622 u16 cmdq_ci; 623 }; 624 625 #pragma pack() 626 627 /* BFI port specific */ 628 #pragma pack(1) 629 630 enum bfi_port_h2i { 631 BFI_PORT_H2I_ENABLE_REQ = (1), 632 BFI_PORT_H2I_DISABLE_REQ = (2), 633 BFI_PORT_H2I_GET_STATS_REQ = (3), 634 BFI_PORT_H2I_CLEAR_STATS_REQ = (4), 635 }; 636 637 enum bfi_port_i2h { 638 BFI_PORT_I2H_ENABLE_RSP = BFA_I2HM(1), 639 BFI_PORT_I2H_DISABLE_RSP = BFA_I2HM(2), 640 BFI_PORT_I2H_GET_STATS_RSP = BFA_I2HM(3), 641 BFI_PORT_I2H_CLEAR_STATS_RSP = BFA_I2HM(4), 642 }; 643 644 /* 645 * Generic REQ type 646 */ 647 struct bfi_port_generic_req_s { 648 struct bfi_mhdr_s mh; /* msg header */ 649 u32 msgtag; /* msgtag for reply */ 650 u32 rsvd; 651 }; 652 653 /* 654 * Generic RSP type 655 */ 656 struct bfi_port_generic_rsp_s { 657 struct bfi_mhdr_s mh; /* common msg header */ 658 u8 status; /* port enable status */ 659 u8 rsvd[3]; 660 u32 msgtag; /* msgtag for reply */ 661 }; 662 663 /* 664 * BFI_PORT_H2I_GET_STATS_REQ 665 */ 666 struct bfi_port_get_stats_req_s { 667 struct bfi_mhdr_s mh; /* common msg header */ 668 union bfi_addr_u dma_addr; 669 }; 670 671 union bfi_port_h2i_msg_u { 672 struct bfi_mhdr_s mh; 673 struct bfi_port_generic_req_s enable_req; 674 struct bfi_port_generic_req_s disable_req; 675 struct bfi_port_get_stats_req_s getstats_req; 676 struct bfi_port_generic_req_s clearstats_req; 677 }; 678 679 union bfi_port_i2h_msg_u { 680 struct bfi_mhdr_s mh; 681 struct bfi_port_generic_rsp_s enable_rsp; 682 struct bfi_port_generic_rsp_s disable_rsp; 683 struct bfi_port_generic_rsp_s getstats_rsp; 684 struct bfi_port_generic_rsp_s clearstats_rsp; 685 }; 686 687 /* 688 *---------------------------------------------------------------------- 689 * ABLK 690 *---------------------------------------------------------------------- 691 */ 692 enum bfi_ablk_h2i_msgs_e { 693 BFI_ABLK_H2I_QUERY = 1, 694 BFI_ABLK_H2I_ADPT_CONFIG = 2, 695 BFI_ABLK_H2I_PORT_CONFIG = 3, 696 BFI_ABLK_H2I_PF_CREATE = 4, 697 BFI_ABLK_H2I_PF_DELETE = 5, 698 BFI_ABLK_H2I_PF_UPDATE = 6, 699 BFI_ABLK_H2I_OPTROM_ENABLE = 7, 700 BFI_ABLK_H2I_OPTROM_DISABLE = 8, 701 }; 702 703 enum bfi_ablk_i2h_msgs_e { 704 BFI_ABLK_I2H_QUERY = BFA_I2HM(BFI_ABLK_H2I_QUERY), 705 BFI_ABLK_I2H_ADPT_CONFIG = BFA_I2HM(BFI_ABLK_H2I_ADPT_CONFIG), 706 BFI_ABLK_I2H_PORT_CONFIG = BFA_I2HM(BFI_ABLK_H2I_PORT_CONFIG), 707 BFI_ABLK_I2H_PF_CREATE = BFA_I2HM(BFI_ABLK_H2I_PF_CREATE), 708 BFI_ABLK_I2H_PF_DELETE = BFA_I2HM(BFI_ABLK_H2I_PF_DELETE), 709 BFI_ABLK_I2H_PF_UPDATE = BFA_I2HM(BFI_ABLK_H2I_PF_UPDATE), 710 BFI_ABLK_I2H_OPTROM_ENABLE = BFA_I2HM(BFI_ABLK_H2I_OPTROM_ENABLE), 711 BFI_ABLK_I2H_OPTROM_DISABLE = BFA_I2HM(BFI_ABLK_H2I_OPTROM_DISABLE), 712 }; 713 714 /* BFI_ABLK_H2I_QUERY */ 715 struct bfi_ablk_h2i_query_s { 716 struct bfi_mhdr_s mh; 717 union bfi_addr_u addr; 718 }; 719 720 /* BFI_ABL_H2I_ADPT_CONFIG, BFI_ABLK_H2I_PORT_CONFIG */ 721 struct bfi_ablk_h2i_cfg_req_s { 722 struct bfi_mhdr_s mh; 723 u8 mode; 724 u8 port; 725 u8 max_pf; 726 u8 max_vf; 727 }; 728 729 /* 730 * BFI_ABLK_H2I_PF_CREATE, BFI_ABLK_H2I_PF_DELETE, 731 */ 732 struct bfi_ablk_h2i_pf_req_s { 733 struct bfi_mhdr_s mh; 734 u8 pcifn; 735 u8 port; 736 u16 pers; 737 u16 bw_min; /* percent BW @ max speed */ 738 u16 bw_max; /* percent BW @ max speed */ 739 }; 740 741 /* BFI_ABLK_H2I_OPTROM_ENABLE, BFI_ABLK_H2I_OPTROM_DISABLE */ 742 struct bfi_ablk_h2i_optrom_s { 743 struct bfi_mhdr_s mh; 744 }; 745 746 /* 747 * BFI_ABLK_I2H_QUERY 748 * BFI_ABLK_I2H_PORT_CONFIG 749 * BFI_ABLK_I2H_PF_CREATE 750 * BFI_ABLK_I2H_PF_DELETE 751 * BFI_ABLK_I2H_PF_UPDATE 752 * BFI_ABLK_I2H_OPTROM_ENABLE 753 * BFI_ABLK_I2H_OPTROM_DISABLE 754 */ 755 struct bfi_ablk_i2h_rsp_s { 756 struct bfi_mhdr_s mh; 757 u8 status; 758 u8 pcifn; 759 u8 port_mode; 760 }; 761 762 763 /* 764 * CEE module specific messages 765 */ 766 767 /* Mailbox commands from host to firmware */ 768 enum bfi_cee_h2i_msgs_e { 769 BFI_CEE_H2I_GET_CFG_REQ = 1, 770 BFI_CEE_H2I_RESET_STATS = 2, 771 BFI_CEE_H2I_GET_STATS_REQ = 3, 772 }; 773 774 enum bfi_cee_i2h_msgs_e { 775 BFI_CEE_I2H_GET_CFG_RSP = BFA_I2HM(1), 776 BFI_CEE_I2H_RESET_STATS_RSP = BFA_I2HM(2), 777 BFI_CEE_I2H_GET_STATS_RSP = BFA_I2HM(3), 778 }; 779 780 /* 781 * H2I command structure for resetting the stats 782 */ 783 struct bfi_cee_reset_stats_s { 784 struct bfi_mhdr_s mh; 785 }; 786 787 /* 788 * Get configuration command from host 789 */ 790 struct bfi_cee_get_req_s { 791 struct bfi_mhdr_s mh; 792 union bfi_addr_u dma_addr; 793 }; 794 795 /* 796 * Reply message from firmware 797 */ 798 struct bfi_cee_get_rsp_s { 799 struct bfi_mhdr_s mh; 800 u8 cmd_status; 801 u8 rsvd[3]; 802 }; 803 804 /* 805 * Reply message from firmware 806 */ 807 struct bfi_cee_stats_rsp_s { 808 struct bfi_mhdr_s mh; 809 u8 cmd_status; 810 u8 rsvd[3]; 811 }; 812 813 /* Mailbox message structures from firmware to host */ 814 union bfi_cee_i2h_msg_u { 815 struct bfi_mhdr_s mh; 816 struct bfi_cee_get_rsp_s get_rsp; 817 struct bfi_cee_stats_rsp_s stats_rsp; 818 }; 819 820 /* 821 * SFP related 822 */ 823 824 enum bfi_sfp_h2i_e { 825 BFI_SFP_H2I_SHOW = 1, 826 BFI_SFP_H2I_SCN = 2, 827 }; 828 829 enum bfi_sfp_i2h_e { 830 BFI_SFP_I2H_SHOW = BFA_I2HM(BFI_SFP_H2I_SHOW), 831 BFI_SFP_I2H_SCN = BFA_I2HM(BFI_SFP_H2I_SCN), 832 }; 833 834 /* 835 * SFP state change notification 836 */ 837 struct bfi_sfp_scn_s { 838 struct bfi_mhdr_s mhr; /* host msg header */ 839 u8 event; 840 u8 sfpid; 841 u8 pomlvl; /* pom level: normal/warning/alarm */ 842 u8 is_elb; /* e-loopback */ 843 }; 844 845 /* 846 * SFP state 847 */ 848 enum bfa_sfp_stat_e { 849 BFA_SFP_STATE_INIT = 0, /* SFP state is uninit */ 850 BFA_SFP_STATE_REMOVED = 1, /* SFP is removed */ 851 BFA_SFP_STATE_INSERTED = 2, /* SFP is inserted */ 852 BFA_SFP_STATE_VALID = 3, /* SFP is valid */ 853 BFA_SFP_STATE_UNSUPPORT = 4, /* SFP is unsupport */ 854 BFA_SFP_STATE_FAILED = 5, /* SFP i2c read fail */ 855 }; 856 857 /* 858 * SFP memory access type 859 */ 860 enum bfi_sfp_mem_e { 861 BFI_SFP_MEM_ALL = 0x1, /* access all data field */ 862 BFI_SFP_MEM_DIAGEXT = 0x2, /* access diag ext data field only */ 863 }; 864 865 struct bfi_sfp_req_s { 866 struct bfi_mhdr_s mh; 867 u8 memtype; 868 u8 rsvd[3]; 869 struct bfi_alen_s alen; 870 }; 871 872 struct bfi_sfp_rsp_s { 873 struct bfi_mhdr_s mh; 874 u8 status; 875 u8 state; 876 u8 rsvd[2]; 877 }; 878 879 /* 880 * FLASH module specific 881 */ 882 enum bfi_flash_h2i_msgs { 883 BFI_FLASH_H2I_QUERY_REQ = 1, 884 BFI_FLASH_H2I_ERASE_REQ = 2, 885 BFI_FLASH_H2I_WRITE_REQ = 3, 886 BFI_FLASH_H2I_READ_REQ = 4, 887 BFI_FLASH_H2I_BOOT_VER_REQ = 5, 888 }; 889 890 enum bfi_flash_i2h_msgs { 891 BFI_FLASH_I2H_QUERY_RSP = BFA_I2HM(1), 892 BFI_FLASH_I2H_ERASE_RSP = BFA_I2HM(2), 893 BFI_FLASH_I2H_WRITE_RSP = BFA_I2HM(3), 894 BFI_FLASH_I2H_READ_RSP = BFA_I2HM(4), 895 BFI_FLASH_I2H_BOOT_VER_RSP = BFA_I2HM(5), 896 BFI_FLASH_I2H_EVENT = BFA_I2HM(127), 897 }; 898 899 /* 900 * Flash query request 901 */ 902 struct bfi_flash_query_req_s { 903 struct bfi_mhdr_s mh; /* Common msg header */ 904 struct bfi_alen_s alen; 905 }; 906 907 /* 908 * Flash erase request 909 */ 910 struct bfi_flash_erase_req_s { 911 struct bfi_mhdr_s mh; /* Common msg header */ 912 u32 type; /* partition type */ 913 u8 instance; /* partition instance */ 914 u8 rsv[3]; 915 }; 916 917 /* 918 * Flash write request 919 */ 920 struct bfi_flash_write_req_s { 921 struct bfi_mhdr_s mh; /* Common msg header */ 922 struct bfi_alen_s alen; 923 u32 type; /* partition type */ 924 u8 instance; /* partition instance */ 925 u8 last; 926 u8 rsv[2]; 927 u32 offset; 928 u32 length; 929 }; 930 931 /* 932 * Flash read request 933 */ 934 struct bfi_flash_read_req_s { 935 struct bfi_mhdr_s mh; /* Common msg header */ 936 u32 type; /* partition type */ 937 u8 instance; /* partition instance */ 938 u8 rsv[3]; 939 u32 offset; 940 u32 length; 941 struct bfi_alen_s alen; 942 }; 943 944 /* 945 * Flash query response 946 */ 947 struct bfi_flash_query_rsp_s { 948 struct bfi_mhdr_s mh; /* Common msg header */ 949 u32 status; 950 }; 951 952 /* 953 * Flash read response 954 */ 955 struct bfi_flash_read_rsp_s { 956 struct bfi_mhdr_s mh; /* Common msg header */ 957 u32 type; /* partition type */ 958 u8 instance; /* partition instance */ 959 u8 rsv[3]; 960 u32 status; 961 u32 length; 962 }; 963 964 /* 965 * Flash write response 966 */ 967 struct bfi_flash_write_rsp_s { 968 struct bfi_mhdr_s mh; /* Common msg header */ 969 u32 type; /* partition type */ 970 u8 instance; /* partition instance */ 971 u8 rsv[3]; 972 u32 status; 973 u32 length; 974 }; 975 976 /* 977 * Flash erase response 978 */ 979 struct bfi_flash_erase_rsp_s { 980 struct bfi_mhdr_s mh; /* Common msg header */ 981 u32 type; /* partition type */ 982 u8 instance; /* partition instance */ 983 u8 rsv[3]; 984 u32 status; 985 }; 986 987 /* 988 * Flash event notification 989 */ 990 struct bfi_flash_event_s { 991 struct bfi_mhdr_s mh; /* Common msg header */ 992 bfa_status_t status; 993 u32 param; 994 }; 995 996 /* 997 *---------------------------------------------------------------------- 998 * DIAG 999 *---------------------------------------------------------------------- 1000 */ 1001 enum bfi_diag_h2i { 1002 BFI_DIAG_H2I_PORTBEACON = 1, 1003 BFI_DIAG_H2I_LOOPBACK = 2, 1004 BFI_DIAG_H2I_FWPING = 3, 1005 BFI_DIAG_H2I_TEMPSENSOR = 4, 1006 BFI_DIAG_H2I_LEDTEST = 5, 1007 BFI_DIAG_H2I_QTEST = 6, 1008 BFI_DIAG_H2I_DPORT = 7, 1009 }; 1010 1011 enum bfi_diag_i2h { 1012 BFI_DIAG_I2H_PORTBEACON = BFA_I2HM(BFI_DIAG_H2I_PORTBEACON), 1013 BFI_DIAG_I2H_LOOPBACK = BFA_I2HM(BFI_DIAG_H2I_LOOPBACK), 1014 BFI_DIAG_I2H_FWPING = BFA_I2HM(BFI_DIAG_H2I_FWPING), 1015 BFI_DIAG_I2H_TEMPSENSOR = BFA_I2HM(BFI_DIAG_H2I_TEMPSENSOR), 1016 BFI_DIAG_I2H_LEDTEST = BFA_I2HM(BFI_DIAG_H2I_LEDTEST), 1017 BFI_DIAG_I2H_QTEST = BFA_I2HM(BFI_DIAG_H2I_QTEST), 1018 BFI_DIAG_I2H_DPORT = BFA_I2HM(BFI_DIAG_H2I_DPORT), 1019 BFI_DIAG_I2H_DPORT_SCN = BFA_I2HM(8), 1020 }; 1021 1022 #define BFI_DIAG_MAX_SGES 2 1023 #define BFI_DIAG_DMA_BUF_SZ (2 * 1024) 1024 #define BFI_BOOT_MEMTEST_RES_ADDR 0x900 1025 #define BFI_BOOT_MEMTEST_RES_SIG 0xA0A1A2A3 1026 1027 struct bfi_diag_lb_req_s { 1028 struct bfi_mhdr_s mh; 1029 u32 loopcnt; 1030 u32 pattern; 1031 u8 lb_mode; /*!< bfa_port_opmode_t */ 1032 u8 speed; /*!< bfa_port_speed_t */ 1033 u8 rsvd[2]; 1034 }; 1035 1036 struct bfi_diag_lb_rsp_s { 1037 struct bfi_mhdr_s mh; /* 4 bytes */ 1038 struct bfa_diag_loopback_result_s res; /* 16 bytes */ 1039 }; 1040 1041 struct bfi_diag_fwping_req_s { 1042 struct bfi_mhdr_s mh; /* 4 bytes */ 1043 struct bfi_alen_s alen; /* 12 bytes */ 1044 u32 data; /* user input data pattern */ 1045 u32 count; /* user input dma count */ 1046 u8 qtag; /* track CPE vc */ 1047 u8 rsv[3]; 1048 }; 1049 1050 struct bfi_diag_fwping_rsp_s { 1051 struct bfi_mhdr_s mh; /* 4 bytes */ 1052 u32 data; /* user input data pattern */ 1053 u8 qtag; /* track CPE vc */ 1054 u8 dma_status; /* dma status */ 1055 u8 rsv[2]; 1056 }; 1057 1058 /* 1059 * Temperature Sensor 1060 */ 1061 struct bfi_diag_ts_req_s { 1062 struct bfi_mhdr_s mh; /* 4 bytes */ 1063 u16 temp; /* 10-bit A/D value */ 1064 u16 brd_temp; /* 9-bit board temp */ 1065 u8 status; 1066 u8 ts_junc; /* show junction tempsensor */ 1067 u8 ts_brd; /* show board tempsensor */ 1068 u8 rsv; 1069 }; 1070 #define bfi_diag_ts_rsp_t struct bfi_diag_ts_req_s 1071 1072 struct bfi_diag_ledtest_req_s { 1073 struct bfi_mhdr_s mh; /* 4 bytes */ 1074 u8 cmd; 1075 u8 color; 1076 u8 portid; 1077 u8 led; /* bitmap of LEDs to be tested */ 1078 u16 freq; /* no. of blinks every 10 secs */ 1079 u8 rsv[2]; 1080 }; 1081 1082 /* notify host led operation is done */ 1083 struct bfi_diag_ledtest_rsp_s { 1084 struct bfi_mhdr_s mh; /* 4 bytes */ 1085 }; 1086 1087 struct bfi_diag_portbeacon_req_s { 1088 struct bfi_mhdr_s mh; /* 4 bytes */ 1089 u32 period; /* beaconing period */ 1090 u8 beacon; /* 1: beacon on */ 1091 u8 rsvd[3]; 1092 }; 1093 1094 /* notify host the beacon is off */ 1095 struct bfi_diag_portbeacon_rsp_s { 1096 struct bfi_mhdr_s mh; /* 4 bytes */ 1097 }; 1098 1099 struct bfi_diag_qtest_req_s { 1100 struct bfi_mhdr_s mh; /* 4 bytes */ 1101 u32 data[BFI_LMSG_PL_WSZ]; /* fill up tcm prefetch area */ 1102 }; 1103 #define bfi_diag_qtest_rsp_t struct bfi_diag_qtest_req_s 1104 1105 /* 1106 * D-port test 1107 */ 1108 enum bfi_dport_req { 1109 BFI_DPORT_DISABLE = 0, /* disable dport request */ 1110 BFI_DPORT_ENABLE = 1, /* enable dport request */ 1111 BFI_DPORT_START = 2, /* start dport request */ 1112 BFI_DPORT_SHOW = 3, /* show dport request */ 1113 BFI_DPORT_DYN_DISABLE = 4, /* disable dynamic dport request */ 1114 }; 1115 1116 enum bfi_dport_scn { 1117 BFI_DPORT_SCN_TESTSTART = 1, 1118 BFI_DPORT_SCN_TESTCOMP = 2, 1119 BFI_DPORT_SCN_SFP_REMOVED = 3, 1120 BFI_DPORT_SCN_DDPORT_ENABLE = 4, 1121 BFI_DPORT_SCN_DDPORT_DISABLE = 5, 1122 BFI_DPORT_SCN_FCPORT_DISABLE = 6, 1123 BFI_DPORT_SCN_SUBTESTSTART = 7, 1124 BFI_DPORT_SCN_TESTSKIP = 8, 1125 BFI_DPORT_SCN_DDPORT_DISABLED = 9, 1126 }; 1127 1128 struct bfi_diag_dport_req_s { 1129 struct bfi_mhdr_s mh; /* 4 bytes */ 1130 u8 req; /* request 1: enable 0: disable */ 1131 u8 rsvd[3]; 1132 u32 lpcnt; 1133 u32 payload; 1134 }; 1135 1136 struct bfi_diag_dport_rsp_s { 1137 struct bfi_mhdr_s mh; /* header 4 bytes */ 1138 bfa_status_t status; /* reply status */ 1139 wwn_t pwwn; /* switch port wwn. 8 bytes */ 1140 wwn_t nwwn; /* switch node wwn. 8 bytes */ 1141 }; 1142 1143 struct bfi_diag_dport_scn_teststart_s { 1144 wwn_t pwwn; /* switch port wwn. 8 bytes */ 1145 wwn_t nwwn; /* switch node wwn. 8 bytes */ 1146 u8 type; /* bfa_diag_dport_test_type_e */ 1147 u8 mode; /* bfa_diag_dport_test_opmode */ 1148 u8 rsvd[2]; 1149 u32 numfrm; /* from switch uint in 1M */ 1150 }; 1151 1152 struct bfi_diag_dport_scn_testcomp_s { 1153 u8 status; /* bfa_diag_dport_test_status_e */ 1154 u8 speed; /* bfa_port_speed_t */ 1155 u16 numbuffer; /* from switch */ 1156 u8 subtest_status[DPORT_TEST_MAX]; /* 4 bytes */ 1157 u32 latency; /* from switch */ 1158 u32 distance; /* from swtich unit in meters */ 1159 /* Buffers required to saturate the link */ 1160 u16 frm_sz; /* from switch for buf_reqd */ 1161 u8 rsvd[2]; 1162 }; 1163 1164 struct bfi_diag_dport_scn_s { /* max size == RDS_RMESZ */ 1165 struct bfi_mhdr_s mh; /* header 4 bytes */ 1166 u8 state; /* new state */ 1167 u8 rsvd[3]; 1168 union { 1169 struct bfi_diag_dport_scn_teststart_s teststart; 1170 struct bfi_diag_dport_scn_testcomp_s testcomp; 1171 } info; 1172 }; 1173 1174 union bfi_diag_dport_msg_u { 1175 struct bfi_diag_dport_req_s req; 1176 struct bfi_diag_dport_rsp_s rsp; 1177 struct bfi_diag_dport_scn_s scn; 1178 }; 1179 1180 /* 1181 * PHY module specific 1182 */ 1183 enum bfi_phy_h2i_msgs_e { 1184 BFI_PHY_H2I_QUERY_REQ = 1, 1185 BFI_PHY_H2I_STATS_REQ = 2, 1186 BFI_PHY_H2I_WRITE_REQ = 3, 1187 BFI_PHY_H2I_READ_REQ = 4, 1188 }; 1189 1190 enum bfi_phy_i2h_msgs_e { 1191 BFI_PHY_I2H_QUERY_RSP = BFA_I2HM(1), 1192 BFI_PHY_I2H_STATS_RSP = BFA_I2HM(2), 1193 BFI_PHY_I2H_WRITE_RSP = BFA_I2HM(3), 1194 BFI_PHY_I2H_READ_RSP = BFA_I2HM(4), 1195 }; 1196 1197 /* 1198 * External PHY query request 1199 */ 1200 struct bfi_phy_query_req_s { 1201 struct bfi_mhdr_s mh; /* Common msg header */ 1202 u8 instance; 1203 u8 rsv[3]; 1204 struct bfi_alen_s alen; 1205 }; 1206 1207 /* 1208 * External PHY stats request 1209 */ 1210 struct bfi_phy_stats_req_s { 1211 struct bfi_mhdr_s mh; /* Common msg header */ 1212 u8 instance; 1213 u8 rsv[3]; 1214 struct bfi_alen_s alen; 1215 }; 1216 1217 /* 1218 * External PHY write request 1219 */ 1220 struct bfi_phy_write_req_s { 1221 struct bfi_mhdr_s mh; /* Common msg header */ 1222 u8 instance; 1223 u8 last; 1224 u8 rsv[2]; 1225 u32 offset; 1226 u32 length; 1227 struct bfi_alen_s alen; 1228 }; 1229 1230 /* 1231 * External PHY read request 1232 */ 1233 struct bfi_phy_read_req_s { 1234 struct bfi_mhdr_s mh; /* Common msg header */ 1235 u8 instance; 1236 u8 rsv[3]; 1237 u32 offset; 1238 u32 length; 1239 struct bfi_alen_s alen; 1240 }; 1241 1242 /* 1243 * External PHY query response 1244 */ 1245 struct bfi_phy_query_rsp_s { 1246 struct bfi_mhdr_s mh; /* Common msg header */ 1247 u32 status; 1248 }; 1249 1250 /* 1251 * External PHY stats response 1252 */ 1253 struct bfi_phy_stats_rsp_s { 1254 struct bfi_mhdr_s mh; /* Common msg header */ 1255 u32 status; 1256 }; 1257 1258 /* 1259 * External PHY read response 1260 */ 1261 struct bfi_phy_read_rsp_s { 1262 struct bfi_mhdr_s mh; /* Common msg header */ 1263 u32 status; 1264 u32 length; 1265 }; 1266 1267 /* 1268 * External PHY write response 1269 */ 1270 struct bfi_phy_write_rsp_s { 1271 struct bfi_mhdr_s mh; /* Common msg header */ 1272 u32 status; 1273 u32 length; 1274 }; 1275 1276 enum bfi_fru_h2i_msgs { 1277 BFI_FRUVPD_H2I_WRITE_REQ = 1, 1278 BFI_FRUVPD_H2I_READ_REQ = 2, 1279 BFI_TFRU_H2I_WRITE_REQ = 3, 1280 BFI_TFRU_H2I_READ_REQ = 4, 1281 }; 1282 1283 enum bfi_fru_i2h_msgs { 1284 BFI_FRUVPD_I2H_WRITE_RSP = BFA_I2HM(1), 1285 BFI_FRUVPD_I2H_READ_RSP = BFA_I2HM(2), 1286 BFI_TFRU_I2H_WRITE_RSP = BFA_I2HM(3), 1287 BFI_TFRU_I2H_READ_RSP = BFA_I2HM(4), 1288 }; 1289 1290 /* 1291 * FRU write request 1292 */ 1293 struct bfi_fru_write_req_s { 1294 struct bfi_mhdr_s mh; /* Common msg header */ 1295 u8 last; 1296 u8 rsv_1[3]; 1297 u8 trfr_cmpl; 1298 u8 rsv_2[3]; 1299 u32 offset; 1300 u32 length; 1301 struct bfi_alen_s alen; 1302 }; 1303 1304 /* 1305 * FRU read request 1306 */ 1307 struct bfi_fru_read_req_s { 1308 struct bfi_mhdr_s mh; /* Common msg header */ 1309 u32 offset; 1310 u32 length; 1311 struct bfi_alen_s alen; 1312 }; 1313 1314 /* 1315 * FRU response 1316 */ 1317 struct bfi_fru_rsp_s { 1318 struct bfi_mhdr_s mh; /* Common msg header */ 1319 u32 status; 1320 u32 length; 1321 }; 1322 #pragma pack() 1323 1324 #endif /* __BFI_H__ */ 1325