1 /* 2 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc. 3 * All rights reserved 4 * www.brocade.com 5 * 6 * Linux driver for Brocade Fibre Channel Host Bus Adapter. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License (GPL) Version 2 as 10 * published by the Free Software Foundation 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 */ 17 18 #include "bfad_drv.h" 19 #include "bfa_ioc.h" 20 #include "bfi_reg.h" 21 #include "bfa_defs.h" 22 23 BFA_TRC_FILE(CNA, IOC_CB); 24 25 #define bfa_ioc_cb_join_pos(__ioc) ((u32) (1 << BFA_IOC_CB_JOIN_SH)) 26 27 /* 28 * forward declarations 29 */ 30 static bfa_boolean_t bfa_ioc_cb_firmware_lock(struct bfa_ioc_s *ioc); 31 static void bfa_ioc_cb_firmware_unlock(struct bfa_ioc_s *ioc); 32 static void bfa_ioc_cb_reg_init(struct bfa_ioc_s *ioc); 33 static void bfa_ioc_cb_map_port(struct bfa_ioc_s *ioc); 34 static void bfa_ioc_cb_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix); 35 static void bfa_ioc_cb_notify_fail(struct bfa_ioc_s *ioc); 36 static void bfa_ioc_cb_ownership_reset(struct bfa_ioc_s *ioc); 37 static bfa_boolean_t bfa_ioc_cb_sync_start(struct bfa_ioc_s *ioc); 38 static void bfa_ioc_cb_sync_join(struct bfa_ioc_s *ioc); 39 static void bfa_ioc_cb_sync_leave(struct bfa_ioc_s *ioc); 40 static void bfa_ioc_cb_sync_ack(struct bfa_ioc_s *ioc); 41 static bfa_boolean_t bfa_ioc_cb_sync_complete(struct bfa_ioc_s *ioc); 42 static void bfa_ioc_cb_set_cur_ioc_fwstate( 43 struct bfa_ioc_s *ioc, enum bfi_ioc_state fwstate); 44 static enum bfi_ioc_state bfa_ioc_cb_get_cur_ioc_fwstate(struct bfa_ioc_s *ioc); 45 static void bfa_ioc_cb_set_alt_ioc_fwstate( 46 struct bfa_ioc_s *ioc, enum bfi_ioc_state fwstate); 47 static enum bfi_ioc_state bfa_ioc_cb_get_alt_ioc_fwstate(struct bfa_ioc_s *ioc); 48 49 static struct bfa_ioc_hwif_s hwif_cb; 50 51 /* 52 * Called from bfa_ioc_attach() to map asic specific calls. 53 */ 54 void 55 bfa_ioc_set_cb_hwif(struct bfa_ioc_s *ioc) 56 { 57 hwif_cb.ioc_pll_init = bfa_ioc_cb_pll_init; 58 hwif_cb.ioc_firmware_lock = bfa_ioc_cb_firmware_lock; 59 hwif_cb.ioc_firmware_unlock = bfa_ioc_cb_firmware_unlock; 60 hwif_cb.ioc_reg_init = bfa_ioc_cb_reg_init; 61 hwif_cb.ioc_map_port = bfa_ioc_cb_map_port; 62 hwif_cb.ioc_isr_mode_set = bfa_ioc_cb_isr_mode_set; 63 hwif_cb.ioc_notify_fail = bfa_ioc_cb_notify_fail; 64 hwif_cb.ioc_ownership_reset = bfa_ioc_cb_ownership_reset; 65 hwif_cb.ioc_sync_start = bfa_ioc_cb_sync_start; 66 hwif_cb.ioc_sync_join = bfa_ioc_cb_sync_join; 67 hwif_cb.ioc_sync_leave = bfa_ioc_cb_sync_leave; 68 hwif_cb.ioc_sync_ack = bfa_ioc_cb_sync_ack; 69 hwif_cb.ioc_sync_complete = bfa_ioc_cb_sync_complete; 70 hwif_cb.ioc_set_fwstate = bfa_ioc_cb_set_cur_ioc_fwstate; 71 hwif_cb.ioc_get_fwstate = bfa_ioc_cb_get_cur_ioc_fwstate; 72 hwif_cb.ioc_set_alt_fwstate = bfa_ioc_cb_set_alt_ioc_fwstate; 73 hwif_cb.ioc_get_alt_fwstate = bfa_ioc_cb_get_alt_ioc_fwstate; 74 75 ioc->ioc_hwif = &hwif_cb; 76 } 77 78 /* 79 * Return true if firmware of current driver matches the running firmware. 80 */ 81 static bfa_boolean_t 82 bfa_ioc_cb_firmware_lock(struct bfa_ioc_s *ioc) 83 { 84 return BFA_TRUE; 85 } 86 87 static void 88 bfa_ioc_cb_firmware_unlock(struct bfa_ioc_s *ioc) 89 { 90 } 91 92 /* 93 * Notify other functions on HB failure. 94 */ 95 static void 96 bfa_ioc_cb_notify_fail(struct bfa_ioc_s *ioc) 97 { 98 writel(~0U, ioc->ioc_regs.err_set); 99 readl(ioc->ioc_regs.err_set); 100 } 101 102 /* 103 * Host to LPU mailbox message addresses 104 */ 105 static struct { u32 hfn_mbox, lpu_mbox, hfn_pgn; } iocreg_fnreg[] = { 106 { HOSTFN0_LPU_MBOX0_0, LPU_HOSTFN0_MBOX0_0, HOST_PAGE_NUM_FN0 }, 107 { HOSTFN1_LPU_MBOX0_8, LPU_HOSTFN1_MBOX0_8, HOST_PAGE_NUM_FN1 } 108 }; 109 110 /* 111 * Host <-> LPU mailbox command/status registers 112 */ 113 static struct { u32 hfn, lpu; } iocreg_mbcmd[] = { 114 115 { HOSTFN0_LPU0_CMD_STAT, LPU0_HOSTFN0_CMD_STAT }, 116 { HOSTFN1_LPU1_CMD_STAT, LPU1_HOSTFN1_CMD_STAT } 117 }; 118 119 static void 120 bfa_ioc_cb_reg_init(struct bfa_ioc_s *ioc) 121 { 122 void __iomem *rb; 123 int pcifn = bfa_ioc_pcifn(ioc); 124 125 rb = bfa_ioc_bar0(ioc); 126 127 ioc->ioc_regs.hfn_mbox = rb + iocreg_fnreg[pcifn].hfn_mbox; 128 ioc->ioc_regs.lpu_mbox = rb + iocreg_fnreg[pcifn].lpu_mbox; 129 ioc->ioc_regs.host_page_num_fn = rb + iocreg_fnreg[pcifn].hfn_pgn; 130 131 if (ioc->port_id == 0) { 132 ioc->ioc_regs.heartbeat = rb + BFA_IOC0_HBEAT_REG; 133 ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC0_STATE_REG; 134 ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC1_STATE_REG; 135 } else { 136 ioc->ioc_regs.heartbeat = (rb + BFA_IOC1_HBEAT_REG); 137 ioc->ioc_regs.ioc_fwstate = (rb + BFA_IOC1_STATE_REG); 138 ioc->ioc_regs.alt_ioc_fwstate = (rb + BFA_IOC0_STATE_REG); 139 } 140 141 /* 142 * Host <-> LPU mailbox command/status registers 143 */ 144 ioc->ioc_regs.hfn_mbox_cmd = rb + iocreg_mbcmd[pcifn].hfn; 145 ioc->ioc_regs.lpu_mbox_cmd = rb + iocreg_mbcmd[pcifn].lpu; 146 147 /* 148 * PSS control registers 149 */ 150 ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG); 151 ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG); 152 ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_LCLK_CTL_REG); 153 ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_SCLK_CTL_REG); 154 155 /* 156 * IOC semaphore registers and serialization 157 */ 158 ioc->ioc_regs.ioc_sem_reg = (rb + HOST_SEM0_REG); 159 ioc->ioc_regs.ioc_init_sem_reg = (rb + HOST_SEM2_REG); 160 161 /* 162 * sram memory access 163 */ 164 ioc->ioc_regs.smem_page_start = (rb + PSS_SMEM_PAGE_START); 165 ioc->ioc_regs.smem_pg0 = BFI_IOC_SMEM_PG0_CB; 166 167 /* 168 * err set reg : for notification of hb failure 169 */ 170 ioc->ioc_regs.err_set = (rb + ERR_SET_REG); 171 } 172 173 /* 174 * Initialize IOC to port mapping. 175 */ 176 177 static void 178 bfa_ioc_cb_map_port(struct bfa_ioc_s *ioc) 179 { 180 /* 181 * For crossbow, port id is same as pci function. 182 */ 183 ioc->port_id = bfa_ioc_pcifn(ioc); 184 185 bfa_trc(ioc, ioc->port_id); 186 } 187 188 /* 189 * Set interrupt mode for a function: INTX or MSIX 190 */ 191 static void 192 bfa_ioc_cb_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix) 193 { 194 } 195 196 /* 197 * Synchronized IOC failure processing routines 198 */ 199 static bfa_boolean_t 200 bfa_ioc_cb_sync_start(struct bfa_ioc_s *ioc) 201 { 202 u32 ioc_fwstate = readl(ioc->ioc_regs.ioc_fwstate); 203 204 /** 205 * Driver load time. If the join bit is set, 206 * it is due to an unclean exit by the driver for this 207 * PCI fn in the previous incarnation. Whoever comes here first 208 * should clean it up, no matter which PCI fn. 209 */ 210 if (ioc_fwstate & BFA_IOC_CB_JOIN_MASK) { 211 writel(BFI_IOC_UNINIT, ioc->ioc_regs.ioc_fwstate); 212 writel(BFI_IOC_UNINIT, ioc->ioc_regs.alt_ioc_fwstate); 213 return BFA_TRUE; 214 } 215 216 return bfa_ioc_cb_sync_complete(ioc); 217 } 218 219 /* 220 * Cleanup hw semaphore and usecnt registers 221 */ 222 static void 223 bfa_ioc_cb_ownership_reset(struct bfa_ioc_s *ioc) 224 { 225 226 /* 227 * Read the hw sem reg to make sure that it is locked 228 * before we clear it. If it is not locked, writing 1 229 * will lock it instead of clearing it. 230 */ 231 readl(ioc->ioc_regs.ioc_sem_reg); 232 writel(1, ioc->ioc_regs.ioc_sem_reg); 233 } 234 235 /* 236 * Synchronized IOC failure processing routines 237 */ 238 static void 239 bfa_ioc_cb_sync_join(struct bfa_ioc_s *ioc) 240 { 241 u32 r32 = readl(ioc->ioc_regs.ioc_fwstate); 242 u32 join_pos = bfa_ioc_cb_join_pos(ioc); 243 244 writel((r32 | join_pos), ioc->ioc_regs.ioc_fwstate); 245 } 246 247 static void 248 bfa_ioc_cb_sync_leave(struct bfa_ioc_s *ioc) 249 { 250 u32 r32 = readl(ioc->ioc_regs.ioc_fwstate); 251 u32 join_pos = bfa_ioc_cb_join_pos(ioc); 252 253 writel((r32 & ~join_pos), ioc->ioc_regs.ioc_fwstate); 254 } 255 256 static void 257 bfa_ioc_cb_set_cur_ioc_fwstate(struct bfa_ioc_s *ioc, 258 enum bfi_ioc_state fwstate) 259 { 260 u32 r32 = readl(ioc->ioc_regs.ioc_fwstate); 261 262 writel((fwstate | (r32 & BFA_IOC_CB_JOIN_MASK)), 263 ioc->ioc_regs.ioc_fwstate); 264 } 265 266 static enum bfi_ioc_state 267 bfa_ioc_cb_get_cur_ioc_fwstate(struct bfa_ioc_s *ioc) 268 { 269 return (enum bfi_ioc_state)(readl(ioc->ioc_regs.ioc_fwstate) & 270 BFA_IOC_CB_FWSTATE_MASK); 271 } 272 273 static void 274 bfa_ioc_cb_set_alt_ioc_fwstate(struct bfa_ioc_s *ioc, 275 enum bfi_ioc_state fwstate) 276 { 277 u32 r32 = readl(ioc->ioc_regs.alt_ioc_fwstate); 278 279 writel((fwstate | (r32 & BFA_IOC_CB_JOIN_MASK)), 280 ioc->ioc_regs.alt_ioc_fwstate); 281 } 282 283 static enum bfi_ioc_state 284 bfa_ioc_cb_get_alt_ioc_fwstate(struct bfa_ioc_s *ioc) 285 { 286 return (enum bfi_ioc_state)(readl(ioc->ioc_regs.alt_ioc_fwstate) & 287 BFA_IOC_CB_FWSTATE_MASK); 288 } 289 290 static void 291 bfa_ioc_cb_sync_ack(struct bfa_ioc_s *ioc) 292 { 293 bfa_ioc_cb_set_cur_ioc_fwstate(ioc, BFI_IOC_FAIL); 294 } 295 296 static bfa_boolean_t 297 bfa_ioc_cb_sync_complete(struct bfa_ioc_s *ioc) 298 { 299 u32 fwstate, alt_fwstate; 300 fwstate = bfa_ioc_cb_get_cur_ioc_fwstate(ioc); 301 302 /* 303 * At this point, this IOC is hoding the hw sem in the 304 * start path (fwcheck) OR in the disable/enable path 305 * OR to check if the other IOC has acknowledged failure. 306 * 307 * So, this IOC can be in UNINIT, INITING, DISABLED, FAIL 308 * or in MEMTEST states. In a normal scenario, this IOC 309 * can not be in OP state when this function is called. 310 * 311 * However, this IOC could still be in OP state when 312 * the OS driver is starting up, if the OptROM code has 313 * left it in that state. 314 * 315 * If we had marked this IOC's fwstate as BFI_IOC_FAIL 316 * in the failure case and now, if the fwstate is not 317 * BFI_IOC_FAIL it implies that the other PCI fn have 318 * reinitialized the ASIC or this IOC got disabled, so 319 * return TRUE. 320 */ 321 if (fwstate == BFI_IOC_UNINIT || 322 fwstate == BFI_IOC_INITING || 323 fwstate == BFI_IOC_DISABLED || 324 fwstate == BFI_IOC_MEMTEST || 325 fwstate == BFI_IOC_OP) 326 return BFA_TRUE; 327 else { 328 alt_fwstate = bfa_ioc_cb_get_alt_ioc_fwstate(ioc); 329 if (alt_fwstate == BFI_IOC_FAIL || 330 alt_fwstate == BFI_IOC_DISABLED || 331 alt_fwstate == BFI_IOC_UNINIT || 332 alt_fwstate == BFI_IOC_INITING || 333 alt_fwstate == BFI_IOC_MEMTEST) 334 return BFA_TRUE; 335 else 336 return BFA_FALSE; 337 } 338 } 339 340 bfa_status_t 341 bfa_ioc_cb_pll_init(void __iomem *rb, enum bfi_asic_mode fcmode) 342 { 343 u32 pll_sclk, pll_fclk, join_bits; 344 345 pll_sclk = __APP_PLL_SCLK_ENABLE | __APP_PLL_SCLK_LRESETN | 346 __APP_PLL_SCLK_P0_1(3U) | 347 __APP_PLL_SCLK_JITLMT0_1(3U) | 348 __APP_PLL_SCLK_CNTLMT0_1(3U); 349 pll_fclk = __APP_PLL_LCLK_ENABLE | __APP_PLL_LCLK_LRESETN | 350 __APP_PLL_LCLK_RSEL200500 | __APP_PLL_LCLK_P0_1(3U) | 351 __APP_PLL_LCLK_JITLMT0_1(3U) | 352 __APP_PLL_LCLK_CNTLMT0_1(3U); 353 join_bits = readl(rb + BFA_IOC0_STATE_REG) & 354 BFA_IOC_CB_JOIN_MASK; 355 writel((BFI_IOC_UNINIT | join_bits), (rb + BFA_IOC0_STATE_REG)); 356 join_bits = readl(rb + BFA_IOC1_STATE_REG) & 357 BFA_IOC_CB_JOIN_MASK; 358 writel((BFI_IOC_UNINIT | join_bits), (rb + BFA_IOC1_STATE_REG)); 359 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK)); 360 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK)); 361 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS)); 362 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS)); 363 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK)); 364 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK)); 365 writel(__APP_PLL_SCLK_LOGIC_SOFT_RESET, rb + APP_PLL_SCLK_CTL_REG); 366 writel(__APP_PLL_SCLK_BYPASS | __APP_PLL_SCLK_LOGIC_SOFT_RESET, 367 rb + APP_PLL_SCLK_CTL_REG); 368 writel(__APP_PLL_LCLK_LOGIC_SOFT_RESET, rb + APP_PLL_LCLK_CTL_REG); 369 writel(__APP_PLL_LCLK_BYPASS | __APP_PLL_LCLK_LOGIC_SOFT_RESET, 370 rb + APP_PLL_LCLK_CTL_REG); 371 udelay(2); 372 writel(__APP_PLL_SCLK_LOGIC_SOFT_RESET, rb + APP_PLL_SCLK_CTL_REG); 373 writel(__APP_PLL_LCLK_LOGIC_SOFT_RESET, rb + APP_PLL_LCLK_CTL_REG); 374 writel(pll_sclk | __APP_PLL_SCLK_LOGIC_SOFT_RESET, 375 rb + APP_PLL_SCLK_CTL_REG); 376 writel(pll_fclk | __APP_PLL_LCLK_LOGIC_SOFT_RESET, 377 rb + APP_PLL_LCLK_CTL_REG); 378 udelay(2000); 379 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS)); 380 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS)); 381 writel(pll_sclk, (rb + APP_PLL_SCLK_CTL_REG)); 382 writel(pll_fclk, (rb + APP_PLL_LCLK_CTL_REG)); 383 384 return BFA_STATUS_OK; 385 } 386