1 /* 2 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc. 3 * All rights reserved 4 * www.brocade.com 5 * 6 * Linux driver for Brocade Fibre Channel Host Bus Adapter. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License (GPL) Version 2 as 10 * published by the Free Software Foundation 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 */ 17 18 #include "bfa_ioc.h" 19 #include "bfi_cbreg.h" 20 #include "bfa_defs.h" 21 22 BFA_TRC_FILE(CNA, IOC_CB); 23 24 /* 25 * forward declarations 26 */ 27 static bfa_boolean_t bfa_ioc_cb_firmware_lock(struct bfa_ioc_s *ioc); 28 static void bfa_ioc_cb_firmware_unlock(struct bfa_ioc_s *ioc); 29 static void bfa_ioc_cb_reg_init(struct bfa_ioc_s *ioc); 30 static void bfa_ioc_cb_map_port(struct bfa_ioc_s *ioc); 31 static void bfa_ioc_cb_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix); 32 static void bfa_ioc_cb_notify_hbfail(struct bfa_ioc_s *ioc); 33 static void bfa_ioc_cb_ownership_reset(struct bfa_ioc_s *ioc); 34 35 struct bfa_ioc_hwif_s hwif_cb; 36 37 /* 38 * Called from bfa_ioc_attach() to map asic specific calls. 39 */ 40 void 41 bfa_ioc_set_cb_hwif(struct bfa_ioc_s *ioc) 42 { 43 hwif_cb.ioc_pll_init = bfa_ioc_cb_pll_init; 44 hwif_cb.ioc_firmware_lock = bfa_ioc_cb_firmware_lock; 45 hwif_cb.ioc_firmware_unlock = bfa_ioc_cb_firmware_unlock; 46 hwif_cb.ioc_reg_init = bfa_ioc_cb_reg_init; 47 hwif_cb.ioc_map_port = bfa_ioc_cb_map_port; 48 hwif_cb.ioc_isr_mode_set = bfa_ioc_cb_isr_mode_set; 49 hwif_cb.ioc_notify_hbfail = bfa_ioc_cb_notify_hbfail; 50 hwif_cb.ioc_ownership_reset = bfa_ioc_cb_ownership_reset; 51 52 ioc->ioc_hwif = &hwif_cb; 53 } 54 55 /* 56 * Return true if firmware of current driver matches the running firmware. 57 */ 58 static bfa_boolean_t 59 bfa_ioc_cb_firmware_lock(struct bfa_ioc_s *ioc) 60 { 61 return BFA_TRUE; 62 } 63 64 static void 65 bfa_ioc_cb_firmware_unlock(struct bfa_ioc_s *ioc) 66 { 67 } 68 69 /* 70 * Notify other functions on HB failure. 71 */ 72 static void 73 bfa_ioc_cb_notify_hbfail(struct bfa_ioc_s *ioc) 74 { 75 writel(__PSS_ERR_STATUS_SET, ioc->ioc_regs.err_set); 76 readl(ioc->ioc_regs.err_set); 77 } 78 79 /* 80 * Host to LPU mailbox message addresses 81 */ 82 static struct { u32 hfn_mbox, lpu_mbox, hfn_pgn; } iocreg_fnreg[] = { 83 { HOSTFN0_LPU_MBOX0_0, LPU_HOSTFN0_MBOX0_0, HOST_PAGE_NUM_FN0 }, 84 { HOSTFN1_LPU_MBOX0_8, LPU_HOSTFN1_MBOX0_8, HOST_PAGE_NUM_FN1 } 85 }; 86 87 /* 88 * Host <-> LPU mailbox command/status registers 89 */ 90 static struct { u32 hfn, lpu; } iocreg_mbcmd[] = { 91 92 { HOSTFN0_LPU0_CMD_STAT, LPU0_HOSTFN0_CMD_STAT }, 93 { HOSTFN1_LPU1_CMD_STAT, LPU1_HOSTFN1_CMD_STAT } 94 }; 95 96 static void 97 bfa_ioc_cb_reg_init(struct bfa_ioc_s *ioc) 98 { 99 void __iomem *rb; 100 int pcifn = bfa_ioc_pcifn(ioc); 101 102 rb = bfa_ioc_bar0(ioc); 103 104 ioc->ioc_regs.hfn_mbox = rb + iocreg_fnreg[pcifn].hfn_mbox; 105 ioc->ioc_regs.lpu_mbox = rb + iocreg_fnreg[pcifn].lpu_mbox; 106 ioc->ioc_regs.host_page_num_fn = rb + iocreg_fnreg[pcifn].hfn_pgn; 107 108 if (ioc->port_id == 0) { 109 ioc->ioc_regs.heartbeat = rb + BFA_IOC0_HBEAT_REG; 110 ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC0_STATE_REG; 111 } else { 112 ioc->ioc_regs.heartbeat = (rb + BFA_IOC1_HBEAT_REG); 113 ioc->ioc_regs.ioc_fwstate = (rb + BFA_IOC1_STATE_REG); 114 } 115 116 /* 117 * Host <-> LPU mailbox command/status registers 118 */ 119 ioc->ioc_regs.hfn_mbox_cmd = rb + iocreg_mbcmd[pcifn].hfn; 120 ioc->ioc_regs.lpu_mbox_cmd = rb + iocreg_mbcmd[pcifn].lpu; 121 122 /* 123 * PSS control registers 124 */ 125 ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG); 126 ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG); 127 ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_400_CTL_REG); 128 ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_212_CTL_REG); 129 130 /* 131 * IOC semaphore registers and serialization 132 */ 133 ioc->ioc_regs.ioc_sem_reg = (rb + HOST_SEM0_REG); 134 ioc->ioc_regs.ioc_init_sem_reg = (rb + HOST_SEM2_REG); 135 136 /* 137 * sram memory access 138 */ 139 ioc->ioc_regs.smem_page_start = (rb + PSS_SMEM_PAGE_START); 140 ioc->ioc_regs.smem_pg0 = BFI_IOC_SMEM_PG0_CB; 141 142 /* 143 * err set reg : for notification of hb failure 144 */ 145 ioc->ioc_regs.err_set = (rb + ERR_SET_REG); 146 } 147 148 /* 149 * Initialize IOC to port mapping. 150 */ 151 152 static void 153 bfa_ioc_cb_map_port(struct bfa_ioc_s *ioc) 154 { 155 /* 156 * For crossbow, port id is same as pci function. 157 */ 158 ioc->port_id = bfa_ioc_pcifn(ioc); 159 160 bfa_trc(ioc, ioc->port_id); 161 } 162 163 /* 164 * Set interrupt mode for a function: INTX or MSIX 165 */ 166 static void 167 bfa_ioc_cb_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix) 168 { 169 } 170 171 /* 172 * Cleanup hw semaphore and usecnt registers 173 */ 174 static void 175 bfa_ioc_cb_ownership_reset(struct bfa_ioc_s *ioc) 176 { 177 178 /* 179 * Read the hw sem reg to make sure that it is locked 180 * before we clear it. If it is not locked, writing 1 181 * will lock it instead of clearing it. 182 */ 183 readl(ioc->ioc_regs.ioc_sem_reg); 184 bfa_ioc_hw_sem_release(ioc); 185 } 186 187 188 189 bfa_status_t 190 bfa_ioc_cb_pll_init(void __iomem *rb, bfa_boolean_t fcmode) 191 { 192 u32 pll_sclk, pll_fclk; 193 194 pll_sclk = __APP_PLL_212_ENABLE | __APP_PLL_212_LRESETN | 195 __APP_PLL_212_P0_1(3U) | 196 __APP_PLL_212_JITLMT0_1(3U) | 197 __APP_PLL_212_CNTLMT0_1(3U); 198 pll_fclk = __APP_PLL_400_ENABLE | __APP_PLL_400_LRESETN | 199 __APP_PLL_400_RSEL200500 | __APP_PLL_400_P0_1(3U) | 200 __APP_PLL_400_JITLMT0_1(3U) | 201 __APP_PLL_400_CNTLMT0_1(3U); 202 writel(BFI_IOC_UNINIT, (rb + BFA_IOC0_STATE_REG)); 203 writel(BFI_IOC_UNINIT, (rb + BFA_IOC1_STATE_REG)); 204 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK)); 205 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK)); 206 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS)); 207 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS)); 208 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK)); 209 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK)); 210 writel(__APP_PLL_212_LOGIC_SOFT_RESET, rb + APP_PLL_212_CTL_REG); 211 writel(__APP_PLL_212_BYPASS | __APP_PLL_212_LOGIC_SOFT_RESET, 212 rb + APP_PLL_212_CTL_REG); 213 writel(__APP_PLL_400_LOGIC_SOFT_RESET, rb + APP_PLL_400_CTL_REG); 214 writel(__APP_PLL_400_BYPASS | __APP_PLL_400_LOGIC_SOFT_RESET, 215 rb + APP_PLL_400_CTL_REG); 216 udelay(2); 217 writel(__APP_PLL_212_LOGIC_SOFT_RESET, rb + APP_PLL_212_CTL_REG); 218 writel(__APP_PLL_400_LOGIC_SOFT_RESET, rb + APP_PLL_400_CTL_REG); 219 writel(pll_sclk | __APP_PLL_212_LOGIC_SOFT_RESET, 220 rb + APP_PLL_212_CTL_REG); 221 writel(pll_fclk | __APP_PLL_400_LOGIC_SOFT_RESET, 222 rb + APP_PLL_400_CTL_REG); 223 udelay(2000); 224 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS)); 225 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS)); 226 writel(pll_sclk, (rb + APP_PLL_212_CTL_REG)); 227 writel(pll_fclk, (rb + APP_PLL_400_CTL_REG)); 228 229 return BFA_STATUS_OK; 230 } 231