1 /* 2 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc. 3 * All rights reserved 4 * www.brocade.com 5 * 6 * Linux driver for Brocade Fibre Channel Host Bus Adapter. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License (GPL) Version 2 as 10 * published by the Free Software Foundation 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 */ 17 18 #include "bfad_drv.h" 19 #include "bfa_modules.h" 20 #include "bfi_reg.h" 21 22 void 23 bfa_hwcb_reginit(struct bfa_s *bfa) 24 { 25 struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs; 26 void __iomem *kva = bfa_ioc_bar0(&bfa->ioc); 27 int fn = bfa_ioc_pcifn(&bfa->ioc); 28 29 if (fn == 0) { 30 bfa_regs->intr_status = (kva + HOSTFN0_INT_STATUS); 31 bfa_regs->intr_mask = (kva + HOSTFN0_INT_MSK); 32 } else { 33 bfa_regs->intr_status = (kva + HOSTFN1_INT_STATUS); 34 bfa_regs->intr_mask = (kva + HOSTFN1_INT_MSK); 35 } 36 } 37 38 static void 39 bfa_hwcb_reqq_ack_msix(struct bfa_s *bfa, int reqq) 40 { 41 writel(__HFN_INT_CPE_Q0 << CPE_Q_NUM(bfa_ioc_pcifn(&bfa->ioc), reqq), 42 bfa->iocfc.bfa_regs.intr_status); 43 } 44 45 /* 46 * Actions to respond RME Interrupt for Crossbow ASIC: 47 * - Write 1 to Interrupt Status register 48 * INTX - done in bfa_intx() 49 * MSIX - done in bfa_hwcb_rspq_ack_msix() 50 * - Update CI (only if new CI) 51 */ 52 static void 53 bfa_hwcb_rspq_ack_msix(struct bfa_s *bfa, int rspq, u32 ci) 54 { 55 writel(__HFN_INT_RME_Q0 << RME_Q_NUM(bfa_ioc_pcifn(&bfa->ioc), rspq), 56 bfa->iocfc.bfa_regs.intr_status); 57 58 if (bfa_rspq_ci(bfa, rspq) == ci) 59 return; 60 61 bfa_rspq_ci(bfa, rspq) = ci; 62 writel(ci, bfa->iocfc.bfa_regs.rme_q_ci[rspq]); 63 mmiowb(); 64 } 65 66 void 67 bfa_hwcb_rspq_ack(struct bfa_s *bfa, int rspq, u32 ci) 68 { 69 if (bfa_rspq_ci(bfa, rspq) == ci) 70 return; 71 72 bfa_rspq_ci(bfa, rspq) = ci; 73 writel(ci, bfa->iocfc.bfa_regs.rme_q_ci[rspq]); 74 mmiowb(); 75 } 76 77 void 78 bfa_hwcb_msix_getvecs(struct bfa_s *bfa, u32 *msix_vecs_bmap, 79 u32 *num_vecs, u32 *max_vec_bit) 80 { 81 #define __HFN_NUMINTS 13 82 if (bfa_ioc_pcifn(&bfa->ioc) == 0) { 83 *msix_vecs_bmap = (__HFN_INT_CPE_Q0 | __HFN_INT_CPE_Q1 | 84 __HFN_INT_CPE_Q2 | __HFN_INT_CPE_Q3 | 85 __HFN_INT_RME_Q0 | __HFN_INT_RME_Q1 | 86 __HFN_INT_RME_Q2 | __HFN_INT_RME_Q3 | 87 __HFN_INT_MBOX_LPU0); 88 *max_vec_bit = __HFN_INT_MBOX_LPU0; 89 } else { 90 *msix_vecs_bmap = (__HFN_INT_CPE_Q4 | __HFN_INT_CPE_Q5 | 91 __HFN_INT_CPE_Q6 | __HFN_INT_CPE_Q7 | 92 __HFN_INT_RME_Q4 | __HFN_INT_RME_Q5 | 93 __HFN_INT_RME_Q6 | __HFN_INT_RME_Q7 | 94 __HFN_INT_MBOX_LPU1); 95 *max_vec_bit = __HFN_INT_MBOX_LPU1; 96 } 97 98 *msix_vecs_bmap |= (__HFN_INT_ERR_EMC | __HFN_INT_ERR_LPU0 | 99 __HFN_INT_ERR_LPU1 | __HFN_INT_ERR_PSS); 100 *num_vecs = __HFN_NUMINTS; 101 } 102 103 /* 104 * Dummy interrupt handler for handling spurious interrupts. 105 */ 106 static void 107 bfa_hwcb_msix_dummy(struct bfa_s *bfa, int vec) 108 { 109 } 110 111 /* 112 * No special setup required for crossbow -- vector assignments are implicit. 113 */ 114 void 115 bfa_hwcb_msix_init(struct bfa_s *bfa, int nvecs) 116 { 117 WARN_ON((nvecs != 1) && (nvecs != __HFN_NUMINTS)); 118 119 bfa->msix.nvecs = nvecs; 120 bfa_hwcb_msix_uninstall(bfa); 121 } 122 123 void 124 bfa_hwcb_msix_ctrl_install(struct bfa_s *bfa) 125 { 126 int i; 127 128 if (bfa->msix.nvecs == 0) 129 return; 130 131 if (bfa->msix.nvecs == 1) { 132 for (i = BFI_MSIX_CPE_QMIN_CB; i < BFI_MSIX_CB_MAX; i++) 133 bfa->msix.handler[i] = bfa_msix_all; 134 return; 135 } 136 137 for (i = BFI_MSIX_RME_QMAX_CB+1; i < BFI_MSIX_CB_MAX; i++) 138 bfa->msix.handler[i] = bfa_msix_lpu_err; 139 } 140 141 void 142 bfa_hwcb_msix_queue_install(struct bfa_s *bfa) 143 { 144 int i; 145 146 if (bfa->msix.nvecs == 0) 147 return; 148 149 if (bfa->msix.nvecs == 1) { 150 for (i = BFI_MSIX_CPE_QMIN_CB; i <= BFI_MSIX_RME_QMAX_CB; i++) 151 bfa->msix.handler[i] = bfa_msix_all; 152 return; 153 } 154 155 for (i = BFI_MSIX_CPE_QMIN_CB; i <= BFI_MSIX_CPE_QMAX_CB; i++) 156 bfa->msix.handler[i] = bfa_msix_reqq; 157 158 for (i = BFI_MSIX_RME_QMIN_CB; i <= BFI_MSIX_RME_QMAX_CB; i++) 159 bfa->msix.handler[i] = bfa_msix_rspq; 160 } 161 162 void 163 bfa_hwcb_msix_uninstall(struct bfa_s *bfa) 164 { 165 int i; 166 167 for (i = 0; i < BFI_MSIX_CB_MAX; i++) 168 bfa->msix.handler[i] = bfa_hwcb_msix_dummy; 169 } 170 171 /* 172 * No special enable/disable -- vector assignments are implicit. 173 */ 174 void 175 bfa_hwcb_isr_mode_set(struct bfa_s *bfa, bfa_boolean_t msix) 176 { 177 if (msix) { 178 bfa->iocfc.hwif.hw_reqq_ack = bfa_hwcb_reqq_ack_msix; 179 bfa->iocfc.hwif.hw_rspq_ack = bfa_hwcb_rspq_ack_msix; 180 } else { 181 bfa->iocfc.hwif.hw_reqq_ack = NULL; 182 bfa->iocfc.hwif.hw_rspq_ack = bfa_hwcb_rspq_ack; 183 } 184 } 185 186 void 187 bfa_hwcb_msix_get_rme_range(struct bfa_s *bfa, u32 *start, u32 *end) 188 { 189 *start = BFI_MSIX_RME_QMIN_CB; 190 *end = BFI_MSIX_RME_QMAX_CB; 191 } 192