1 /* 2 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc. 3 * Copyright (c) 2014- QLogic Corporation. 4 * All rights reserved 5 * www.qlogic.com 6 * 7 * Linux driver for QLogic BR-series Fibre Channel Host Bus Adapter. 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License (GPL) Version 2 as 11 * published by the Free Software Foundation 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 */ 18 19 #include "bfad_drv.h" 20 #include "bfa_modules.h" 21 #include "bfi_reg.h" 22 23 void 24 bfa_hwcb_reginit(struct bfa_s *bfa) 25 { 26 struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs; 27 void __iomem *kva = bfa_ioc_bar0(&bfa->ioc); 28 int fn = bfa_ioc_pcifn(&bfa->ioc); 29 30 if (fn == 0) { 31 bfa_regs->intr_status = (kva + HOSTFN0_INT_STATUS); 32 bfa_regs->intr_mask = (kva + HOSTFN0_INT_MSK); 33 } else { 34 bfa_regs->intr_status = (kva + HOSTFN1_INT_STATUS); 35 bfa_regs->intr_mask = (kva + HOSTFN1_INT_MSK); 36 } 37 } 38 39 static void 40 bfa_hwcb_reqq_ack_msix(struct bfa_s *bfa, int reqq) 41 { 42 writel(__HFN_INT_CPE_Q0 << CPE_Q_NUM(bfa_ioc_pcifn(&bfa->ioc), reqq), 43 bfa->iocfc.bfa_regs.intr_status); 44 } 45 46 /* 47 * Actions to respond RME Interrupt for Crossbow ASIC: 48 * - Write 1 to Interrupt Status register 49 * INTX - done in bfa_intx() 50 * MSIX - done in bfa_hwcb_rspq_ack_msix() 51 * - Update CI (only if new CI) 52 */ 53 static void 54 bfa_hwcb_rspq_ack_msix(struct bfa_s *bfa, int rspq, u32 ci) 55 { 56 writel(__HFN_INT_RME_Q0 << RME_Q_NUM(bfa_ioc_pcifn(&bfa->ioc), rspq), 57 bfa->iocfc.bfa_regs.intr_status); 58 59 if (bfa_rspq_ci(bfa, rspq) == ci) 60 return; 61 62 bfa_rspq_ci(bfa, rspq) = ci; 63 writel(ci, bfa->iocfc.bfa_regs.rme_q_ci[rspq]); 64 } 65 66 void 67 bfa_hwcb_rspq_ack(struct bfa_s *bfa, int rspq, u32 ci) 68 { 69 if (bfa_rspq_ci(bfa, rspq) == ci) 70 return; 71 72 bfa_rspq_ci(bfa, rspq) = ci; 73 writel(ci, bfa->iocfc.bfa_regs.rme_q_ci[rspq]); 74 } 75 76 void 77 bfa_hwcb_msix_getvecs(struct bfa_s *bfa, u32 *msix_vecs_bmap, 78 u32 *num_vecs, u32 *max_vec_bit) 79 { 80 #define __HFN_NUMINTS 13 81 if (bfa_ioc_pcifn(&bfa->ioc) == 0) { 82 *msix_vecs_bmap = (__HFN_INT_CPE_Q0 | __HFN_INT_CPE_Q1 | 83 __HFN_INT_CPE_Q2 | __HFN_INT_CPE_Q3 | 84 __HFN_INT_RME_Q0 | __HFN_INT_RME_Q1 | 85 __HFN_INT_RME_Q2 | __HFN_INT_RME_Q3 | 86 __HFN_INT_MBOX_LPU0); 87 *max_vec_bit = __HFN_INT_MBOX_LPU0; 88 } else { 89 *msix_vecs_bmap = (__HFN_INT_CPE_Q4 | __HFN_INT_CPE_Q5 | 90 __HFN_INT_CPE_Q6 | __HFN_INT_CPE_Q7 | 91 __HFN_INT_RME_Q4 | __HFN_INT_RME_Q5 | 92 __HFN_INT_RME_Q6 | __HFN_INT_RME_Q7 | 93 __HFN_INT_MBOX_LPU1); 94 *max_vec_bit = __HFN_INT_MBOX_LPU1; 95 } 96 97 *msix_vecs_bmap |= (__HFN_INT_ERR_EMC | __HFN_INT_ERR_LPU0 | 98 __HFN_INT_ERR_LPU1 | __HFN_INT_ERR_PSS); 99 *num_vecs = __HFN_NUMINTS; 100 } 101 102 /* 103 * Dummy interrupt handler for handling spurious interrupts. 104 */ 105 static void 106 bfa_hwcb_msix_dummy(struct bfa_s *bfa, int vec) 107 { 108 } 109 110 /* 111 * No special setup required for crossbow -- vector assignments are implicit. 112 */ 113 void 114 bfa_hwcb_msix_init(struct bfa_s *bfa, int nvecs) 115 { 116 WARN_ON((nvecs != 1) && (nvecs != __HFN_NUMINTS)); 117 118 bfa->msix.nvecs = nvecs; 119 bfa_hwcb_msix_uninstall(bfa); 120 } 121 122 void 123 bfa_hwcb_msix_ctrl_install(struct bfa_s *bfa) 124 { 125 int i; 126 127 if (bfa->msix.nvecs == 0) 128 return; 129 130 if (bfa->msix.nvecs == 1) { 131 for (i = BFI_MSIX_CPE_QMIN_CB; i < BFI_MSIX_CB_MAX; i++) 132 bfa->msix.handler[i] = bfa_msix_all; 133 return; 134 } 135 136 for (i = BFI_MSIX_RME_QMAX_CB+1; i < BFI_MSIX_CB_MAX; i++) 137 bfa->msix.handler[i] = bfa_msix_lpu_err; 138 } 139 140 void 141 bfa_hwcb_msix_queue_install(struct bfa_s *bfa) 142 { 143 int i; 144 145 if (bfa->msix.nvecs == 0) 146 return; 147 148 if (bfa->msix.nvecs == 1) { 149 for (i = BFI_MSIX_CPE_QMIN_CB; i <= BFI_MSIX_RME_QMAX_CB; i++) 150 bfa->msix.handler[i] = bfa_msix_all; 151 return; 152 } 153 154 for (i = BFI_MSIX_CPE_QMIN_CB; i <= BFI_MSIX_CPE_QMAX_CB; i++) 155 bfa->msix.handler[i] = bfa_msix_reqq; 156 157 for (i = BFI_MSIX_RME_QMIN_CB; i <= BFI_MSIX_RME_QMAX_CB; i++) 158 bfa->msix.handler[i] = bfa_msix_rspq; 159 } 160 161 void 162 bfa_hwcb_msix_uninstall(struct bfa_s *bfa) 163 { 164 int i; 165 166 for (i = 0; i < BFI_MSIX_CB_MAX; i++) 167 bfa->msix.handler[i] = bfa_hwcb_msix_dummy; 168 } 169 170 /* 171 * No special enable/disable -- vector assignments are implicit. 172 */ 173 void 174 bfa_hwcb_isr_mode_set(struct bfa_s *bfa, bfa_boolean_t msix) 175 { 176 if (msix) { 177 bfa->iocfc.hwif.hw_reqq_ack = bfa_hwcb_reqq_ack_msix; 178 bfa->iocfc.hwif.hw_rspq_ack = bfa_hwcb_rspq_ack_msix; 179 } else { 180 bfa->iocfc.hwif.hw_reqq_ack = NULL; 181 bfa->iocfc.hwif.hw_rspq_ack = bfa_hwcb_rspq_ack; 182 } 183 } 184 185 void 186 bfa_hwcb_msix_get_rme_range(struct bfa_s *bfa, u32 *start, u32 *end) 187 { 188 *start = BFI_MSIX_RME_QMIN_CB; 189 *end = BFI_MSIX_RME_QMAX_CB; 190 } 191