1 /* 2 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc. 3 * All rights reserved 4 * www.brocade.com 5 * 6 * Linux driver for Brocade Fibre Channel Host Bus Adapter. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License (GPL) Version 2 as 10 * published by the Free Software Foundation 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 */ 17 18 #ifndef __BFA_DEFS_H__ 19 #define __BFA_DEFS_H__ 20 21 #include "bfa_fc.h" 22 #include "bfad_drv.h" 23 24 #define BFA_MFG_SERIALNUM_SIZE 11 25 #define STRSZ(_n) (((_n) + 4) & ~3) 26 27 /* 28 * Manufacturing card type 29 */ 30 enum { 31 BFA_MFG_TYPE_CB_MAX = 825, /* Crossbow card type max */ 32 BFA_MFG_TYPE_FC8P2 = 825, /* 8G 2port FC card */ 33 BFA_MFG_TYPE_FC8P1 = 815, /* 8G 1port FC card */ 34 BFA_MFG_TYPE_FC4P2 = 425, /* 4G 2port FC card */ 35 BFA_MFG_TYPE_FC4P1 = 415, /* 4G 1port FC card */ 36 BFA_MFG_TYPE_CNA10P2 = 1020, /* 10G 2port CNA card */ 37 BFA_MFG_TYPE_CNA10P1 = 1010, /* 10G 1port CNA card */ 38 BFA_MFG_TYPE_JAYHAWK = 804, /* Jayhawk mezz card */ 39 BFA_MFG_TYPE_WANCHESE = 1007, /* Wanchese mezz card */ 40 BFA_MFG_TYPE_ASTRA = 807, /* Astra mezz card */ 41 BFA_MFG_TYPE_LIGHTNING_P0 = 902, /* Lightning mezz card - old */ 42 BFA_MFG_TYPE_LIGHTNING = 1741, /* Lightning mezz card */ 43 BFA_MFG_TYPE_PROWLER_F = 1560, /* Prowler FC only cards */ 44 BFA_MFG_TYPE_PROWLER_N = 1410, /* Prowler NIC only cards */ 45 BFA_MFG_TYPE_PROWLER_C = 1710, /* Prowler CNA only cards */ 46 BFA_MFG_TYPE_PROWLER_D = 1860, /* Prowler Dual cards */ 47 BFA_MFG_TYPE_CHINOOK = 1867, /* Chinook cards */ 48 BFA_MFG_TYPE_INVALID = 0, /* Invalid card type */ 49 }; 50 51 #pragma pack(1) 52 53 /* 54 * Check if Mezz card 55 */ 56 #define bfa_mfg_is_mezz(type) (( \ 57 (type) == BFA_MFG_TYPE_JAYHAWK || \ 58 (type) == BFA_MFG_TYPE_WANCHESE || \ 59 (type) == BFA_MFG_TYPE_ASTRA || \ 60 (type) == BFA_MFG_TYPE_LIGHTNING_P0 || \ 61 (type) == BFA_MFG_TYPE_LIGHTNING || \ 62 (type) == BFA_MFG_TYPE_CHINOOK)) 63 64 /* 65 * Check if the card having old wwn/mac handling 66 */ 67 #define bfa_mfg_is_old_wwn_mac_model(type) (( \ 68 (type) == BFA_MFG_TYPE_FC8P2 || \ 69 (type) == BFA_MFG_TYPE_FC8P1 || \ 70 (type) == BFA_MFG_TYPE_FC4P2 || \ 71 (type) == BFA_MFG_TYPE_FC4P1 || \ 72 (type) == BFA_MFG_TYPE_CNA10P2 || \ 73 (type) == BFA_MFG_TYPE_CNA10P1 || \ 74 (type) == BFA_MFG_TYPE_JAYHAWK || \ 75 (type) == BFA_MFG_TYPE_WANCHESE)) 76 77 #define bfa_mfg_increment_wwn_mac(m, i) \ 78 do { \ 79 u32 t = ((u32)(m)[0] << 16) | ((u32)(m)[1] << 8) | \ 80 (u32)(m)[2]; \ 81 t += (i); \ 82 (m)[0] = (t >> 16) & 0xFF; \ 83 (m)[1] = (t >> 8) & 0xFF; \ 84 (m)[2] = t & 0xFF; \ 85 } while (0) 86 87 /* 88 * VPD data length 89 */ 90 #define BFA_MFG_VPD_LEN 512 91 92 /* 93 * VPD vendor tag 94 */ 95 enum { 96 BFA_MFG_VPD_UNKNOWN = 0, /* vendor unknown */ 97 BFA_MFG_VPD_IBM = 1, /* vendor IBM */ 98 BFA_MFG_VPD_HP = 2, /* vendor HP */ 99 BFA_MFG_VPD_DELL = 3, /* vendor DELL */ 100 BFA_MFG_VPD_PCI_IBM = 0x08, /* PCI VPD IBM */ 101 BFA_MFG_VPD_PCI_HP = 0x10, /* PCI VPD HP */ 102 BFA_MFG_VPD_PCI_DELL = 0x20, /* PCI VPD DELL */ 103 BFA_MFG_VPD_PCI_BRCD = 0xf8, /* PCI VPD Brocade */ 104 }; 105 106 /* 107 * All numerical fields are in big-endian format. 108 */ 109 struct bfa_mfg_vpd_s { 110 u8 version; /* vpd data version */ 111 u8 vpd_sig[3]; /* characters 'V', 'P', 'D' */ 112 u8 chksum; /* u8 checksum */ 113 u8 vendor; /* vendor */ 114 u8 len; /* vpd data length excluding header */ 115 u8 rsv; 116 u8 data[BFA_MFG_VPD_LEN]; /* vpd data */ 117 }; 118 119 #pragma pack() 120 121 /* 122 * Status return values 123 */ 124 enum bfa_status { 125 BFA_STATUS_OK = 0, /* Success */ 126 BFA_STATUS_FAILED = 1, /* Operation failed */ 127 BFA_STATUS_EINVAL = 2, /* Invalid params Check input 128 * parameters */ 129 BFA_STATUS_ENOMEM = 3, /* Out of resources */ 130 BFA_STATUS_ETIMER = 5, /* Timer expired - Retry, if persists, 131 * contact support */ 132 BFA_STATUS_EPROTOCOL = 6, /* Protocol error */ 133 BFA_STATUS_SFP_UNSUPP = 10, /* Unsupported SFP - Replace SFP */ 134 BFA_STATUS_UNKNOWN_VFID = 11, /* VF_ID not found */ 135 BFA_STATUS_DATACORRUPTED = 12, /* Diag returned data corrupted */ 136 BFA_STATUS_DEVBUSY = 13, /* Device busy - Retry operation */ 137 BFA_STATUS_HDMA_FAILED = 16, /* Host dma failed contact support */ 138 BFA_STATUS_FLASH_BAD_LEN = 17, /* Flash bad length */ 139 BFA_STATUS_UNKNOWN_LWWN = 18, /* LPORT PWWN not found */ 140 BFA_STATUS_UNKNOWN_RWWN = 19, /* RPORT PWWN not found */ 141 BFA_STATUS_VPORT_EXISTS = 21, /* VPORT already exists */ 142 BFA_STATUS_VPORT_MAX = 22, /* Reached max VPORT supported limit */ 143 BFA_STATUS_UNSUPP_SPEED = 23, /* Invalid Speed Check speed setting */ 144 BFA_STATUS_INVLD_DFSZ = 24, /* Invalid Max data field size */ 145 BFA_STATUS_CMD_NOTSUPP = 26, /* Command/API not supported */ 146 BFA_STATUS_FABRIC_RJT = 29, /* Reject from attached fabric */ 147 BFA_STATUS_PORT_OFFLINE = 34, /* Port is not online */ 148 BFA_STATUS_VPORT_WWN_BP = 46, /* WWN is same as base port's WWN */ 149 BFA_STATUS_PORT_NOT_DISABLED = 47, /* Port not disabled disable port */ 150 BFA_STATUS_NO_FCPIM_NEXUS = 52, /* No FCP Nexus exists with the rport */ 151 BFA_STATUS_IOC_FAILURE = 56, /* IOC failure - Retry, if persists 152 * contact support */ 153 BFA_STATUS_INVALID_WWN = 57, /* Invalid WWN */ 154 BFA_STATUS_ADAPTER_ENABLED = 60, /* Adapter is not disabled */ 155 BFA_STATUS_IOC_NON_OP = 61, /* IOC is not operational */ 156 BFA_STATUS_VERSION_FAIL = 70, /* Application/Driver version mismatch */ 157 BFA_STATUS_DIAG_BUSY = 71, /* diag busy */ 158 BFA_STATUS_BEACON_ON = 72, /* Port Beacon already on */ 159 BFA_STATUS_ENOFSAVE = 78, /* No saved firmware trace */ 160 BFA_STATUS_IOC_DISABLED = 82, /* IOC is already disabled */ 161 BFA_STATUS_NO_SFP_DEV = 89, /* No SFP device check or replace SFP */ 162 BFA_STATUS_MEMTEST_FAILED = 90, /* Memory test failed contact support */ 163 BFA_STATUS_LEDTEST_OP = 109, /* LED test is operating */ 164 BFA_STATUS_INVALID_MAC = 134, /* Invalid MAC address */ 165 BFA_STATUS_PBC = 154, /* Operation not allowed for pre-boot 166 * configuration */ 167 BFA_STATUS_SFP_NOT_READY = 159, /* SFP info is not ready. Retry */ 168 BFA_STATUS_TRUNK_ENABLED = 164, /* Trunk is already enabled on 169 * this adapter */ 170 BFA_STATUS_TRUNK_DISABLED = 165, /* Trunking is disabled on 171 * the adapter */ 172 BFA_STATUS_IOPROFILE_OFF = 175, /* IO profile OFF */ 173 BFA_STATUS_PHY_NOT_PRESENT = 183, /* PHY module not present */ 174 BFA_STATUS_FEATURE_NOT_SUPPORTED = 192, /* Feature not supported */ 175 BFA_STATUS_FAA_ENABLED = 197, /* FAA is already enabled */ 176 BFA_STATUS_FAA_DISABLED = 198, /* FAA is already disabled */ 177 BFA_STATUS_FAA_ACQUIRED = 199, /* FAA is already acquired */ 178 BFA_STATUS_FAA_ACQ_ADDR = 200, /* Acquiring addr */ 179 BFA_STATUS_ERROR_TRUNK_ENABLED = 203, /* Trunk enabled on adapter */ 180 BFA_STATUS_MAX_VAL /* Unknown error code */ 181 }; 182 #define bfa_status_t enum bfa_status 183 184 enum bfa_eproto_status { 185 BFA_EPROTO_BAD_ACCEPT = 0, 186 BFA_EPROTO_UNKNOWN_RSP = 1 187 }; 188 #define bfa_eproto_status_t enum bfa_eproto_status 189 190 enum bfa_boolean { 191 BFA_FALSE = 0, 192 BFA_TRUE = 1 193 }; 194 #define bfa_boolean_t enum bfa_boolean 195 196 #define BFA_STRING_32 32 197 #define BFA_VERSION_LEN 64 198 199 /* 200 * ---------------------- adapter definitions ------------ 201 */ 202 203 /* 204 * BFA adapter level attributes. 205 */ 206 enum { 207 BFA_ADAPTER_SERIAL_NUM_LEN = STRSZ(BFA_MFG_SERIALNUM_SIZE), 208 /* 209 *!< adapter serial num length 210 */ 211 BFA_ADAPTER_MODEL_NAME_LEN = 16, /* model name length */ 212 BFA_ADAPTER_MODEL_DESCR_LEN = 128, /* model description length */ 213 BFA_ADAPTER_MFG_NAME_LEN = 8, /* manufacturer name length */ 214 BFA_ADAPTER_SYM_NAME_LEN = 64, /* adapter symbolic name length */ 215 BFA_ADAPTER_OS_TYPE_LEN = 64, /* adapter os type length */ 216 }; 217 218 struct bfa_adapter_attr_s { 219 char manufacturer[BFA_ADAPTER_MFG_NAME_LEN]; 220 char serial_num[BFA_ADAPTER_SERIAL_NUM_LEN]; 221 u32 card_type; 222 char model[BFA_ADAPTER_MODEL_NAME_LEN]; 223 char model_descr[BFA_ADAPTER_MODEL_DESCR_LEN]; 224 wwn_t pwwn; 225 char node_symname[FC_SYMNAME_MAX]; 226 char hw_ver[BFA_VERSION_LEN]; 227 char fw_ver[BFA_VERSION_LEN]; 228 char optrom_ver[BFA_VERSION_LEN]; 229 char os_type[BFA_ADAPTER_OS_TYPE_LEN]; 230 struct bfa_mfg_vpd_s vpd; 231 struct mac_s mac; 232 233 u8 nports; 234 u8 max_speed; 235 u8 prototype; 236 char asic_rev; 237 238 u8 pcie_gen; 239 u8 pcie_lanes_orig; 240 u8 pcie_lanes; 241 u8 cna_capable; 242 243 u8 is_mezz; 244 u8 trunk_capable; 245 }; 246 247 /* 248 * ---------------------- IOC definitions ------------ 249 */ 250 251 enum { 252 BFA_IOC_DRIVER_LEN = 16, 253 BFA_IOC_CHIP_REV_LEN = 8, 254 }; 255 256 /* 257 * Driver and firmware versions. 258 */ 259 struct bfa_ioc_driver_attr_s { 260 char driver[BFA_IOC_DRIVER_LEN]; /* driver name */ 261 char driver_ver[BFA_VERSION_LEN]; /* driver version */ 262 char fw_ver[BFA_VERSION_LEN]; /* firmware version */ 263 char bios_ver[BFA_VERSION_LEN]; /* bios version */ 264 char efi_ver[BFA_VERSION_LEN]; /* EFI version */ 265 char ob_ver[BFA_VERSION_LEN]; /* openboot version */ 266 }; 267 268 /* 269 * IOC PCI device attributes 270 */ 271 struct bfa_ioc_pci_attr_s { 272 u16 vendor_id; /* PCI vendor ID */ 273 u16 device_id; /* PCI device ID */ 274 u16 ssid; /* subsystem ID */ 275 u16 ssvid; /* subsystem vendor ID */ 276 u32 pcifn; /* PCI device function */ 277 u32 rsvd; /* padding */ 278 char chip_rev[BFA_IOC_CHIP_REV_LEN]; /* chip revision */ 279 }; 280 281 /* 282 * IOC states 283 */ 284 enum bfa_ioc_state { 285 BFA_IOC_UNINIT = 1, /* IOC is in uninit state */ 286 BFA_IOC_RESET = 2, /* IOC is in reset state */ 287 BFA_IOC_SEMWAIT = 3, /* Waiting for IOC h/w semaphore */ 288 BFA_IOC_HWINIT = 4, /* IOC h/w is being initialized */ 289 BFA_IOC_GETATTR = 5, /* IOC is being configured */ 290 BFA_IOC_OPERATIONAL = 6, /* IOC is operational */ 291 BFA_IOC_INITFAIL = 7, /* IOC hardware failure */ 292 BFA_IOC_FAIL = 8, /* IOC heart-beat failure */ 293 BFA_IOC_DISABLING = 9, /* IOC is being disabled */ 294 BFA_IOC_DISABLED = 10, /* IOC is disabled */ 295 BFA_IOC_FWMISMATCH = 11, /* IOC f/w different from drivers */ 296 BFA_IOC_ENABLING = 12, /* IOC is being enabled */ 297 BFA_IOC_HWFAIL = 13, /* PCI mapping doesn't exist */ 298 BFA_IOC_ACQ_ADDR = 14, /* Acquiring addr from fabric */ 299 }; 300 301 /* 302 * IOC firmware stats 303 */ 304 struct bfa_fw_ioc_stats_s { 305 u32 enable_reqs; 306 u32 disable_reqs; 307 u32 get_attr_reqs; 308 u32 dbg_sync; 309 u32 dbg_dump; 310 u32 unknown_reqs; 311 }; 312 313 /* 314 * IOC driver stats 315 */ 316 struct bfa_ioc_drv_stats_s { 317 u32 ioc_isrs; 318 u32 ioc_enables; 319 u32 ioc_disables; 320 u32 ioc_hbfails; 321 u32 ioc_boots; 322 u32 stats_tmos; 323 u32 hb_count; 324 u32 disable_reqs; 325 u32 enable_reqs; 326 u32 disable_replies; 327 u32 enable_replies; 328 u32 rsvd; 329 }; 330 331 /* 332 * IOC statistics 333 */ 334 struct bfa_ioc_stats_s { 335 struct bfa_ioc_drv_stats_s drv_stats; /* driver IOC stats */ 336 struct bfa_fw_ioc_stats_s fw_stats; /* firmware IOC stats */ 337 }; 338 339 enum bfa_ioc_type_e { 340 BFA_IOC_TYPE_FC = 1, 341 BFA_IOC_TYPE_FCoE = 2, 342 BFA_IOC_TYPE_LL = 3, 343 }; 344 345 /* 346 * IOC attributes returned in queries 347 */ 348 struct bfa_ioc_attr_s { 349 enum bfa_ioc_type_e ioc_type; 350 enum bfa_ioc_state state; /* IOC state */ 351 struct bfa_adapter_attr_s adapter_attr; /* HBA attributes */ 352 struct bfa_ioc_driver_attr_s driver_attr; /* driver attr */ 353 struct bfa_ioc_pci_attr_s pci_attr; 354 u8 port_id; /* port number */ 355 u8 port_mode; /* bfa_mode_s */ 356 u8 cap_bm; /* capability */ 357 u8 port_mode_cfg; /* bfa_mode_s */ 358 u8 rsvd[4]; /* 64bit align */ 359 }; 360 361 /* 362 * ---------------------- mfg definitions ------------ 363 */ 364 365 /* 366 * Checksum size 367 */ 368 #define BFA_MFG_CHKSUM_SIZE 16 369 370 #define BFA_MFG_PARTNUM_SIZE 14 371 #define BFA_MFG_SUPPLIER_ID_SIZE 10 372 #define BFA_MFG_SUPPLIER_PARTNUM_SIZE 20 373 #define BFA_MFG_SUPPLIER_SERIALNUM_SIZE 20 374 #define BFA_MFG_SUPPLIER_REVISION_SIZE 4 375 /* 376 * Initial capability definition 377 */ 378 #define BFA_MFG_IC_FC 0x01 379 #define BFA_MFG_IC_ETH 0x02 380 381 /* 382 * Adapter capability mask definition 383 */ 384 #define BFA_CM_HBA 0x01 385 #define BFA_CM_CNA 0x02 386 #define BFA_CM_NIC 0x04 387 #define BFA_CM_FC16G 0x08 388 #define BFA_CM_SRIOV 0x10 389 #define BFA_CM_MEZZ 0x20 390 391 #pragma pack(1) 392 393 /* 394 * All numerical fields are in big-endian format. 395 */ 396 struct bfa_mfg_block_s { 397 u8 version; /*!< manufacturing block version */ 398 u8 mfg_sig[3]; /*!< characters 'M', 'F', 'G' */ 399 u16 mfgsize; /*!< mfg block size */ 400 u16 u16_chksum; /*!< old u16 checksum */ 401 char brcd_serialnum[STRSZ(BFA_MFG_SERIALNUM_SIZE)]; 402 char brcd_partnum[STRSZ(BFA_MFG_PARTNUM_SIZE)]; 403 u8 mfg_day; /*!< manufacturing day */ 404 u8 mfg_month; /*!< manufacturing month */ 405 u16 mfg_year; /*!< manufacturing year */ 406 wwn_t mfg_wwn; /*!< wwn base for this adapter */ 407 u8 num_wwn; /*!< number of wwns assigned */ 408 u8 mfg_speeds; /*!< speeds allowed for this adapter */ 409 u8 rsv[2]; 410 char supplier_id[STRSZ(BFA_MFG_SUPPLIER_ID_SIZE)]; 411 char supplier_partnum[STRSZ(BFA_MFG_SUPPLIER_PARTNUM_SIZE)]; 412 char supplier_serialnum[STRSZ(BFA_MFG_SUPPLIER_SERIALNUM_SIZE)]; 413 char supplier_revision[STRSZ(BFA_MFG_SUPPLIER_REVISION_SIZE)]; 414 mac_t mfg_mac; /*!< base mac address */ 415 u8 num_mac; /*!< number of mac addresses */ 416 u8 rsv2; 417 u32 card_type; /*!< card type */ 418 char cap_nic; /*!< capability nic */ 419 char cap_cna; /*!< capability cna */ 420 char cap_hba; /*!< capability hba */ 421 char cap_fc16g; /*!< capability fc 16g */ 422 char cap_sriov; /*!< capability sriov */ 423 char cap_mezz; /*!< capability mezz */ 424 u8 rsv3; 425 u8 mfg_nports; /*!< number of ports */ 426 char media[8]; /*!< xfi/xaui */ 427 char initial_mode[8]; /*!< initial mode: hba/cna/nic */ 428 u8 rsv4[84]; 429 u8 md5_chksum[BFA_MFG_CHKSUM_SIZE]; /*!< md5 checksum */ 430 }; 431 432 #pragma pack() 433 434 /* 435 * ---------------------- pci definitions ------------ 436 */ 437 438 /* 439 * PCI device and vendor ID information 440 */ 441 enum { 442 BFA_PCI_VENDOR_ID_BROCADE = 0x1657, 443 BFA_PCI_DEVICE_ID_FC_8G2P = 0x13, 444 BFA_PCI_DEVICE_ID_FC_8G1P = 0x17, 445 BFA_PCI_DEVICE_ID_CT = 0x14, 446 BFA_PCI_DEVICE_ID_CT_FC = 0x21, 447 BFA_PCI_DEVICE_ID_CT2 = 0x22, 448 }; 449 450 #define bfa_asic_id_cb(__d) \ 451 ((__d) == BFA_PCI_DEVICE_ID_FC_8G2P || \ 452 (__d) == BFA_PCI_DEVICE_ID_FC_8G1P) 453 #define bfa_asic_id_ct(__d) \ 454 ((__d) == BFA_PCI_DEVICE_ID_CT || \ 455 (__d) == BFA_PCI_DEVICE_ID_CT_FC) 456 #define bfa_asic_id_ct2(__d) ((__d) == BFA_PCI_DEVICE_ID_CT2) 457 #define bfa_asic_id_ctc(__d) \ 458 (bfa_asic_id_ct(__d) || bfa_asic_id_ct2(__d)) 459 460 /* 461 * PCI sub-system device and vendor ID information 462 */ 463 enum { 464 BFA_PCI_FCOE_SSDEVICE_ID = 0x14, 465 BFA_PCI_CT2_SSID_FCoE = 0x22, 466 BFA_PCI_CT2_SSID_ETH = 0x23, 467 BFA_PCI_CT2_SSID_FC = 0x24, 468 }; 469 470 /* 471 * Maximum number of device address ranges mapped through different BAR(s) 472 */ 473 #define BFA_PCI_ACCESS_RANGES 1 474 475 /* 476 * Port speed settings. Each specific speed is a bit field. Use multiple 477 * bits to specify speeds to be selected for auto-negotiation. 478 */ 479 enum bfa_port_speed { 480 BFA_PORT_SPEED_UNKNOWN = 0, 481 BFA_PORT_SPEED_1GBPS = 1, 482 BFA_PORT_SPEED_2GBPS = 2, 483 BFA_PORT_SPEED_4GBPS = 4, 484 BFA_PORT_SPEED_8GBPS = 8, 485 BFA_PORT_SPEED_10GBPS = 10, 486 BFA_PORT_SPEED_16GBPS = 16, 487 BFA_PORT_SPEED_AUTO = 0xf, 488 }; 489 #define bfa_port_speed_t enum bfa_port_speed 490 491 enum { 492 BFA_BOOT_BOOTLUN_MAX = 4, /* maximum boot lun per IOC */ 493 BFA_PREBOOT_BOOTLUN_MAX = 8, /* maximum preboot lun per IOC */ 494 }; 495 496 #define BOOT_CFG_REV1 1 497 #define BOOT_CFG_VLAN 1 498 499 /* 500 * Boot options setting. Boot options setting determines from where 501 * to get the boot lun information 502 */ 503 enum bfa_boot_bootopt { 504 BFA_BOOT_AUTO_DISCOVER = 0, /* Boot from blun provided by fabric */ 505 BFA_BOOT_STORED_BLUN = 1, /* Boot from bluns stored in flash */ 506 BFA_BOOT_FIRST_LUN = 2, /* Boot from first discovered blun */ 507 BFA_BOOT_PBC = 3, /* Boot from pbc configured blun */ 508 }; 509 510 #pragma pack(1) 511 /* 512 * Boot lun information. 513 */ 514 struct bfa_boot_bootlun_s { 515 wwn_t pwwn; /* port wwn of target */ 516 struct scsi_lun lun; /* 64-bit lun */ 517 }; 518 #pragma pack() 519 520 /* 521 * BOOT boot configuraton 522 */ 523 struct bfa_boot_pbc_s { 524 u8 enable; /* enable/disable SAN boot */ 525 u8 speed; /* boot speed settings */ 526 u8 topology; /* boot topology setting */ 527 u8 rsvd1; 528 u32 nbluns; /* number of boot luns */ 529 struct bfa_boot_bootlun_s pblun[BFA_PREBOOT_BOOTLUN_MAX]; 530 }; 531 532 /* 533 * ASIC block configuration related structures 534 */ 535 #define BFA_ABLK_MAX_PORTS 2 536 #define BFA_ABLK_MAX_PFS 16 537 #define BFA_ABLK_MAX 2 538 539 #pragma pack(1) 540 enum bfa_mode_s { 541 BFA_MODE_HBA = 1, 542 BFA_MODE_CNA = 2, 543 BFA_MODE_NIC = 3 544 }; 545 546 struct bfa_adapter_cfg_mode_s { 547 u16 max_pf; 548 u16 max_vf; 549 enum bfa_mode_s mode; 550 }; 551 552 struct bfa_ablk_cfg_pf_s { 553 u16 pers; 554 u8 port_id; 555 u8 optrom; 556 u8 valid; 557 u8 sriov; 558 u8 max_vfs; 559 u8 rsvd[1]; 560 u16 num_qpairs; 561 u16 num_vectors; 562 u32 bw; 563 }; 564 565 struct bfa_ablk_cfg_port_s { 566 u8 mode; 567 u8 type; 568 u8 max_pfs; 569 u8 rsvd[5]; 570 }; 571 572 struct bfa_ablk_cfg_inst_s { 573 u8 nports; 574 u8 max_pfs; 575 u8 rsvd[6]; 576 struct bfa_ablk_cfg_pf_s pf_cfg[BFA_ABLK_MAX_PFS]; 577 struct bfa_ablk_cfg_port_s port_cfg[BFA_ABLK_MAX_PORTS]; 578 }; 579 580 struct bfa_ablk_cfg_s { 581 struct bfa_ablk_cfg_inst_s inst[BFA_ABLK_MAX]; 582 }; 583 584 585 /* 586 * SFP module specific 587 */ 588 #define SFP_DIAGMON_SIZE 10 /* num bytes of diag monitor data */ 589 590 enum bfa_defs_sfp_media_e { 591 BFA_SFP_MEDIA_UNKNOWN = 0x00, 592 BFA_SFP_MEDIA_CU = 0x01, 593 BFA_SFP_MEDIA_LW = 0x02, 594 BFA_SFP_MEDIA_SW = 0x03, 595 BFA_SFP_MEDIA_EL = 0x04, 596 BFA_SFP_MEDIA_UNSUPPORT = 0x05, 597 }; 598 599 /* 600 * values for xmtr_tech above 601 */ 602 enum { 603 SFP_XMTR_TECH_CU = (1 << 0), /* copper FC-BaseT */ 604 SFP_XMTR_TECH_CP = (1 << 1), /* copper passive */ 605 SFP_XMTR_TECH_CA = (1 << 2), /* copper active */ 606 SFP_XMTR_TECH_LL = (1 << 3), /* longwave laser */ 607 SFP_XMTR_TECH_SL = (1 << 4), /* shortwave laser w/ OFC */ 608 SFP_XMTR_TECH_SN = (1 << 5), /* shortwave laser w/o OFC */ 609 SFP_XMTR_TECH_EL_INTRA = (1 << 6), /* elec intra-enclosure */ 610 SFP_XMTR_TECH_EL_INTER = (1 << 7), /* elec inter-enclosure */ 611 SFP_XMTR_TECH_LC = (1 << 8), /* longwave laser */ 612 SFP_XMTR_TECH_SA = (1 << 9) 613 }; 614 615 /* 616 * Serial ID: Data Fields -- Address A0h 617 * Basic ID field total 64 bytes 618 */ 619 struct sfp_srlid_base_s { 620 u8 id; /* 00: Identifier */ 621 u8 extid; /* 01: Extended Identifier */ 622 u8 connector; /* 02: Connector */ 623 u8 xcvr[8]; /* 03-10: Transceiver */ 624 u8 encoding; /* 11: Encoding */ 625 u8 br_norm; /* 12: BR, Nominal */ 626 u8 rate_id; /* 13: Rate Identifier */ 627 u8 len_km; /* 14: Length single mode km */ 628 u8 len_100m; /* 15: Length single mode 100m */ 629 u8 len_om2; /* 16: Length om2 fiber 10m */ 630 u8 len_om1; /* 17: Length om1 fiber 10m */ 631 u8 len_cu; /* 18: Length copper 1m */ 632 u8 len_om3; /* 19: Length om3 fiber 10m */ 633 u8 vendor_name[16];/* 20-35 */ 634 u8 unalloc1; 635 u8 vendor_oui[3]; /* 37-39 */ 636 u8 vendor_pn[16]; /* 40-55 */ 637 u8 vendor_rev[4]; /* 56-59 */ 638 u8 wavelen[2]; /* 60-61 */ 639 u8 unalloc2; 640 u8 cc_base; /* 63: check code for base id field */ 641 }; 642 643 /* 644 * Serial ID: Data Fields -- Address A0h 645 * Extended id field total 32 bytes 646 */ 647 struct sfp_srlid_ext_s { 648 u8 options[2]; 649 u8 br_max; 650 u8 br_min; 651 u8 vendor_sn[16]; 652 u8 date_code[8]; 653 u8 diag_mon_type; /* 92: Diagnostic Monitoring type */ 654 u8 en_options; 655 u8 sff_8472; 656 u8 cc_ext; 657 }; 658 659 /* 660 * Diagnostic: Data Fields -- Address A2h 661 * Diagnostic and control/status base field total 96 bytes 662 */ 663 struct sfp_diag_base_s { 664 /* 665 * Alarm and warning Thresholds 40 bytes 666 */ 667 u8 temp_high_alarm[2]; /* 00-01 */ 668 u8 temp_low_alarm[2]; /* 02-03 */ 669 u8 temp_high_warning[2]; /* 04-05 */ 670 u8 temp_low_warning[2]; /* 06-07 */ 671 672 u8 volt_high_alarm[2]; /* 08-09 */ 673 u8 volt_low_alarm[2]; /* 10-11 */ 674 u8 volt_high_warning[2]; /* 12-13 */ 675 u8 volt_low_warning[2]; /* 14-15 */ 676 677 u8 bias_high_alarm[2]; /* 16-17 */ 678 u8 bias_low_alarm[2]; /* 18-19 */ 679 u8 bias_high_warning[2]; /* 20-21 */ 680 u8 bias_low_warning[2]; /* 22-23 */ 681 682 u8 tx_pwr_high_alarm[2]; /* 24-25 */ 683 u8 tx_pwr_low_alarm[2]; /* 26-27 */ 684 u8 tx_pwr_high_warning[2]; /* 28-29 */ 685 u8 tx_pwr_low_warning[2]; /* 30-31 */ 686 687 u8 rx_pwr_high_alarm[2]; /* 32-33 */ 688 u8 rx_pwr_low_alarm[2]; /* 34-35 */ 689 u8 rx_pwr_high_warning[2]; /* 36-37 */ 690 u8 rx_pwr_low_warning[2]; /* 38-39 */ 691 692 u8 unallocate_1[16]; 693 694 /* 695 * ext_cal_const[36] 696 */ 697 u8 rx_pwr[20]; 698 u8 tx_i[4]; 699 u8 tx_pwr[4]; 700 u8 temp[4]; 701 u8 volt[4]; 702 u8 unallocate_2[3]; 703 u8 cc_dmi; 704 }; 705 706 /* 707 * Diagnostic: Data Fields -- Address A2h 708 * Diagnostic and control/status extended field total 24 bytes 709 */ 710 struct sfp_diag_ext_s { 711 u8 diag[SFP_DIAGMON_SIZE]; 712 u8 unalloc1[4]; 713 u8 status_ctl; 714 u8 rsvd; 715 u8 alarm_flags[2]; 716 u8 unalloc2[2]; 717 u8 warning_flags[2]; 718 u8 ext_status_ctl[2]; 719 }; 720 721 struct sfp_mem_s { 722 struct sfp_srlid_base_s srlid_base; 723 struct sfp_srlid_ext_s srlid_ext; 724 struct sfp_diag_base_s diag_base; 725 struct sfp_diag_ext_s diag_ext; 726 }; 727 728 /* 729 * transceiver codes (SFF-8472 Rev 10.2 Table 3.5) 730 */ 731 union sfp_xcvr_e10g_code_u { 732 u8 b; 733 struct { 734 #ifdef __BIGENDIAN 735 u8 e10g_unall:1; /* 10G Ethernet compliance */ 736 u8 e10g_lrm:1; 737 u8 e10g_lr:1; 738 u8 e10g_sr:1; 739 u8 ib_sx:1; /* Infiniband compliance */ 740 u8 ib_lx:1; 741 u8 ib_cu_a:1; 742 u8 ib_cu_p:1; 743 #else 744 u8 ib_cu_p:1; 745 u8 ib_cu_a:1; 746 u8 ib_lx:1; 747 u8 ib_sx:1; /* Infiniband compliance */ 748 u8 e10g_sr:1; 749 u8 e10g_lr:1; 750 u8 e10g_lrm:1; 751 u8 e10g_unall:1; /* 10G Ethernet compliance */ 752 #endif 753 } r; 754 }; 755 756 union sfp_xcvr_so1_code_u { 757 u8 b; 758 struct { 759 u8 escon:2; /* ESCON compliance code */ 760 u8 oc192_reach:1; /* SONET compliance code */ 761 u8 so_reach:2; 762 u8 oc48_reach:3; 763 } r; 764 }; 765 766 union sfp_xcvr_so2_code_u { 767 u8 b; 768 struct { 769 u8 reserved:1; 770 u8 oc12_reach:3; /* OC12 reach */ 771 u8 reserved1:1; 772 u8 oc3_reach:3; /* OC3 reach */ 773 } r; 774 }; 775 776 union sfp_xcvr_eth_code_u { 777 u8 b; 778 struct { 779 u8 base_px:1; 780 u8 base_bx10:1; 781 u8 e100base_fx:1; 782 u8 e100base_lx:1; 783 u8 e1000base_t:1; 784 u8 e1000base_cx:1; 785 u8 e1000base_lx:1; 786 u8 e1000base_sx:1; 787 } r; 788 }; 789 790 struct sfp_xcvr_fc1_code_s { 791 u8 link_len:5; /* FC link length */ 792 u8 xmtr_tech2:3; 793 u8 xmtr_tech1:7; /* FC transmitter technology */ 794 u8 reserved1:1; 795 }; 796 797 union sfp_xcvr_fc2_code_u { 798 u8 b; 799 struct { 800 u8 tw_media:1; /* twin axial pair (tw) */ 801 u8 tp_media:1; /* shielded twisted pair (sp) */ 802 u8 mi_media:1; /* miniature coax (mi) */ 803 u8 tv_media:1; /* video coax (tv) */ 804 u8 m6_media:1; /* multimode, 62.5m (m6) */ 805 u8 m5_media:1; /* multimode, 50m (m5) */ 806 u8 reserved:1; 807 u8 sm_media:1; /* single mode (sm) */ 808 } r; 809 }; 810 811 union sfp_xcvr_fc3_code_u { 812 u8 b; 813 struct { 814 #ifdef __BIGENDIAN 815 u8 rsv4:1; 816 u8 mb800:1; /* 800 Mbytes/sec */ 817 u8 mb1600:1; /* 1600 Mbytes/sec */ 818 u8 mb400:1; /* 400 Mbytes/sec */ 819 u8 rsv2:1; 820 u8 mb200:1; /* 200 Mbytes/sec */ 821 u8 rsv1:1; 822 u8 mb100:1; /* 100 Mbytes/sec */ 823 #else 824 u8 mb100:1; /* 100 Mbytes/sec */ 825 u8 rsv1:1; 826 u8 mb200:1; /* 200 Mbytes/sec */ 827 u8 rsv2:1; 828 u8 mb400:1; /* 400 Mbytes/sec */ 829 u8 mb1600:1; /* 1600 Mbytes/sec */ 830 u8 mb800:1; /* 800 Mbytes/sec */ 831 u8 rsv4:1; 832 #endif 833 } r; 834 }; 835 836 struct sfp_xcvr_s { 837 union sfp_xcvr_e10g_code_u e10g; 838 union sfp_xcvr_so1_code_u so1; 839 union sfp_xcvr_so2_code_u so2; 840 union sfp_xcvr_eth_code_u eth; 841 struct sfp_xcvr_fc1_code_s fc1; 842 union sfp_xcvr_fc2_code_u fc2; 843 union sfp_xcvr_fc3_code_u fc3; 844 }; 845 846 /* 847 * Flash module specific 848 */ 849 #define BFA_FLASH_PART_ENTRY_SIZE 32 /* partition entry size */ 850 #define BFA_FLASH_PART_MAX 32 /* maximal # of partitions */ 851 852 enum bfa_flash_part_type { 853 BFA_FLASH_PART_OPTROM = 1, /* option rom partition */ 854 BFA_FLASH_PART_FWIMG = 2, /* firmware image partition */ 855 BFA_FLASH_PART_FWCFG = 3, /* firmware tuneable config */ 856 BFA_FLASH_PART_DRV = 4, /* IOC driver config */ 857 BFA_FLASH_PART_BOOT = 5, /* boot config */ 858 BFA_FLASH_PART_ASIC = 6, /* asic bootstrap configuration */ 859 BFA_FLASH_PART_MFG = 7, /* manufacturing block partition */ 860 BFA_FLASH_PART_OPTROM2 = 8, /* 2nd option rom partition */ 861 BFA_FLASH_PART_VPD = 9, /* vpd data of OEM info */ 862 BFA_FLASH_PART_PBC = 10, /* pre-boot config */ 863 BFA_FLASH_PART_BOOTOVL = 11, /* boot overlay partition */ 864 BFA_FLASH_PART_LOG = 12, /* firmware log partition */ 865 BFA_FLASH_PART_PXECFG = 13, /* pxe boot config partition */ 866 BFA_FLASH_PART_PXEOVL = 14, /* pxe boot overlay partition */ 867 BFA_FLASH_PART_PORTCFG = 15, /* port cfg partition */ 868 BFA_FLASH_PART_ASICBK = 16, /* asic backup partition */ 869 }; 870 871 /* 872 * flash partition attributes 873 */ 874 struct bfa_flash_part_attr_s { 875 u32 part_type; /* partition type */ 876 u32 part_instance; /* partition instance */ 877 u32 part_off; /* partition offset */ 878 u32 part_size; /* partition size */ 879 u32 part_len; /* partition content length */ 880 u32 part_status; /* partition status */ 881 char rsv[BFA_FLASH_PART_ENTRY_SIZE - 24]; 882 }; 883 884 /* 885 * flash attributes 886 */ 887 struct bfa_flash_attr_s { 888 u32 status; /* flash overall status */ 889 u32 npart; /* num of partitions */ 890 struct bfa_flash_part_attr_s part[BFA_FLASH_PART_MAX]; 891 }; 892 893 /* 894 * DIAG module specific 895 */ 896 #define LB_PATTERN_DEFAULT 0xB5B5B5B5 897 #define QTEST_CNT_DEFAULT 10 898 #define QTEST_PAT_DEFAULT LB_PATTERN_DEFAULT 899 900 struct bfa_diag_memtest_s { 901 u8 algo; 902 u8 rsvd[7]; 903 }; 904 905 struct bfa_diag_memtest_result { 906 u32 status; 907 u32 addr; 908 u32 exp; /* expect value read from reg */ 909 u32 act; /* actually value read */ 910 u32 err_status; /* error status reg */ 911 u32 err_status1; /* extra error info reg */ 912 u32 err_addr; /* error address reg */ 913 u8 algo; 914 u8 rsv[3]; 915 }; 916 917 struct bfa_diag_loopback_result_s { 918 u32 numtxmfrm; /* no. of transmit frame */ 919 u32 numosffrm; /* no. of outstanding frame */ 920 u32 numrcvfrm; /* no. of received good frame */ 921 u32 badfrminf; /* mis-match info */ 922 u32 badfrmnum; /* mis-match fram number */ 923 u8 status; /* loopback test result */ 924 u8 rsvd[3]; 925 }; 926 927 struct bfa_diag_ledtest_s { 928 u32 cmd; /* bfa_led_op_t */ 929 u32 color; /* bfa_led_color_t */ 930 u16 freq; /* no. of blinks every 10 secs */ 931 u8 led; /* bitmap of LEDs to be tested */ 932 u8 rsvd[5]; 933 }; 934 935 struct bfa_diag_loopback_s { 936 u32 loopcnt; 937 u32 pattern; 938 u8 lb_mode; /* bfa_port_opmode_t */ 939 u8 speed; /* bfa_port_speed_t */ 940 u8 rsvd[2]; 941 }; 942 943 /* 944 * PHY module specific 945 */ 946 enum bfa_phy_status_e { 947 BFA_PHY_STATUS_GOOD = 0, /* phy is good */ 948 BFA_PHY_STATUS_NOT_PRESENT = 1, /* phy does not exist */ 949 BFA_PHY_STATUS_BAD = 2, /* phy is bad */ 950 }; 951 952 /* 953 * phy attributes for phy query 954 */ 955 struct bfa_phy_attr_s { 956 u32 status; /* phy present/absent status */ 957 u32 length; /* firmware length */ 958 u32 fw_ver; /* firmware version */ 959 u32 an_status; /* AN status */ 960 u32 pma_pmd_status; /* PMA/PMD link status */ 961 u32 pma_pmd_signal; /* PMA/PMD signal detect */ 962 u32 pcs_status; /* PCS link status */ 963 }; 964 965 /* 966 * phy stats 967 */ 968 struct bfa_phy_stats_s { 969 u32 status; /* phy stats status */ 970 u32 link_breaks; /* Num of link breaks after linkup */ 971 u32 pma_pmd_fault; /* NPMA/PMD fault */ 972 u32 pcs_fault; /* PCS fault */ 973 u32 speed_neg; /* Num of speed negotiation */ 974 u32 tx_eq_training; /* Num of TX EQ training */ 975 u32 tx_eq_timeout; /* Num of TX EQ timeout */ 976 u32 crc_error; /* Num of CRC errors */ 977 }; 978 979 #pragma pack() 980 981 #endif /* __BFA_DEFS_H__ */ 982