1 /* 2 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc. 3 * Copyright (c) 2014- QLogic Corporation. 4 * All rights reserved 5 * www.qlogic.com 6 * 7 * Linux driver for QLogic BR-series Fibre Channel Host Bus Adapter. 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License (GPL) Version 2 as 11 * published by the Free Software Foundation 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 */ 18 19 #ifndef __BFA_DEFS_H__ 20 #define __BFA_DEFS_H__ 21 22 #include "bfa_fc.h" 23 #include "bfad_drv.h" 24 25 #define BFA_MFG_SERIALNUM_SIZE 11 26 #define STRSZ(_n) (((_n) + 4) & ~3) 27 28 /* 29 * Manufacturing card type 30 */ 31 enum { 32 BFA_MFG_TYPE_CB_MAX = 825, /* Crossbow card type max */ 33 BFA_MFG_TYPE_FC8P2 = 825, /* 8G 2port FC card */ 34 BFA_MFG_TYPE_FC8P1 = 815, /* 8G 1port FC card */ 35 BFA_MFG_TYPE_FC4P2 = 425, /* 4G 2port FC card */ 36 BFA_MFG_TYPE_FC4P1 = 415, /* 4G 1port FC card */ 37 BFA_MFG_TYPE_CNA10P2 = 1020, /* 10G 2port CNA card */ 38 BFA_MFG_TYPE_CNA10P1 = 1010, /* 10G 1port CNA card */ 39 BFA_MFG_TYPE_JAYHAWK = 804, /* Jayhawk mezz card */ 40 BFA_MFG_TYPE_WANCHESE = 1007, /* Wanchese mezz card */ 41 BFA_MFG_TYPE_ASTRA = 807, /* Astra mezz card */ 42 BFA_MFG_TYPE_LIGHTNING_P0 = 902, /* Lightning mezz card - old */ 43 BFA_MFG_TYPE_LIGHTNING = 1741, /* Lightning mezz card */ 44 BFA_MFG_TYPE_PROWLER_F = 1560, /* Prowler FC only cards */ 45 BFA_MFG_TYPE_PROWLER_N = 1410, /* Prowler NIC only cards */ 46 BFA_MFG_TYPE_PROWLER_C = 1710, /* Prowler CNA only cards */ 47 BFA_MFG_TYPE_PROWLER_D = 1860, /* Prowler Dual cards */ 48 BFA_MFG_TYPE_CHINOOK = 1867, /* Chinook cards */ 49 BFA_MFG_TYPE_CHINOOK2 = 1869, /*!< Chinook2 cards */ 50 BFA_MFG_TYPE_INVALID = 0, /* Invalid card type */ 51 }; 52 53 #pragma pack(1) 54 55 /* 56 * Check if Mezz card 57 */ 58 #define bfa_mfg_is_mezz(type) (( \ 59 (type) == BFA_MFG_TYPE_JAYHAWK || \ 60 (type) == BFA_MFG_TYPE_WANCHESE || \ 61 (type) == BFA_MFG_TYPE_ASTRA || \ 62 (type) == BFA_MFG_TYPE_LIGHTNING_P0 || \ 63 (type) == BFA_MFG_TYPE_LIGHTNING || \ 64 (type) == BFA_MFG_TYPE_CHINOOK || \ 65 (type) == BFA_MFG_TYPE_CHINOOK2)) 66 67 /* 68 * Check if the card having old wwn/mac handling 69 */ 70 #define bfa_mfg_is_old_wwn_mac_model(type) (( \ 71 (type) == BFA_MFG_TYPE_FC8P2 || \ 72 (type) == BFA_MFG_TYPE_FC8P1 || \ 73 (type) == BFA_MFG_TYPE_FC4P2 || \ 74 (type) == BFA_MFG_TYPE_FC4P1 || \ 75 (type) == BFA_MFG_TYPE_CNA10P2 || \ 76 (type) == BFA_MFG_TYPE_CNA10P1 || \ 77 (type) == BFA_MFG_TYPE_JAYHAWK || \ 78 (type) == BFA_MFG_TYPE_WANCHESE)) 79 80 #define bfa_mfg_increment_wwn_mac(m, i) \ 81 do { \ 82 u32 t = ((u32)(m)[0] << 16) | ((u32)(m)[1] << 8) | \ 83 (u32)(m)[2]; \ 84 t += (i); \ 85 (m)[0] = (t >> 16) & 0xFF; \ 86 (m)[1] = (t >> 8) & 0xFF; \ 87 (m)[2] = t & 0xFF; \ 88 } while (0) 89 90 /* 91 * VPD data length 92 */ 93 #define BFA_MFG_VPD_LEN 512 94 95 /* 96 * VPD vendor tag 97 */ 98 enum { 99 BFA_MFG_VPD_UNKNOWN = 0, /* vendor unknown */ 100 BFA_MFG_VPD_IBM = 1, /* vendor IBM */ 101 BFA_MFG_VPD_HP = 2, /* vendor HP */ 102 BFA_MFG_VPD_DELL = 3, /* vendor DELL */ 103 BFA_MFG_VPD_PCI_IBM = 0x08, /* PCI VPD IBM */ 104 BFA_MFG_VPD_PCI_HP = 0x10, /* PCI VPD HP */ 105 BFA_MFG_VPD_PCI_DELL = 0x20, /* PCI VPD DELL */ 106 BFA_MFG_VPD_PCI_BRCD = 0xf8, /* PCI VPD Brocade */ 107 }; 108 109 /* 110 * All numerical fields are in big-endian format. 111 */ 112 struct bfa_mfg_vpd_s { 113 u8 version; /* vpd data version */ 114 u8 vpd_sig[3]; /* characters 'V', 'P', 'D' */ 115 u8 chksum; /* u8 checksum */ 116 u8 vendor; /* vendor */ 117 u8 len; /* vpd data length excluding header */ 118 u8 rsv; 119 u8 data[BFA_MFG_VPD_LEN]; /* vpd data */ 120 }; 121 122 #pragma pack() 123 124 /* 125 * Status return values 126 */ 127 enum bfa_status { 128 BFA_STATUS_OK = 0, /* Success */ 129 BFA_STATUS_FAILED = 1, /* Operation failed */ 130 BFA_STATUS_EINVAL = 2, /* Invalid params Check input 131 * parameters */ 132 BFA_STATUS_ENOMEM = 3, /* Out of resources */ 133 BFA_STATUS_ETIMER = 5, /* Timer expired - Retry, if persists, 134 * contact support */ 135 BFA_STATUS_EPROTOCOL = 6, /* Protocol error */ 136 BFA_STATUS_BADFLASH = 9, /* Flash is bad */ 137 BFA_STATUS_SFP_UNSUPP = 10, /* Unsupported SFP - Replace SFP */ 138 BFA_STATUS_UNKNOWN_VFID = 11, /* VF_ID not found */ 139 BFA_STATUS_DATACORRUPTED = 12, /* Diag returned data corrupted */ 140 BFA_STATUS_DEVBUSY = 13, /* Device busy - Retry operation */ 141 BFA_STATUS_HDMA_FAILED = 16, /* Host dma failed contact support */ 142 BFA_STATUS_FLASH_BAD_LEN = 17, /* Flash bad length */ 143 BFA_STATUS_UNKNOWN_LWWN = 18, /* LPORT PWWN not found */ 144 BFA_STATUS_UNKNOWN_RWWN = 19, /* RPORT PWWN not found */ 145 BFA_STATUS_VPORT_EXISTS = 21, /* VPORT already exists */ 146 BFA_STATUS_VPORT_MAX = 22, /* Reached max VPORT supported limit */ 147 BFA_STATUS_UNSUPP_SPEED = 23, /* Invalid Speed Check speed setting */ 148 BFA_STATUS_INVLD_DFSZ = 24, /* Invalid Max data field size */ 149 BFA_STATUS_CMD_NOTSUPP = 26, /* Command/API not supported */ 150 BFA_STATUS_FABRIC_RJT = 29, /* Reject from attached fabric */ 151 BFA_STATUS_UNKNOWN_VWWN = 30, /* VPORT PWWN not found */ 152 BFA_STATUS_PORT_OFFLINE = 34, /* Port is not online */ 153 BFA_STATUS_VPORT_WWN_BP = 46, /* WWN is same as base port's WWN */ 154 BFA_STATUS_PORT_NOT_DISABLED = 47, /* Port not disabled disable port */ 155 BFA_STATUS_NO_FCPIM_NEXUS = 52, /* No FCP Nexus exists with the rport */ 156 BFA_STATUS_IOC_FAILURE = 56, /* IOC failure - Retry, if persists 157 * contact support */ 158 BFA_STATUS_INVALID_WWN = 57, /* Invalid WWN */ 159 BFA_STATUS_ADAPTER_ENABLED = 60, /* Adapter is not disabled */ 160 BFA_STATUS_IOC_NON_OP = 61, /* IOC is not operational */ 161 BFA_STATUS_VERSION_FAIL = 70, /* Application/Driver version mismatch */ 162 BFA_STATUS_DIAG_BUSY = 71, /* diag busy */ 163 BFA_STATUS_BEACON_ON = 72, /* Port Beacon already on */ 164 BFA_STATUS_ENOFSAVE = 78, /* No saved firmware trace */ 165 BFA_STATUS_IOC_DISABLED = 82, /* IOC is already disabled */ 166 BFA_STATUS_ERROR_TRL_ENABLED = 87, /* TRL is enabled */ 167 BFA_STATUS_ERROR_QOS_ENABLED = 88, /* QoS is enabled */ 168 BFA_STATUS_NO_SFP_DEV = 89, /* No SFP device check or replace SFP */ 169 BFA_STATUS_MEMTEST_FAILED = 90, /* Memory test failed contact support */ 170 BFA_STATUS_LEDTEST_OP = 109, /* LED test is operating */ 171 BFA_STATUS_INVALID_MAC = 134, /* Invalid MAC address */ 172 BFA_STATUS_CMD_NOTSUPP_CNA = 146, /* Command not supported for CNA */ 173 BFA_STATUS_PBC = 154, /* Operation not allowed for pre-boot 174 * configuration */ 175 BFA_STATUS_BAD_FWCFG = 156, /* Bad firmware configuration */ 176 BFA_STATUS_INVALID_VENDOR = 158, /* Invalid switch vendor */ 177 BFA_STATUS_SFP_NOT_READY = 159, /* SFP info is not ready. Retry */ 178 BFA_STATUS_TRUNK_ENABLED = 164, /* Trunk is already enabled on 179 * this adapter */ 180 BFA_STATUS_TRUNK_DISABLED = 165, /* Trunking is disabled on 181 * the adapter */ 182 BFA_STATUS_IOPROFILE_OFF = 175, /* IO profile OFF */ 183 BFA_STATUS_PHY_NOT_PRESENT = 183, /* PHY module not present */ 184 BFA_STATUS_FEATURE_NOT_SUPPORTED = 192, /* Feature not supported */ 185 BFA_STATUS_ENTRY_EXISTS = 193, /* Entry already exists */ 186 BFA_STATUS_ENTRY_NOT_EXISTS = 194, /* Entry does not exist */ 187 BFA_STATUS_NO_CHANGE = 195, /* Feature already in that state */ 188 BFA_STATUS_FAA_ENABLED = 197, /* FAA is already enabled */ 189 BFA_STATUS_FAA_DISABLED = 198, /* FAA is already disabled */ 190 BFA_STATUS_FAA_ACQUIRED = 199, /* FAA is already acquired */ 191 BFA_STATUS_FAA_ACQ_ADDR = 200, /* Acquiring addr */ 192 BFA_STATUS_BBCR_FC_ONLY = 201, /*!< BBCredit Recovery is supported for * 193 * FC mode only */ 194 BFA_STATUS_ERROR_TRUNK_ENABLED = 203, /* Trunk enabled on adapter */ 195 BFA_STATUS_MAX_ENTRY_REACHED = 212, /* MAX entry reached */ 196 BFA_STATUS_TOPOLOGY_LOOP = 230, /* Topology is set to Loop */ 197 BFA_STATUS_LOOP_UNSUPP_MEZZ = 231, /* Loop topology is not supported 198 * on mezz cards */ 199 BFA_STATUS_INVALID_BW = 233, /* Invalid bandwidth value */ 200 BFA_STATUS_QOS_BW_INVALID = 234, /* Invalid QOS bandwidth 201 * configuration */ 202 BFA_STATUS_DPORT_ENABLED = 235, /* D-port mode is already enabled */ 203 BFA_STATUS_DPORT_DISABLED = 236, /* D-port mode is already disabled */ 204 BFA_STATUS_CMD_NOTSUPP_MEZZ = 239, /* Cmd not supported for MEZZ card */ 205 BFA_STATUS_FRU_NOT_PRESENT = 240, /* fru module not present */ 206 BFA_STATUS_DPORT_NO_SFP = 243, /* SFP is not present.\n D-port will be 207 * enabled but it will be operational 208 * only after inserting a valid SFP. */ 209 BFA_STATUS_DPORT_ERR = 245, /* D-port mode is enabled */ 210 BFA_STATUS_DPORT_ENOSYS = 254, /* Switch has no D_Port functionality */ 211 BFA_STATUS_DPORT_CANT_PERF = 255, /* Switch port is not D_Port capable 212 * or D_Port is disabled */ 213 BFA_STATUS_DPORT_LOGICALERR = 256, /* Switch D_Port fail */ 214 BFA_STATUS_DPORT_SWBUSY = 257, /* Switch port busy */ 215 BFA_STATUS_ERR_BBCR_SPEED_UNSUPPORT = 258, /*!< BB credit recovery is 216 * supported at max port speed alone */ 217 BFA_STATUS_ERROR_BBCR_ENABLED = 259, /*!< BB credit recovery 218 * is enabled */ 219 BFA_STATUS_INVALID_BBSCN = 260, /*!< Invalid BBSCN value. 220 * Valid range is [1-15] */ 221 BFA_STATUS_DDPORT_ERR = 261, /* Dynamic D_Port mode is active.\n To 222 * exit dynamic mode, disable D_Port on 223 * the remote port */ 224 BFA_STATUS_DPORT_SFPWRAP_ERR = 262, /* Clear e/o_wrap fail, check or 225 * replace SFP */ 226 BFA_STATUS_BBCR_CFG_NO_CHANGE = 265, /*!< BBCR is operational. 227 * Disable BBCR and try this operation again. */ 228 BFA_STATUS_DPORT_SW_NOTREADY = 268, /* Remote port is not ready to 229 * start dport test. Check remote 230 * port status. */ 231 BFA_STATUS_DPORT_INV_SFP = 271, /* Invalid SFP for D-PORT mode. */ 232 BFA_STATUS_DPORT_CMD_NOTSUPP = 273, /* Dport is not supported by 233 * remote port */ 234 BFA_STATUS_MAX_VAL /* Unknown error code */ 235 }; 236 #define bfa_status_t enum bfa_status 237 238 enum bfa_eproto_status { 239 BFA_EPROTO_BAD_ACCEPT = 0, 240 BFA_EPROTO_UNKNOWN_RSP = 1 241 }; 242 #define bfa_eproto_status_t enum bfa_eproto_status 243 244 enum bfa_boolean { 245 BFA_FALSE = 0, 246 BFA_TRUE = 1 247 }; 248 #define bfa_boolean_t enum bfa_boolean 249 250 #define BFA_STRING_32 32 251 #define BFA_VERSION_LEN 64 252 253 /* 254 * ---------------------- adapter definitions ------------ 255 */ 256 257 /* 258 * BFA adapter level attributes. 259 */ 260 enum { 261 BFA_ADAPTER_SERIAL_NUM_LEN = STRSZ(BFA_MFG_SERIALNUM_SIZE), 262 /* 263 *!< adapter serial num length 264 */ 265 BFA_ADAPTER_MODEL_NAME_LEN = 16, /* model name length */ 266 BFA_ADAPTER_MODEL_DESCR_LEN = 128, /* model description length */ 267 BFA_ADAPTER_MFG_NAME_LEN = 8, /* manufacturer name length */ 268 BFA_ADAPTER_SYM_NAME_LEN = 64, /* adapter symbolic name length */ 269 BFA_ADAPTER_OS_TYPE_LEN = 64, /* adapter os type length */ 270 BFA_ADAPTER_UUID_LEN = 16, /* adapter uuid length */ 271 }; 272 273 struct bfa_adapter_attr_s { 274 char manufacturer[BFA_ADAPTER_MFG_NAME_LEN]; 275 char serial_num[BFA_ADAPTER_SERIAL_NUM_LEN]; 276 u32 card_type; 277 char model[BFA_ADAPTER_MODEL_NAME_LEN]; 278 char model_descr[BFA_ADAPTER_MODEL_DESCR_LEN]; 279 wwn_t pwwn; 280 char node_symname[FC_SYMNAME_MAX]; 281 char hw_ver[BFA_VERSION_LEN]; 282 char fw_ver[BFA_VERSION_LEN]; 283 char optrom_ver[BFA_VERSION_LEN]; 284 char os_type[BFA_ADAPTER_OS_TYPE_LEN]; 285 struct bfa_mfg_vpd_s vpd; 286 struct mac_s mac; 287 288 u8 nports; 289 u8 max_speed; 290 u8 prototype; 291 char asic_rev; 292 293 u8 pcie_gen; 294 u8 pcie_lanes_orig; 295 u8 pcie_lanes; 296 u8 cna_capable; 297 298 u8 is_mezz; 299 u8 trunk_capable; 300 u8 mfg_day; /* manufacturing day */ 301 u8 mfg_month; /* manufacturing month */ 302 u16 mfg_year; /* manufacturing year */ 303 u16 rsvd; 304 u8 uuid[BFA_ADAPTER_UUID_LEN]; 305 }; 306 307 /* 308 * ---------------------- IOC definitions ------------ 309 */ 310 311 enum { 312 BFA_IOC_DRIVER_LEN = 16, 313 BFA_IOC_CHIP_REV_LEN = 8, 314 }; 315 316 /* 317 * Driver and firmware versions. 318 */ 319 struct bfa_ioc_driver_attr_s { 320 char driver[BFA_IOC_DRIVER_LEN]; /* driver name */ 321 char driver_ver[BFA_VERSION_LEN]; /* driver version */ 322 char fw_ver[BFA_VERSION_LEN]; /* firmware version */ 323 char bios_ver[BFA_VERSION_LEN]; /* bios version */ 324 char efi_ver[BFA_VERSION_LEN]; /* EFI version */ 325 char ob_ver[BFA_VERSION_LEN]; /* openboot version */ 326 }; 327 328 /* 329 * IOC PCI device attributes 330 */ 331 struct bfa_ioc_pci_attr_s { 332 u16 vendor_id; /* PCI vendor ID */ 333 u16 device_id; /* PCI device ID */ 334 u16 ssid; /* subsystem ID */ 335 u16 ssvid; /* subsystem vendor ID */ 336 u32 pcifn; /* PCI device function */ 337 u32 rsvd; /* padding */ 338 char chip_rev[BFA_IOC_CHIP_REV_LEN]; /* chip revision */ 339 }; 340 341 /* 342 * IOC states 343 */ 344 enum bfa_ioc_state { 345 BFA_IOC_UNINIT = 1, /* IOC is in uninit state */ 346 BFA_IOC_RESET = 2, /* IOC is in reset state */ 347 BFA_IOC_SEMWAIT = 3, /* Waiting for IOC h/w semaphore */ 348 BFA_IOC_HWINIT = 4, /* IOC h/w is being initialized */ 349 BFA_IOC_GETATTR = 5, /* IOC is being configured */ 350 BFA_IOC_OPERATIONAL = 6, /* IOC is operational */ 351 BFA_IOC_INITFAIL = 7, /* IOC hardware failure */ 352 BFA_IOC_FAIL = 8, /* IOC heart-beat failure */ 353 BFA_IOC_DISABLING = 9, /* IOC is being disabled */ 354 BFA_IOC_DISABLED = 10, /* IOC is disabled */ 355 BFA_IOC_FWMISMATCH = 11, /* IOC f/w different from drivers */ 356 BFA_IOC_ENABLING = 12, /* IOC is being enabled */ 357 BFA_IOC_HWFAIL = 13, /* PCI mapping doesn't exist */ 358 BFA_IOC_ACQ_ADDR = 14, /* Acquiring addr from fabric */ 359 }; 360 361 /* 362 * IOC firmware stats 363 */ 364 struct bfa_fw_ioc_stats_s { 365 u32 enable_reqs; 366 u32 disable_reqs; 367 u32 get_attr_reqs; 368 u32 dbg_sync; 369 u32 dbg_dump; 370 u32 unknown_reqs; 371 }; 372 373 /* 374 * IOC driver stats 375 */ 376 struct bfa_ioc_drv_stats_s { 377 u32 ioc_isrs; 378 u32 ioc_enables; 379 u32 ioc_disables; 380 u32 ioc_hbfails; 381 u32 ioc_boots; 382 u32 stats_tmos; 383 u32 hb_count; 384 u32 disable_reqs; 385 u32 enable_reqs; 386 u32 disable_replies; 387 u32 enable_replies; 388 u32 rsvd; 389 }; 390 391 /* 392 * IOC statistics 393 */ 394 struct bfa_ioc_stats_s { 395 struct bfa_ioc_drv_stats_s drv_stats; /* driver IOC stats */ 396 struct bfa_fw_ioc_stats_s fw_stats; /* firmware IOC stats */ 397 }; 398 399 enum bfa_ioc_type_e { 400 BFA_IOC_TYPE_FC = 1, 401 BFA_IOC_TYPE_FCoE = 2, 402 BFA_IOC_TYPE_LL = 3, 403 }; 404 405 /* 406 * IOC attributes returned in queries 407 */ 408 struct bfa_ioc_attr_s { 409 enum bfa_ioc_type_e ioc_type; 410 enum bfa_ioc_state state; /* IOC state */ 411 struct bfa_adapter_attr_s adapter_attr; /* HBA attributes */ 412 struct bfa_ioc_driver_attr_s driver_attr; /* driver attr */ 413 struct bfa_ioc_pci_attr_s pci_attr; 414 u8 port_id; /* port number */ 415 u8 port_mode; /* bfa_mode_s */ 416 u8 cap_bm; /* capability */ 417 u8 port_mode_cfg; /* bfa_mode_s */ 418 u8 def_fn; /* 1 if default fn */ 419 u8 rsvd[3]; /* 64bit align */ 420 }; 421 422 /* 423 * AEN related definitions 424 */ 425 enum bfa_aen_category { 426 BFA_AEN_CAT_ADAPTER = 1, 427 BFA_AEN_CAT_PORT = 2, 428 BFA_AEN_CAT_LPORT = 3, 429 BFA_AEN_CAT_RPORT = 4, 430 BFA_AEN_CAT_ITNIM = 5, 431 BFA_AEN_CAT_AUDIT = 8, 432 BFA_AEN_CAT_IOC = 9, 433 }; 434 435 /* BFA adapter level events */ 436 enum bfa_adapter_aen_event { 437 BFA_ADAPTER_AEN_ADD = 1, /* New Adapter found event */ 438 BFA_ADAPTER_AEN_REMOVE = 2, /* Adapter removed event */ 439 }; 440 441 struct bfa_adapter_aen_data_s { 442 char serial_num[BFA_ADAPTER_SERIAL_NUM_LEN]; 443 u32 nports; /* Number of NPorts */ 444 wwn_t pwwn; /* WWN of one of its physical port */ 445 }; 446 447 /* BFA physical port Level events */ 448 enum bfa_port_aen_event { 449 BFA_PORT_AEN_ONLINE = 1, /* Physical Port online event */ 450 BFA_PORT_AEN_OFFLINE = 2, /* Physical Port offline event */ 451 BFA_PORT_AEN_RLIR = 3, /* RLIR event, not supported */ 452 BFA_PORT_AEN_SFP_INSERT = 4, /* SFP inserted event */ 453 BFA_PORT_AEN_SFP_REMOVE = 5, /* SFP removed event */ 454 BFA_PORT_AEN_SFP_POM = 6, /* SFP POM event */ 455 BFA_PORT_AEN_ENABLE = 7, /* Physical Port enable event */ 456 BFA_PORT_AEN_DISABLE = 8, /* Physical Port disable event */ 457 BFA_PORT_AEN_AUTH_ON = 9, /* Physical Port auth success event */ 458 BFA_PORT_AEN_AUTH_OFF = 10, /* Physical Port auth fail event */ 459 BFA_PORT_AEN_DISCONNECT = 11, /* Physical Port disconnect event */ 460 BFA_PORT_AEN_QOS_NEG = 12, /* Base Port QOS negotiation event */ 461 BFA_PORT_AEN_FABRIC_NAME_CHANGE = 13, /* Fabric Name/WWN change */ 462 BFA_PORT_AEN_SFP_ACCESS_ERROR = 14, /* SFP read error event */ 463 BFA_PORT_AEN_SFP_UNSUPPORT = 15, /* Unsupported SFP event */ 464 }; 465 466 enum bfa_port_aen_sfp_pom { 467 BFA_PORT_AEN_SFP_POM_GREEN = 1, /* Normal */ 468 BFA_PORT_AEN_SFP_POM_AMBER = 2, /* Warning */ 469 BFA_PORT_AEN_SFP_POM_RED = 3, /* Critical */ 470 BFA_PORT_AEN_SFP_POM_MAX = BFA_PORT_AEN_SFP_POM_RED 471 }; 472 473 struct bfa_port_aen_data_s { 474 wwn_t pwwn; /* WWN of the physical port */ 475 wwn_t fwwn; /* WWN of the fabric port */ 476 u32 phy_port_num; /* For SFP related events */ 477 u16 ioc_type; 478 u16 level; /* Only transitions will be informed */ 479 mac_t mac; /* MAC address of the ethernet port */ 480 u16 rsvd; 481 }; 482 483 /* BFA AEN logical port events */ 484 enum bfa_lport_aen_event { 485 BFA_LPORT_AEN_NEW = 1, /* LPort created event */ 486 BFA_LPORT_AEN_DELETE = 2, /* LPort deleted event */ 487 BFA_LPORT_AEN_ONLINE = 3, /* LPort online event */ 488 BFA_LPORT_AEN_OFFLINE = 4, /* LPort offline event */ 489 BFA_LPORT_AEN_DISCONNECT = 5, /* LPort disconnect event */ 490 BFA_LPORT_AEN_NEW_PROP = 6, /* VPort created event */ 491 BFA_LPORT_AEN_DELETE_PROP = 7, /* VPort deleted event */ 492 BFA_LPORT_AEN_NEW_STANDARD = 8, /* VPort created event */ 493 BFA_LPORT_AEN_DELETE_STANDARD = 9, /* VPort deleted event */ 494 BFA_LPORT_AEN_NPIV_DUP_WWN = 10, /* VPort with duplicate WWN */ 495 BFA_LPORT_AEN_NPIV_FABRIC_MAX = 11, /* Max NPIV in fabric/fport */ 496 BFA_LPORT_AEN_NPIV_UNKNOWN = 12, /* Unknown NPIV Error code */ 497 }; 498 499 struct bfa_lport_aen_data_s { 500 u16 vf_id; /* vf_id of this logical port */ 501 u16 roles; /* Logical port mode,IM/TM/IP etc */ 502 u32 rsvd; 503 wwn_t ppwwn; /* WWN of its physical port */ 504 wwn_t lpwwn; /* WWN of this logical port */ 505 }; 506 507 /* BFA ITNIM events */ 508 enum bfa_itnim_aen_event { 509 BFA_ITNIM_AEN_ONLINE = 1, /* Target online */ 510 BFA_ITNIM_AEN_OFFLINE = 2, /* Target offline */ 511 BFA_ITNIM_AEN_DISCONNECT = 3, /* Target disconnected */ 512 }; 513 514 struct bfa_itnim_aen_data_s { 515 u16 vf_id; /* vf_id of the IT nexus */ 516 u16 rsvd[3]; 517 wwn_t ppwwn; /* WWN of its physical port */ 518 wwn_t lpwwn; /* WWN of logical port */ 519 wwn_t rpwwn; /* WWN of remote(target) port */ 520 }; 521 522 /* BFA audit events */ 523 enum bfa_audit_aen_event { 524 BFA_AUDIT_AEN_AUTH_ENABLE = 1, 525 BFA_AUDIT_AEN_AUTH_DISABLE = 2, 526 BFA_AUDIT_AEN_FLASH_ERASE = 3, 527 BFA_AUDIT_AEN_FLASH_UPDATE = 4, 528 }; 529 530 struct bfa_audit_aen_data_s { 531 wwn_t pwwn; 532 int partition_inst; 533 int partition_type; 534 }; 535 536 /* BFA IOC level events */ 537 enum bfa_ioc_aen_event { 538 BFA_IOC_AEN_HBGOOD = 1, /* Heart Beat restore event */ 539 BFA_IOC_AEN_HBFAIL = 2, /* Heart Beat failure event */ 540 BFA_IOC_AEN_ENABLE = 3, /* IOC enabled event */ 541 BFA_IOC_AEN_DISABLE = 4, /* IOC disabled event */ 542 BFA_IOC_AEN_FWMISMATCH = 5, /* IOC firmware mismatch */ 543 BFA_IOC_AEN_FWCFG_ERROR = 6, /* IOC firmware config error */ 544 BFA_IOC_AEN_INVALID_VENDOR = 7, 545 BFA_IOC_AEN_INVALID_NWWN = 8, /* Zero NWWN */ 546 BFA_IOC_AEN_INVALID_PWWN = 9 /* Zero PWWN */ 547 }; 548 549 struct bfa_ioc_aen_data_s { 550 wwn_t pwwn; 551 u16 ioc_type; 552 mac_t mac; 553 }; 554 555 /* 556 * ---------------------- mfg definitions ------------ 557 */ 558 559 /* 560 * Checksum size 561 */ 562 #define BFA_MFG_CHKSUM_SIZE 16 563 564 #define BFA_MFG_PARTNUM_SIZE 14 565 #define BFA_MFG_SUPPLIER_ID_SIZE 10 566 #define BFA_MFG_SUPPLIER_PARTNUM_SIZE 20 567 #define BFA_MFG_SUPPLIER_SERIALNUM_SIZE 20 568 #define BFA_MFG_SUPPLIER_REVISION_SIZE 4 569 /* 570 * Initial capability definition 571 */ 572 #define BFA_MFG_IC_FC 0x01 573 #define BFA_MFG_IC_ETH 0x02 574 575 /* 576 * Adapter capability mask definition 577 */ 578 #define BFA_CM_HBA 0x01 579 #define BFA_CM_CNA 0x02 580 #define BFA_CM_NIC 0x04 581 #define BFA_CM_FC16G 0x08 582 #define BFA_CM_SRIOV 0x10 583 #define BFA_CM_MEZZ 0x20 584 585 #pragma pack(1) 586 587 /* 588 * All numerical fields are in big-endian format. 589 */ 590 struct bfa_mfg_block_s { 591 u8 version; /*!< manufacturing block version */ 592 u8 mfg_sig[3]; /*!< characters 'M', 'F', 'G' */ 593 u16 mfgsize; /*!< mfg block size */ 594 u16 u16_chksum; /*!< old u16 checksum */ 595 char brcd_serialnum[STRSZ(BFA_MFG_SERIALNUM_SIZE)]; 596 char brcd_partnum[STRSZ(BFA_MFG_PARTNUM_SIZE)]; 597 u8 mfg_day; /*!< manufacturing day */ 598 u8 mfg_month; /*!< manufacturing month */ 599 u16 mfg_year; /*!< manufacturing year */ 600 wwn_t mfg_wwn; /*!< wwn base for this adapter */ 601 u8 num_wwn; /*!< number of wwns assigned */ 602 u8 mfg_speeds; /*!< speeds allowed for this adapter */ 603 u8 rsv[2]; 604 char supplier_id[STRSZ(BFA_MFG_SUPPLIER_ID_SIZE)]; 605 char supplier_partnum[STRSZ(BFA_MFG_SUPPLIER_PARTNUM_SIZE)]; 606 char supplier_serialnum[STRSZ(BFA_MFG_SUPPLIER_SERIALNUM_SIZE)]; 607 char supplier_revision[STRSZ(BFA_MFG_SUPPLIER_REVISION_SIZE)]; 608 mac_t mfg_mac; /*!< base mac address */ 609 u8 num_mac; /*!< number of mac addresses */ 610 u8 rsv2; 611 u32 card_type; /*!< card type */ 612 char cap_nic; /*!< capability nic */ 613 char cap_cna; /*!< capability cna */ 614 char cap_hba; /*!< capability hba */ 615 char cap_fc16g; /*!< capability fc 16g */ 616 char cap_sriov; /*!< capability sriov */ 617 char cap_mezz; /*!< capability mezz */ 618 u8 rsv3; 619 u8 mfg_nports; /*!< number of ports */ 620 char media[8]; /*!< xfi/xaui */ 621 char initial_mode[8]; /*!< initial mode: hba/cna/nic */ 622 u8 rsv4[84]; 623 u8 md5_chksum[BFA_MFG_CHKSUM_SIZE]; /*!< md5 checksum */ 624 }; 625 626 #pragma pack() 627 628 /* 629 * ---------------------- pci definitions ------------ 630 */ 631 632 /* 633 * PCI device and vendor ID information 634 */ 635 enum { 636 BFA_PCI_VENDOR_ID_BROCADE = 0x1657, 637 BFA_PCI_DEVICE_ID_FC_8G2P = 0x13, 638 BFA_PCI_DEVICE_ID_FC_8G1P = 0x17, 639 BFA_PCI_DEVICE_ID_CT = 0x14, 640 BFA_PCI_DEVICE_ID_CT_FC = 0x21, 641 BFA_PCI_DEVICE_ID_CT2 = 0x22, 642 BFA_PCI_DEVICE_ID_CT2_QUAD = 0x23, 643 }; 644 645 #define bfa_asic_id_cb(__d) \ 646 ((__d) == BFA_PCI_DEVICE_ID_FC_8G2P || \ 647 (__d) == BFA_PCI_DEVICE_ID_FC_8G1P) 648 #define bfa_asic_id_ct(__d) \ 649 ((__d) == BFA_PCI_DEVICE_ID_CT || \ 650 (__d) == BFA_PCI_DEVICE_ID_CT_FC) 651 #define bfa_asic_id_ct2(__d) \ 652 ((__d) == BFA_PCI_DEVICE_ID_CT2 || \ 653 (__d) == BFA_PCI_DEVICE_ID_CT2_QUAD) 654 #define bfa_asic_id_ctc(__d) \ 655 (bfa_asic_id_ct(__d) || bfa_asic_id_ct2(__d)) 656 657 /* 658 * PCI sub-system device and vendor ID information 659 */ 660 enum { 661 BFA_PCI_FCOE_SSDEVICE_ID = 0x14, 662 BFA_PCI_CT2_SSID_FCoE = 0x22, 663 BFA_PCI_CT2_SSID_ETH = 0x23, 664 BFA_PCI_CT2_SSID_FC = 0x24, 665 }; 666 667 /* 668 * Maximum number of device address ranges mapped through different BAR(s) 669 */ 670 #define BFA_PCI_ACCESS_RANGES 1 671 672 /* 673 * Port speed settings. Each specific speed is a bit field. Use multiple 674 * bits to specify speeds to be selected for auto-negotiation. 675 */ 676 enum bfa_port_speed { 677 BFA_PORT_SPEED_UNKNOWN = 0, 678 BFA_PORT_SPEED_1GBPS = 1, 679 BFA_PORT_SPEED_2GBPS = 2, 680 BFA_PORT_SPEED_4GBPS = 4, 681 BFA_PORT_SPEED_8GBPS = 8, 682 BFA_PORT_SPEED_10GBPS = 10, 683 BFA_PORT_SPEED_16GBPS = 16, 684 BFA_PORT_SPEED_AUTO = 0xf, 685 }; 686 #define bfa_port_speed_t enum bfa_port_speed 687 688 enum { 689 BFA_BOOT_BOOTLUN_MAX = 4, /* maximum boot lun per IOC */ 690 BFA_PREBOOT_BOOTLUN_MAX = 8, /* maximum preboot lun per IOC */ 691 }; 692 693 #define BOOT_CFG_REV1 1 694 #define BOOT_CFG_VLAN 1 695 696 /* 697 * Boot options setting. Boot options setting determines from where 698 * to get the boot lun information 699 */ 700 enum bfa_boot_bootopt { 701 BFA_BOOT_AUTO_DISCOVER = 0, /* Boot from blun provided by fabric */ 702 BFA_BOOT_STORED_BLUN = 1, /* Boot from bluns stored in flash */ 703 BFA_BOOT_FIRST_LUN = 2, /* Boot from first discovered blun */ 704 BFA_BOOT_PBC = 3, /* Boot from pbc configured blun */ 705 }; 706 707 #pragma pack(1) 708 /* 709 * Boot lun information. 710 */ 711 struct bfa_boot_bootlun_s { 712 wwn_t pwwn; /* port wwn of target */ 713 struct scsi_lun lun; /* 64-bit lun */ 714 }; 715 #pragma pack() 716 717 /* 718 * BOOT boot configuraton 719 */ 720 struct bfa_boot_cfg_s { 721 u8 version; 722 u8 rsvd1; 723 u16 chksum; 724 u8 enable; /* enable/disable SAN boot */ 725 u8 speed; /* boot speed settings */ 726 u8 topology; /* boot topology setting */ 727 u8 bootopt; /* bfa_boot_bootopt_t */ 728 u32 nbluns; /* number of boot luns */ 729 u32 rsvd2; 730 struct bfa_boot_bootlun_s blun[BFA_BOOT_BOOTLUN_MAX]; 731 struct bfa_boot_bootlun_s blun_disc[BFA_BOOT_BOOTLUN_MAX]; 732 }; 733 734 struct bfa_boot_pbc_s { 735 u8 enable; /* enable/disable SAN boot */ 736 u8 speed; /* boot speed settings */ 737 u8 topology; /* boot topology setting */ 738 u8 rsvd1; 739 u32 nbluns; /* number of boot luns */ 740 struct bfa_boot_bootlun_s pblun[BFA_PREBOOT_BOOTLUN_MAX]; 741 }; 742 743 struct bfa_ethboot_cfg_s { 744 u8 version; 745 u8 rsvd1; 746 u16 chksum; 747 u8 enable; /* enable/disable Eth/PXE boot */ 748 u8 rsvd2; 749 u16 vlan; 750 }; 751 752 /* 753 * ASIC block configuration related structures 754 */ 755 #define BFA_ABLK_MAX_PORTS 2 756 #define BFA_ABLK_MAX_PFS 16 757 #define BFA_ABLK_MAX 2 758 759 #pragma pack(1) 760 enum bfa_mode_s { 761 BFA_MODE_HBA = 1, 762 BFA_MODE_CNA = 2, 763 BFA_MODE_NIC = 3 764 }; 765 766 struct bfa_adapter_cfg_mode_s { 767 u16 max_pf; 768 u16 max_vf; 769 enum bfa_mode_s mode; 770 }; 771 772 struct bfa_ablk_cfg_pf_s { 773 u16 pers; 774 u8 port_id; 775 u8 optrom; 776 u8 valid; 777 u8 sriov; 778 u8 max_vfs; 779 u8 rsvd[1]; 780 u16 num_qpairs; 781 u16 num_vectors; 782 u16 bw_min; 783 u16 bw_max; 784 }; 785 786 struct bfa_ablk_cfg_port_s { 787 u8 mode; 788 u8 type; 789 u8 max_pfs; 790 u8 rsvd[5]; 791 }; 792 793 struct bfa_ablk_cfg_inst_s { 794 u8 nports; 795 u8 max_pfs; 796 u8 rsvd[6]; 797 struct bfa_ablk_cfg_pf_s pf_cfg[BFA_ABLK_MAX_PFS]; 798 struct bfa_ablk_cfg_port_s port_cfg[BFA_ABLK_MAX_PORTS]; 799 }; 800 801 struct bfa_ablk_cfg_s { 802 struct bfa_ablk_cfg_inst_s inst[BFA_ABLK_MAX]; 803 }; 804 805 806 /* 807 * SFP module specific 808 */ 809 #define SFP_DIAGMON_SIZE 10 /* num bytes of diag monitor data */ 810 811 /* SFP state change notification event */ 812 #define BFA_SFP_SCN_REMOVED 0 813 #define BFA_SFP_SCN_INSERTED 1 814 #define BFA_SFP_SCN_POM 2 815 #define BFA_SFP_SCN_FAILED 3 816 #define BFA_SFP_SCN_UNSUPPORT 4 817 #define BFA_SFP_SCN_VALID 5 818 819 enum bfa_defs_sfp_media_e { 820 BFA_SFP_MEDIA_UNKNOWN = 0x00, 821 BFA_SFP_MEDIA_CU = 0x01, 822 BFA_SFP_MEDIA_LW = 0x02, 823 BFA_SFP_MEDIA_SW = 0x03, 824 BFA_SFP_MEDIA_EL = 0x04, 825 BFA_SFP_MEDIA_UNSUPPORT = 0x05, 826 }; 827 828 /* 829 * values for xmtr_tech above 830 */ 831 enum { 832 SFP_XMTR_TECH_CU = (1 << 0), /* copper FC-BaseT */ 833 SFP_XMTR_TECH_CP = (1 << 1), /* copper passive */ 834 SFP_XMTR_TECH_CA = (1 << 2), /* copper active */ 835 SFP_XMTR_TECH_LL = (1 << 3), /* longwave laser */ 836 SFP_XMTR_TECH_SL = (1 << 4), /* shortwave laser w/ OFC */ 837 SFP_XMTR_TECH_SN = (1 << 5), /* shortwave laser w/o OFC */ 838 SFP_XMTR_TECH_EL_INTRA = (1 << 6), /* elec intra-enclosure */ 839 SFP_XMTR_TECH_EL_INTER = (1 << 7), /* elec inter-enclosure */ 840 SFP_XMTR_TECH_LC = (1 << 8), /* longwave laser */ 841 SFP_XMTR_TECH_SA = (1 << 9) 842 }; 843 844 /* 845 * Serial ID: Data Fields -- Address A0h 846 * Basic ID field total 64 bytes 847 */ 848 struct sfp_srlid_base_s { 849 u8 id; /* 00: Identifier */ 850 u8 extid; /* 01: Extended Identifier */ 851 u8 connector; /* 02: Connector */ 852 u8 xcvr[8]; /* 03-10: Transceiver */ 853 u8 encoding; /* 11: Encoding */ 854 u8 br_norm; /* 12: BR, Nominal */ 855 u8 rate_id; /* 13: Rate Identifier */ 856 u8 len_km; /* 14: Length single mode km */ 857 u8 len_100m; /* 15: Length single mode 100m */ 858 u8 len_om2; /* 16: Length om2 fiber 10m */ 859 u8 len_om1; /* 17: Length om1 fiber 10m */ 860 u8 len_cu; /* 18: Length copper 1m */ 861 u8 len_om3; /* 19: Length om3 fiber 10m */ 862 u8 vendor_name[16];/* 20-35 */ 863 u8 unalloc1; 864 u8 vendor_oui[3]; /* 37-39 */ 865 u8 vendor_pn[16]; /* 40-55 */ 866 u8 vendor_rev[4]; /* 56-59 */ 867 u8 wavelen[2]; /* 60-61 */ 868 u8 unalloc2; 869 u8 cc_base; /* 63: check code for base id field */ 870 }; 871 872 /* 873 * Serial ID: Data Fields -- Address A0h 874 * Extended id field total 32 bytes 875 */ 876 struct sfp_srlid_ext_s { 877 u8 options[2]; 878 u8 br_max; 879 u8 br_min; 880 u8 vendor_sn[16]; 881 u8 date_code[8]; 882 u8 diag_mon_type; /* 92: Diagnostic Monitoring type */ 883 u8 en_options; 884 u8 sff_8472; 885 u8 cc_ext; 886 }; 887 888 /* 889 * Diagnostic: Data Fields -- Address A2h 890 * Diagnostic and control/status base field total 96 bytes 891 */ 892 struct sfp_diag_base_s { 893 /* 894 * Alarm and warning Thresholds 40 bytes 895 */ 896 u8 temp_high_alarm[2]; /* 00-01 */ 897 u8 temp_low_alarm[2]; /* 02-03 */ 898 u8 temp_high_warning[2]; /* 04-05 */ 899 u8 temp_low_warning[2]; /* 06-07 */ 900 901 u8 volt_high_alarm[2]; /* 08-09 */ 902 u8 volt_low_alarm[2]; /* 10-11 */ 903 u8 volt_high_warning[2]; /* 12-13 */ 904 u8 volt_low_warning[2]; /* 14-15 */ 905 906 u8 bias_high_alarm[2]; /* 16-17 */ 907 u8 bias_low_alarm[2]; /* 18-19 */ 908 u8 bias_high_warning[2]; /* 20-21 */ 909 u8 bias_low_warning[2]; /* 22-23 */ 910 911 u8 tx_pwr_high_alarm[2]; /* 24-25 */ 912 u8 tx_pwr_low_alarm[2]; /* 26-27 */ 913 u8 tx_pwr_high_warning[2]; /* 28-29 */ 914 u8 tx_pwr_low_warning[2]; /* 30-31 */ 915 916 u8 rx_pwr_high_alarm[2]; /* 32-33 */ 917 u8 rx_pwr_low_alarm[2]; /* 34-35 */ 918 u8 rx_pwr_high_warning[2]; /* 36-37 */ 919 u8 rx_pwr_low_warning[2]; /* 38-39 */ 920 921 u8 unallocate_1[16]; 922 923 /* 924 * ext_cal_const[36] 925 */ 926 u8 rx_pwr[20]; 927 u8 tx_i[4]; 928 u8 tx_pwr[4]; 929 u8 temp[4]; 930 u8 volt[4]; 931 u8 unallocate_2[3]; 932 u8 cc_dmi; 933 }; 934 935 /* 936 * Diagnostic: Data Fields -- Address A2h 937 * Diagnostic and control/status extended field total 24 bytes 938 */ 939 struct sfp_diag_ext_s { 940 u8 diag[SFP_DIAGMON_SIZE]; 941 u8 unalloc1[4]; 942 u8 status_ctl; 943 u8 rsvd; 944 u8 alarm_flags[2]; 945 u8 unalloc2[2]; 946 u8 warning_flags[2]; 947 u8 ext_status_ctl[2]; 948 }; 949 950 /* 951 * Diagnostic: Data Fields -- Address A2h 952 * General Use Fields: User Writable Table - Features's Control Registers 953 * Total 32 bytes 954 */ 955 struct sfp_usr_eeprom_s { 956 u8 rsvd1[2]; /* 128-129 */ 957 u8 ewrap; /* 130 */ 958 u8 rsvd2[2]; /* */ 959 u8 owrap; /* 133 */ 960 u8 rsvd3[2]; /* */ 961 u8 prbs; /* 136: PRBS 7 generator */ 962 u8 rsvd4[2]; /* */ 963 u8 tx_eqz_16; /* 139: TX Equalizer (16xFC) */ 964 u8 tx_eqz_8; /* 140: TX Equalizer (8xFC) */ 965 u8 rsvd5[2]; /* */ 966 u8 rx_emp_16; /* 143: RX Emphasis (16xFC) */ 967 u8 rx_emp_8; /* 144: RX Emphasis (8xFC) */ 968 u8 rsvd6[2]; /* */ 969 u8 tx_eye_adj; /* 147: TX eye Threshold Adjust */ 970 u8 rsvd7[3]; /* */ 971 u8 tx_eye_qctl; /* 151: TX eye Quality Control */ 972 u8 tx_eye_qres; /* 152: TX eye Quality Result */ 973 u8 rsvd8[2]; /* */ 974 u8 poh[3]; /* 155-157: Power On Hours */ 975 u8 rsvd9[2]; /* */ 976 }; 977 978 struct sfp_mem_s { 979 struct sfp_srlid_base_s srlid_base; 980 struct sfp_srlid_ext_s srlid_ext; 981 struct sfp_diag_base_s diag_base; 982 struct sfp_diag_ext_s diag_ext; 983 struct sfp_usr_eeprom_s usr_eeprom; 984 }; 985 986 /* 987 * transceiver codes (SFF-8472 Rev 10.2 Table 3.5) 988 */ 989 union sfp_xcvr_e10g_code_u { 990 u8 b; 991 struct { 992 #ifdef __BIG_ENDIAN 993 u8 e10g_unall:1; /* 10G Ethernet compliance */ 994 u8 e10g_lrm:1; 995 u8 e10g_lr:1; 996 u8 e10g_sr:1; 997 u8 ib_sx:1; /* Infiniband compliance */ 998 u8 ib_lx:1; 999 u8 ib_cu_a:1; 1000 u8 ib_cu_p:1; 1001 #else 1002 u8 ib_cu_p:1; 1003 u8 ib_cu_a:1; 1004 u8 ib_lx:1; 1005 u8 ib_sx:1; /* Infiniband compliance */ 1006 u8 e10g_sr:1; 1007 u8 e10g_lr:1; 1008 u8 e10g_lrm:1; 1009 u8 e10g_unall:1; /* 10G Ethernet compliance */ 1010 #endif 1011 } r; 1012 }; 1013 1014 union sfp_xcvr_so1_code_u { 1015 u8 b; 1016 struct { 1017 u8 escon:2; /* ESCON compliance code */ 1018 u8 oc192_reach:1; /* SONET compliance code */ 1019 u8 so_reach:2; 1020 u8 oc48_reach:3; 1021 } r; 1022 }; 1023 1024 union sfp_xcvr_so2_code_u { 1025 u8 b; 1026 struct { 1027 u8 reserved:1; 1028 u8 oc12_reach:3; /* OC12 reach */ 1029 u8 reserved1:1; 1030 u8 oc3_reach:3; /* OC3 reach */ 1031 } r; 1032 }; 1033 1034 union sfp_xcvr_eth_code_u { 1035 u8 b; 1036 struct { 1037 u8 base_px:1; 1038 u8 base_bx10:1; 1039 u8 e100base_fx:1; 1040 u8 e100base_lx:1; 1041 u8 e1000base_t:1; 1042 u8 e1000base_cx:1; 1043 u8 e1000base_lx:1; 1044 u8 e1000base_sx:1; 1045 } r; 1046 }; 1047 1048 struct sfp_xcvr_fc1_code_s { 1049 u8 link_len:5; /* FC link length */ 1050 u8 xmtr_tech2:3; 1051 u8 xmtr_tech1:7; /* FC transmitter technology */ 1052 u8 reserved1:1; 1053 }; 1054 1055 union sfp_xcvr_fc2_code_u { 1056 u8 b; 1057 struct { 1058 u8 tw_media:1; /* twin axial pair (tw) */ 1059 u8 tp_media:1; /* shielded twisted pair (sp) */ 1060 u8 mi_media:1; /* miniature coax (mi) */ 1061 u8 tv_media:1; /* video coax (tv) */ 1062 u8 m6_media:1; /* multimode, 62.5m (m6) */ 1063 u8 m5_media:1; /* multimode, 50m (m5) */ 1064 u8 reserved:1; 1065 u8 sm_media:1; /* single mode (sm) */ 1066 } r; 1067 }; 1068 1069 union sfp_xcvr_fc3_code_u { 1070 u8 b; 1071 struct { 1072 #ifdef __BIG_ENDIAN 1073 u8 rsv4:1; 1074 u8 mb800:1; /* 800 Mbytes/sec */ 1075 u8 mb1600:1; /* 1600 Mbytes/sec */ 1076 u8 mb400:1; /* 400 Mbytes/sec */ 1077 u8 rsv2:1; 1078 u8 mb200:1; /* 200 Mbytes/sec */ 1079 u8 rsv1:1; 1080 u8 mb100:1; /* 100 Mbytes/sec */ 1081 #else 1082 u8 mb100:1; /* 100 Mbytes/sec */ 1083 u8 rsv1:1; 1084 u8 mb200:1; /* 200 Mbytes/sec */ 1085 u8 rsv2:1; 1086 u8 mb400:1; /* 400 Mbytes/sec */ 1087 u8 mb1600:1; /* 1600 Mbytes/sec */ 1088 u8 mb800:1; /* 800 Mbytes/sec */ 1089 u8 rsv4:1; 1090 #endif 1091 } r; 1092 }; 1093 1094 struct sfp_xcvr_s { 1095 union sfp_xcvr_e10g_code_u e10g; 1096 union sfp_xcvr_so1_code_u so1; 1097 union sfp_xcvr_so2_code_u so2; 1098 union sfp_xcvr_eth_code_u eth; 1099 struct sfp_xcvr_fc1_code_s fc1; 1100 union sfp_xcvr_fc2_code_u fc2; 1101 union sfp_xcvr_fc3_code_u fc3; 1102 }; 1103 1104 /* 1105 * Flash module specific 1106 */ 1107 #define BFA_FLASH_PART_ENTRY_SIZE 32 /* partition entry size */ 1108 #define BFA_FLASH_PART_MAX 32 /* maximal # of partitions */ 1109 1110 enum bfa_flash_part_type { 1111 BFA_FLASH_PART_OPTROM = 1, /* option rom partition */ 1112 BFA_FLASH_PART_FWIMG = 2, /* firmware image partition */ 1113 BFA_FLASH_PART_FWCFG = 3, /* firmware tuneable config */ 1114 BFA_FLASH_PART_DRV = 4, /* IOC driver config */ 1115 BFA_FLASH_PART_BOOT = 5, /* boot config */ 1116 BFA_FLASH_PART_ASIC = 6, /* asic bootstrap configuration */ 1117 BFA_FLASH_PART_MFG = 7, /* manufacturing block partition */ 1118 BFA_FLASH_PART_OPTROM2 = 8, /* 2nd option rom partition */ 1119 BFA_FLASH_PART_VPD = 9, /* vpd data of OEM info */ 1120 BFA_FLASH_PART_PBC = 10, /* pre-boot config */ 1121 BFA_FLASH_PART_BOOTOVL = 11, /* boot overlay partition */ 1122 BFA_FLASH_PART_LOG = 12, /* firmware log partition */ 1123 BFA_FLASH_PART_PXECFG = 13, /* pxe boot config partition */ 1124 BFA_FLASH_PART_PXEOVL = 14, /* pxe boot overlay partition */ 1125 BFA_FLASH_PART_PORTCFG = 15, /* port cfg partition */ 1126 BFA_FLASH_PART_ASICBK = 16, /* asic backup partition */ 1127 }; 1128 1129 /* 1130 * flash partition attributes 1131 */ 1132 struct bfa_flash_part_attr_s { 1133 u32 part_type; /* partition type */ 1134 u32 part_instance; /* partition instance */ 1135 u32 part_off; /* partition offset */ 1136 u32 part_size; /* partition size */ 1137 u32 part_len; /* partition content length */ 1138 u32 part_status; /* partition status */ 1139 char rsv[BFA_FLASH_PART_ENTRY_SIZE - 24]; 1140 }; 1141 1142 /* 1143 * flash attributes 1144 */ 1145 struct bfa_flash_attr_s { 1146 u32 status; /* flash overall status */ 1147 u32 npart; /* num of partitions */ 1148 struct bfa_flash_part_attr_s part[BFA_FLASH_PART_MAX]; 1149 }; 1150 1151 /* 1152 * DIAG module specific 1153 */ 1154 #define LB_PATTERN_DEFAULT 0xB5B5B5B5 1155 #define QTEST_CNT_DEFAULT 10 1156 #define QTEST_PAT_DEFAULT LB_PATTERN_DEFAULT 1157 #define DPORT_ENABLE_LOOPCNT_DEFAULT (1024 * 1024) 1158 1159 struct bfa_diag_memtest_s { 1160 u8 algo; 1161 u8 rsvd[7]; 1162 }; 1163 1164 struct bfa_diag_memtest_result { 1165 u32 status; 1166 u32 addr; 1167 u32 exp; /* expect value read from reg */ 1168 u32 act; /* actually value read */ 1169 u32 err_status; /* error status reg */ 1170 u32 err_status1; /* extra error info reg */ 1171 u32 err_addr; /* error address reg */ 1172 u8 algo; 1173 u8 rsv[3]; 1174 }; 1175 1176 struct bfa_diag_loopback_result_s { 1177 u32 numtxmfrm; /* no. of transmit frame */ 1178 u32 numosffrm; /* no. of outstanding frame */ 1179 u32 numrcvfrm; /* no. of received good frame */ 1180 u32 badfrminf; /* mis-match info */ 1181 u32 badfrmnum; /* mis-match fram number */ 1182 u8 status; /* loopback test result */ 1183 u8 rsvd[3]; 1184 }; 1185 1186 enum bfa_diag_dport_test_status { 1187 DPORT_TEST_ST_IDLE = 0, /* the test has not started yet. */ 1188 DPORT_TEST_ST_FINAL = 1, /* the test done successfully */ 1189 DPORT_TEST_ST_SKIP = 2, /* the test skipped */ 1190 DPORT_TEST_ST_FAIL = 3, /* the test failed */ 1191 DPORT_TEST_ST_INPRG = 4, /* the testing is in progress */ 1192 DPORT_TEST_ST_RESPONDER = 5, /* test triggered from remote port */ 1193 DPORT_TEST_ST_STOPPED = 6, /* the test stopped by user. */ 1194 DPORT_TEST_ST_MAX 1195 }; 1196 1197 enum bfa_diag_dport_test_type { 1198 DPORT_TEST_ELOOP = 0, 1199 DPORT_TEST_OLOOP = 1, 1200 DPORT_TEST_ROLOOP = 2, 1201 DPORT_TEST_LINK = 3, 1202 DPORT_TEST_MAX 1203 }; 1204 1205 enum bfa_diag_dport_test_opmode { 1206 BFA_DPORT_OPMODE_AUTO = 0, 1207 BFA_DPORT_OPMODE_MANU = 1, 1208 }; 1209 1210 struct bfa_diag_dport_subtest_result_s { 1211 u8 status; /* bfa_diag_dport_test_status */ 1212 u8 rsvd[7]; /* 64bit align */ 1213 u64 start_time; /* timestamp */ 1214 }; 1215 1216 struct bfa_diag_dport_result_s { 1217 wwn_t rp_pwwn; /* switch port wwn */ 1218 wwn_t rp_nwwn; /* switch node wwn */ 1219 u64 start_time; /* user/sw start time */ 1220 u64 end_time; /* timestamp */ 1221 u8 status; /* bfa_diag_dport_test_status */ 1222 u8 mode; /* bfa_diag_dport_test_opmode */ 1223 u8 rsvd; /* 64bit align */ 1224 u8 speed; /* link speed for buf_reqd */ 1225 u16 buffer_required; 1226 u16 frmsz; /* frame size for buf_reqd */ 1227 u32 lpcnt; /* Frame count */ 1228 u32 pat; /* Pattern */ 1229 u32 roundtrip_latency; /* in nano sec */ 1230 u32 est_cable_distance; /* in meter */ 1231 struct bfa_diag_dport_subtest_result_s subtest[DPORT_TEST_MAX]; 1232 }; 1233 1234 struct bfa_diag_ledtest_s { 1235 u32 cmd; /* bfa_led_op_t */ 1236 u32 color; /* bfa_led_color_t */ 1237 u16 freq; /* no. of blinks every 10 secs */ 1238 u8 led; /* bitmap of LEDs to be tested */ 1239 u8 rsvd[5]; 1240 }; 1241 1242 struct bfa_diag_loopback_s { 1243 u32 loopcnt; 1244 u32 pattern; 1245 u8 lb_mode; /* bfa_port_opmode_t */ 1246 u8 speed; /* bfa_port_speed_t */ 1247 u8 rsvd[2]; 1248 }; 1249 1250 /* 1251 * PHY module specific 1252 */ 1253 enum bfa_phy_status_e { 1254 BFA_PHY_STATUS_GOOD = 0, /* phy is good */ 1255 BFA_PHY_STATUS_NOT_PRESENT = 1, /* phy does not exist */ 1256 BFA_PHY_STATUS_BAD = 2, /* phy is bad */ 1257 }; 1258 1259 /* 1260 * phy attributes for phy query 1261 */ 1262 struct bfa_phy_attr_s { 1263 u32 status; /* phy present/absent status */ 1264 u32 length; /* firmware length */ 1265 u32 fw_ver; /* firmware version */ 1266 u32 an_status; /* AN status */ 1267 u32 pma_pmd_status; /* PMA/PMD link status */ 1268 u32 pma_pmd_signal; /* PMA/PMD signal detect */ 1269 u32 pcs_status; /* PCS link status */ 1270 }; 1271 1272 /* 1273 * phy stats 1274 */ 1275 struct bfa_phy_stats_s { 1276 u32 status; /* phy stats status */ 1277 u32 link_breaks; /* Num of link breaks after linkup */ 1278 u32 pma_pmd_fault; /* NPMA/PMD fault */ 1279 u32 pcs_fault; /* PCS fault */ 1280 u32 speed_neg; /* Num of speed negotiation */ 1281 u32 tx_eq_training; /* Num of TX EQ training */ 1282 u32 tx_eq_timeout; /* Num of TX EQ timeout */ 1283 u32 crc_error; /* Num of CRC errors */ 1284 }; 1285 1286 #pragma pack() 1287 1288 #endif /* __BFA_DEFS_H__ */ 1289