1 /* 2 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc. 3 * Copyright (c) 2014- QLogic Corporation. 4 * All rights reserved 5 * www.qlogic.com 6 * 7 * Linux driver for QLogic BR-series Fibre Channel Host Bus Adapter. 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License (GPL) Version 2 as 11 * published by the Free Software Foundation 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 */ 18 19 #include "bfad_drv.h" 20 #include "bfa_modules.h" 21 #include "bfi_reg.h" 22 23 BFA_TRC_FILE(HAL, CORE); 24 25 /* 26 * BFA module list terminated by NULL 27 */ 28 static struct bfa_module_s *hal_mods[] = { 29 &hal_mod_fcdiag, 30 &hal_mod_sgpg, 31 &hal_mod_fcport, 32 &hal_mod_fcxp, 33 &hal_mod_lps, 34 &hal_mod_uf, 35 &hal_mod_rport, 36 &hal_mod_fcp, 37 &hal_mod_dconf, 38 NULL 39 }; 40 41 /* 42 * Message handlers for various modules. 43 */ 44 static bfa_isr_func_t bfa_isrs[BFI_MC_MAX] = { 45 bfa_isr_unhandled, /* NONE */ 46 bfa_isr_unhandled, /* BFI_MC_IOC */ 47 bfa_fcdiag_intr, /* BFI_MC_DIAG */ 48 bfa_isr_unhandled, /* BFI_MC_FLASH */ 49 bfa_isr_unhandled, /* BFI_MC_CEE */ 50 bfa_fcport_isr, /* BFI_MC_FCPORT */ 51 bfa_isr_unhandled, /* BFI_MC_IOCFC */ 52 bfa_isr_unhandled, /* BFI_MC_LL */ 53 bfa_uf_isr, /* BFI_MC_UF */ 54 bfa_fcxp_isr, /* BFI_MC_FCXP */ 55 bfa_lps_isr, /* BFI_MC_LPS */ 56 bfa_rport_isr, /* BFI_MC_RPORT */ 57 bfa_itn_isr, /* BFI_MC_ITN */ 58 bfa_isr_unhandled, /* BFI_MC_IOIM_READ */ 59 bfa_isr_unhandled, /* BFI_MC_IOIM_WRITE */ 60 bfa_isr_unhandled, /* BFI_MC_IOIM_IO */ 61 bfa_ioim_isr, /* BFI_MC_IOIM */ 62 bfa_ioim_good_comp_isr, /* BFI_MC_IOIM_IOCOM */ 63 bfa_tskim_isr, /* BFI_MC_TSKIM */ 64 bfa_isr_unhandled, /* BFI_MC_SBOOT */ 65 bfa_isr_unhandled, /* BFI_MC_IPFC */ 66 bfa_isr_unhandled, /* BFI_MC_PORT */ 67 bfa_isr_unhandled, /* --------- */ 68 bfa_isr_unhandled, /* --------- */ 69 bfa_isr_unhandled, /* --------- */ 70 bfa_isr_unhandled, /* --------- */ 71 bfa_isr_unhandled, /* --------- */ 72 bfa_isr_unhandled, /* --------- */ 73 bfa_isr_unhandled, /* --------- */ 74 bfa_isr_unhandled, /* --------- */ 75 bfa_isr_unhandled, /* --------- */ 76 bfa_isr_unhandled, /* --------- */ 77 }; 78 /* 79 * Message handlers for mailbox command classes 80 */ 81 static bfa_ioc_mbox_mcfunc_t bfa_mbox_isrs[BFI_MC_MAX] = { 82 NULL, 83 NULL, /* BFI_MC_IOC */ 84 NULL, /* BFI_MC_DIAG */ 85 NULL, /* BFI_MC_FLASH */ 86 NULL, /* BFI_MC_CEE */ 87 NULL, /* BFI_MC_PORT */ 88 bfa_iocfc_isr, /* BFI_MC_IOCFC */ 89 NULL, 90 }; 91 92 93 94 static void 95 bfa_com_port_attach(struct bfa_s *bfa) 96 { 97 struct bfa_port_s *port = &bfa->modules.port; 98 struct bfa_mem_dma_s *port_dma = BFA_MEM_PORT_DMA(bfa); 99 100 bfa_port_attach(port, &bfa->ioc, bfa, bfa->trcmod); 101 bfa_port_mem_claim(port, port_dma->kva_curp, port_dma->dma_curp); 102 } 103 104 /* 105 * ablk module attach 106 */ 107 static void 108 bfa_com_ablk_attach(struct bfa_s *bfa) 109 { 110 struct bfa_ablk_s *ablk = &bfa->modules.ablk; 111 struct bfa_mem_dma_s *ablk_dma = BFA_MEM_ABLK_DMA(bfa); 112 113 bfa_ablk_attach(ablk, &bfa->ioc); 114 bfa_ablk_memclaim(ablk, ablk_dma->kva_curp, ablk_dma->dma_curp); 115 } 116 117 static void 118 bfa_com_cee_attach(struct bfa_s *bfa) 119 { 120 struct bfa_cee_s *cee = &bfa->modules.cee; 121 struct bfa_mem_dma_s *cee_dma = BFA_MEM_CEE_DMA(bfa); 122 123 cee->trcmod = bfa->trcmod; 124 bfa_cee_attach(cee, &bfa->ioc, bfa); 125 bfa_cee_mem_claim(cee, cee_dma->kva_curp, cee_dma->dma_curp); 126 } 127 128 static void 129 bfa_com_sfp_attach(struct bfa_s *bfa) 130 { 131 struct bfa_sfp_s *sfp = BFA_SFP_MOD(bfa); 132 struct bfa_mem_dma_s *sfp_dma = BFA_MEM_SFP_DMA(bfa); 133 134 bfa_sfp_attach(sfp, &bfa->ioc, bfa, bfa->trcmod); 135 bfa_sfp_memclaim(sfp, sfp_dma->kva_curp, sfp_dma->dma_curp); 136 } 137 138 static void 139 bfa_com_flash_attach(struct bfa_s *bfa, bfa_boolean_t mincfg) 140 { 141 struct bfa_flash_s *flash = BFA_FLASH(bfa); 142 struct bfa_mem_dma_s *flash_dma = BFA_MEM_FLASH_DMA(bfa); 143 144 bfa_flash_attach(flash, &bfa->ioc, bfa, bfa->trcmod, mincfg); 145 bfa_flash_memclaim(flash, flash_dma->kva_curp, 146 flash_dma->dma_curp, mincfg); 147 } 148 149 static void 150 bfa_com_diag_attach(struct bfa_s *bfa) 151 { 152 struct bfa_diag_s *diag = BFA_DIAG_MOD(bfa); 153 struct bfa_mem_dma_s *diag_dma = BFA_MEM_DIAG_DMA(bfa); 154 155 bfa_diag_attach(diag, &bfa->ioc, bfa, bfa_fcport_beacon, bfa->trcmod); 156 bfa_diag_memclaim(diag, diag_dma->kva_curp, diag_dma->dma_curp); 157 } 158 159 static void 160 bfa_com_phy_attach(struct bfa_s *bfa, bfa_boolean_t mincfg) 161 { 162 struct bfa_phy_s *phy = BFA_PHY(bfa); 163 struct bfa_mem_dma_s *phy_dma = BFA_MEM_PHY_DMA(bfa); 164 165 bfa_phy_attach(phy, &bfa->ioc, bfa, bfa->trcmod, mincfg); 166 bfa_phy_memclaim(phy, phy_dma->kva_curp, phy_dma->dma_curp, mincfg); 167 } 168 169 static void 170 bfa_com_fru_attach(struct bfa_s *bfa, bfa_boolean_t mincfg) 171 { 172 struct bfa_fru_s *fru = BFA_FRU(bfa); 173 struct bfa_mem_dma_s *fru_dma = BFA_MEM_FRU_DMA(bfa); 174 175 bfa_fru_attach(fru, &bfa->ioc, bfa, bfa->trcmod, mincfg); 176 bfa_fru_memclaim(fru, fru_dma->kva_curp, fru_dma->dma_curp, mincfg); 177 } 178 179 /* 180 * BFA IOC FC related definitions 181 */ 182 183 /* 184 * IOC local definitions 185 */ 186 #define BFA_IOCFC_TOV 5000 /* msecs */ 187 188 enum { 189 BFA_IOCFC_ACT_NONE = 0, 190 BFA_IOCFC_ACT_INIT = 1, 191 BFA_IOCFC_ACT_STOP = 2, 192 BFA_IOCFC_ACT_DISABLE = 3, 193 BFA_IOCFC_ACT_ENABLE = 4, 194 }; 195 196 #define DEF_CFG_NUM_FABRICS 1 197 #define DEF_CFG_NUM_LPORTS 256 198 #define DEF_CFG_NUM_CQS 4 199 #define DEF_CFG_NUM_IOIM_REQS (BFA_IOIM_MAX) 200 #define DEF_CFG_NUM_TSKIM_REQS 128 201 #define DEF_CFG_NUM_FCXP_REQS 64 202 #define DEF_CFG_NUM_UF_BUFS 64 203 #define DEF_CFG_NUM_RPORTS 1024 204 #define DEF_CFG_NUM_ITNIMS (DEF_CFG_NUM_RPORTS) 205 #define DEF_CFG_NUM_TINS 256 206 207 #define DEF_CFG_NUM_SGPGS 2048 208 #define DEF_CFG_NUM_REQQ_ELEMS 256 209 #define DEF_CFG_NUM_RSPQ_ELEMS 64 210 #define DEF_CFG_NUM_SBOOT_TGTS 16 211 #define DEF_CFG_NUM_SBOOT_LUNS 16 212 213 /* 214 * IOCFC state machine definitions/declarations 215 */ 216 bfa_fsm_state_decl(bfa_iocfc, stopped, struct bfa_iocfc_s, enum iocfc_event); 217 bfa_fsm_state_decl(bfa_iocfc, initing, struct bfa_iocfc_s, enum iocfc_event); 218 bfa_fsm_state_decl(bfa_iocfc, dconf_read, struct bfa_iocfc_s, enum iocfc_event); 219 bfa_fsm_state_decl(bfa_iocfc, init_cfg_wait, 220 struct bfa_iocfc_s, enum iocfc_event); 221 bfa_fsm_state_decl(bfa_iocfc, init_cfg_done, 222 struct bfa_iocfc_s, enum iocfc_event); 223 bfa_fsm_state_decl(bfa_iocfc, operational, 224 struct bfa_iocfc_s, enum iocfc_event); 225 bfa_fsm_state_decl(bfa_iocfc, dconf_write, 226 struct bfa_iocfc_s, enum iocfc_event); 227 bfa_fsm_state_decl(bfa_iocfc, stopping, struct bfa_iocfc_s, enum iocfc_event); 228 bfa_fsm_state_decl(bfa_iocfc, enabling, struct bfa_iocfc_s, enum iocfc_event); 229 bfa_fsm_state_decl(bfa_iocfc, cfg_wait, struct bfa_iocfc_s, enum iocfc_event); 230 bfa_fsm_state_decl(bfa_iocfc, disabling, struct bfa_iocfc_s, enum iocfc_event); 231 bfa_fsm_state_decl(bfa_iocfc, disabled, struct bfa_iocfc_s, enum iocfc_event); 232 bfa_fsm_state_decl(bfa_iocfc, failed, struct bfa_iocfc_s, enum iocfc_event); 233 bfa_fsm_state_decl(bfa_iocfc, init_failed, 234 struct bfa_iocfc_s, enum iocfc_event); 235 236 /* 237 * forward declaration for IOC FC functions 238 */ 239 static void bfa_iocfc_start_submod(struct bfa_s *bfa); 240 static void bfa_iocfc_disable_submod(struct bfa_s *bfa); 241 static void bfa_iocfc_send_cfg(void *bfa_arg); 242 static void bfa_iocfc_enable_cbfn(void *bfa_arg, enum bfa_status status); 243 static void bfa_iocfc_disable_cbfn(void *bfa_arg); 244 static void bfa_iocfc_hbfail_cbfn(void *bfa_arg); 245 static void bfa_iocfc_reset_cbfn(void *bfa_arg); 246 static struct bfa_ioc_cbfn_s bfa_iocfc_cbfn; 247 static void bfa_iocfc_init_cb(void *bfa_arg, bfa_boolean_t complete); 248 static void bfa_iocfc_stop_cb(void *bfa_arg, bfa_boolean_t compl); 249 static void bfa_iocfc_enable_cb(void *bfa_arg, bfa_boolean_t compl); 250 static void bfa_iocfc_disable_cb(void *bfa_arg, bfa_boolean_t compl); 251 252 static void 253 bfa_iocfc_sm_stopped_entry(struct bfa_iocfc_s *iocfc) 254 { 255 } 256 257 static void 258 bfa_iocfc_sm_stopped(struct bfa_iocfc_s *iocfc, enum iocfc_event event) 259 { 260 bfa_trc(iocfc->bfa, event); 261 262 switch (event) { 263 case IOCFC_E_INIT: 264 case IOCFC_E_ENABLE: 265 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_initing); 266 break; 267 default: 268 bfa_sm_fault(iocfc->bfa, event); 269 break; 270 } 271 } 272 273 static void 274 bfa_iocfc_sm_initing_entry(struct bfa_iocfc_s *iocfc) 275 { 276 bfa_ioc_enable(&iocfc->bfa->ioc); 277 } 278 279 static void 280 bfa_iocfc_sm_initing(struct bfa_iocfc_s *iocfc, enum iocfc_event event) 281 { 282 bfa_trc(iocfc->bfa, event); 283 284 switch (event) { 285 case IOCFC_E_IOC_ENABLED: 286 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_dconf_read); 287 break; 288 289 case IOCFC_E_DISABLE: 290 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_disabling); 291 break; 292 293 case IOCFC_E_STOP: 294 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_stopping); 295 break; 296 297 case IOCFC_E_IOC_FAILED: 298 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_init_failed); 299 break; 300 default: 301 bfa_sm_fault(iocfc->bfa, event); 302 break; 303 } 304 } 305 306 static void 307 bfa_iocfc_sm_dconf_read_entry(struct bfa_iocfc_s *iocfc) 308 { 309 bfa_dconf_modinit(iocfc->bfa); 310 } 311 312 static void 313 bfa_iocfc_sm_dconf_read(struct bfa_iocfc_s *iocfc, enum iocfc_event event) 314 { 315 bfa_trc(iocfc->bfa, event); 316 317 switch (event) { 318 case IOCFC_E_DCONF_DONE: 319 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_init_cfg_wait); 320 break; 321 322 case IOCFC_E_DISABLE: 323 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_disabling); 324 break; 325 326 case IOCFC_E_STOP: 327 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_stopping); 328 break; 329 330 case IOCFC_E_IOC_FAILED: 331 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_init_failed); 332 break; 333 default: 334 bfa_sm_fault(iocfc->bfa, event); 335 break; 336 } 337 } 338 339 static void 340 bfa_iocfc_sm_init_cfg_wait_entry(struct bfa_iocfc_s *iocfc) 341 { 342 bfa_iocfc_send_cfg(iocfc->bfa); 343 } 344 345 static void 346 bfa_iocfc_sm_init_cfg_wait(struct bfa_iocfc_s *iocfc, enum iocfc_event event) 347 { 348 bfa_trc(iocfc->bfa, event); 349 350 switch (event) { 351 case IOCFC_E_CFG_DONE: 352 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_init_cfg_done); 353 break; 354 355 case IOCFC_E_DISABLE: 356 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_disabling); 357 break; 358 359 case IOCFC_E_STOP: 360 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_stopping); 361 break; 362 363 case IOCFC_E_IOC_FAILED: 364 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_init_failed); 365 break; 366 default: 367 bfa_sm_fault(iocfc->bfa, event); 368 break; 369 } 370 } 371 372 static void 373 bfa_iocfc_sm_init_cfg_done_entry(struct bfa_iocfc_s *iocfc) 374 { 375 iocfc->bfa->iocfc.op_status = BFA_STATUS_OK; 376 bfa_cb_queue(iocfc->bfa, &iocfc->bfa->iocfc.init_hcb_qe, 377 bfa_iocfc_init_cb, iocfc->bfa); 378 } 379 380 static void 381 bfa_iocfc_sm_init_cfg_done(struct bfa_iocfc_s *iocfc, enum iocfc_event event) 382 { 383 bfa_trc(iocfc->bfa, event); 384 385 switch (event) { 386 case IOCFC_E_START: 387 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_operational); 388 break; 389 case IOCFC_E_STOP: 390 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_stopping); 391 break; 392 case IOCFC_E_DISABLE: 393 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_disabling); 394 break; 395 case IOCFC_E_IOC_FAILED: 396 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_failed); 397 break; 398 default: 399 bfa_sm_fault(iocfc->bfa, event); 400 break; 401 } 402 } 403 404 static void 405 bfa_iocfc_sm_operational_entry(struct bfa_iocfc_s *iocfc) 406 { 407 bfa_fcport_init(iocfc->bfa); 408 bfa_iocfc_start_submod(iocfc->bfa); 409 } 410 411 static void 412 bfa_iocfc_sm_operational(struct bfa_iocfc_s *iocfc, enum iocfc_event event) 413 { 414 bfa_trc(iocfc->bfa, event); 415 416 switch (event) { 417 case IOCFC_E_STOP: 418 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_dconf_write); 419 break; 420 case IOCFC_E_DISABLE: 421 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_disabling); 422 break; 423 case IOCFC_E_IOC_FAILED: 424 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_failed); 425 break; 426 default: 427 bfa_sm_fault(iocfc->bfa, event); 428 break; 429 } 430 } 431 432 static void 433 bfa_iocfc_sm_dconf_write_entry(struct bfa_iocfc_s *iocfc) 434 { 435 bfa_dconf_modexit(iocfc->bfa); 436 } 437 438 static void 439 bfa_iocfc_sm_dconf_write(struct bfa_iocfc_s *iocfc, enum iocfc_event event) 440 { 441 bfa_trc(iocfc->bfa, event); 442 443 switch (event) { 444 case IOCFC_E_DCONF_DONE: 445 case IOCFC_E_IOC_FAILED: 446 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_stopping); 447 break; 448 default: 449 bfa_sm_fault(iocfc->bfa, event); 450 break; 451 } 452 } 453 454 static void 455 bfa_iocfc_sm_stopping_entry(struct bfa_iocfc_s *iocfc) 456 { 457 bfa_ioc_disable(&iocfc->bfa->ioc); 458 } 459 460 static void 461 bfa_iocfc_sm_stopping(struct bfa_iocfc_s *iocfc, enum iocfc_event event) 462 { 463 bfa_trc(iocfc->bfa, event); 464 465 switch (event) { 466 case IOCFC_E_IOC_DISABLED: 467 bfa_isr_disable(iocfc->bfa); 468 bfa_iocfc_disable_submod(iocfc->bfa); 469 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_stopped); 470 iocfc->bfa->iocfc.op_status = BFA_STATUS_OK; 471 bfa_cb_queue(iocfc->bfa, &iocfc->bfa->iocfc.stop_hcb_qe, 472 bfa_iocfc_stop_cb, iocfc->bfa); 473 break; 474 475 case IOCFC_E_IOC_ENABLED: 476 case IOCFC_E_DCONF_DONE: 477 case IOCFC_E_CFG_DONE: 478 break; 479 480 default: 481 bfa_sm_fault(iocfc->bfa, event); 482 break; 483 } 484 } 485 486 static void 487 bfa_iocfc_sm_enabling_entry(struct bfa_iocfc_s *iocfc) 488 { 489 bfa_ioc_enable(&iocfc->bfa->ioc); 490 } 491 492 static void 493 bfa_iocfc_sm_enabling(struct bfa_iocfc_s *iocfc, enum iocfc_event event) 494 { 495 bfa_trc(iocfc->bfa, event); 496 497 switch (event) { 498 case IOCFC_E_IOC_ENABLED: 499 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_cfg_wait); 500 break; 501 502 case IOCFC_E_DISABLE: 503 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_disabling); 504 break; 505 506 case IOCFC_E_STOP: 507 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_dconf_write); 508 break; 509 510 case IOCFC_E_IOC_FAILED: 511 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_failed); 512 513 if (iocfc->bfa->iocfc.cb_reqd == BFA_FALSE) 514 break; 515 516 iocfc->bfa->iocfc.op_status = BFA_STATUS_FAILED; 517 bfa_cb_queue(iocfc->bfa, &iocfc->bfa->iocfc.en_hcb_qe, 518 bfa_iocfc_enable_cb, iocfc->bfa); 519 iocfc->bfa->iocfc.cb_reqd = BFA_FALSE; 520 break; 521 default: 522 bfa_sm_fault(iocfc->bfa, event); 523 break; 524 } 525 } 526 527 static void 528 bfa_iocfc_sm_cfg_wait_entry(struct bfa_iocfc_s *iocfc) 529 { 530 bfa_iocfc_send_cfg(iocfc->bfa); 531 } 532 533 static void 534 bfa_iocfc_sm_cfg_wait(struct bfa_iocfc_s *iocfc, enum iocfc_event event) 535 { 536 bfa_trc(iocfc->bfa, event); 537 538 switch (event) { 539 case IOCFC_E_CFG_DONE: 540 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_operational); 541 if (iocfc->bfa->iocfc.cb_reqd == BFA_FALSE) 542 break; 543 544 iocfc->bfa->iocfc.op_status = BFA_STATUS_OK; 545 bfa_cb_queue(iocfc->bfa, &iocfc->bfa->iocfc.en_hcb_qe, 546 bfa_iocfc_enable_cb, iocfc->bfa); 547 iocfc->bfa->iocfc.cb_reqd = BFA_FALSE; 548 break; 549 case IOCFC_E_DISABLE: 550 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_disabling); 551 break; 552 553 case IOCFC_E_STOP: 554 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_dconf_write); 555 break; 556 case IOCFC_E_IOC_FAILED: 557 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_failed); 558 if (iocfc->bfa->iocfc.cb_reqd == BFA_FALSE) 559 break; 560 561 iocfc->bfa->iocfc.op_status = BFA_STATUS_FAILED; 562 bfa_cb_queue(iocfc->bfa, &iocfc->bfa->iocfc.en_hcb_qe, 563 bfa_iocfc_enable_cb, iocfc->bfa); 564 iocfc->bfa->iocfc.cb_reqd = BFA_FALSE; 565 break; 566 default: 567 bfa_sm_fault(iocfc->bfa, event); 568 break; 569 } 570 } 571 572 static void 573 bfa_iocfc_sm_disabling_entry(struct bfa_iocfc_s *iocfc) 574 { 575 bfa_ioc_disable(&iocfc->bfa->ioc); 576 } 577 578 static void 579 bfa_iocfc_sm_disabling(struct bfa_iocfc_s *iocfc, enum iocfc_event event) 580 { 581 bfa_trc(iocfc->bfa, event); 582 583 switch (event) { 584 case IOCFC_E_IOC_DISABLED: 585 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_disabled); 586 break; 587 case IOCFC_E_IOC_ENABLED: 588 case IOCFC_E_DCONF_DONE: 589 case IOCFC_E_CFG_DONE: 590 break; 591 default: 592 bfa_sm_fault(iocfc->bfa, event); 593 break; 594 } 595 } 596 597 static void 598 bfa_iocfc_sm_disabled_entry(struct bfa_iocfc_s *iocfc) 599 { 600 bfa_isr_disable(iocfc->bfa); 601 bfa_iocfc_disable_submod(iocfc->bfa); 602 iocfc->bfa->iocfc.op_status = BFA_STATUS_OK; 603 bfa_cb_queue(iocfc->bfa, &iocfc->bfa->iocfc.dis_hcb_qe, 604 bfa_iocfc_disable_cb, iocfc->bfa); 605 } 606 607 static void 608 bfa_iocfc_sm_disabled(struct bfa_iocfc_s *iocfc, enum iocfc_event event) 609 { 610 bfa_trc(iocfc->bfa, event); 611 612 switch (event) { 613 case IOCFC_E_STOP: 614 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_dconf_write); 615 break; 616 case IOCFC_E_ENABLE: 617 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_enabling); 618 break; 619 default: 620 bfa_sm_fault(iocfc->bfa, event); 621 break; 622 } 623 } 624 625 static void 626 bfa_iocfc_sm_failed_entry(struct bfa_iocfc_s *iocfc) 627 { 628 bfa_isr_disable(iocfc->bfa); 629 bfa_iocfc_disable_submod(iocfc->bfa); 630 } 631 632 static void 633 bfa_iocfc_sm_failed(struct bfa_iocfc_s *iocfc, enum iocfc_event event) 634 { 635 bfa_trc(iocfc->bfa, event); 636 637 switch (event) { 638 case IOCFC_E_STOP: 639 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_dconf_write); 640 break; 641 case IOCFC_E_DISABLE: 642 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_disabling); 643 break; 644 case IOCFC_E_IOC_ENABLED: 645 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_cfg_wait); 646 break; 647 case IOCFC_E_IOC_FAILED: 648 break; 649 default: 650 bfa_sm_fault(iocfc->bfa, event); 651 break; 652 } 653 } 654 655 static void 656 bfa_iocfc_sm_init_failed_entry(struct bfa_iocfc_s *iocfc) 657 { 658 bfa_isr_disable(iocfc->bfa); 659 iocfc->bfa->iocfc.op_status = BFA_STATUS_FAILED; 660 bfa_cb_queue(iocfc->bfa, &iocfc->bfa->iocfc.init_hcb_qe, 661 bfa_iocfc_init_cb, iocfc->bfa); 662 } 663 664 static void 665 bfa_iocfc_sm_init_failed(struct bfa_iocfc_s *iocfc, enum iocfc_event event) 666 { 667 bfa_trc(iocfc->bfa, event); 668 669 switch (event) { 670 case IOCFC_E_STOP: 671 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_stopping); 672 break; 673 case IOCFC_E_DISABLE: 674 bfa_ioc_disable(&iocfc->bfa->ioc); 675 break; 676 case IOCFC_E_IOC_ENABLED: 677 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_dconf_read); 678 break; 679 case IOCFC_E_IOC_DISABLED: 680 bfa_fsm_set_state(iocfc, bfa_iocfc_sm_stopped); 681 iocfc->bfa->iocfc.op_status = BFA_STATUS_OK; 682 bfa_cb_queue(iocfc->bfa, &iocfc->bfa->iocfc.dis_hcb_qe, 683 bfa_iocfc_disable_cb, iocfc->bfa); 684 break; 685 case IOCFC_E_IOC_FAILED: 686 break; 687 default: 688 bfa_sm_fault(iocfc->bfa, event); 689 break; 690 } 691 } 692 693 /* 694 * BFA Interrupt handling functions 695 */ 696 static void 697 bfa_reqq_resume(struct bfa_s *bfa, int qid) 698 { 699 struct list_head *waitq, *qe, *qen; 700 struct bfa_reqq_wait_s *wqe; 701 702 waitq = bfa_reqq(bfa, qid); 703 list_for_each_safe(qe, qen, waitq) { 704 /* 705 * Callback only as long as there is room in request queue 706 */ 707 if (bfa_reqq_full(bfa, qid)) 708 break; 709 710 list_del(qe); 711 wqe = (struct bfa_reqq_wait_s *) qe; 712 wqe->qresume(wqe->cbarg); 713 } 714 } 715 716 bfa_boolean_t 717 bfa_isr_rspq(struct bfa_s *bfa, int qid) 718 { 719 struct bfi_msg_s *m; 720 u32 pi, ci; 721 struct list_head *waitq; 722 bfa_boolean_t ret; 723 724 ci = bfa_rspq_ci(bfa, qid); 725 pi = bfa_rspq_pi(bfa, qid); 726 727 ret = (ci != pi); 728 729 while (ci != pi) { 730 m = bfa_rspq_elem(bfa, qid, ci); 731 WARN_ON(m->mhdr.msg_class >= BFI_MC_MAX); 732 733 bfa_isrs[m->mhdr.msg_class] (bfa, m); 734 CQ_INCR(ci, bfa->iocfc.cfg.drvcfg.num_rspq_elems); 735 } 736 737 /* 738 * acknowledge RME completions and update CI 739 */ 740 bfa_isr_rspq_ack(bfa, qid, ci); 741 742 /* 743 * Resume any pending requests in the corresponding reqq. 744 */ 745 waitq = bfa_reqq(bfa, qid); 746 if (!list_empty(waitq)) 747 bfa_reqq_resume(bfa, qid); 748 749 return ret; 750 } 751 752 static inline void 753 bfa_isr_reqq(struct bfa_s *bfa, int qid) 754 { 755 struct list_head *waitq; 756 757 bfa_isr_reqq_ack(bfa, qid); 758 759 /* 760 * Resume any pending requests in the corresponding reqq. 761 */ 762 waitq = bfa_reqq(bfa, qid); 763 if (!list_empty(waitq)) 764 bfa_reqq_resume(bfa, qid); 765 } 766 767 void 768 bfa_msix_all(struct bfa_s *bfa, int vec) 769 { 770 u32 intr, qintr; 771 int queue; 772 773 intr = readl(bfa->iocfc.bfa_regs.intr_status); 774 if (!intr) 775 return; 776 777 /* 778 * RME completion queue interrupt 779 */ 780 qintr = intr & __HFN_INT_RME_MASK; 781 if (qintr && bfa->queue_process) { 782 for (queue = 0; queue < BFI_IOC_MAX_CQS; queue++) 783 bfa_isr_rspq(bfa, queue); 784 } 785 786 intr &= ~qintr; 787 if (!intr) 788 return; 789 790 /* 791 * CPE completion queue interrupt 792 */ 793 qintr = intr & __HFN_INT_CPE_MASK; 794 if (qintr && bfa->queue_process) { 795 for (queue = 0; queue < BFI_IOC_MAX_CQS; queue++) 796 bfa_isr_reqq(bfa, queue); 797 } 798 intr &= ~qintr; 799 if (!intr) 800 return; 801 802 bfa_msix_lpu_err(bfa, intr); 803 } 804 805 bfa_boolean_t 806 bfa_intx(struct bfa_s *bfa) 807 { 808 u32 intr, qintr; 809 int queue; 810 bfa_boolean_t rspq_comp = BFA_FALSE; 811 812 intr = readl(bfa->iocfc.bfa_regs.intr_status); 813 814 qintr = intr & (__HFN_INT_RME_MASK | __HFN_INT_CPE_MASK); 815 if (qintr) 816 writel(qintr, bfa->iocfc.bfa_regs.intr_status); 817 818 /* 819 * Unconditional RME completion queue interrupt 820 */ 821 if (bfa->queue_process) { 822 for (queue = 0; queue < BFI_IOC_MAX_CQS; queue++) 823 if (bfa_isr_rspq(bfa, queue)) 824 rspq_comp = BFA_TRUE; 825 } 826 827 if (!intr) 828 return (qintr | rspq_comp) ? BFA_TRUE : BFA_FALSE; 829 830 /* 831 * CPE completion queue interrupt 832 */ 833 qintr = intr & __HFN_INT_CPE_MASK; 834 if (qintr && bfa->queue_process) { 835 for (queue = 0; queue < BFI_IOC_MAX_CQS; queue++) 836 bfa_isr_reqq(bfa, queue); 837 } 838 intr &= ~qintr; 839 if (!intr) 840 return BFA_TRUE; 841 842 if (bfa->intr_enabled) 843 bfa_msix_lpu_err(bfa, intr); 844 845 return BFA_TRUE; 846 } 847 848 void 849 bfa_isr_enable(struct bfa_s *bfa) 850 { 851 u32 umsk; 852 int port_id = bfa_ioc_portid(&bfa->ioc); 853 854 bfa_trc(bfa, bfa_ioc_pcifn(&bfa->ioc)); 855 bfa_trc(bfa, port_id); 856 857 bfa_msix_ctrl_install(bfa); 858 859 if (bfa_asic_id_ct2(bfa->ioc.pcidev.device_id)) { 860 umsk = __HFN_INT_ERR_MASK_CT2; 861 umsk |= port_id == 0 ? 862 __HFN_INT_FN0_MASK_CT2 : __HFN_INT_FN1_MASK_CT2; 863 } else { 864 umsk = __HFN_INT_ERR_MASK; 865 umsk |= port_id == 0 ? __HFN_INT_FN0_MASK : __HFN_INT_FN1_MASK; 866 } 867 868 writel(umsk, bfa->iocfc.bfa_regs.intr_status); 869 writel(~umsk, bfa->iocfc.bfa_regs.intr_mask); 870 bfa->iocfc.intr_mask = ~umsk; 871 bfa_isr_mode_set(bfa, bfa->msix.nvecs != 0); 872 873 /* 874 * Set the flag indicating successful enabling of interrupts 875 */ 876 bfa->intr_enabled = BFA_TRUE; 877 } 878 879 void 880 bfa_isr_disable(struct bfa_s *bfa) 881 { 882 bfa->intr_enabled = BFA_FALSE; 883 bfa_isr_mode_set(bfa, BFA_FALSE); 884 writel(-1L, bfa->iocfc.bfa_regs.intr_mask); 885 bfa_msix_uninstall(bfa); 886 } 887 888 void 889 bfa_msix_reqq(struct bfa_s *bfa, int vec) 890 { 891 bfa_isr_reqq(bfa, vec - bfa->iocfc.hwif.cpe_vec_q0); 892 } 893 894 void 895 bfa_isr_unhandled(struct bfa_s *bfa, struct bfi_msg_s *m) 896 { 897 bfa_trc(bfa, m->mhdr.msg_class); 898 bfa_trc(bfa, m->mhdr.msg_id); 899 bfa_trc(bfa, m->mhdr.mtag.i2htok); 900 WARN_ON(1); 901 bfa_trc_stop(bfa->trcmod); 902 } 903 904 void 905 bfa_msix_rspq(struct bfa_s *bfa, int vec) 906 { 907 bfa_isr_rspq(bfa, vec - bfa->iocfc.hwif.rme_vec_q0); 908 } 909 910 void 911 bfa_msix_lpu_err(struct bfa_s *bfa, int vec) 912 { 913 u32 intr, curr_value; 914 bfa_boolean_t lpu_isr, halt_isr, pss_isr; 915 916 intr = readl(bfa->iocfc.bfa_regs.intr_status); 917 918 if (bfa_asic_id_ct2(bfa->ioc.pcidev.device_id)) { 919 halt_isr = intr & __HFN_INT_CPQ_HALT_CT2; 920 pss_isr = intr & __HFN_INT_ERR_PSS_CT2; 921 lpu_isr = intr & (__HFN_INT_MBOX_LPU0_CT2 | 922 __HFN_INT_MBOX_LPU1_CT2); 923 intr &= __HFN_INT_ERR_MASK_CT2; 924 } else { 925 halt_isr = bfa_asic_id_ct(bfa->ioc.pcidev.device_id) ? 926 (intr & __HFN_INT_LL_HALT) : 0; 927 pss_isr = intr & __HFN_INT_ERR_PSS; 928 lpu_isr = intr & (__HFN_INT_MBOX_LPU0 | __HFN_INT_MBOX_LPU1); 929 intr &= __HFN_INT_ERR_MASK; 930 } 931 932 if (lpu_isr) 933 bfa_ioc_mbox_isr(&bfa->ioc); 934 935 if (intr) { 936 if (halt_isr) { 937 /* 938 * If LL_HALT bit is set then FW Init Halt LL Port 939 * Register needs to be cleared as well so Interrupt 940 * Status Register will be cleared. 941 */ 942 curr_value = readl(bfa->ioc.ioc_regs.ll_halt); 943 curr_value &= ~__FW_INIT_HALT_P; 944 writel(curr_value, bfa->ioc.ioc_regs.ll_halt); 945 } 946 947 if (pss_isr) { 948 /* 949 * ERR_PSS bit needs to be cleared as well in case 950 * interrups are shared so driver's interrupt handler is 951 * still called even though it is already masked out. 952 */ 953 curr_value = readl( 954 bfa->ioc.ioc_regs.pss_err_status_reg); 955 writel(curr_value, 956 bfa->ioc.ioc_regs.pss_err_status_reg); 957 } 958 959 writel(intr, bfa->iocfc.bfa_regs.intr_status); 960 bfa_ioc_error_isr(&bfa->ioc); 961 } 962 } 963 964 /* 965 * BFA IOC FC related functions 966 */ 967 968 /* 969 * BFA IOC private functions 970 */ 971 972 /* 973 * Use the Mailbox interface to send BFI_IOCFC_H2I_CFG_REQ 974 */ 975 static void 976 bfa_iocfc_send_cfg(void *bfa_arg) 977 { 978 struct bfa_s *bfa = bfa_arg; 979 struct bfa_iocfc_s *iocfc = &bfa->iocfc; 980 struct bfi_iocfc_cfg_req_s cfg_req; 981 struct bfi_iocfc_cfg_s *cfg_info = iocfc->cfginfo; 982 struct bfa_iocfc_cfg_s *cfg = &iocfc->cfg; 983 int i; 984 985 WARN_ON(cfg->fwcfg.num_cqs > BFI_IOC_MAX_CQS); 986 bfa_trc(bfa, cfg->fwcfg.num_cqs); 987 988 bfa_iocfc_reset_queues(bfa); 989 990 /* 991 * initialize IOC configuration info 992 */ 993 cfg_info->single_msix_vec = 0; 994 if (bfa->msix.nvecs == 1) 995 cfg_info->single_msix_vec = 1; 996 cfg_info->endian_sig = BFI_IOC_ENDIAN_SIG; 997 cfg_info->num_cqs = cfg->fwcfg.num_cqs; 998 cfg_info->num_ioim_reqs = cpu_to_be16(bfa_fcpim_get_throttle_cfg(bfa, 999 cfg->fwcfg.num_ioim_reqs)); 1000 cfg_info->num_fwtio_reqs = cpu_to_be16(cfg->fwcfg.num_fwtio_reqs); 1001 1002 bfa_dma_be_addr_set(cfg_info->cfgrsp_addr, iocfc->cfgrsp_dma.pa); 1003 /* 1004 * dma map REQ and RSP circular queues and shadow pointers 1005 */ 1006 for (i = 0; i < cfg->fwcfg.num_cqs; i++) { 1007 bfa_dma_be_addr_set(cfg_info->req_cq_ba[i], 1008 iocfc->req_cq_ba[i].pa); 1009 bfa_dma_be_addr_set(cfg_info->req_shadow_ci[i], 1010 iocfc->req_cq_shadow_ci[i].pa); 1011 cfg_info->req_cq_elems[i] = 1012 cpu_to_be16(cfg->drvcfg.num_reqq_elems); 1013 1014 bfa_dma_be_addr_set(cfg_info->rsp_cq_ba[i], 1015 iocfc->rsp_cq_ba[i].pa); 1016 bfa_dma_be_addr_set(cfg_info->rsp_shadow_pi[i], 1017 iocfc->rsp_cq_shadow_pi[i].pa); 1018 cfg_info->rsp_cq_elems[i] = 1019 cpu_to_be16(cfg->drvcfg.num_rspq_elems); 1020 } 1021 1022 /* 1023 * Enable interrupt coalescing if it is driver init path 1024 * and not ioc disable/enable path. 1025 */ 1026 if (bfa_fsm_cmp_state(iocfc, bfa_iocfc_sm_init_cfg_wait)) 1027 cfg_info->intr_attr.coalesce = BFA_TRUE; 1028 1029 /* 1030 * dma map IOC configuration itself 1031 */ 1032 bfi_h2i_set(cfg_req.mh, BFI_MC_IOCFC, BFI_IOCFC_H2I_CFG_REQ, 1033 bfa_fn_lpu(bfa)); 1034 bfa_dma_be_addr_set(cfg_req.ioc_cfg_dma_addr, iocfc->cfg_info.pa); 1035 1036 bfa_ioc_mbox_send(&bfa->ioc, &cfg_req, 1037 sizeof(struct bfi_iocfc_cfg_req_s)); 1038 } 1039 1040 static void 1041 bfa_iocfc_init_mem(struct bfa_s *bfa, void *bfad, struct bfa_iocfc_cfg_s *cfg, 1042 struct bfa_pcidev_s *pcidev) 1043 { 1044 struct bfa_iocfc_s *iocfc = &bfa->iocfc; 1045 1046 bfa->bfad = bfad; 1047 iocfc->bfa = bfa; 1048 iocfc->cfg = *cfg; 1049 1050 /* 1051 * Initialize chip specific handlers. 1052 */ 1053 if (bfa_asic_id_ctc(bfa_ioc_devid(&bfa->ioc))) { 1054 iocfc->hwif.hw_reginit = bfa_hwct_reginit; 1055 iocfc->hwif.hw_reqq_ack = bfa_hwct_reqq_ack; 1056 iocfc->hwif.hw_rspq_ack = bfa_hwct_rspq_ack; 1057 iocfc->hwif.hw_msix_init = bfa_hwct_msix_init; 1058 iocfc->hwif.hw_msix_ctrl_install = bfa_hwct_msix_ctrl_install; 1059 iocfc->hwif.hw_msix_queue_install = bfa_hwct_msix_queue_install; 1060 iocfc->hwif.hw_msix_uninstall = bfa_hwct_msix_uninstall; 1061 iocfc->hwif.hw_isr_mode_set = bfa_hwct_isr_mode_set; 1062 iocfc->hwif.hw_msix_getvecs = bfa_hwct_msix_getvecs; 1063 iocfc->hwif.hw_msix_get_rme_range = bfa_hwct_msix_get_rme_range; 1064 iocfc->hwif.rme_vec_q0 = BFI_MSIX_RME_QMIN_CT; 1065 iocfc->hwif.cpe_vec_q0 = BFI_MSIX_CPE_QMIN_CT; 1066 } else { 1067 iocfc->hwif.hw_reginit = bfa_hwcb_reginit; 1068 iocfc->hwif.hw_reqq_ack = NULL; 1069 iocfc->hwif.hw_rspq_ack = bfa_hwcb_rspq_ack; 1070 iocfc->hwif.hw_msix_init = bfa_hwcb_msix_init; 1071 iocfc->hwif.hw_msix_ctrl_install = bfa_hwcb_msix_ctrl_install; 1072 iocfc->hwif.hw_msix_queue_install = bfa_hwcb_msix_queue_install; 1073 iocfc->hwif.hw_msix_uninstall = bfa_hwcb_msix_uninstall; 1074 iocfc->hwif.hw_isr_mode_set = bfa_hwcb_isr_mode_set; 1075 iocfc->hwif.hw_msix_getvecs = bfa_hwcb_msix_getvecs; 1076 iocfc->hwif.hw_msix_get_rme_range = bfa_hwcb_msix_get_rme_range; 1077 iocfc->hwif.rme_vec_q0 = BFI_MSIX_RME_QMIN_CB + 1078 bfa_ioc_pcifn(&bfa->ioc) * BFI_IOC_MAX_CQS; 1079 iocfc->hwif.cpe_vec_q0 = BFI_MSIX_CPE_QMIN_CB + 1080 bfa_ioc_pcifn(&bfa->ioc) * BFI_IOC_MAX_CQS; 1081 } 1082 1083 if (bfa_asic_id_ct2(bfa_ioc_devid(&bfa->ioc))) { 1084 iocfc->hwif.hw_reginit = bfa_hwct2_reginit; 1085 iocfc->hwif.hw_isr_mode_set = NULL; 1086 iocfc->hwif.hw_rspq_ack = bfa_hwct2_rspq_ack; 1087 } 1088 1089 iocfc->hwif.hw_reginit(bfa); 1090 bfa->msix.nvecs = 0; 1091 } 1092 1093 static void 1094 bfa_iocfc_mem_claim(struct bfa_s *bfa, struct bfa_iocfc_cfg_s *cfg) 1095 { 1096 u8 *dm_kva = NULL; 1097 u64 dm_pa = 0; 1098 int i, per_reqq_sz, per_rspq_sz; 1099 struct bfa_iocfc_s *iocfc = &bfa->iocfc; 1100 struct bfa_mem_dma_s *ioc_dma = BFA_MEM_IOC_DMA(bfa); 1101 struct bfa_mem_dma_s *iocfc_dma = BFA_MEM_IOCFC_DMA(bfa); 1102 struct bfa_mem_dma_s *reqq_dma, *rspq_dma; 1103 1104 /* First allocate dma memory for IOC */ 1105 bfa_ioc_mem_claim(&bfa->ioc, bfa_mem_dma_virt(ioc_dma), 1106 bfa_mem_dma_phys(ioc_dma)); 1107 1108 /* Claim DMA-able memory for the request/response queues */ 1109 per_reqq_sz = BFA_ROUNDUP((cfg->drvcfg.num_reqq_elems * BFI_LMSG_SZ), 1110 BFA_DMA_ALIGN_SZ); 1111 per_rspq_sz = BFA_ROUNDUP((cfg->drvcfg.num_rspq_elems * BFI_LMSG_SZ), 1112 BFA_DMA_ALIGN_SZ); 1113 1114 for (i = 0; i < cfg->fwcfg.num_cqs; i++) { 1115 reqq_dma = BFA_MEM_REQQ_DMA(bfa, i); 1116 iocfc->req_cq_ba[i].kva = bfa_mem_dma_virt(reqq_dma); 1117 iocfc->req_cq_ba[i].pa = bfa_mem_dma_phys(reqq_dma); 1118 memset(iocfc->req_cq_ba[i].kva, 0, per_reqq_sz); 1119 1120 rspq_dma = BFA_MEM_RSPQ_DMA(bfa, i); 1121 iocfc->rsp_cq_ba[i].kva = bfa_mem_dma_virt(rspq_dma); 1122 iocfc->rsp_cq_ba[i].pa = bfa_mem_dma_phys(rspq_dma); 1123 memset(iocfc->rsp_cq_ba[i].kva, 0, per_rspq_sz); 1124 } 1125 1126 /* Claim IOCFC dma memory - for shadow CI/PI */ 1127 dm_kva = bfa_mem_dma_virt(iocfc_dma); 1128 dm_pa = bfa_mem_dma_phys(iocfc_dma); 1129 1130 for (i = 0; i < cfg->fwcfg.num_cqs; i++) { 1131 iocfc->req_cq_shadow_ci[i].kva = dm_kva; 1132 iocfc->req_cq_shadow_ci[i].pa = dm_pa; 1133 dm_kva += BFA_CACHELINE_SZ; 1134 dm_pa += BFA_CACHELINE_SZ; 1135 1136 iocfc->rsp_cq_shadow_pi[i].kva = dm_kva; 1137 iocfc->rsp_cq_shadow_pi[i].pa = dm_pa; 1138 dm_kva += BFA_CACHELINE_SZ; 1139 dm_pa += BFA_CACHELINE_SZ; 1140 } 1141 1142 /* Claim IOCFC dma memory - for the config info page */ 1143 bfa->iocfc.cfg_info.kva = dm_kva; 1144 bfa->iocfc.cfg_info.pa = dm_pa; 1145 bfa->iocfc.cfginfo = (struct bfi_iocfc_cfg_s *) dm_kva; 1146 dm_kva += BFA_ROUNDUP(sizeof(struct bfi_iocfc_cfg_s), BFA_CACHELINE_SZ); 1147 dm_pa += BFA_ROUNDUP(sizeof(struct bfi_iocfc_cfg_s), BFA_CACHELINE_SZ); 1148 1149 /* Claim IOCFC dma memory - for the config response */ 1150 bfa->iocfc.cfgrsp_dma.kva = dm_kva; 1151 bfa->iocfc.cfgrsp_dma.pa = dm_pa; 1152 bfa->iocfc.cfgrsp = (struct bfi_iocfc_cfgrsp_s *) dm_kva; 1153 dm_kva += BFA_ROUNDUP(sizeof(struct bfi_iocfc_cfgrsp_s), 1154 BFA_CACHELINE_SZ); 1155 dm_pa += BFA_ROUNDUP(sizeof(struct bfi_iocfc_cfgrsp_s), 1156 BFA_CACHELINE_SZ); 1157 1158 /* Claim IOCFC kva memory */ 1159 bfa_ioc_debug_memclaim(&bfa->ioc, bfa_mem_kva_curp(iocfc)); 1160 bfa_mem_kva_curp(iocfc) += BFA_DBG_FWTRC_LEN; 1161 } 1162 1163 /* 1164 * Start BFA submodules. 1165 */ 1166 static void 1167 bfa_iocfc_start_submod(struct bfa_s *bfa) 1168 { 1169 int i; 1170 1171 bfa->queue_process = BFA_TRUE; 1172 for (i = 0; i < BFI_IOC_MAX_CQS; i++) 1173 bfa_isr_rspq_ack(bfa, i, bfa_rspq_ci(bfa, i)); 1174 1175 for (i = 0; hal_mods[i]; i++) 1176 hal_mods[i]->start(bfa); 1177 1178 bfa->iocfc.submod_enabled = BFA_TRUE; 1179 } 1180 1181 /* 1182 * Disable BFA submodules. 1183 */ 1184 static void 1185 bfa_iocfc_disable_submod(struct bfa_s *bfa) 1186 { 1187 int i; 1188 1189 if (bfa->iocfc.submod_enabled == BFA_FALSE) 1190 return; 1191 1192 for (i = 0; hal_mods[i]; i++) 1193 hal_mods[i]->iocdisable(bfa); 1194 1195 bfa->iocfc.submod_enabled = BFA_FALSE; 1196 } 1197 1198 static void 1199 bfa_iocfc_init_cb(void *bfa_arg, bfa_boolean_t complete) 1200 { 1201 struct bfa_s *bfa = bfa_arg; 1202 1203 if (complete) 1204 bfa_cb_init(bfa->bfad, bfa->iocfc.op_status); 1205 } 1206 1207 static void 1208 bfa_iocfc_stop_cb(void *bfa_arg, bfa_boolean_t compl) 1209 { 1210 struct bfa_s *bfa = bfa_arg; 1211 struct bfad_s *bfad = bfa->bfad; 1212 1213 if (compl) 1214 complete(&bfad->comp); 1215 } 1216 1217 static void 1218 bfa_iocfc_enable_cb(void *bfa_arg, bfa_boolean_t compl) 1219 { 1220 struct bfa_s *bfa = bfa_arg; 1221 struct bfad_s *bfad = bfa->bfad; 1222 1223 if (compl) 1224 complete(&bfad->enable_comp); 1225 } 1226 1227 static void 1228 bfa_iocfc_disable_cb(void *bfa_arg, bfa_boolean_t compl) 1229 { 1230 struct bfa_s *bfa = bfa_arg; 1231 struct bfad_s *bfad = bfa->bfad; 1232 1233 if (compl) 1234 complete(&bfad->disable_comp); 1235 } 1236 1237 /** 1238 * configure queue registers from firmware response 1239 */ 1240 static void 1241 bfa_iocfc_qreg(struct bfa_s *bfa, struct bfi_iocfc_qreg_s *qreg) 1242 { 1243 int i; 1244 struct bfa_iocfc_regs_s *r = &bfa->iocfc.bfa_regs; 1245 void __iomem *kva = bfa_ioc_bar0(&bfa->ioc); 1246 1247 for (i = 0; i < BFI_IOC_MAX_CQS; i++) { 1248 bfa->iocfc.hw_qid[i] = qreg->hw_qid[i]; 1249 r->cpe_q_ci[i] = kva + be32_to_cpu(qreg->cpe_q_ci_off[i]); 1250 r->cpe_q_pi[i] = kva + be32_to_cpu(qreg->cpe_q_pi_off[i]); 1251 r->cpe_q_ctrl[i] = kva + be32_to_cpu(qreg->cpe_qctl_off[i]); 1252 r->rme_q_ci[i] = kva + be32_to_cpu(qreg->rme_q_ci_off[i]); 1253 r->rme_q_pi[i] = kva + be32_to_cpu(qreg->rme_q_pi_off[i]); 1254 r->rme_q_ctrl[i] = kva + be32_to_cpu(qreg->rme_qctl_off[i]); 1255 } 1256 } 1257 1258 static void 1259 bfa_iocfc_res_recfg(struct bfa_s *bfa, struct bfa_iocfc_fwcfg_s *fwcfg) 1260 { 1261 struct bfa_iocfc_s *iocfc = &bfa->iocfc; 1262 struct bfi_iocfc_cfg_s *cfg_info = iocfc->cfginfo; 1263 1264 bfa_fcxp_res_recfg(bfa, fwcfg->num_fcxp_reqs); 1265 bfa_uf_res_recfg(bfa, fwcfg->num_uf_bufs); 1266 bfa_rport_res_recfg(bfa, fwcfg->num_rports); 1267 bfa_fcp_res_recfg(bfa, cpu_to_be16(cfg_info->num_ioim_reqs), 1268 fwcfg->num_ioim_reqs); 1269 bfa_tskim_res_recfg(bfa, fwcfg->num_tskim_reqs); 1270 } 1271 1272 /* 1273 * Update BFA configuration from firmware configuration. 1274 */ 1275 static void 1276 bfa_iocfc_cfgrsp(struct bfa_s *bfa) 1277 { 1278 struct bfa_iocfc_s *iocfc = &bfa->iocfc; 1279 struct bfi_iocfc_cfgrsp_s *cfgrsp = iocfc->cfgrsp; 1280 struct bfa_iocfc_fwcfg_s *fwcfg = &cfgrsp->fwcfg; 1281 1282 fwcfg->num_cqs = fwcfg->num_cqs; 1283 fwcfg->num_ioim_reqs = be16_to_cpu(fwcfg->num_ioim_reqs); 1284 fwcfg->num_fwtio_reqs = be16_to_cpu(fwcfg->num_fwtio_reqs); 1285 fwcfg->num_tskim_reqs = be16_to_cpu(fwcfg->num_tskim_reqs); 1286 fwcfg->num_fcxp_reqs = be16_to_cpu(fwcfg->num_fcxp_reqs); 1287 fwcfg->num_uf_bufs = be16_to_cpu(fwcfg->num_uf_bufs); 1288 fwcfg->num_rports = be16_to_cpu(fwcfg->num_rports); 1289 1290 /* 1291 * configure queue register offsets as learnt from firmware 1292 */ 1293 bfa_iocfc_qreg(bfa, &cfgrsp->qreg); 1294 1295 /* 1296 * Re-configure resources as learnt from Firmware 1297 */ 1298 bfa_iocfc_res_recfg(bfa, fwcfg); 1299 1300 /* 1301 * Install MSIX queue handlers 1302 */ 1303 bfa_msix_queue_install(bfa); 1304 1305 if (bfa->iocfc.cfgrsp->pbc_cfg.pbc_pwwn != 0) { 1306 bfa->ioc.attr->pwwn = bfa->iocfc.cfgrsp->pbc_cfg.pbc_pwwn; 1307 bfa->ioc.attr->nwwn = bfa->iocfc.cfgrsp->pbc_cfg.pbc_nwwn; 1308 bfa_fsm_send_event(iocfc, IOCFC_E_CFG_DONE); 1309 } 1310 } 1311 1312 void 1313 bfa_iocfc_reset_queues(struct bfa_s *bfa) 1314 { 1315 int q; 1316 1317 for (q = 0; q < BFI_IOC_MAX_CQS; q++) { 1318 bfa_reqq_ci(bfa, q) = 0; 1319 bfa_reqq_pi(bfa, q) = 0; 1320 bfa_rspq_ci(bfa, q) = 0; 1321 bfa_rspq_pi(bfa, q) = 0; 1322 } 1323 } 1324 1325 /* 1326 * Process FAA pwwn msg from fw. 1327 */ 1328 static void 1329 bfa_iocfc_process_faa_addr(struct bfa_s *bfa, struct bfi_faa_addr_msg_s *msg) 1330 { 1331 struct bfa_iocfc_s *iocfc = &bfa->iocfc; 1332 struct bfi_iocfc_cfgrsp_s *cfgrsp = iocfc->cfgrsp; 1333 1334 cfgrsp->pbc_cfg.pbc_pwwn = msg->pwwn; 1335 cfgrsp->pbc_cfg.pbc_nwwn = msg->nwwn; 1336 1337 bfa->ioc.attr->pwwn = msg->pwwn; 1338 bfa->ioc.attr->nwwn = msg->nwwn; 1339 bfa_fsm_send_event(iocfc, IOCFC_E_CFG_DONE); 1340 } 1341 1342 /* Fabric Assigned Address specific functions */ 1343 1344 /* 1345 * Check whether IOC is ready before sending command down 1346 */ 1347 static bfa_status_t 1348 bfa_faa_validate_request(struct bfa_s *bfa) 1349 { 1350 enum bfa_ioc_type_e ioc_type = bfa_get_type(bfa); 1351 u32 card_type = bfa->ioc.attr->card_type; 1352 1353 if (bfa_ioc_is_operational(&bfa->ioc)) { 1354 if ((ioc_type != BFA_IOC_TYPE_FC) || bfa_mfg_is_mezz(card_type)) 1355 return BFA_STATUS_FEATURE_NOT_SUPPORTED; 1356 } else { 1357 return BFA_STATUS_IOC_NON_OP; 1358 } 1359 1360 return BFA_STATUS_OK; 1361 } 1362 1363 bfa_status_t 1364 bfa_faa_query(struct bfa_s *bfa, struct bfa_faa_attr_s *attr, 1365 bfa_cb_iocfc_t cbfn, void *cbarg) 1366 { 1367 struct bfi_faa_query_s faa_attr_req; 1368 struct bfa_iocfc_s *iocfc = &bfa->iocfc; 1369 bfa_status_t status; 1370 1371 status = bfa_faa_validate_request(bfa); 1372 if (status != BFA_STATUS_OK) 1373 return status; 1374 1375 if (iocfc->faa_args.busy == BFA_TRUE) 1376 return BFA_STATUS_DEVBUSY; 1377 1378 iocfc->faa_args.faa_attr = attr; 1379 iocfc->faa_args.faa_cb.faa_cbfn = cbfn; 1380 iocfc->faa_args.faa_cb.faa_cbarg = cbarg; 1381 1382 iocfc->faa_args.busy = BFA_TRUE; 1383 memset(&faa_attr_req, 0, sizeof(struct bfi_faa_query_s)); 1384 bfi_h2i_set(faa_attr_req.mh, BFI_MC_IOCFC, 1385 BFI_IOCFC_H2I_FAA_QUERY_REQ, bfa_fn_lpu(bfa)); 1386 1387 bfa_ioc_mbox_send(&bfa->ioc, &faa_attr_req, 1388 sizeof(struct bfi_faa_query_s)); 1389 1390 return BFA_STATUS_OK; 1391 } 1392 1393 /* 1394 * FAA query response 1395 */ 1396 static void 1397 bfa_faa_query_reply(struct bfa_iocfc_s *iocfc, 1398 bfi_faa_query_rsp_t *rsp) 1399 { 1400 void *cbarg = iocfc->faa_args.faa_cb.faa_cbarg; 1401 1402 if (iocfc->faa_args.faa_attr) { 1403 iocfc->faa_args.faa_attr->faa = rsp->faa; 1404 iocfc->faa_args.faa_attr->faa_state = rsp->faa_status; 1405 iocfc->faa_args.faa_attr->pwwn_source = rsp->addr_source; 1406 } 1407 1408 WARN_ON(!iocfc->faa_args.faa_cb.faa_cbfn); 1409 1410 iocfc->faa_args.faa_cb.faa_cbfn(cbarg, BFA_STATUS_OK); 1411 iocfc->faa_args.busy = BFA_FALSE; 1412 } 1413 1414 /* 1415 * IOC enable request is complete 1416 */ 1417 static void 1418 bfa_iocfc_enable_cbfn(void *bfa_arg, enum bfa_status status) 1419 { 1420 struct bfa_s *bfa = bfa_arg; 1421 1422 if (status == BFA_STATUS_OK) 1423 bfa_fsm_send_event(&bfa->iocfc, IOCFC_E_IOC_ENABLED); 1424 else 1425 bfa_fsm_send_event(&bfa->iocfc, IOCFC_E_IOC_FAILED); 1426 } 1427 1428 /* 1429 * IOC disable request is complete 1430 */ 1431 static void 1432 bfa_iocfc_disable_cbfn(void *bfa_arg) 1433 { 1434 struct bfa_s *bfa = bfa_arg; 1435 1436 bfa->queue_process = BFA_FALSE; 1437 bfa_fsm_send_event(&bfa->iocfc, IOCFC_E_IOC_DISABLED); 1438 } 1439 1440 /* 1441 * Notify sub-modules of hardware failure. 1442 */ 1443 static void 1444 bfa_iocfc_hbfail_cbfn(void *bfa_arg) 1445 { 1446 struct bfa_s *bfa = bfa_arg; 1447 1448 bfa->queue_process = BFA_FALSE; 1449 bfa_fsm_send_event(&bfa->iocfc, IOCFC_E_IOC_FAILED); 1450 } 1451 1452 /* 1453 * Actions on chip-reset completion. 1454 */ 1455 static void 1456 bfa_iocfc_reset_cbfn(void *bfa_arg) 1457 { 1458 struct bfa_s *bfa = bfa_arg; 1459 1460 bfa_iocfc_reset_queues(bfa); 1461 bfa_isr_enable(bfa); 1462 } 1463 1464 /* 1465 * Query IOC memory requirement information. 1466 */ 1467 void 1468 bfa_iocfc_meminfo(struct bfa_iocfc_cfg_s *cfg, struct bfa_meminfo_s *meminfo, 1469 struct bfa_s *bfa) 1470 { 1471 int q, per_reqq_sz, per_rspq_sz; 1472 struct bfa_mem_dma_s *ioc_dma = BFA_MEM_IOC_DMA(bfa); 1473 struct bfa_mem_dma_s *iocfc_dma = BFA_MEM_IOCFC_DMA(bfa); 1474 struct bfa_mem_kva_s *iocfc_kva = BFA_MEM_IOCFC_KVA(bfa); 1475 u32 dm_len = 0; 1476 1477 /* dma memory setup for IOC */ 1478 bfa_mem_dma_setup(meminfo, ioc_dma, 1479 BFA_ROUNDUP(sizeof(struct bfi_ioc_attr_s), BFA_DMA_ALIGN_SZ)); 1480 1481 /* dma memory setup for REQ/RSP queues */ 1482 per_reqq_sz = BFA_ROUNDUP((cfg->drvcfg.num_reqq_elems * BFI_LMSG_SZ), 1483 BFA_DMA_ALIGN_SZ); 1484 per_rspq_sz = BFA_ROUNDUP((cfg->drvcfg.num_rspq_elems * BFI_LMSG_SZ), 1485 BFA_DMA_ALIGN_SZ); 1486 1487 for (q = 0; q < cfg->fwcfg.num_cqs; q++) { 1488 bfa_mem_dma_setup(meminfo, BFA_MEM_REQQ_DMA(bfa, q), 1489 per_reqq_sz); 1490 bfa_mem_dma_setup(meminfo, BFA_MEM_RSPQ_DMA(bfa, q), 1491 per_rspq_sz); 1492 } 1493 1494 /* IOCFC dma memory - calculate Shadow CI/PI size */ 1495 for (q = 0; q < cfg->fwcfg.num_cqs; q++) 1496 dm_len += (2 * BFA_CACHELINE_SZ); 1497 1498 /* IOCFC dma memory - calculate config info / rsp size */ 1499 dm_len += BFA_ROUNDUP(sizeof(struct bfi_iocfc_cfg_s), BFA_CACHELINE_SZ); 1500 dm_len += BFA_ROUNDUP(sizeof(struct bfi_iocfc_cfgrsp_s), 1501 BFA_CACHELINE_SZ); 1502 1503 /* dma memory setup for IOCFC */ 1504 bfa_mem_dma_setup(meminfo, iocfc_dma, dm_len); 1505 1506 /* kva memory setup for IOCFC */ 1507 bfa_mem_kva_setup(meminfo, iocfc_kva, BFA_DBG_FWTRC_LEN); 1508 } 1509 1510 /* 1511 * Query IOC memory requirement information. 1512 */ 1513 void 1514 bfa_iocfc_attach(struct bfa_s *bfa, void *bfad, struct bfa_iocfc_cfg_s *cfg, 1515 struct bfa_pcidev_s *pcidev) 1516 { 1517 int i; 1518 struct bfa_ioc_s *ioc = &bfa->ioc; 1519 1520 bfa_iocfc_cbfn.enable_cbfn = bfa_iocfc_enable_cbfn; 1521 bfa_iocfc_cbfn.disable_cbfn = bfa_iocfc_disable_cbfn; 1522 bfa_iocfc_cbfn.hbfail_cbfn = bfa_iocfc_hbfail_cbfn; 1523 bfa_iocfc_cbfn.reset_cbfn = bfa_iocfc_reset_cbfn; 1524 1525 ioc->trcmod = bfa->trcmod; 1526 bfa_ioc_attach(&bfa->ioc, bfa, &bfa_iocfc_cbfn, &bfa->timer_mod); 1527 1528 bfa_ioc_pci_init(&bfa->ioc, pcidev, BFI_PCIFN_CLASS_FC); 1529 bfa_ioc_mbox_register(&bfa->ioc, bfa_mbox_isrs); 1530 1531 bfa_iocfc_init_mem(bfa, bfad, cfg, pcidev); 1532 bfa_iocfc_mem_claim(bfa, cfg); 1533 INIT_LIST_HEAD(&bfa->timer_mod.timer_q); 1534 1535 INIT_LIST_HEAD(&bfa->comp_q); 1536 for (i = 0; i < BFI_IOC_MAX_CQS; i++) 1537 INIT_LIST_HEAD(&bfa->reqq_waitq[i]); 1538 1539 bfa->iocfc.cb_reqd = BFA_FALSE; 1540 bfa->iocfc.op_status = BFA_STATUS_OK; 1541 bfa->iocfc.submod_enabled = BFA_FALSE; 1542 1543 bfa_fsm_set_state(&bfa->iocfc, bfa_iocfc_sm_stopped); 1544 } 1545 1546 /* 1547 * Query IOC memory requirement information. 1548 */ 1549 void 1550 bfa_iocfc_init(struct bfa_s *bfa) 1551 { 1552 bfa_fsm_send_event(&bfa->iocfc, IOCFC_E_INIT); 1553 } 1554 1555 /* 1556 * IOC start called from bfa_start(). Called to start IOC operations 1557 * at driver instantiation for this instance. 1558 */ 1559 void 1560 bfa_iocfc_start(struct bfa_s *bfa) 1561 { 1562 bfa_fsm_send_event(&bfa->iocfc, IOCFC_E_START); 1563 } 1564 1565 /* 1566 * IOC stop called from bfa_stop(). Called only when driver is unloaded 1567 * for this instance. 1568 */ 1569 void 1570 bfa_iocfc_stop(struct bfa_s *bfa) 1571 { 1572 bfa_fsm_send_event(&bfa->iocfc, IOCFC_E_STOP); 1573 } 1574 1575 void 1576 bfa_iocfc_isr(void *bfaarg, struct bfi_mbmsg_s *m) 1577 { 1578 struct bfa_s *bfa = bfaarg; 1579 struct bfa_iocfc_s *iocfc = &bfa->iocfc; 1580 union bfi_iocfc_i2h_msg_u *msg; 1581 1582 msg = (union bfi_iocfc_i2h_msg_u *) m; 1583 bfa_trc(bfa, msg->mh.msg_id); 1584 1585 switch (msg->mh.msg_id) { 1586 case BFI_IOCFC_I2H_CFG_REPLY: 1587 bfa_iocfc_cfgrsp(bfa); 1588 break; 1589 case BFI_IOCFC_I2H_UPDATEQ_RSP: 1590 iocfc->updateq_cbfn(iocfc->updateq_cbarg, BFA_STATUS_OK); 1591 break; 1592 case BFI_IOCFC_I2H_ADDR_MSG: 1593 bfa_iocfc_process_faa_addr(bfa, 1594 (struct bfi_faa_addr_msg_s *)msg); 1595 break; 1596 case BFI_IOCFC_I2H_FAA_QUERY_RSP: 1597 bfa_faa_query_reply(iocfc, (bfi_faa_query_rsp_t *)msg); 1598 break; 1599 default: 1600 WARN_ON(1); 1601 } 1602 } 1603 1604 void 1605 bfa_iocfc_get_attr(struct bfa_s *bfa, struct bfa_iocfc_attr_s *attr) 1606 { 1607 struct bfa_iocfc_s *iocfc = &bfa->iocfc; 1608 1609 attr->intr_attr.coalesce = iocfc->cfginfo->intr_attr.coalesce; 1610 1611 attr->intr_attr.delay = iocfc->cfginfo->intr_attr.delay ? 1612 be16_to_cpu(iocfc->cfginfo->intr_attr.delay) : 1613 be16_to_cpu(iocfc->cfgrsp->intr_attr.delay); 1614 1615 attr->intr_attr.latency = iocfc->cfginfo->intr_attr.latency ? 1616 be16_to_cpu(iocfc->cfginfo->intr_attr.latency) : 1617 be16_to_cpu(iocfc->cfgrsp->intr_attr.latency); 1618 1619 attr->config = iocfc->cfg; 1620 } 1621 1622 bfa_status_t 1623 bfa_iocfc_israttr_set(struct bfa_s *bfa, struct bfa_iocfc_intr_attr_s *attr) 1624 { 1625 struct bfa_iocfc_s *iocfc = &bfa->iocfc; 1626 struct bfi_iocfc_set_intr_req_s *m; 1627 1628 iocfc->cfginfo->intr_attr.coalesce = attr->coalesce; 1629 iocfc->cfginfo->intr_attr.delay = cpu_to_be16(attr->delay); 1630 iocfc->cfginfo->intr_attr.latency = cpu_to_be16(attr->latency); 1631 1632 if (!bfa_iocfc_is_operational(bfa)) 1633 return BFA_STATUS_OK; 1634 1635 m = bfa_reqq_next(bfa, BFA_REQQ_IOC); 1636 if (!m) 1637 return BFA_STATUS_DEVBUSY; 1638 1639 bfi_h2i_set(m->mh, BFI_MC_IOCFC, BFI_IOCFC_H2I_SET_INTR_REQ, 1640 bfa_fn_lpu(bfa)); 1641 m->coalesce = iocfc->cfginfo->intr_attr.coalesce; 1642 m->delay = iocfc->cfginfo->intr_attr.delay; 1643 m->latency = iocfc->cfginfo->intr_attr.latency; 1644 1645 bfa_trc(bfa, attr->delay); 1646 bfa_trc(bfa, attr->latency); 1647 1648 bfa_reqq_produce(bfa, BFA_REQQ_IOC, m->mh); 1649 return BFA_STATUS_OK; 1650 } 1651 1652 void 1653 bfa_iocfc_set_snsbase(struct bfa_s *bfa, int seg_no, u64 snsbase_pa) 1654 { 1655 struct bfa_iocfc_s *iocfc = &bfa->iocfc; 1656 1657 iocfc->cfginfo->sense_buf_len = (BFI_IOIM_SNSLEN - 1); 1658 bfa_dma_be_addr_set(iocfc->cfginfo->ioim_snsbase[seg_no], snsbase_pa); 1659 } 1660 /* 1661 * Enable IOC after it is disabled. 1662 */ 1663 void 1664 bfa_iocfc_enable(struct bfa_s *bfa) 1665 { 1666 bfa_plog_str(bfa->plog, BFA_PL_MID_HAL, BFA_PL_EID_MISC, 0, 1667 "IOC Enable"); 1668 bfa->iocfc.cb_reqd = BFA_TRUE; 1669 bfa_fsm_send_event(&bfa->iocfc, IOCFC_E_ENABLE); 1670 } 1671 1672 void 1673 bfa_iocfc_disable(struct bfa_s *bfa) 1674 { 1675 bfa_plog_str(bfa->plog, BFA_PL_MID_HAL, BFA_PL_EID_MISC, 0, 1676 "IOC Disable"); 1677 1678 bfa_fsm_send_event(&bfa->iocfc, IOCFC_E_DISABLE); 1679 } 1680 1681 bfa_boolean_t 1682 bfa_iocfc_is_operational(struct bfa_s *bfa) 1683 { 1684 return bfa_ioc_is_operational(&bfa->ioc) && 1685 bfa_fsm_cmp_state(&bfa->iocfc, bfa_iocfc_sm_operational); 1686 } 1687 1688 /* 1689 * Return boot target port wwns -- read from boot information in flash. 1690 */ 1691 void 1692 bfa_iocfc_get_bootwwns(struct bfa_s *bfa, u8 *nwwns, wwn_t *wwns) 1693 { 1694 struct bfa_iocfc_s *iocfc = &bfa->iocfc; 1695 struct bfi_iocfc_cfgrsp_s *cfgrsp = iocfc->cfgrsp; 1696 int i; 1697 1698 if (cfgrsp->pbc_cfg.boot_enabled && cfgrsp->pbc_cfg.nbluns) { 1699 bfa_trc(bfa, cfgrsp->pbc_cfg.nbluns); 1700 *nwwns = cfgrsp->pbc_cfg.nbluns; 1701 for (i = 0; i < cfgrsp->pbc_cfg.nbluns; i++) 1702 wwns[i] = cfgrsp->pbc_cfg.blun[i].tgt_pwwn; 1703 1704 return; 1705 } 1706 1707 *nwwns = cfgrsp->bootwwns.nwwns; 1708 memcpy(wwns, cfgrsp->bootwwns.wwn, sizeof(cfgrsp->bootwwns.wwn)); 1709 } 1710 1711 int 1712 bfa_iocfc_get_pbc_vports(struct bfa_s *bfa, struct bfi_pbc_vport_s *pbc_vport) 1713 { 1714 struct bfa_iocfc_s *iocfc = &bfa->iocfc; 1715 struct bfi_iocfc_cfgrsp_s *cfgrsp = iocfc->cfgrsp; 1716 1717 memcpy(pbc_vport, cfgrsp->pbc_cfg.vport, sizeof(cfgrsp->pbc_cfg.vport)); 1718 return cfgrsp->pbc_cfg.nvports; 1719 } 1720 1721 1722 /* 1723 * Use this function query the memory requirement of the BFA library. 1724 * This function needs to be called before bfa_attach() to get the 1725 * memory required of the BFA layer for a given driver configuration. 1726 * 1727 * This call will fail, if the cap is out of range compared to pre-defined 1728 * values within the BFA library 1729 * 1730 * @param[in] cfg - pointer to bfa_ioc_cfg_t. Driver layer should indicate 1731 * its configuration in this structure. 1732 * The default values for struct bfa_iocfc_cfg_s can be 1733 * fetched using bfa_cfg_get_default() API. 1734 * 1735 * If cap's boundary check fails, the library will use 1736 * the default bfa_cap_t values (and log a warning msg). 1737 * 1738 * @param[out] meminfo - pointer to bfa_meminfo_t. This content 1739 * indicates the memory type (see bfa_mem_type_t) and 1740 * amount of memory required. 1741 * 1742 * Driver should allocate the memory, populate the 1743 * starting address for each block and provide the same 1744 * structure as input parameter to bfa_attach() call. 1745 * 1746 * @param[in] bfa - pointer to the bfa structure, used while fetching the 1747 * dma, kva memory information of the bfa sub-modules. 1748 * 1749 * @return void 1750 * 1751 * Special Considerations: @note 1752 */ 1753 void 1754 bfa_cfg_get_meminfo(struct bfa_iocfc_cfg_s *cfg, struct bfa_meminfo_s *meminfo, 1755 struct bfa_s *bfa) 1756 { 1757 int i; 1758 struct bfa_mem_dma_s *port_dma = BFA_MEM_PORT_DMA(bfa); 1759 struct bfa_mem_dma_s *ablk_dma = BFA_MEM_ABLK_DMA(bfa); 1760 struct bfa_mem_dma_s *cee_dma = BFA_MEM_CEE_DMA(bfa); 1761 struct bfa_mem_dma_s *sfp_dma = BFA_MEM_SFP_DMA(bfa); 1762 struct bfa_mem_dma_s *flash_dma = BFA_MEM_FLASH_DMA(bfa); 1763 struct bfa_mem_dma_s *diag_dma = BFA_MEM_DIAG_DMA(bfa); 1764 struct bfa_mem_dma_s *phy_dma = BFA_MEM_PHY_DMA(bfa); 1765 struct bfa_mem_dma_s *fru_dma = BFA_MEM_FRU_DMA(bfa); 1766 1767 WARN_ON((cfg == NULL) || (meminfo == NULL)); 1768 1769 memset((void *)meminfo, 0, sizeof(struct bfa_meminfo_s)); 1770 1771 /* Initialize the DMA & KVA meminfo queues */ 1772 INIT_LIST_HEAD(&meminfo->dma_info.qe); 1773 INIT_LIST_HEAD(&meminfo->kva_info.qe); 1774 1775 bfa_iocfc_meminfo(cfg, meminfo, bfa); 1776 1777 for (i = 0; hal_mods[i]; i++) 1778 hal_mods[i]->meminfo(cfg, meminfo, bfa); 1779 1780 /* dma info setup */ 1781 bfa_mem_dma_setup(meminfo, port_dma, bfa_port_meminfo()); 1782 bfa_mem_dma_setup(meminfo, ablk_dma, bfa_ablk_meminfo()); 1783 bfa_mem_dma_setup(meminfo, cee_dma, bfa_cee_meminfo()); 1784 bfa_mem_dma_setup(meminfo, sfp_dma, bfa_sfp_meminfo()); 1785 bfa_mem_dma_setup(meminfo, flash_dma, 1786 bfa_flash_meminfo(cfg->drvcfg.min_cfg)); 1787 bfa_mem_dma_setup(meminfo, diag_dma, bfa_diag_meminfo()); 1788 bfa_mem_dma_setup(meminfo, phy_dma, 1789 bfa_phy_meminfo(cfg->drvcfg.min_cfg)); 1790 bfa_mem_dma_setup(meminfo, fru_dma, 1791 bfa_fru_meminfo(cfg->drvcfg.min_cfg)); 1792 } 1793 1794 /* 1795 * Use this function to do attach the driver instance with the BFA 1796 * library. This function will not trigger any HW initialization 1797 * process (which will be done in bfa_init() call) 1798 * 1799 * This call will fail, if the cap is out of range compared to 1800 * pre-defined values within the BFA library 1801 * 1802 * @param[out] bfa Pointer to bfa_t. 1803 * @param[in] bfad Opaque handle back to the driver's IOC structure 1804 * @param[in] cfg Pointer to bfa_ioc_cfg_t. Should be same structure 1805 * that was used in bfa_cfg_get_meminfo(). 1806 * @param[in] meminfo Pointer to bfa_meminfo_t. The driver should 1807 * use the bfa_cfg_get_meminfo() call to 1808 * find the memory blocks required, allocate the 1809 * required memory and provide the starting addresses. 1810 * @param[in] pcidev pointer to struct bfa_pcidev_s 1811 * 1812 * @return 1813 * void 1814 * 1815 * Special Considerations: 1816 * 1817 * @note 1818 * 1819 */ 1820 void 1821 bfa_attach(struct bfa_s *bfa, void *bfad, struct bfa_iocfc_cfg_s *cfg, 1822 struct bfa_meminfo_s *meminfo, struct bfa_pcidev_s *pcidev) 1823 { 1824 int i; 1825 struct bfa_mem_dma_s *dma_info, *dma_elem; 1826 struct bfa_mem_kva_s *kva_info, *kva_elem; 1827 struct list_head *dm_qe, *km_qe; 1828 1829 bfa->fcs = BFA_FALSE; 1830 1831 WARN_ON((cfg == NULL) || (meminfo == NULL)); 1832 1833 /* Initialize memory pointers for iterative allocation */ 1834 dma_info = &meminfo->dma_info; 1835 dma_info->kva_curp = dma_info->kva; 1836 dma_info->dma_curp = dma_info->dma; 1837 1838 kva_info = &meminfo->kva_info; 1839 kva_info->kva_curp = kva_info->kva; 1840 1841 list_for_each(dm_qe, &dma_info->qe) { 1842 dma_elem = (struct bfa_mem_dma_s *) dm_qe; 1843 dma_elem->kva_curp = dma_elem->kva; 1844 dma_elem->dma_curp = dma_elem->dma; 1845 } 1846 1847 list_for_each(km_qe, &kva_info->qe) { 1848 kva_elem = (struct bfa_mem_kva_s *) km_qe; 1849 kva_elem->kva_curp = kva_elem->kva; 1850 } 1851 1852 bfa_iocfc_attach(bfa, bfad, cfg, pcidev); 1853 1854 for (i = 0; hal_mods[i]; i++) 1855 hal_mods[i]->attach(bfa, bfad, cfg, pcidev); 1856 1857 bfa_com_port_attach(bfa); 1858 bfa_com_ablk_attach(bfa); 1859 bfa_com_cee_attach(bfa); 1860 bfa_com_sfp_attach(bfa); 1861 bfa_com_flash_attach(bfa, cfg->drvcfg.min_cfg); 1862 bfa_com_diag_attach(bfa); 1863 bfa_com_phy_attach(bfa, cfg->drvcfg.min_cfg); 1864 bfa_com_fru_attach(bfa, cfg->drvcfg.min_cfg); 1865 } 1866 1867 /* 1868 * Use this function to delete a BFA IOC. IOC should be stopped (by 1869 * calling bfa_stop()) before this function call. 1870 * 1871 * @param[in] bfa - pointer to bfa_t. 1872 * 1873 * @return 1874 * void 1875 * 1876 * Special Considerations: 1877 * 1878 * @note 1879 */ 1880 void 1881 bfa_detach(struct bfa_s *bfa) 1882 { 1883 int i; 1884 1885 for (i = 0; hal_mods[i]; i++) 1886 hal_mods[i]->detach(bfa); 1887 bfa_ioc_detach(&bfa->ioc); 1888 } 1889 1890 void 1891 bfa_comp_deq(struct bfa_s *bfa, struct list_head *comp_q) 1892 { 1893 INIT_LIST_HEAD(comp_q); 1894 list_splice_tail_init(&bfa->comp_q, comp_q); 1895 } 1896 1897 void 1898 bfa_comp_process(struct bfa_s *bfa, struct list_head *comp_q) 1899 { 1900 struct list_head *qe; 1901 struct list_head *qen; 1902 struct bfa_cb_qe_s *hcb_qe; 1903 bfa_cb_cbfn_status_t cbfn; 1904 1905 list_for_each_safe(qe, qen, comp_q) { 1906 hcb_qe = (struct bfa_cb_qe_s *) qe; 1907 if (hcb_qe->pre_rmv) { 1908 /* qe is invalid after return, dequeue before cbfn() */ 1909 list_del(qe); 1910 cbfn = (bfa_cb_cbfn_status_t)(hcb_qe->cbfn); 1911 cbfn(hcb_qe->cbarg, hcb_qe->fw_status); 1912 } else 1913 hcb_qe->cbfn(hcb_qe->cbarg, BFA_TRUE); 1914 } 1915 } 1916 1917 void 1918 bfa_comp_free(struct bfa_s *bfa, struct list_head *comp_q) 1919 { 1920 struct list_head *qe; 1921 struct bfa_cb_qe_s *hcb_qe; 1922 1923 while (!list_empty(comp_q)) { 1924 bfa_q_deq(comp_q, &qe); 1925 hcb_qe = (struct bfa_cb_qe_s *) qe; 1926 WARN_ON(hcb_qe->pre_rmv); 1927 hcb_qe->cbfn(hcb_qe->cbarg, BFA_FALSE); 1928 } 1929 } 1930 1931 /* 1932 * Return the list of PCI vendor/device id lists supported by this 1933 * BFA instance. 1934 */ 1935 void 1936 bfa_get_pciids(struct bfa_pciid_s **pciids, int *npciids) 1937 { 1938 static struct bfa_pciid_s __pciids[] = { 1939 {BFA_PCI_VENDOR_ID_BROCADE, BFA_PCI_DEVICE_ID_FC_8G2P}, 1940 {BFA_PCI_VENDOR_ID_BROCADE, BFA_PCI_DEVICE_ID_FC_8G1P}, 1941 {BFA_PCI_VENDOR_ID_BROCADE, BFA_PCI_DEVICE_ID_CT}, 1942 {BFA_PCI_VENDOR_ID_BROCADE, BFA_PCI_DEVICE_ID_CT_FC}, 1943 }; 1944 1945 *npciids = sizeof(__pciids) / sizeof(__pciids[0]); 1946 *pciids = __pciids; 1947 } 1948 1949 /* 1950 * Use this function query the default struct bfa_iocfc_cfg_s value (compiled 1951 * into BFA layer). The OS driver can then turn back and overwrite entries that 1952 * have been configured by the user. 1953 * 1954 * @param[in] cfg - pointer to bfa_ioc_cfg_t 1955 * 1956 * @return 1957 * void 1958 * 1959 * Special Considerations: 1960 * note 1961 */ 1962 void 1963 bfa_cfg_get_default(struct bfa_iocfc_cfg_s *cfg) 1964 { 1965 cfg->fwcfg.num_fabrics = DEF_CFG_NUM_FABRICS; 1966 cfg->fwcfg.num_lports = DEF_CFG_NUM_LPORTS; 1967 cfg->fwcfg.num_rports = DEF_CFG_NUM_RPORTS; 1968 cfg->fwcfg.num_ioim_reqs = DEF_CFG_NUM_IOIM_REQS; 1969 cfg->fwcfg.num_tskim_reqs = DEF_CFG_NUM_TSKIM_REQS; 1970 cfg->fwcfg.num_fcxp_reqs = DEF_CFG_NUM_FCXP_REQS; 1971 cfg->fwcfg.num_uf_bufs = DEF_CFG_NUM_UF_BUFS; 1972 cfg->fwcfg.num_cqs = DEF_CFG_NUM_CQS; 1973 cfg->fwcfg.num_fwtio_reqs = 0; 1974 1975 cfg->drvcfg.num_reqq_elems = DEF_CFG_NUM_REQQ_ELEMS; 1976 cfg->drvcfg.num_rspq_elems = DEF_CFG_NUM_RSPQ_ELEMS; 1977 cfg->drvcfg.num_sgpgs = DEF_CFG_NUM_SGPGS; 1978 cfg->drvcfg.num_sboot_tgts = DEF_CFG_NUM_SBOOT_TGTS; 1979 cfg->drvcfg.num_sboot_luns = DEF_CFG_NUM_SBOOT_LUNS; 1980 cfg->drvcfg.path_tov = BFA_FCPIM_PATHTOV_DEF; 1981 cfg->drvcfg.ioc_recover = BFA_FALSE; 1982 cfg->drvcfg.delay_comp = BFA_FALSE; 1983 1984 } 1985 1986 void 1987 bfa_cfg_get_min(struct bfa_iocfc_cfg_s *cfg) 1988 { 1989 bfa_cfg_get_default(cfg); 1990 cfg->fwcfg.num_ioim_reqs = BFA_IOIM_MIN; 1991 cfg->fwcfg.num_tskim_reqs = BFA_TSKIM_MIN; 1992 cfg->fwcfg.num_fcxp_reqs = BFA_FCXP_MIN; 1993 cfg->fwcfg.num_uf_bufs = BFA_UF_MIN; 1994 cfg->fwcfg.num_rports = BFA_RPORT_MIN; 1995 cfg->fwcfg.num_fwtio_reqs = 0; 1996 1997 cfg->drvcfg.num_sgpgs = BFA_SGPG_MIN; 1998 cfg->drvcfg.num_reqq_elems = BFA_REQQ_NELEMS_MIN; 1999 cfg->drvcfg.num_rspq_elems = BFA_RSPQ_NELEMS_MIN; 2000 cfg->drvcfg.min_cfg = BFA_TRUE; 2001 } 2002