xref: /openbmc/linux/drivers/scsi/be2iscsi/be_main.h (revision b6bec26c) 
1 /**
2  * Copyright (C) 2005 - 2012 Emulex
3  * All rights reserved.
4  *
5  * This program is free software; you can redistribute it and/or
6  * modify it under the terms of the GNU General Public License version 2
7  * as published by the Free Software Foundation.  The full GNU General
8  * Public License is included in this distribution in the file called COPYING.
9  *
10  * Written by: Jayamohan Kallickal (jayamohan.kallickal@emulex.com)
11  *
12  * Contact Information:
13  * linux-drivers@emulex.com
14  *
15  * Emulex
16  * 3333 Susan Street
17  * Costa Mesa, CA 92626
18  */
19 
20 #ifndef _BEISCSI_MAIN_
21 #define _BEISCSI_MAIN_
22 
23 #include <linux/kernel.h>
24 #include <linux/pci.h>
25 #include <linux/if_ether.h>
26 #include <linux/in.h>
27 #include <linux/ctype.h>
28 #include <linux/module.h>
29 #include <scsi/scsi.h>
30 #include <scsi/scsi_cmnd.h>
31 #include <scsi/scsi_device.h>
32 #include <scsi/scsi_host.h>
33 #include <scsi/iscsi_proto.h>
34 #include <scsi/libiscsi.h>
35 #include <scsi/scsi_transport_iscsi.h>
36 
37 #include "be.h"
38 #define DRV_NAME		"be2iscsi"
39 #define BUILD_STR		"10.0.272.0"
40 #define BE_NAME			"Emulex OneConnect" \
41 				"Open-iSCSI Driver version" BUILD_STR
42 #define DRV_DESC		BE_NAME " " "Driver"
43 
44 #define BE_VENDOR_ID		0x19A2
45 #define ELX_VENDOR_ID		0x10DF
46 /* DEVICE ID's for BE2 */
47 #define BE_DEVICE_ID1		0x212
48 #define OC_DEVICE_ID1		0x702
49 #define OC_DEVICE_ID2		0x703
50 
51 /* DEVICE ID's for BE3 */
52 #define BE_DEVICE_ID2		0x222
53 #define OC_DEVICE_ID3		0x712
54 
55 /* DEVICE ID for SKH */
56 #define OC_SKH_ID1		0x722
57 
58 #define BE2_IO_DEPTH		1024
59 #define BE2_MAX_SESSIONS	256
60 #define BE2_CMDS_PER_CXN	128
61 #define BE2_TMFS		16
62 #define BE2_NOPOUT_REQ		16
63 #define BE2_SGE			32
64 #define BE2_DEFPDU_HDR_SZ	64
65 #define BE2_DEFPDU_DATA_SZ	8192
66 
67 #define MAX_CPUS		64
68 #define BEISCSI_MAX_NUM_CPUS	7
69 #define OC_SKH_MAX_NUM_CPUS	63
70 
71 
72 #define BEISCSI_SGLIST_ELEMENTS	30
73 
74 #define BEISCSI_CMD_PER_LUN	128	/* scsi_host->cmd_per_lun */
75 #define BEISCSI_MAX_SECTORS	2048	/* scsi_host->max_sectors */
76 
77 #define BEISCSI_MAX_CMD_LEN	16	/* scsi_host->max_cmd_len */
78 #define BEISCSI_NUM_MAX_LUN	256	/* scsi_host->max_lun */
79 #define BEISCSI_NUM_DEVICES_SUPPORTED	0x01
80 #define BEISCSI_MAX_FRAGS_INIT	192
81 #define BE_NUM_MSIX_ENTRIES	1
82 
83 #define MPU_EP_CONTROL          0
84 #define MPU_EP_SEMAPHORE        0xac
85 #define BE2_SOFT_RESET          0x5c
86 #define BE2_PCI_ONLINE0         0xb0
87 #define BE2_PCI_ONLINE1         0xb4
88 #define BE2_SET_RESET           0x80
89 #define BE2_MPU_IRAM_ONLINE     0x00000080
90 
91 #define BE_SENSE_INFO_SIZE		258
92 #define BE_ISCSI_PDU_HEADER_SIZE	64
93 #define BE_MIN_MEM_SIZE			16384
94 #define MAX_CMD_SZ			65536
95 #define IIOC_SCSI_DATA                  0x05	/* Write Operation */
96 
97 #define INVALID_SESS_HANDLE	0xFFFFFFFF
98 
99 #define BE_ADAPTER_UP		0x00000000
100 #define BE_ADAPTER_LINK_DOWN	0x00000001
101 /**
102  * hardware needs the async PDU buffers to be posted in multiples of 8
103  * So have atleast 8 of them by default
104  */
105 
106 #define HWI_GET_ASYNC_PDU_CTX(phwi)	(phwi->phwi_ctxt->pasync_ctx)
107 
108 /********* Memory BAR register ************/
109 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET	0xfc
110 /**
111  * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
112  * Disable" may still globally block interrupts in addition to individual
113  * interrupt masks; a mechanism for the device driver to block all interrupts
114  * atomically without having to arbitrate for the PCI Interrupt Disable bit
115  * with the OS.
116  */
117 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK	(1 << 29)	/* bit 29 */
118 
119 /********* ISR0 Register offset **********/
120 #define CEV_ISR0_OFFSET				0xC18
121 #define CEV_ISR_SIZE				4
122 
123 /**
124  * Macros for reading/writing a protection domain or CSR registers
125  * in BladeEngine.
126  */
127 
128 #define DB_TXULP0_OFFSET 0x40
129 #define DB_RXULP0_OFFSET 0xA0
130 /********* Event Q door bell *************/
131 #define DB_EQ_OFFSET			DB_CQ_OFFSET
132 #define DB_EQ_RING_ID_MASK		0x1FF	/* bits 0 - 8 */
133 /* Clear the interrupt for this eq */
134 #define DB_EQ_CLR_SHIFT			(9)	/* bit 9 */
135 /* Must be 1 */
136 #define DB_EQ_EVNT_SHIFT		(10)	/* bit 10 */
137 /* Number of event entries processed */
138 #define DB_EQ_NUM_POPPED_SHIFT		(16)	/* bits 16 - 28 */
139 /* Rearm bit */
140 #define DB_EQ_REARM_SHIFT		(29)	/* bit 29 */
141 
142 /********* Compl Q door bell *************/
143 #define DB_CQ_OFFSET			0x120
144 #define DB_CQ_RING_ID_MASK		0x3FF	/* bits 0 - 9 */
145 /* Number of event entries processed */
146 #define DB_CQ_NUM_POPPED_SHIFT		(16)	/* bits 16 - 28 */
147 /* Rearm bit */
148 #define DB_CQ_REARM_SHIFT		(29)	/* bit 29 */
149 
150 #define GET_HWI_CONTROLLER_WS(pc)	(pc->phwi_ctrlr)
151 #define HWI_GET_DEF_BUFQ_ID(pc) (((struct hwi_controller *)\
152 		(GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data.id)
153 #define HWI_GET_DEF_HDRQ_ID(pc) (((struct hwi_controller *)\
154 		(GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr.id)
155 
156 #define PAGES_REQUIRED(x) \
157 	((x < PAGE_SIZE) ? 1 :  ((x + PAGE_SIZE - 1) / PAGE_SIZE))
158 
159 #define BEISCSI_MSI_NAME 20 /* size of msi_name string */
160 
161 enum be_mem_enum {
162 	HWI_MEM_ADDN_CONTEXT,
163 	HWI_MEM_WRB,
164 	HWI_MEM_WRBH,
165 	HWI_MEM_SGLH,
166 	HWI_MEM_SGE,
167 	HWI_MEM_ASYNC_HEADER_BUF,	/* 5 */
168 	HWI_MEM_ASYNC_DATA_BUF,
169 	HWI_MEM_ASYNC_HEADER_RING,
170 	HWI_MEM_ASYNC_DATA_RING,
171 	HWI_MEM_ASYNC_HEADER_HANDLE,
172 	HWI_MEM_ASYNC_DATA_HANDLE,	/* 10 */
173 	HWI_MEM_ASYNC_PDU_CONTEXT,
174 	ISCSI_MEM_GLOBAL_HEADER,
175 	SE_MEM_MAX
176 };
177 
178 struct be_bus_address32 {
179 	unsigned int address_lo;
180 	unsigned int address_hi;
181 };
182 
183 struct be_bus_address64 {
184 	unsigned long long address;
185 };
186 
187 struct be_bus_address {
188 	union {
189 		struct be_bus_address32 a32;
190 		struct be_bus_address64 a64;
191 	} u;
192 };
193 
194 struct mem_array {
195 	struct be_bus_address bus_address;	/* Bus address of location */
196 	void *virtual_address;		/* virtual address to the location */
197 	unsigned int size;		/* Size required by memory block */
198 };
199 
200 struct be_mem_descriptor {
201 	unsigned int index;	/* Index of this memory parameter */
202 	unsigned int category;	/* type indicates cached/non-cached */
203 	unsigned int num_elements;	/* number of elements in this
204 					 * descriptor
205 					 */
206 	unsigned int alignment_mask;	/* Alignment mask for this block */
207 	unsigned int size_in_bytes;	/* Size required by memory block */
208 	struct mem_array *mem_array;
209 };
210 
211 struct sgl_handle {
212 	unsigned int sgl_index;
213 	unsigned int type;
214 	unsigned int cid;
215 	struct iscsi_task *task;
216 	struct iscsi_sge *pfrag;
217 };
218 
219 struct hba_parameters {
220 	unsigned int ios_per_ctrl;
221 	unsigned int cxns_per_ctrl;
222 	unsigned int asyncpdus_per_ctrl;
223 	unsigned int icds_per_ctrl;
224 	unsigned int num_sge_per_io;
225 	unsigned int defpdu_hdr_sz;
226 	unsigned int defpdu_data_sz;
227 	unsigned int num_cq_entries;
228 	unsigned int num_eq_entries;
229 	unsigned int wrbs_per_cxn;
230 	unsigned int crashmode;
231 	unsigned int hba_num;
232 
233 	unsigned int mgmt_ws_sz;
234 	unsigned int hwi_ws_sz;
235 
236 	unsigned int eto;
237 	unsigned int ldto;
238 
239 	unsigned int dbg_flags;
240 	unsigned int num_cxn;
241 
242 	unsigned int eq_timer;
243 	/**
244 	 * These are calculated from other params. They're here
245 	 * for debug purposes
246 	 */
247 	unsigned int num_mcc_pages;
248 	unsigned int num_mcc_cq_pages;
249 	unsigned int num_cq_pages;
250 	unsigned int num_eq_pages;
251 
252 	unsigned int num_async_pdu_buf_pages;
253 	unsigned int num_async_pdu_buf_sgl_pages;
254 	unsigned int num_async_pdu_buf_cq_pages;
255 
256 	unsigned int num_async_pdu_hdr_pages;
257 	unsigned int num_async_pdu_hdr_sgl_pages;
258 	unsigned int num_async_pdu_hdr_cq_pages;
259 
260 	unsigned int num_sge;
261 };
262 
263 struct invalidate_command_table {
264 	unsigned short icd;
265 	unsigned short cid;
266 } __packed;
267 
268 #define chip_skh_r(pdev)	(pdev->device == OC_SKH_ID1)
269 struct beiscsi_hba {
270 	struct hba_parameters params;
271 	struct hwi_controller *phwi_ctrlr;
272 	unsigned int mem_req[SE_MEM_MAX];
273 	/* PCI BAR mapped addresses */
274 	u8 __iomem *csr_va;	/* CSR */
275 	u8 __iomem *db_va;	/* Door  Bell  */
276 	u8 __iomem *pci_va;	/* PCI Config */
277 	struct be_bus_address csr_pa;	/* CSR */
278 	struct be_bus_address db_pa;	/* CSR */
279 	struct be_bus_address pci_pa;	/* CSR */
280 	/* PCI representation of our HBA */
281 	struct pci_dev *pcidev;
282 	unsigned short asic_revision;
283 	unsigned int num_cpus;
284 	unsigned int nxt_cqid;
285 	struct msix_entry msix_entries[MAX_CPUS];
286 	char *msi_name[MAX_CPUS];
287 	bool msix_enabled;
288 	struct be_mem_descriptor *init_mem;
289 
290 	unsigned short io_sgl_alloc_index;
291 	unsigned short io_sgl_free_index;
292 	unsigned short io_sgl_hndl_avbl;
293 	struct sgl_handle **io_sgl_hndl_base;
294 	struct sgl_handle **sgl_hndl_array;
295 
296 	unsigned short eh_sgl_alloc_index;
297 	unsigned short eh_sgl_free_index;
298 	unsigned short eh_sgl_hndl_avbl;
299 	struct sgl_handle **eh_sgl_hndl_base;
300 	spinlock_t io_sgl_lock;
301 	spinlock_t mgmt_sgl_lock;
302 	spinlock_t isr_lock;
303 	unsigned int age;
304 	unsigned short avlbl_cids;
305 	unsigned short cid_alloc;
306 	unsigned short cid_free;
307 	struct beiscsi_conn *conn_table[BE2_MAX_SESSIONS * 2];
308 	struct list_head hba_queue;
309 	unsigned short *cid_array;
310 	struct iscsi_endpoint **ep_array;
311 	struct iscsi_boot_kset *boot_kset;
312 	struct Scsi_Host *shost;
313 	struct iscsi_iface *ipv4_iface;
314 	struct iscsi_iface *ipv6_iface;
315 	struct {
316 		/**
317 		 * group together since they are used most frequently
318 		 * for cid to cri conversion
319 		 */
320 		unsigned int iscsi_cid_start;
321 		unsigned int phys_port;
322 
323 		unsigned int isr_offset;
324 		unsigned int iscsi_icd_start;
325 		unsigned int iscsi_cid_count;
326 		unsigned int iscsi_icd_count;
327 		unsigned int pci_function;
328 
329 		unsigned short cid_alloc;
330 		unsigned short cid_free;
331 		unsigned short avlbl_cids;
332 		unsigned short iscsi_features;
333 		spinlock_t cid_lock;
334 	} fw_config;
335 
336 	unsigned int state;
337 	bool fw_timeout;
338 	bool ue_detected;
339 	struct delayed_work beiscsi_hw_check_task;
340 
341 	u8 mac_address[ETH_ALEN];
342 	char wq_name[20];
343 	struct workqueue_struct *wq;	/* The actuak work queue */
344 	struct be_ctrl_info ctrl;
345 	unsigned int generation;
346 	unsigned int interface_handle;
347 	struct mgmt_session_info boot_sess;
348 	struct invalidate_command_table inv_tbl[128];
349 
350 	unsigned int attr_log_enable;
351 	int (*iotask_fn)(struct iscsi_task *,
352 			struct scatterlist *sg,
353 			uint32_t num_sg, uint32_t xferlen,
354 			uint32_t writedir);
355 };
356 
357 struct beiscsi_session {
358 	struct pci_pool *bhs_pool;
359 };
360 
361 /**
362  * struct beiscsi_conn - iscsi connection structure
363  */
364 struct beiscsi_conn {
365 	struct iscsi_conn *conn;
366 	struct beiscsi_hba *phba;
367 	u32 exp_statsn;
368 	u32 beiscsi_conn_cid;
369 	struct beiscsi_endpoint *ep;
370 	unsigned short login_in_progress;
371 	struct wrb_handle *plogin_wrb_handle;
372 	struct sgl_handle *plogin_sgl_handle;
373 	struct beiscsi_session *beiscsi_sess;
374 	struct iscsi_task *task;
375 };
376 
377 /* This structure is used by the chip */
378 struct pdu_data_out {
379 	u32 dw[12];
380 };
381 /**
382  * Pseudo amap definition in which each bit of the actual structure is defined
383  * as a byte: used to calculate offset/shift/mask of each field
384  */
385 struct amap_pdu_data_out {
386 	u8 opcode[6];		/* opcode */
387 	u8 rsvd0[2];		/* should be 0 */
388 	u8 rsvd1[7];
389 	u8 final_bit;		/* F bit */
390 	u8 rsvd2[16];
391 	u8 ahs_length[8];	/* no AHS */
392 	u8 data_len_hi[8];
393 	u8 data_len_lo[16];	/* DataSegmentLength */
394 	u8 lun[64];
395 	u8 itt[32];		/* ITT; initiator task tag */
396 	u8 ttt[32];		/* TTT; valid for R2T or 0xffffffff */
397 	u8 rsvd3[32];
398 	u8 exp_stat_sn[32];
399 	u8 rsvd4[32];
400 	u8 data_sn[32];
401 	u8 buffer_offset[32];
402 	u8 rsvd5[32];
403 };
404 
405 struct be_cmd_bhs {
406 	struct iscsi_scsi_req iscsi_hdr;
407 	unsigned char pad1[16];
408 	struct pdu_data_out iscsi_data_pdu;
409 	unsigned char pad2[BE_SENSE_INFO_SIZE -
410 			sizeof(struct pdu_data_out)];
411 };
412 
413 struct beiscsi_io_task {
414 	struct wrb_handle *pwrb_handle;
415 	struct sgl_handle *psgl_handle;
416 	struct beiscsi_conn *conn;
417 	struct scsi_cmnd *scsi_cmnd;
418 	unsigned int cmd_sn;
419 	unsigned int flags;
420 	unsigned short cid;
421 	unsigned short header_len;
422 	itt_t libiscsi_itt;
423 	struct be_cmd_bhs *cmd_bhs;
424 	struct be_bus_address bhs_pa;
425 	unsigned short bhs_len;
426 	dma_addr_t mtask_addr;
427 	uint32_t mtask_data_count;
428 	uint8_t wrb_type;
429 };
430 
431 struct be_nonio_bhs {
432 	struct iscsi_hdr iscsi_hdr;
433 	unsigned char pad1[16];
434 	struct pdu_data_out iscsi_data_pdu;
435 	unsigned char pad2[BE_SENSE_INFO_SIZE -
436 			sizeof(struct pdu_data_out)];
437 };
438 
439 struct be_status_bhs {
440 	struct iscsi_scsi_req iscsi_hdr;
441 	unsigned char pad1[16];
442 	/**
443 	 * The plus 2 below is to hold the sense info length that gets
444 	 * DMA'ed by RxULP
445 	 */
446 	unsigned char sense_info[BE_SENSE_INFO_SIZE];
447 };
448 
449 struct iscsi_sge {
450 	u32 dw[4];
451 };
452 
453 /**
454  * Pseudo amap definition in which each bit of the actual structure is defined
455  * as a byte: used to calculate offset/shift/mask of each field
456  */
457 struct amap_iscsi_sge {
458 	u8 addr_hi[32];
459 	u8 addr_lo[32];
460 	u8 sge_offset[22];	/* DWORD 2 */
461 	u8 rsvd0[9];		/* DWORD 2 */
462 	u8 last_sge;		/* DWORD 2 */
463 	u8 len[17];		/* DWORD 3 */
464 	u8 rsvd1[15];		/* DWORD 3 */
465 };
466 
467 struct beiscsi_offload_params {
468 	u32 dw[5];
469 };
470 
471 #define OFFLD_PARAMS_ERL	0x00000003
472 #define OFFLD_PARAMS_DDE	0x00000004
473 #define OFFLD_PARAMS_HDE	0x00000008
474 #define OFFLD_PARAMS_IR2T	0x00000010
475 #define OFFLD_PARAMS_IMD	0x00000020
476 #define OFFLD_PARAMS_DATA_SEQ_INORDER   0x00000040
477 #define OFFLD_PARAMS_PDU_SEQ_INORDER    0x00000080
478 #define OFFLD_PARAMS_MAX_R2T 0x00FFFF00
479 
480 /**
481  * Pseudo amap definition in which each bit of the actual structure is defined
482  * as a byte: used to calculate offset/shift/mask of each field
483  */
484 struct amap_beiscsi_offload_params {
485 	u8 max_burst_length[32];
486 	u8 max_send_data_segment_length[32];
487 	u8 first_burst_length[32];
488 	u8 erl[2];
489 	u8 dde[1];
490 	u8 hde[1];
491 	u8 ir2t[1];
492 	u8 imd[1];
493 	u8 data_seq_inorder[1];
494 	u8 pdu_seq_inorder[1];
495 	u8 max_r2t[16];
496 	u8 pad[8];
497 	u8 exp_statsn[32];
498 };
499 
500 /* void hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
501 		struct beiscsi_hba *phba, struct sol_cqe *psol);*/
502 
503 struct async_pdu_handle {
504 	struct list_head link;
505 	struct be_bus_address pa;
506 	void *pbuffer;
507 	unsigned int consumed;
508 	unsigned char index;
509 	unsigned char is_header;
510 	unsigned short cri;
511 	unsigned long buffer_len;
512 };
513 
514 struct hwi_async_entry {
515 	struct {
516 		unsigned char hdr_received;
517 		unsigned char hdr_len;
518 		unsigned short bytes_received;
519 		unsigned int bytes_needed;
520 		struct list_head list;
521 	} wait_queue;
522 
523 	struct list_head header_busy_list;
524 	struct list_head data_busy_list;
525 };
526 
527 struct hwi_async_pdu_context {
528 	struct {
529 		struct be_bus_address pa_base;
530 		void *va_base;
531 		void *ring_base;
532 		struct async_pdu_handle *handle_base;
533 
534 		unsigned int host_write_ptr;
535 		unsigned int ep_read_ptr;
536 		unsigned int writables;
537 
538 		unsigned int free_entries;
539 		unsigned int busy_entries;
540 
541 		struct list_head free_list;
542 	} async_header;
543 
544 	struct {
545 		struct be_bus_address pa_base;
546 		void *va_base;
547 		void *ring_base;
548 		struct async_pdu_handle *handle_base;
549 
550 		unsigned int host_write_ptr;
551 		unsigned int ep_read_ptr;
552 		unsigned int writables;
553 
554 		unsigned int free_entries;
555 		unsigned int busy_entries;
556 		struct list_head free_list;
557 	} async_data;
558 
559 	unsigned int buffer_size;
560 	unsigned int num_entries;
561 
562 	/**
563 	 * This is a varying size list! Do not add anything
564 	 * after this entry!!
565 	 */
566 	struct hwi_async_entry async_entry[BE2_MAX_SESSIONS * 2];
567 };
568 
569 #define PDUCQE_CODE_MASK	0x0000003F
570 #define PDUCQE_DPL_MASK		0xFFFF0000
571 #define PDUCQE_INDEX_MASK	0x0000FFFF
572 
573 struct i_t_dpdu_cqe {
574 	u32 dw[4];
575 } __packed;
576 
577 /**
578  * Pseudo amap definition in which each bit of the actual structure is defined
579  * as a byte: used to calculate offset/shift/mask of each field
580  */
581 struct amap_i_t_dpdu_cqe {
582 	u8 db_addr_hi[32];
583 	u8 db_addr_lo[32];
584 	u8 code[6];
585 	u8 cid[10];
586 	u8 dpl[16];
587 	u8 index[16];
588 	u8 num_cons[10];
589 	u8 rsvd0[4];
590 	u8 final;
591 	u8 valid;
592 } __packed;
593 
594 struct amap_i_t_dpdu_cqe_v2 {
595 	u8 db_addr_hi[32];  /* DWORD 0 */
596 	u8 db_addr_lo[32];  /* DWORD 1 */
597 	u8 code[6]; /* DWORD 2 */
598 	u8 num_cons; /* DWORD 2*/
599 	u8 rsvd0[8]; /* DWORD 2 */
600 	u8 dpl[17]; /* DWORD 2 */
601 	u8 index[16]; /* DWORD 3 */
602 	u8 cid[13]; /* DWORD 3 */
603 	u8 rsvd1; /* DWORD 3 */
604 	u8 final; /* DWORD 3 */
605 	u8 valid; /* DWORD 3 */
606 } __packed;
607 
608 #define CQE_VALID_MASK	0x80000000
609 #define CQE_CODE_MASK	0x0000003F
610 #define CQE_CID_MASK	0x0000FFC0
611 
612 #define EQE_VALID_MASK		0x00000001
613 #define EQE_MAJORCODE_MASK	0x0000000E
614 #define EQE_RESID_MASK		0xFFFF0000
615 
616 struct be_eq_entry {
617 	u32 dw[1];
618 } __packed;
619 
620 /**
621  * Pseudo amap definition in which each bit of the actual structure is defined
622  * as a byte: used to calculate offset/shift/mask of each field
623  */
624 struct amap_eq_entry {
625 	u8 valid;		/* DWORD 0 */
626 	u8 major_code[3];	/* DWORD 0 */
627 	u8 minor_code[12];	/* DWORD 0 */
628 	u8 resource_id[16];	/* DWORD 0 */
629 
630 } __packed;
631 
632 struct cq_db {
633 	u32 dw[1];
634 } __packed;
635 
636 /**
637  * Pseudo amap definition in which each bit of the actual structure is defined
638  * as a byte: used to calculate offset/shift/mask of each field
639  */
640 struct amap_cq_db {
641 	u8 qid[10];
642 	u8 event[1];
643 	u8 rsvd0[5];
644 	u8 num_popped[13];
645 	u8 rearm[1];
646 	u8 rsvd1[2];
647 } __packed;
648 
649 void beiscsi_process_eq(struct beiscsi_hba *phba);
650 
651 struct iscsi_wrb {
652 	u32 dw[16];
653 } __packed;
654 
655 #define WRB_TYPE_MASK 0xF0000000
656 #define SKH_WRB_TYPE_OFFSET 27
657 #define BE_WRB_TYPE_OFFSET  28
658 
659 #define ADAPTER_SET_WRB_TYPE(pwrb, wrb_type, type_offset) \
660 		(pwrb->dw[0] |= (wrb_type << type_offset))
661 
662 /**
663  * Pseudo amap definition in which each bit of the actual structure is defined
664  * as a byte: used to calculate offset/shift/mask of each field
665  */
666 struct amap_iscsi_wrb {
667 	u8 lun[14];		/* DWORD 0 */
668 	u8 lt;			/* DWORD 0 */
669 	u8 invld;		/* DWORD 0 */
670 	u8 wrb_idx[8];		/* DWORD 0 */
671 	u8 dsp;			/* DWORD 0 */
672 	u8 dmsg;		/* DWORD 0 */
673 	u8 undr_run;		/* DWORD 0 */
674 	u8 over_run;		/* DWORD 0 */
675 	u8 type[4];		/* DWORD 0 */
676 	u8 ptr2nextwrb[8];	/* DWORD 1 */
677 	u8 r2t_exp_dtl[24];	/* DWORD 1 */
678 	u8 sgl_icd_idx[12];	/* DWORD 2 */
679 	u8 rsvd0[20];		/* DWORD 2 */
680 	u8 exp_data_sn[32];	/* DWORD 3 */
681 	u8 iscsi_bhs_addr_hi[32];	/* DWORD 4 */
682 	u8 iscsi_bhs_addr_lo[32];	/* DWORD 5 */
683 	u8 cmdsn_itt[32];	/* DWORD 6 */
684 	u8 dif_ref_tag[32];	/* DWORD 7 */
685 	u8 sge0_addr_hi[32];	/* DWORD 8 */
686 	u8 sge0_addr_lo[32];	/* DWORD 9  */
687 	u8 sge0_offset[22];	/* DWORD 10 */
688 	u8 pbs;			/* DWORD 10 */
689 	u8 dif_mode[2];		/* DWORD 10 */
690 	u8 rsvd1[6];		/* DWORD 10 */
691 	u8 sge0_last;		/* DWORD 10 */
692 	u8 sge0_len[17];	/* DWORD 11 */
693 	u8 dif_meta_tag[14];	/* DWORD 11 */
694 	u8 sge0_in_ddr;		/* DWORD 11 */
695 	u8 sge1_addr_hi[32];	/* DWORD 12 */
696 	u8 sge1_addr_lo[32];	/* DWORD 13 */
697 	u8 sge1_r2t_offset[22];	/* DWORD 14 */
698 	u8 rsvd2[9];		/* DWORD 14 */
699 	u8 sge1_last;		/* DWORD 14 */
700 	u8 sge1_len[17];	/* DWORD 15 */
701 	u8 ref_sgl_icd_idx[12];	/* DWORD 15 */
702 	u8 rsvd3[2];		/* DWORD 15 */
703 	u8 sge1_in_ddr;		/* DWORD 15 */
704 
705 } __packed;
706 
707 struct amap_iscsi_wrb_v2 {
708 	u8 r2t_exp_dtl[25]; /* DWORD 0 */
709 	u8 rsvd0[2];    /* DWORD 0*/
710 	u8 type[5];     /* DWORD 0 */
711 	u8 ptr2nextwrb[8];  /* DWORD 1 */
712 	u8 wrb_idx[8];      /* DWORD 1 */
713 	u8 lun[16];     /* DWORD 1 */
714 	u8 sgl_idx[16]; /* DWORD 2 */
715 	u8 ref_sgl_icd_idx[16]; /* DWORD 2 */
716 	u8 exp_data_sn[32]; /* DWORD 3 */
717 	u8 iscsi_bhs_addr_hi[32];   /* DWORD 4 */
718 	u8 iscsi_bhs_addr_lo[32];   /* DWORD 5 */
719 	u8 cq_id[16];   /* DWORD 6 */
720 	u8 rsvd1[16];   /* DWORD 6 */
721 	u8 cmdsn_itt[32];   /* DWORD 7 */
722 	u8 sge0_addr_hi[32];    /* DWORD 8 */
723 	u8 sge0_addr_lo[32];    /* DWORD 9 */
724 	u8 sge0_offset[24]; /* DWORD 10 */
725 	u8 rsvd2[7];    /* DWORD 10 */
726 	u8 sge0_last;   /* DWORD 10 */
727 	u8 sge0_len[17];    /* DWORD 11 */
728 	u8 rsvd3[7];    /* DWORD 11 */
729 	u8 diff_enbl;   /* DWORD 11 */
730 	u8 u_run;       /* DWORD 11 */
731 	u8 o_run;       /* DWORD 11 */
732 	u8 invalid;     /* DWORD 11 */
733 	u8 dsp;         /* DWORD 11 */
734 	u8 dmsg;        /* DWORD 11 */
735 	u8 rsvd4;       /* DWORD 11 */
736 	u8 lt;          /* DWORD 11 */
737 	u8 sge1_addr_hi[32];    /* DWORD 12 */
738 	u8 sge1_addr_lo[32];    /* DWORD 13 */
739 	u8 sge1_r2t_offset[24]; /* DWORD 14 */
740 	u8 rsvd5[7];    /* DWORD 14 */
741 	u8 sge1_last;   /* DWORD 14 */
742 	u8 sge1_len[17];    /* DWORD 15 */
743 	u8 rsvd6[15];   /* DWORD 15 */
744 } __packed;
745 
746 
747 struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid);
748 void
749 free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle);
750 
751 void beiscsi_process_all_cqs(struct work_struct *work);
752 
753 static inline bool beiscsi_error(struct beiscsi_hba *phba)
754 {
755 	return phba->ue_detected || phba->fw_timeout;
756 }
757 
758 struct pdu_nop_out {
759 	u32 dw[12];
760 };
761 
762 /**
763  * Pseudo amap definition in which each bit of the actual structure is defined
764  * as a byte: used to calculate offset/shift/mask of each field
765  */
766 struct amap_pdu_nop_out {
767 	u8 opcode[6];		/* opcode 0x00 */
768 	u8 i_bit;		/* I Bit */
769 	u8 x_bit;		/* reserved; should be 0 */
770 	u8 fp_bit_filler1[7];
771 	u8 f_bit;		/* always 1 */
772 	u8 reserved1[16];
773 	u8 ahs_length[8];	/* no AHS */
774 	u8 data_len_hi[8];
775 	u8 data_len_lo[16];	/* DataSegmentLength */
776 	u8 lun[64];
777 	u8 itt[32];		/* initiator id for ping or 0xffffffff */
778 	u8 ttt[32];		/* target id for ping or 0xffffffff */
779 	u8 cmd_sn[32];
780 	u8 exp_stat_sn[32];
781 	u8 reserved5[128];
782 };
783 
784 #define PDUBASE_OPCODE_MASK	0x0000003F
785 #define PDUBASE_DATALENHI_MASK	0x0000FF00
786 #define PDUBASE_DATALENLO_MASK	0xFFFF0000
787 
788 struct pdu_base {
789 	u32 dw[16];
790 } __packed;
791 
792 /**
793  * Pseudo amap definition in which each bit of the actual structure is defined
794  * as a byte: used to calculate offset/shift/mask of each field
795  */
796 struct amap_pdu_base {
797 	u8 opcode[6];
798 	u8 i_bit;		/* immediate bit */
799 	u8 x_bit;		/* reserved, always 0 */
800 	u8 reserved1[24];	/* opcode-specific fields */
801 	u8 ahs_length[8];	/* length units is 4 byte words */
802 	u8 data_len_hi[8];
803 	u8 data_len_lo[16];	/* DatasegmentLength */
804 	u8 lun[64];		/* lun or opcode-specific fields */
805 	u8 itt[32];		/* initiator task tag */
806 	u8 reserved4[224];
807 };
808 
809 struct iscsi_target_context_update_wrb {
810 	u32 dw[16];
811 } __packed;
812 
813 /**
814  * Pseudo amap definition in which each bit of the actual structure is defined
815  * as a byte: used to calculate offset/shift/mask of each field
816  */
817 #define BE_TGT_CTX_UPDT_CMD 0x07
818 struct amap_iscsi_target_context_update_wrb {
819 	u8 lun[14];		/* DWORD 0 */
820 	u8 lt;			/* DWORD 0 */
821 	u8 invld;		/* DWORD 0 */
822 	u8 wrb_idx[8];		/* DWORD 0 */
823 	u8 dsp;			/* DWORD 0 */
824 	u8 dmsg;		/* DWORD 0 */
825 	u8 undr_run;		/* DWORD 0 */
826 	u8 over_run;		/* DWORD 0 */
827 	u8 type[4];		/* DWORD 0 */
828 	u8 ptr2nextwrb[8];	/* DWORD 1 */
829 	u8 max_burst_length[19];	/* DWORD 1 */
830 	u8 rsvd0[5];		/* DWORD 1 */
831 	u8 rsvd1[15];		/* DWORD 2 */
832 	u8 max_send_data_segment_length[17];	/* DWORD 2 */
833 	u8 first_burst_length[14];	/* DWORD 3 */
834 	u8 rsvd2[2];		/* DWORD 3 */
835 	u8 tx_wrbindex_drv_msg[8];	/* DWORD 3 */
836 	u8 rsvd3[5];		/* DWORD 3 */
837 	u8 session_state[3];	/* DWORD 3 */
838 	u8 rsvd4[16];		/* DWORD 4 */
839 	u8 tx_jumbo;		/* DWORD 4 */
840 	u8 hde;			/* DWORD 4 */
841 	u8 dde;			/* DWORD 4 */
842 	u8 erl[2];		/* DWORD 4 */
843 	u8 domain_id[5];		/* DWORD 4 */
844 	u8 mode;		/* DWORD 4 */
845 	u8 imd;			/* DWORD 4 */
846 	u8 ir2t;		/* DWORD 4 */
847 	u8 notpredblq[2];	/* DWORD 4 */
848 	u8 compltonack;		/* DWORD 4 */
849 	u8 stat_sn[32];		/* DWORD 5 */
850 	u8 pad_buffer_addr_hi[32];	/* DWORD 6 */
851 	u8 pad_buffer_addr_lo[32];	/* DWORD 7 */
852 	u8 pad_addr_hi[32];	/* DWORD 8 */
853 	u8 pad_addr_lo[32];	/* DWORD 9 */
854 	u8 rsvd5[32];		/* DWORD 10 */
855 	u8 rsvd6[32];		/* DWORD 11 */
856 	u8 rsvd7[32];		/* DWORD 12 */
857 	u8 rsvd8[32];		/* DWORD 13 */
858 	u8 rsvd9[32];		/* DWORD 14 */
859 	u8 rsvd10[32];		/* DWORD 15 */
860 
861 } __packed;
862 
863 #define BEISCSI_MAX_RECV_DATASEG_LEN    (64 * 1024)
864 #define BEISCSI_MAX_CXNS    1
865 struct amap_iscsi_target_context_update_wrb_v2 {
866 	u8 max_burst_length[24];    /* DWORD 0 */
867 	u8 rsvd0[3];    /* DWORD 0 */
868 	u8 type[5];     /* DWORD 0 */
869 	u8 ptr2nextwrb[8];  /* DWORD 1 */
870 	u8 wrb_idx[8];      /* DWORD 1 */
871 	u8 rsvd1[16];       /* DWORD 1 */
872 	u8 max_send_data_segment_length[24];    /* DWORD 2 */
873 	u8 rsvd2[8];    /* DWORD 2 */
874 	u8 first_burst_length[24]; /* DWORD 3 */
875 	u8 rsvd3[8]; /* DOWRD 3 */
876 	u8 max_r2t[16]; /* DWORD 4 */
877 	u8 rsvd4[10];   /* DWORD 4 */
878 	u8 hde;         /* DWORD 4 */
879 	u8 dde;         /* DWORD 4 */
880 	u8 erl[2];      /* DWORD 4 */
881 	u8 imd;         /* DWORD 4 */
882 	u8 ir2t;        /* DWORD 4 */
883 	u8 stat_sn[32];     /* DWORD 5 */
884 	u8 rsvd5[32];   /* DWORD 6 */
885 	u8 rsvd6[32];   /* DWORD 7 */
886 	u8 max_recv_dataseg_len[24];    /* DWORD 8 */
887 	u8 rsvd7[8]; /* DWORD 8 */
888 	u8 rsvd8[32];   /* DWORD 9 */
889 	u8 rsvd9[32];   /* DWORD 10 */
890 	u8 max_cxns[16]; /* DWORD 11 */
891 	u8 rsvd10[11]; /* DWORD  11*/
892 	u8 invld; /* DWORD 11 */
893 	u8 rsvd11;/* DWORD 11*/
894 	u8 dmsg; /* DWORD 11 */
895 	u8 data_seq_inorder; /* DWORD 11 */
896 	u8 pdu_seq_inorder; /* DWORD 11 */
897 	u8 rsvd12[32]; /*DWORD 12 */
898 	u8 rsvd13[32]; /* DWORD 13 */
899 	u8 rsvd14[32]; /* DWORD 14 */
900 	u8 rsvd15[32]; /* DWORD 15 */
901 } __packed;
902 
903 
904 struct be_ring {
905 	u32 pages;		/* queue size in pages */
906 	u32 id;			/* queue id assigned by beklib */
907 	u32 num;		/* number of elements in queue */
908 	u32 cidx;		/* consumer index */
909 	u32 pidx;		/* producer index -- not used by most rings */
910 	u32 item_size;		/* size in bytes of one object */
911 
912 	void *va;		/* The virtual address of the ring.  This
913 				 * should be last to allow 32 & 64 bit debugger
914 				 * extensions to work.
915 				 */
916 };
917 
918 struct hwi_wrb_context {
919 	struct list_head wrb_handle_list;
920 	struct list_head wrb_handle_drvr_list;
921 	struct wrb_handle **pwrb_handle_base;
922 	struct wrb_handle **pwrb_handle_basestd;
923 	struct iscsi_wrb *plast_wrb;
924 	unsigned short alloc_index;
925 	unsigned short free_index;
926 	unsigned short wrb_handles_available;
927 	unsigned short cid;
928 };
929 
930 struct hwi_controller {
931 	struct list_head io_sgl_list;
932 	struct list_head eh_sgl_list;
933 	struct sgl_handle *psgl_handle_base;
934 	unsigned int wrb_mem_index;
935 
936 	struct hwi_wrb_context wrb_context[BE2_MAX_SESSIONS * 2];
937 	struct mcc_wrb *pmcc_wrb_base;
938 	struct be_ring default_pdu_hdr;
939 	struct be_ring default_pdu_data;
940 	struct hwi_context_memory *phwi_ctxt;
941 };
942 
943 enum hwh_type_enum {
944 	HWH_TYPE_IO = 1,
945 	HWH_TYPE_LOGOUT = 2,
946 	HWH_TYPE_TMF = 3,
947 	HWH_TYPE_NOP = 4,
948 	HWH_TYPE_IO_RD = 5,
949 	HWH_TYPE_LOGIN = 11,
950 	HWH_TYPE_INVALID = 0xFFFFFFFF
951 };
952 
953 struct wrb_handle {
954 	enum hwh_type_enum type;
955 	unsigned short wrb_index;
956 	unsigned short nxt_wrb_index;
957 
958 	struct iscsi_task *pio_handle;
959 	struct iscsi_wrb *pwrb;
960 };
961 
962 struct hwi_context_memory {
963 	/* Adaptive interrupt coalescing (AIC) info */
964 	u16 min_eqd;		/* in usecs */
965 	u16 max_eqd;		/* in usecs */
966 	u16 cur_eqd;		/* in usecs */
967 	struct be_eq_obj be_eq[MAX_CPUS];
968 	struct be_queue_info be_cq[MAX_CPUS - 1];
969 
970 	struct be_queue_info be_def_hdrq;
971 	struct be_queue_info be_def_dataq;
972 
973 	struct be_queue_info be_wrbq[BE2_MAX_SESSIONS];
974 	struct be_mcc_wrb_context *pbe_mcc_context;
975 
976 	struct hwi_async_pdu_context *pasync_ctx;
977 };
978 
979 /* Logging related definitions */
980 #define BEISCSI_LOG_INIT	0x0001	/* Initialization events */
981 #define BEISCSI_LOG_MBOX	0x0002	/* Mailbox Events */
982 #define BEISCSI_LOG_MISC	0x0004	/* Miscllaneous Events */
983 #define BEISCSI_LOG_EH		0x0008	/* Error Handler */
984 #define BEISCSI_LOG_IO		0x0010	/* IO Code Path */
985 #define BEISCSI_LOG_CONFIG	0x0020	/* CONFIG Code Path */
986 
987 #define beiscsi_log(phba, level, mask, fmt, arg...) \
988 do { \
989 	uint32_t log_value = phba->attr_log_enable; \
990 		if (((mask) & log_value) || (level[1] <= '3')) \
991 			shost_printk(level, phba->shost, \
992 				     fmt, __LINE__, ##arg); \
993 } while (0)
994 
995 #endif
996