1 /** 2 * Copyright (C) 2005 - 2009 ServerEngines 3 * All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License version 2 7 * as published by the Free Software Foundation. The full GNU General 8 * Public License is included in this distribution in the file called COPYING. 9 * 10 * Written by: Jayamohan Kallickal (jayamohank@serverengines.com) 11 * 12 * Contact Information: 13 * linux-drivers@serverengines.com 14 * 15 * ServerEngines 16 * 209 N. Fair Oaks Ave 17 * Sunnyvale, CA 94085 18 * 19 */ 20 21 #ifndef _BEISCSI_MAIN_ 22 #define _BEISCSI_MAIN_ 23 24 #include <linux/kernel.h> 25 #include <linux/pci.h> 26 #include <linux/in.h> 27 #include <scsi/scsi.h> 28 #include <scsi/scsi_cmnd.h> 29 #include <scsi/scsi_device.h> 30 #include <scsi/scsi_host.h> 31 #include <scsi/iscsi_proto.h> 32 #include <scsi/libiscsi.h> 33 #include <scsi/scsi_transport_iscsi.h> 34 35 #include "be.h" 36 #define DRV_NAME "be2iscsi" 37 #define BUILD_STR "2.0.527.0" 38 #define BE_NAME "ServerEngines BladeEngine2" \ 39 "Linux iSCSI Driver version" BUILD_STR 40 #define DRV_DESC BE_NAME " " "Driver" 41 42 #define BE_VENDOR_ID 0x19A2 43 #define BE_DEVICE_ID1 0x212 44 #define OC_DEVICE_ID1 0x702 45 #define OC_DEVICE_ID2 0x703 46 #define OC_DEVICE_ID3 0x712 47 #define OC_DEVICE_ID4 0x222 48 49 #define BE2_MAX_SESSIONS 64 50 #define BE2_CMDS_PER_CXN 128 51 #define BE2_LOGOUTS BE2_MAX_SESSIONS 52 #define BE2_TMFS 16 53 #define BE2_NOPOUT_REQ 16 54 #define BE2_ASYNCPDUS BE2_MAX_SESSIONS 55 #define BE2_MAX_ICDS 2048 56 #define BE2_SGE 32 57 #define BE2_DEFPDU_HDR_SZ 64 58 #define BE2_DEFPDU_DATA_SZ 8192 59 #define BE2_IO_DEPTH \ 60 (BE2_MAX_ICDS / 2 - (BE2_LOGOUTS + BE2_TMFS + BE2_NOPOUT_REQ)) 61 62 #define MAX_CPUS 31 63 #define BEISCSI_SGLIST_ELEMENTS BE2_SGE 64 65 #define BEISCSI_MAX_CMNDS 1024 /* Max IO's per Ctrlr sht->can_queue */ 66 #define BEISCSI_CMD_PER_LUN 128 /* scsi_host->cmd_per_lun */ 67 #define BEISCSI_MAX_SECTORS 2048 /* scsi_host->max_sectors */ 68 69 #define BEISCSI_MAX_CMD_LEN 16 /* scsi_host->max_cmd_len */ 70 #define BEISCSI_NUM_MAX_LUN 256 /* scsi_host->max_lun */ 71 #define BEISCSI_NUM_DEVICES_SUPPORTED 0x01 72 #define BEISCSI_MAX_FRAGS_INIT 192 73 #define BE_NUM_MSIX_ENTRIES 1 74 #define MPU_EP_SEMAPHORE 0xac 75 76 #define BE_SENSE_INFO_SIZE 258 77 #define BE_ISCSI_PDU_HEADER_SIZE 64 78 #define BE_MIN_MEM_SIZE 16384 79 #define MAX_CMD_SZ 65536 80 #define IIOC_SCSI_DATA 0x05 /* Write Operation */ 81 82 #define DBG_LVL 0x00000001 83 #define DBG_LVL_1 0x00000001 84 #define DBG_LVL_2 0x00000002 85 #define DBG_LVL_3 0x00000004 86 #define DBG_LVL_4 0x00000008 87 #define DBG_LVL_5 0x00000010 88 #define DBG_LVL_6 0x00000020 89 #define DBG_LVL_7 0x00000040 90 #define DBG_LVL_8 0x00000080 91 92 #define SE_DEBUG(debug_mask, fmt, args...) \ 93 do { \ 94 if (debug_mask & DBG_LVL) { \ 95 printk(KERN_ERR "(%s():%d):", __func__, __LINE__);\ 96 printk(fmt, ##args); \ 97 } \ 98 } while (0); 99 100 #define BE_ADAPTER_UP 0x00000000 101 #define BE_ADAPTER_LINK_DOWN 0x00000001 102 /** 103 * hardware needs the async PDU buffers to be posted in multiples of 8 104 * So have atleast 8 of them by default 105 */ 106 107 #define HWI_GET_ASYNC_PDU_CTX(phwi) (phwi->phwi_ctxt->pasync_ctx) 108 109 /********* Memory BAR register ************/ 110 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc 111 /** 112 * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt 113 * Disable" may still globally block interrupts in addition to individual 114 * interrupt masks; a mechanism for the device driver to block all interrupts 115 * atomically without having to arbitrate for the PCI Interrupt Disable bit 116 * with the OS. 117 */ 118 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */ 119 120 /********* ISR0 Register offset **********/ 121 #define CEV_ISR0_OFFSET 0xC18 122 #define CEV_ISR_SIZE 4 123 124 /** 125 * Macros for reading/writing a protection domain or CSR registers 126 * in BladeEngine. 127 */ 128 129 #define DB_TXULP0_OFFSET 0x40 130 #define DB_RXULP0_OFFSET 0xA0 131 /********* Event Q door bell *************/ 132 #define DB_EQ_OFFSET DB_CQ_OFFSET 133 #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */ 134 /* Clear the interrupt for this eq */ 135 #define DB_EQ_CLR_SHIFT (9) /* bit 9 */ 136 /* Must be 1 */ 137 #define DB_EQ_EVNT_SHIFT (10) /* bit 10 */ 138 /* Number of event entries processed */ 139 #define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */ 140 /* Rearm bit */ 141 #define DB_EQ_REARM_SHIFT (29) /* bit 29 */ 142 143 /********* Compl Q door bell *************/ 144 #define DB_CQ_OFFSET 0x120 145 #define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */ 146 /* Number of event entries processed */ 147 #define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */ 148 /* Rearm bit */ 149 #define DB_CQ_REARM_SHIFT (29) /* bit 29 */ 150 151 #define GET_HWI_CONTROLLER_WS(pc) (pc->phwi_ctrlr) 152 #define HWI_GET_DEF_BUFQ_ID(pc) (((struct hwi_controller *)\ 153 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data.id) 154 #define HWI_GET_DEF_HDRQ_ID(pc) (((struct hwi_controller *)\ 155 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr.id) 156 157 #define PAGES_REQUIRED(x) \ 158 ((x < PAGE_SIZE) ? 1 : ((x + PAGE_SIZE - 1) / PAGE_SIZE)) 159 160 enum be_mem_enum { 161 HWI_MEM_ADDN_CONTEXT, 162 HWI_MEM_WRB, 163 HWI_MEM_WRBH, 164 HWI_MEM_SGLH, 165 HWI_MEM_SGE, 166 HWI_MEM_ASYNC_HEADER_BUF, /* 5 */ 167 HWI_MEM_ASYNC_DATA_BUF, 168 HWI_MEM_ASYNC_HEADER_RING, 169 HWI_MEM_ASYNC_DATA_RING, 170 HWI_MEM_ASYNC_HEADER_HANDLE, 171 HWI_MEM_ASYNC_DATA_HANDLE, /* 10 */ 172 HWI_MEM_ASYNC_PDU_CONTEXT, 173 ISCSI_MEM_GLOBAL_HEADER, 174 SE_MEM_MAX 175 }; 176 177 struct be_bus_address32 { 178 unsigned int address_lo; 179 unsigned int address_hi; 180 }; 181 182 struct be_bus_address64 { 183 unsigned long long address; 184 }; 185 186 struct be_bus_address { 187 union { 188 struct be_bus_address32 a32; 189 struct be_bus_address64 a64; 190 } u; 191 }; 192 193 struct mem_array { 194 struct be_bus_address bus_address; /* Bus address of location */ 195 void *virtual_address; /* virtual address to the location */ 196 unsigned int size; /* Size required by memory block */ 197 }; 198 199 struct be_mem_descriptor { 200 unsigned int index; /* Index of this memory parameter */ 201 unsigned int category; /* type indicates cached/non-cached */ 202 unsigned int num_elements; /* number of elements in this 203 * descriptor 204 */ 205 unsigned int alignment_mask; /* Alignment mask for this block */ 206 unsigned int size_in_bytes; /* Size required by memory block */ 207 struct mem_array *mem_array; 208 }; 209 210 struct sgl_handle { 211 unsigned int sgl_index; 212 unsigned int type; 213 unsigned int cid; 214 struct iscsi_task *task; 215 struct iscsi_sge *pfrag; 216 }; 217 218 struct hba_parameters { 219 unsigned int ios_per_ctrl; 220 unsigned int cxns_per_ctrl; 221 unsigned int asyncpdus_per_ctrl; 222 unsigned int icds_per_ctrl; 223 unsigned int num_sge_per_io; 224 unsigned int defpdu_hdr_sz; 225 unsigned int defpdu_data_sz; 226 unsigned int num_cq_entries; 227 unsigned int num_eq_entries; 228 unsigned int wrbs_per_cxn; 229 unsigned int crashmode; 230 unsigned int hba_num; 231 232 unsigned int mgmt_ws_sz; 233 unsigned int hwi_ws_sz; 234 235 unsigned int eto; 236 unsigned int ldto; 237 238 unsigned int dbg_flags; 239 unsigned int num_cxn; 240 241 unsigned int eq_timer; 242 /** 243 * These are calculated from other params. They're here 244 * for debug purposes 245 */ 246 unsigned int num_mcc_pages; 247 unsigned int num_mcc_cq_pages; 248 unsigned int num_cq_pages; 249 unsigned int num_eq_pages; 250 251 unsigned int num_async_pdu_buf_pages; 252 unsigned int num_async_pdu_buf_sgl_pages; 253 unsigned int num_async_pdu_buf_cq_pages; 254 255 unsigned int num_async_pdu_hdr_pages; 256 unsigned int num_async_pdu_hdr_sgl_pages; 257 unsigned int num_async_pdu_hdr_cq_pages; 258 259 unsigned int num_sge; 260 }; 261 262 struct beiscsi_hba { 263 struct hba_parameters params; 264 struct hwi_controller *phwi_ctrlr; 265 unsigned int mem_req[SE_MEM_MAX]; 266 /* PCI BAR mapped addresses */ 267 u8 __iomem *csr_va; /* CSR */ 268 u8 __iomem *db_va; /* Door Bell */ 269 u8 __iomem *pci_va; /* PCI Config */ 270 struct be_bus_address csr_pa; /* CSR */ 271 struct be_bus_address db_pa; /* CSR */ 272 struct be_bus_address pci_pa; /* CSR */ 273 /* PCI representation of our HBA */ 274 struct pci_dev *pcidev; 275 unsigned int state; 276 unsigned short asic_revision; 277 unsigned int num_cpus; 278 unsigned int nxt_cqid; 279 struct msix_entry msix_entries[MAX_CPUS + 1]; 280 bool msix_enabled; 281 struct be_mem_descriptor *init_mem; 282 283 unsigned short io_sgl_alloc_index; 284 unsigned short io_sgl_free_index; 285 unsigned short io_sgl_hndl_avbl; 286 struct sgl_handle **io_sgl_hndl_base; 287 struct sgl_handle **sgl_hndl_array; 288 289 unsigned short eh_sgl_alloc_index; 290 unsigned short eh_sgl_free_index; 291 unsigned short eh_sgl_hndl_avbl; 292 struct sgl_handle **eh_sgl_hndl_base; 293 spinlock_t io_sgl_lock; 294 spinlock_t mgmt_sgl_lock; 295 spinlock_t isr_lock; 296 unsigned int age; 297 unsigned short avlbl_cids; 298 unsigned short cid_alloc; 299 unsigned short cid_free; 300 struct beiscsi_conn *conn_table[BE2_MAX_SESSIONS * 2]; 301 struct list_head hba_queue; 302 unsigned short *cid_array; 303 struct iscsi_endpoint **ep_array; 304 struct Scsi_Host *shost; 305 struct { 306 /** 307 * group together since they are used most frequently 308 * for cid to cri conversion 309 */ 310 unsigned int iscsi_cid_start; 311 unsigned int phys_port; 312 313 unsigned int isr_offset; 314 unsigned int iscsi_icd_start; 315 unsigned int iscsi_cid_count; 316 unsigned int iscsi_icd_count; 317 unsigned int pci_function; 318 319 unsigned short cid_alloc; 320 unsigned short cid_free; 321 unsigned short avlbl_cids; 322 unsigned short iscsi_features; 323 spinlock_t cid_lock; 324 } fw_config; 325 326 u8 mac_address[ETH_ALEN]; 327 unsigned short todo_cq; 328 unsigned short todo_mcc_cq; 329 char wq_name[20]; 330 struct workqueue_struct *wq; /* The actuak work queue */ 331 struct work_struct work_cqs; /* The work being queued */ 332 struct be_ctrl_info ctrl; 333 }; 334 335 struct beiscsi_session { 336 struct pci_pool *bhs_pool; 337 }; 338 339 /** 340 * struct beiscsi_conn - iscsi connection structure 341 */ 342 struct beiscsi_conn { 343 struct iscsi_conn *conn; 344 struct beiscsi_hba *phba; 345 u32 exp_statsn; 346 u32 beiscsi_conn_cid; 347 struct beiscsi_endpoint *ep; 348 unsigned short login_in_progress; 349 struct sgl_handle *plogin_sgl_handle; 350 struct beiscsi_session *beiscsi_sess; 351 struct iscsi_task *task; 352 }; 353 354 /* This structure is used by the chip */ 355 struct pdu_data_out { 356 u32 dw[12]; 357 }; 358 /** 359 * Pseudo amap definition in which each bit of the actual structure is defined 360 * as a byte: used to calculate offset/shift/mask of each field 361 */ 362 struct amap_pdu_data_out { 363 u8 opcode[6]; /* opcode */ 364 u8 rsvd0[2]; /* should be 0 */ 365 u8 rsvd1[7]; 366 u8 final_bit; /* F bit */ 367 u8 rsvd2[16]; 368 u8 ahs_length[8]; /* no AHS */ 369 u8 data_len_hi[8]; 370 u8 data_len_lo[16]; /* DataSegmentLength */ 371 u8 lun[64]; 372 u8 itt[32]; /* ITT; initiator task tag */ 373 u8 ttt[32]; /* TTT; valid for R2T or 0xffffffff */ 374 u8 rsvd3[32]; 375 u8 exp_stat_sn[32]; 376 u8 rsvd4[32]; 377 u8 data_sn[32]; 378 u8 buffer_offset[32]; 379 u8 rsvd5[32]; 380 }; 381 382 struct be_cmd_bhs { 383 struct iscsi_cmd iscsi_hdr; 384 unsigned char pad1[16]; 385 struct pdu_data_out iscsi_data_pdu; 386 unsigned char pad2[BE_SENSE_INFO_SIZE - 387 sizeof(struct pdu_data_out)]; 388 }; 389 390 struct beiscsi_io_task { 391 struct wrb_handle *pwrb_handle; 392 struct sgl_handle *psgl_handle; 393 struct beiscsi_conn *conn; 394 struct scsi_cmnd *scsi_cmnd; 395 unsigned int cmd_sn; 396 unsigned int flags; 397 unsigned short cid; 398 unsigned short header_len; 399 itt_t libiscsi_itt; 400 struct be_cmd_bhs *cmd_bhs; 401 struct be_bus_address bhs_pa; 402 unsigned short bhs_len; 403 }; 404 405 struct be_nonio_bhs { 406 struct iscsi_hdr iscsi_hdr; 407 unsigned char pad1[16]; 408 struct pdu_data_out iscsi_data_pdu; 409 unsigned char pad2[BE_SENSE_INFO_SIZE - 410 sizeof(struct pdu_data_out)]; 411 }; 412 413 struct be_status_bhs { 414 struct iscsi_cmd iscsi_hdr; 415 unsigned char pad1[16]; 416 /** 417 * The plus 2 below is to hold the sense info length that gets 418 * DMA'ed by RxULP 419 */ 420 unsigned char sense_info[BE_SENSE_INFO_SIZE]; 421 }; 422 423 struct iscsi_sge { 424 u32 dw[4]; 425 }; 426 427 /** 428 * Pseudo amap definition in which each bit of the actual structure is defined 429 * as a byte: used to calculate offset/shift/mask of each field 430 */ 431 struct amap_iscsi_sge { 432 u8 addr_hi[32]; 433 u8 addr_lo[32]; 434 u8 sge_offset[22]; /* DWORD 2 */ 435 u8 rsvd0[9]; /* DWORD 2 */ 436 u8 last_sge; /* DWORD 2 */ 437 u8 len[17]; /* DWORD 3 */ 438 u8 rsvd1[15]; /* DWORD 3 */ 439 }; 440 441 struct beiscsi_offload_params { 442 u32 dw[5]; 443 }; 444 445 #define OFFLD_PARAMS_ERL 0x00000003 446 #define OFFLD_PARAMS_DDE 0x00000004 447 #define OFFLD_PARAMS_HDE 0x00000008 448 #define OFFLD_PARAMS_IR2T 0x00000010 449 #define OFFLD_PARAMS_IMD 0x00000020 450 451 /** 452 * Pseudo amap definition in which each bit of the actual structure is defined 453 * as a byte: used to calculate offset/shift/mask of each field 454 */ 455 struct amap_beiscsi_offload_params { 456 u8 max_burst_length[32]; 457 u8 max_send_data_segment_length[32]; 458 u8 first_burst_length[32]; 459 u8 erl[2]; 460 u8 dde[1]; 461 u8 hde[1]; 462 u8 ir2t[1]; 463 u8 imd[1]; 464 u8 pad[26]; 465 u8 exp_statsn[32]; 466 }; 467 468 /* void hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn, 469 struct beiscsi_hba *phba, struct sol_cqe *psol);*/ 470 471 struct async_pdu_handle { 472 struct list_head link; 473 struct be_bus_address pa; 474 void *pbuffer; 475 unsigned int consumed; 476 unsigned char index; 477 unsigned char is_header; 478 unsigned short cri; 479 unsigned long buffer_len; 480 }; 481 482 struct hwi_async_entry { 483 struct { 484 unsigned char hdr_received; 485 unsigned char hdr_len; 486 unsigned short bytes_received; 487 unsigned int bytes_needed; 488 struct list_head list; 489 } wait_queue; 490 491 struct list_head header_busy_list; 492 struct list_head data_busy_list; 493 }; 494 495 #define BE_MIN_ASYNC_ENTRIES 128 496 497 struct hwi_async_pdu_context { 498 struct { 499 struct be_bus_address pa_base; 500 void *va_base; 501 void *ring_base; 502 struct async_pdu_handle *handle_base; 503 504 unsigned int host_write_ptr; 505 unsigned int ep_read_ptr; 506 unsigned int writables; 507 508 unsigned int free_entries; 509 unsigned int busy_entries; 510 unsigned int buffer_size; 511 unsigned int num_entries; 512 513 struct list_head free_list; 514 } async_header; 515 516 struct { 517 struct be_bus_address pa_base; 518 void *va_base; 519 void *ring_base; 520 struct async_pdu_handle *handle_base; 521 522 unsigned int host_write_ptr; 523 unsigned int ep_read_ptr; 524 unsigned int writables; 525 526 unsigned int free_entries; 527 unsigned int busy_entries; 528 unsigned int buffer_size; 529 struct list_head free_list; 530 unsigned int num_entries; 531 } async_data; 532 533 /** 534 * This is a varying size list! Do not add anything 535 * after this entry!! 536 */ 537 struct hwi_async_entry async_entry[BE_MIN_ASYNC_ENTRIES]; 538 }; 539 540 #define PDUCQE_CODE_MASK 0x0000003F 541 #define PDUCQE_DPL_MASK 0xFFFF0000 542 #define PDUCQE_INDEX_MASK 0x0000FFFF 543 544 struct i_t_dpdu_cqe { 545 u32 dw[4]; 546 } __packed; 547 548 /** 549 * Pseudo amap definition in which each bit of the actual structure is defined 550 * as a byte: used to calculate offset/shift/mask of each field 551 */ 552 struct amap_i_t_dpdu_cqe { 553 u8 db_addr_hi[32]; 554 u8 db_addr_lo[32]; 555 u8 code[6]; 556 u8 cid[10]; 557 u8 dpl[16]; 558 u8 index[16]; 559 u8 num_cons[10]; 560 u8 rsvd0[4]; 561 u8 final; 562 u8 valid; 563 } __packed; 564 565 #define CQE_VALID_MASK 0x80000000 566 #define CQE_CODE_MASK 0x0000003F 567 #define CQE_CID_MASK 0x0000FFC0 568 569 #define EQE_VALID_MASK 0x00000001 570 #define EQE_MAJORCODE_MASK 0x0000000E 571 #define EQE_RESID_MASK 0xFFFF0000 572 573 struct be_eq_entry { 574 u32 dw[1]; 575 } __packed; 576 577 /** 578 * Pseudo amap definition in which each bit of the actual structure is defined 579 * as a byte: used to calculate offset/shift/mask of each field 580 */ 581 struct amap_eq_entry { 582 u8 valid; /* DWORD 0 */ 583 u8 major_code[3]; /* DWORD 0 */ 584 u8 minor_code[12]; /* DWORD 0 */ 585 u8 resource_id[16]; /* DWORD 0 */ 586 587 } __packed; 588 589 struct cq_db { 590 u32 dw[1]; 591 } __packed; 592 593 /** 594 * Pseudo amap definition in which each bit of the actual structure is defined 595 * as a byte: used to calculate offset/shift/mask of each field 596 */ 597 struct amap_cq_db { 598 u8 qid[10]; 599 u8 event[1]; 600 u8 rsvd0[5]; 601 u8 num_popped[13]; 602 u8 rearm[1]; 603 u8 rsvd1[2]; 604 } __packed; 605 606 void beiscsi_process_eq(struct beiscsi_hba *phba); 607 608 struct iscsi_wrb { 609 u32 dw[16]; 610 } __packed; 611 612 #define WRB_TYPE_MASK 0xF0000000 613 614 /** 615 * Pseudo amap definition in which each bit of the actual structure is defined 616 * as a byte: used to calculate offset/shift/mask of each field 617 */ 618 struct amap_iscsi_wrb { 619 u8 lun[14]; /* DWORD 0 */ 620 u8 lt; /* DWORD 0 */ 621 u8 invld; /* DWORD 0 */ 622 u8 wrb_idx[8]; /* DWORD 0 */ 623 u8 dsp; /* DWORD 0 */ 624 u8 dmsg; /* DWORD 0 */ 625 u8 undr_run; /* DWORD 0 */ 626 u8 over_run; /* DWORD 0 */ 627 u8 type[4]; /* DWORD 0 */ 628 u8 ptr2nextwrb[8]; /* DWORD 1 */ 629 u8 r2t_exp_dtl[24]; /* DWORD 1 */ 630 u8 sgl_icd_idx[12]; /* DWORD 2 */ 631 u8 rsvd0[20]; /* DWORD 2 */ 632 u8 exp_data_sn[32]; /* DWORD 3 */ 633 u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */ 634 u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */ 635 u8 cmdsn_itt[32]; /* DWORD 6 */ 636 u8 dif_ref_tag[32]; /* DWORD 7 */ 637 u8 sge0_addr_hi[32]; /* DWORD 8 */ 638 u8 sge0_addr_lo[32]; /* DWORD 9 */ 639 u8 sge0_offset[22]; /* DWORD 10 */ 640 u8 pbs; /* DWORD 10 */ 641 u8 dif_mode[2]; /* DWORD 10 */ 642 u8 rsvd1[6]; /* DWORD 10 */ 643 u8 sge0_last; /* DWORD 10 */ 644 u8 sge0_len[17]; /* DWORD 11 */ 645 u8 dif_meta_tag[14]; /* DWORD 11 */ 646 u8 sge0_in_ddr; /* DWORD 11 */ 647 u8 sge1_addr_hi[32]; /* DWORD 12 */ 648 u8 sge1_addr_lo[32]; /* DWORD 13 */ 649 u8 sge1_r2t_offset[22]; /* DWORD 14 */ 650 u8 rsvd2[9]; /* DWORD 14 */ 651 u8 sge1_last; /* DWORD 14 */ 652 u8 sge1_len[17]; /* DWORD 15 */ 653 u8 ref_sgl_icd_idx[12]; /* DWORD 15 */ 654 u8 rsvd3[2]; /* DWORD 15 */ 655 u8 sge1_in_ddr; /* DWORD 15 */ 656 657 } __packed; 658 659 struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid, 660 int index); 661 void 662 free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle); 663 664 struct pdu_nop_out { 665 u32 dw[12]; 666 }; 667 668 /** 669 * Pseudo amap definition in which each bit of the actual structure is defined 670 * as a byte: used to calculate offset/shift/mask of each field 671 */ 672 struct amap_pdu_nop_out { 673 u8 opcode[6]; /* opcode 0x00 */ 674 u8 i_bit; /* I Bit */ 675 u8 x_bit; /* reserved; should be 0 */ 676 u8 fp_bit_filler1[7]; 677 u8 f_bit; /* always 1 */ 678 u8 reserved1[16]; 679 u8 ahs_length[8]; /* no AHS */ 680 u8 data_len_hi[8]; 681 u8 data_len_lo[16]; /* DataSegmentLength */ 682 u8 lun[64]; 683 u8 itt[32]; /* initiator id for ping or 0xffffffff */ 684 u8 ttt[32]; /* target id for ping or 0xffffffff */ 685 u8 cmd_sn[32]; 686 u8 exp_stat_sn[32]; 687 u8 reserved5[128]; 688 }; 689 690 #define PDUBASE_OPCODE_MASK 0x0000003F 691 #define PDUBASE_DATALENHI_MASK 0x0000FF00 692 #define PDUBASE_DATALENLO_MASK 0xFFFF0000 693 694 struct pdu_base { 695 u32 dw[16]; 696 } __packed; 697 698 /** 699 * Pseudo amap definition in which each bit of the actual structure is defined 700 * as a byte: used to calculate offset/shift/mask of each field 701 */ 702 struct amap_pdu_base { 703 u8 opcode[6]; 704 u8 i_bit; /* immediate bit */ 705 u8 x_bit; /* reserved, always 0 */ 706 u8 reserved1[24]; /* opcode-specific fields */ 707 u8 ahs_length[8]; /* length units is 4 byte words */ 708 u8 data_len_hi[8]; 709 u8 data_len_lo[16]; /* DatasegmentLength */ 710 u8 lun[64]; /* lun or opcode-specific fields */ 711 u8 itt[32]; /* initiator task tag */ 712 u8 reserved4[224]; 713 }; 714 715 struct iscsi_target_context_update_wrb { 716 u32 dw[16]; 717 } __packed; 718 719 /** 720 * Pseudo amap definition in which each bit of the actual structure is defined 721 * as a byte: used to calculate offset/shift/mask of each field 722 */ 723 struct amap_iscsi_target_context_update_wrb { 724 u8 lun[14]; /* DWORD 0 */ 725 u8 lt; /* DWORD 0 */ 726 u8 invld; /* DWORD 0 */ 727 u8 wrb_idx[8]; /* DWORD 0 */ 728 u8 dsp; /* DWORD 0 */ 729 u8 dmsg; /* DWORD 0 */ 730 u8 undr_run; /* DWORD 0 */ 731 u8 over_run; /* DWORD 0 */ 732 u8 type[4]; /* DWORD 0 */ 733 u8 ptr2nextwrb[8]; /* DWORD 1 */ 734 u8 max_burst_length[19]; /* DWORD 1 */ 735 u8 rsvd0[5]; /* DWORD 1 */ 736 u8 rsvd1[15]; /* DWORD 2 */ 737 u8 max_send_data_segment_length[17]; /* DWORD 2 */ 738 u8 first_burst_length[14]; /* DWORD 3 */ 739 u8 rsvd2[2]; /* DWORD 3 */ 740 u8 tx_wrbindex_drv_msg[8]; /* DWORD 3 */ 741 u8 rsvd3[5]; /* DWORD 3 */ 742 u8 session_state[3]; /* DWORD 3 */ 743 u8 rsvd4[16]; /* DWORD 4 */ 744 u8 tx_jumbo; /* DWORD 4 */ 745 u8 hde; /* DWORD 4 */ 746 u8 dde; /* DWORD 4 */ 747 u8 erl[2]; /* DWORD 4 */ 748 u8 domain_id[5]; /* DWORD 4 */ 749 u8 mode; /* DWORD 4 */ 750 u8 imd; /* DWORD 4 */ 751 u8 ir2t; /* DWORD 4 */ 752 u8 notpredblq[2]; /* DWORD 4 */ 753 u8 compltonack; /* DWORD 4 */ 754 u8 stat_sn[32]; /* DWORD 5 */ 755 u8 pad_buffer_addr_hi[32]; /* DWORD 6 */ 756 u8 pad_buffer_addr_lo[32]; /* DWORD 7 */ 757 u8 pad_addr_hi[32]; /* DWORD 8 */ 758 u8 pad_addr_lo[32]; /* DWORD 9 */ 759 u8 rsvd5[32]; /* DWORD 10 */ 760 u8 rsvd6[32]; /* DWORD 11 */ 761 u8 rsvd7[32]; /* DWORD 12 */ 762 u8 rsvd8[32]; /* DWORD 13 */ 763 u8 rsvd9[32]; /* DWORD 14 */ 764 u8 rsvd10[32]; /* DWORD 15 */ 765 766 } __packed; 767 768 struct be_ring { 769 u32 pages; /* queue size in pages */ 770 u32 id; /* queue id assigned by beklib */ 771 u32 num; /* number of elements in queue */ 772 u32 cidx; /* consumer index */ 773 u32 pidx; /* producer index -- not used by most rings */ 774 u32 item_size; /* size in bytes of one object */ 775 776 void *va; /* The virtual address of the ring. This 777 * should be last to allow 32 & 64 bit debugger 778 * extensions to work. 779 */ 780 }; 781 782 struct hwi_wrb_context { 783 struct list_head wrb_handle_list; 784 struct list_head wrb_handle_drvr_list; 785 struct wrb_handle **pwrb_handle_base; 786 struct wrb_handle **pwrb_handle_basestd; 787 struct iscsi_wrb *plast_wrb; 788 unsigned short alloc_index; 789 unsigned short free_index; 790 unsigned short wrb_handles_available; 791 unsigned short cid; 792 }; 793 794 struct hwi_controller { 795 struct list_head io_sgl_list; 796 struct list_head eh_sgl_list; 797 struct sgl_handle *psgl_handle_base; 798 unsigned int wrb_mem_index; 799 800 struct hwi_wrb_context wrb_context[BE2_MAX_SESSIONS * 2]; 801 struct mcc_wrb *pmcc_wrb_base; 802 struct be_ring default_pdu_hdr; 803 struct be_ring default_pdu_data; 804 struct hwi_context_memory *phwi_ctxt; 805 unsigned short cq_errors[CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN]; 806 }; 807 808 enum hwh_type_enum { 809 HWH_TYPE_IO = 1, 810 HWH_TYPE_LOGOUT = 2, 811 HWH_TYPE_TMF = 3, 812 HWH_TYPE_NOP = 4, 813 HWH_TYPE_IO_RD = 5, 814 HWH_TYPE_LOGIN = 11, 815 HWH_TYPE_INVALID = 0xFFFFFFFF 816 }; 817 818 struct wrb_handle { 819 enum hwh_type_enum type; 820 unsigned short wrb_index; 821 unsigned short nxt_wrb_index; 822 823 struct iscsi_task *pio_handle; 824 struct iscsi_wrb *pwrb; 825 }; 826 827 struct hwi_context_memory { 828 /* Adaptive interrupt coalescing (AIC) info */ 829 u16 min_eqd; /* in usecs */ 830 u16 max_eqd; /* in usecs */ 831 u16 cur_eqd; /* in usecs */ 832 struct be_eq_obj be_eq[MAX_CPUS]; 833 struct be_queue_info be_cq[MAX_CPUS]; 834 835 struct be_queue_info be_def_hdrq; 836 struct be_queue_info be_def_dataq; 837 838 struct be_queue_info be_wrbq[BE2_MAX_SESSIONS]; 839 struct be_mcc_wrb_context *pbe_mcc_context; 840 841 struct hwi_async_pdu_context *pasync_ctx; 842 }; 843 844 #endif 845