1 /** 2 * Copyright (C) 2005 - 2013 Emulex 3 * All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License version 2 7 * as published by the Free Software Foundation. The full GNU General 8 * Public License is included in this distribution in the file called COPYING. 9 * 10 * Written by: Jayamohan Kallickal (jayamohan.kallickal@emulex.com) 11 * 12 * Contact Information: 13 * linux-drivers@emulex.com 14 * 15 * Emulex 16 * 3333 Susan Street 17 * Costa Mesa, CA 92626 18 */ 19 20 #ifndef _BEISCSI_MAIN_ 21 #define _BEISCSI_MAIN_ 22 23 #include <linux/kernel.h> 24 #include <linux/pci.h> 25 #include <linux/if_ether.h> 26 #include <linux/in.h> 27 #include <linux/ctype.h> 28 #include <linux/module.h> 29 #include <scsi/scsi.h> 30 #include <scsi/scsi_cmnd.h> 31 #include <scsi/scsi_device.h> 32 #include <scsi/scsi_host.h> 33 #include <scsi/iscsi_proto.h> 34 #include <scsi/libiscsi.h> 35 #include <scsi/scsi_transport_iscsi.h> 36 37 #include "be.h" 38 #define DRV_NAME "be2iscsi" 39 #define BUILD_STR "10.0.467.0" 40 #define BE_NAME "Emulex OneConnect" \ 41 "Open-iSCSI Driver version" BUILD_STR 42 #define DRV_DESC BE_NAME " " "Driver" 43 44 #define BE_VENDOR_ID 0x19A2 45 #define ELX_VENDOR_ID 0x10DF 46 /* DEVICE ID's for BE2 */ 47 #define BE_DEVICE_ID1 0x212 48 #define OC_DEVICE_ID1 0x702 49 #define OC_DEVICE_ID2 0x703 50 51 /* DEVICE ID's for BE3 */ 52 #define BE_DEVICE_ID2 0x222 53 #define OC_DEVICE_ID3 0x712 54 55 /* DEVICE ID for SKH */ 56 #define OC_SKH_ID1 0x722 57 58 #define BE2_IO_DEPTH 1024 59 #define BE2_MAX_SESSIONS 256 60 #define BE2_CMDS_PER_CXN 128 61 #define BE2_TMFS 16 62 #define BE2_NOPOUT_REQ 16 63 #define BE2_SGE 32 64 #define BE2_DEFPDU_HDR_SZ 64 65 #define BE2_DEFPDU_DATA_SZ 8192 66 67 #define MAX_CPUS 64 68 #define BEISCSI_MAX_NUM_CPUS 7 69 #define OC_SKH_MAX_NUM_CPUS 31 70 71 #define BEISCSI_VER_STRLEN 32 72 73 #define BEISCSI_SGLIST_ELEMENTS 30 74 75 #define BEISCSI_CMD_PER_LUN 128 /* scsi_host->cmd_per_lun */ 76 #define BEISCSI_MAX_SECTORS 2048 /* scsi_host->max_sectors */ 77 78 #define BEISCSI_MAX_CMD_LEN 16 /* scsi_host->max_cmd_len */ 79 #define BEISCSI_NUM_MAX_LUN 256 /* scsi_host->max_lun */ 80 #define BEISCSI_NUM_DEVICES_SUPPORTED 0x01 81 #define BEISCSI_MAX_FRAGS_INIT 192 82 #define BE_NUM_MSIX_ENTRIES 1 83 84 #define MPU_EP_CONTROL 0 85 #define MPU_EP_SEMAPHORE 0xac 86 #define BE2_SOFT_RESET 0x5c 87 #define BE2_PCI_ONLINE0 0xb0 88 #define BE2_PCI_ONLINE1 0xb4 89 #define BE2_SET_RESET 0x80 90 #define BE2_MPU_IRAM_ONLINE 0x00000080 91 92 #define BE_SENSE_INFO_SIZE 258 93 #define BE_ISCSI_PDU_HEADER_SIZE 64 94 #define BE_MIN_MEM_SIZE 16384 95 #define MAX_CMD_SZ 65536 96 #define IIOC_SCSI_DATA 0x05 /* Write Operation */ 97 98 #define INVALID_SESS_HANDLE 0xFFFFFFFF 99 100 #define BE_ADAPTER_UP 0x00000000 101 #define BE_ADAPTER_LINK_DOWN 0x00000001 102 /** 103 * hardware needs the async PDU buffers to be posted in multiples of 8 104 * So have atleast 8 of them by default 105 */ 106 107 #define HWI_GET_ASYNC_PDU_CTX(phwi) (phwi->phwi_ctxt->pasync_ctx) 108 109 /********* Memory BAR register ************/ 110 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc 111 /** 112 * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt 113 * Disable" may still globally block interrupts in addition to individual 114 * interrupt masks; a mechanism for the device driver to block all interrupts 115 * atomically without having to arbitrate for the PCI Interrupt Disable bit 116 * with the OS. 117 */ 118 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */ 119 120 /********* ISR0 Register offset **********/ 121 #define CEV_ISR0_OFFSET 0xC18 122 #define CEV_ISR_SIZE 4 123 124 /** 125 * Macros for reading/writing a protection domain or CSR registers 126 * in BladeEngine. 127 */ 128 129 #define DB_TXULP0_OFFSET 0x40 130 #define DB_RXULP0_OFFSET 0xA0 131 /********* Event Q door bell *************/ 132 #define DB_EQ_OFFSET DB_CQ_OFFSET 133 #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */ 134 /* Clear the interrupt for this eq */ 135 #define DB_EQ_CLR_SHIFT (9) /* bit 9 */ 136 /* Must be 1 */ 137 #define DB_EQ_EVNT_SHIFT (10) /* bit 10 */ 138 /* Number of event entries processed */ 139 #define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */ 140 /* Rearm bit */ 141 #define DB_EQ_REARM_SHIFT (29) /* bit 29 */ 142 143 /********* Compl Q door bell *************/ 144 #define DB_CQ_OFFSET 0x120 145 #define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */ 146 /* Number of event entries processed */ 147 #define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */ 148 /* Rearm bit */ 149 #define DB_CQ_REARM_SHIFT (29) /* bit 29 */ 150 151 #define GET_HWI_CONTROLLER_WS(pc) (pc->phwi_ctrlr) 152 #define HWI_GET_DEF_BUFQ_ID(pc) (((struct hwi_controller *)\ 153 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data.id) 154 #define HWI_GET_DEF_HDRQ_ID(pc) (((struct hwi_controller *)\ 155 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr.id) 156 157 #define PAGES_REQUIRED(x) \ 158 ((x < PAGE_SIZE) ? 1 : ((x + PAGE_SIZE - 1) / PAGE_SIZE)) 159 160 #define BEISCSI_MSI_NAME 20 /* size of msi_name string */ 161 162 enum be_mem_enum { 163 HWI_MEM_ADDN_CONTEXT, 164 HWI_MEM_WRB, 165 HWI_MEM_WRBH, 166 HWI_MEM_SGLH, 167 HWI_MEM_SGE, 168 HWI_MEM_ASYNC_HEADER_BUF, /* 5 */ 169 HWI_MEM_ASYNC_DATA_BUF, 170 HWI_MEM_ASYNC_HEADER_RING, 171 HWI_MEM_ASYNC_DATA_RING, 172 HWI_MEM_ASYNC_HEADER_HANDLE, 173 HWI_MEM_ASYNC_DATA_HANDLE, /* 10 */ 174 HWI_MEM_ASYNC_PDU_CONTEXT, 175 ISCSI_MEM_GLOBAL_HEADER, 176 SE_MEM_MAX 177 }; 178 179 struct be_bus_address32 { 180 unsigned int address_lo; 181 unsigned int address_hi; 182 }; 183 184 struct be_bus_address64 { 185 unsigned long long address; 186 }; 187 188 struct be_bus_address { 189 union { 190 struct be_bus_address32 a32; 191 struct be_bus_address64 a64; 192 } u; 193 }; 194 195 struct mem_array { 196 struct be_bus_address bus_address; /* Bus address of location */ 197 void *virtual_address; /* virtual address to the location */ 198 unsigned int size; /* Size required by memory block */ 199 }; 200 201 struct be_mem_descriptor { 202 unsigned int index; /* Index of this memory parameter */ 203 unsigned int category; /* type indicates cached/non-cached */ 204 unsigned int num_elements; /* number of elements in this 205 * descriptor 206 */ 207 unsigned int alignment_mask; /* Alignment mask for this block */ 208 unsigned int size_in_bytes; /* Size required by memory block */ 209 struct mem_array *mem_array; 210 }; 211 212 struct sgl_handle { 213 unsigned int sgl_index; 214 unsigned int type; 215 unsigned int cid; 216 struct iscsi_task *task; 217 struct iscsi_sge *pfrag; 218 }; 219 220 struct hba_parameters { 221 unsigned int ios_per_ctrl; 222 unsigned int cxns_per_ctrl; 223 unsigned int asyncpdus_per_ctrl; 224 unsigned int icds_per_ctrl; 225 unsigned int num_sge_per_io; 226 unsigned int defpdu_hdr_sz; 227 unsigned int defpdu_data_sz; 228 unsigned int num_cq_entries; 229 unsigned int num_eq_entries; 230 unsigned int wrbs_per_cxn; 231 unsigned int crashmode; 232 unsigned int hba_num; 233 234 unsigned int mgmt_ws_sz; 235 unsigned int hwi_ws_sz; 236 237 unsigned int eto; 238 unsigned int ldto; 239 240 unsigned int dbg_flags; 241 unsigned int num_cxn; 242 243 unsigned int eq_timer; 244 /** 245 * These are calculated from other params. They're here 246 * for debug purposes 247 */ 248 unsigned int num_mcc_pages; 249 unsigned int num_mcc_cq_pages; 250 unsigned int num_cq_pages; 251 unsigned int num_eq_pages; 252 253 unsigned int num_async_pdu_buf_pages; 254 unsigned int num_async_pdu_buf_sgl_pages; 255 unsigned int num_async_pdu_buf_cq_pages; 256 257 unsigned int num_async_pdu_hdr_pages; 258 unsigned int num_async_pdu_hdr_sgl_pages; 259 unsigned int num_async_pdu_hdr_cq_pages; 260 261 unsigned int num_sge; 262 }; 263 264 struct invalidate_command_table { 265 unsigned short icd; 266 unsigned short cid; 267 } __packed; 268 269 #define chip_be2(phba) (phba->generation == BE_GEN2) 270 #define chip_be3_r(phba) (phba->generation == BE_GEN3) 271 #define is_chip_be2_be3r(phba) (chip_be3_r(phba) || (chip_be2(phba))) 272 struct beiscsi_hba { 273 struct hba_parameters params; 274 struct hwi_controller *phwi_ctrlr; 275 unsigned int mem_req[SE_MEM_MAX]; 276 /* PCI BAR mapped addresses */ 277 u8 __iomem *csr_va; /* CSR */ 278 u8 __iomem *db_va; /* Door Bell */ 279 u8 __iomem *pci_va; /* PCI Config */ 280 struct be_bus_address csr_pa; /* CSR */ 281 struct be_bus_address db_pa; /* CSR */ 282 struct be_bus_address pci_pa; /* CSR */ 283 /* PCI representation of our HBA */ 284 struct pci_dev *pcidev; 285 unsigned short asic_revision; 286 unsigned int num_cpus; 287 unsigned int nxt_cqid; 288 struct msix_entry msix_entries[MAX_CPUS]; 289 char *msi_name[MAX_CPUS]; 290 bool msix_enabled; 291 struct be_mem_descriptor *init_mem; 292 293 unsigned short io_sgl_alloc_index; 294 unsigned short io_sgl_free_index; 295 unsigned short io_sgl_hndl_avbl; 296 struct sgl_handle **io_sgl_hndl_base; 297 struct sgl_handle **sgl_hndl_array; 298 299 unsigned short eh_sgl_alloc_index; 300 unsigned short eh_sgl_free_index; 301 unsigned short eh_sgl_hndl_avbl; 302 struct sgl_handle **eh_sgl_hndl_base; 303 spinlock_t io_sgl_lock; 304 spinlock_t mgmt_sgl_lock; 305 spinlock_t isr_lock; 306 unsigned int age; 307 unsigned short avlbl_cids; 308 unsigned short cid_alloc; 309 unsigned short cid_free; 310 struct list_head hba_queue; 311 #define BE_MAX_SESSION 2048 312 #define BE_SET_CID_TO_CRI(cri_index, cid) \ 313 (phba->cid_to_cri_map[cid] = cri_index) 314 #define BE_GET_CRI_FROM_CID(cid) (phba->cid_to_cri_map[cid]) 315 unsigned short cid_to_cri_map[BE_MAX_SESSION]; 316 unsigned short *cid_array; 317 struct iscsi_endpoint **ep_array; 318 struct beiscsi_conn **conn_table; 319 struct iscsi_boot_kset *boot_kset; 320 struct Scsi_Host *shost; 321 struct iscsi_iface *ipv4_iface; 322 struct iscsi_iface *ipv6_iface; 323 struct { 324 /** 325 * group together since they are used most frequently 326 * for cid to cri conversion 327 */ 328 unsigned int iscsi_cid_start; 329 unsigned int phys_port; 330 331 unsigned int isr_offset; 332 unsigned int iscsi_icd_start; 333 unsigned int iscsi_cid_count; 334 unsigned int iscsi_icd_count; 335 unsigned int pci_function; 336 337 unsigned short cid_alloc; 338 unsigned short cid_free; 339 unsigned short avlbl_cids; 340 unsigned short iscsi_features; 341 spinlock_t cid_lock; 342 } fw_config; 343 344 unsigned int state; 345 bool fw_timeout; 346 bool ue_detected; 347 struct delayed_work beiscsi_hw_check_task; 348 349 u8 mac_address[ETH_ALEN]; 350 char fw_ver_str[BEISCSI_VER_STRLEN]; 351 char wq_name[20]; 352 struct workqueue_struct *wq; /* The actuak work queue */ 353 struct be_ctrl_info ctrl; 354 unsigned int generation; 355 unsigned int interface_handle; 356 struct mgmt_session_info boot_sess; 357 struct invalidate_command_table inv_tbl[128]; 358 359 unsigned int attr_log_enable; 360 int (*iotask_fn)(struct iscsi_task *, 361 struct scatterlist *sg, 362 uint32_t num_sg, uint32_t xferlen, 363 uint32_t writedir); 364 }; 365 366 struct beiscsi_session { 367 struct pci_pool *bhs_pool; 368 }; 369 370 /** 371 * struct beiscsi_conn - iscsi connection structure 372 */ 373 struct beiscsi_conn { 374 struct iscsi_conn *conn; 375 struct beiscsi_hba *phba; 376 u32 exp_statsn; 377 u32 beiscsi_conn_cid; 378 struct beiscsi_endpoint *ep; 379 unsigned short login_in_progress; 380 struct wrb_handle *plogin_wrb_handle; 381 struct sgl_handle *plogin_sgl_handle; 382 struct beiscsi_session *beiscsi_sess; 383 struct iscsi_task *task; 384 }; 385 386 /* This structure is used by the chip */ 387 struct pdu_data_out { 388 u32 dw[12]; 389 }; 390 /** 391 * Pseudo amap definition in which each bit of the actual structure is defined 392 * as a byte: used to calculate offset/shift/mask of each field 393 */ 394 struct amap_pdu_data_out { 395 u8 opcode[6]; /* opcode */ 396 u8 rsvd0[2]; /* should be 0 */ 397 u8 rsvd1[7]; 398 u8 final_bit; /* F bit */ 399 u8 rsvd2[16]; 400 u8 ahs_length[8]; /* no AHS */ 401 u8 data_len_hi[8]; 402 u8 data_len_lo[16]; /* DataSegmentLength */ 403 u8 lun[64]; 404 u8 itt[32]; /* ITT; initiator task tag */ 405 u8 ttt[32]; /* TTT; valid for R2T or 0xffffffff */ 406 u8 rsvd3[32]; 407 u8 exp_stat_sn[32]; 408 u8 rsvd4[32]; 409 u8 data_sn[32]; 410 u8 buffer_offset[32]; 411 u8 rsvd5[32]; 412 }; 413 414 struct be_cmd_bhs { 415 struct iscsi_scsi_req iscsi_hdr; 416 unsigned char pad1[16]; 417 struct pdu_data_out iscsi_data_pdu; 418 unsigned char pad2[BE_SENSE_INFO_SIZE - 419 sizeof(struct pdu_data_out)]; 420 }; 421 422 struct beiscsi_io_task { 423 struct wrb_handle *pwrb_handle; 424 struct sgl_handle *psgl_handle; 425 struct beiscsi_conn *conn; 426 struct scsi_cmnd *scsi_cmnd; 427 unsigned int cmd_sn; 428 unsigned int flags; 429 unsigned short cid; 430 unsigned short header_len; 431 itt_t libiscsi_itt; 432 struct be_cmd_bhs *cmd_bhs; 433 struct be_bus_address bhs_pa; 434 unsigned short bhs_len; 435 dma_addr_t mtask_addr; 436 uint32_t mtask_data_count; 437 uint8_t wrb_type; 438 }; 439 440 struct be_nonio_bhs { 441 struct iscsi_hdr iscsi_hdr; 442 unsigned char pad1[16]; 443 struct pdu_data_out iscsi_data_pdu; 444 unsigned char pad2[BE_SENSE_INFO_SIZE - 445 sizeof(struct pdu_data_out)]; 446 }; 447 448 struct be_status_bhs { 449 struct iscsi_scsi_req iscsi_hdr; 450 unsigned char pad1[16]; 451 /** 452 * The plus 2 below is to hold the sense info length that gets 453 * DMA'ed by RxULP 454 */ 455 unsigned char sense_info[BE_SENSE_INFO_SIZE]; 456 }; 457 458 struct iscsi_sge { 459 u32 dw[4]; 460 }; 461 462 /** 463 * Pseudo amap definition in which each bit of the actual structure is defined 464 * as a byte: used to calculate offset/shift/mask of each field 465 */ 466 struct amap_iscsi_sge { 467 u8 addr_hi[32]; 468 u8 addr_lo[32]; 469 u8 sge_offset[22]; /* DWORD 2 */ 470 u8 rsvd0[9]; /* DWORD 2 */ 471 u8 last_sge; /* DWORD 2 */ 472 u8 len[17]; /* DWORD 3 */ 473 u8 rsvd1[15]; /* DWORD 3 */ 474 }; 475 476 struct beiscsi_offload_params { 477 u32 dw[5]; 478 }; 479 480 #define OFFLD_PARAMS_ERL 0x00000003 481 #define OFFLD_PARAMS_DDE 0x00000004 482 #define OFFLD_PARAMS_HDE 0x00000008 483 #define OFFLD_PARAMS_IR2T 0x00000010 484 #define OFFLD_PARAMS_IMD 0x00000020 485 #define OFFLD_PARAMS_DATA_SEQ_INORDER 0x00000040 486 #define OFFLD_PARAMS_PDU_SEQ_INORDER 0x00000080 487 #define OFFLD_PARAMS_MAX_R2T 0x00FFFF00 488 489 /** 490 * Pseudo amap definition in which each bit of the actual structure is defined 491 * as a byte: used to calculate offset/shift/mask of each field 492 */ 493 struct amap_beiscsi_offload_params { 494 u8 max_burst_length[32]; 495 u8 max_send_data_segment_length[32]; 496 u8 first_burst_length[32]; 497 u8 erl[2]; 498 u8 dde[1]; 499 u8 hde[1]; 500 u8 ir2t[1]; 501 u8 imd[1]; 502 u8 data_seq_inorder[1]; 503 u8 pdu_seq_inorder[1]; 504 u8 max_r2t[16]; 505 u8 pad[8]; 506 u8 exp_statsn[32]; 507 }; 508 509 /* void hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn, 510 struct beiscsi_hba *phba, struct sol_cqe *psol);*/ 511 512 struct async_pdu_handle { 513 struct list_head link; 514 struct be_bus_address pa; 515 void *pbuffer; 516 unsigned int consumed; 517 unsigned char index; 518 unsigned char is_header; 519 unsigned short cri; 520 unsigned long buffer_len; 521 }; 522 523 struct hwi_async_entry { 524 struct { 525 unsigned char hdr_received; 526 unsigned char hdr_len; 527 unsigned short bytes_received; 528 unsigned int bytes_needed; 529 struct list_head list; 530 } wait_queue; 531 532 struct list_head header_busy_list; 533 struct list_head data_busy_list; 534 }; 535 536 struct hwi_async_pdu_context { 537 struct { 538 struct be_bus_address pa_base; 539 void *va_base; 540 void *ring_base; 541 struct async_pdu_handle *handle_base; 542 543 unsigned int host_write_ptr; 544 unsigned int ep_read_ptr; 545 unsigned int writables; 546 547 unsigned int free_entries; 548 unsigned int busy_entries; 549 550 struct list_head free_list; 551 } async_header; 552 553 struct { 554 struct be_bus_address pa_base; 555 void *va_base; 556 void *ring_base; 557 struct async_pdu_handle *handle_base; 558 559 unsigned int host_write_ptr; 560 unsigned int ep_read_ptr; 561 unsigned int writables; 562 563 unsigned int free_entries; 564 unsigned int busy_entries; 565 struct list_head free_list; 566 } async_data; 567 568 unsigned int buffer_size; 569 unsigned int num_entries; 570 571 /** 572 * This is a varying size list! Do not add anything 573 * after this entry!! 574 */ 575 struct hwi_async_entry *async_entry; 576 }; 577 578 #define PDUCQE_CODE_MASK 0x0000003F 579 #define PDUCQE_DPL_MASK 0xFFFF0000 580 #define PDUCQE_INDEX_MASK 0x0000FFFF 581 582 struct i_t_dpdu_cqe { 583 u32 dw[4]; 584 } __packed; 585 586 /** 587 * Pseudo amap definition in which each bit of the actual structure is defined 588 * as a byte: used to calculate offset/shift/mask of each field 589 */ 590 struct amap_i_t_dpdu_cqe { 591 u8 db_addr_hi[32]; 592 u8 db_addr_lo[32]; 593 u8 code[6]; 594 u8 cid[10]; 595 u8 dpl[16]; 596 u8 index[16]; 597 u8 num_cons[10]; 598 u8 rsvd0[4]; 599 u8 final; 600 u8 valid; 601 } __packed; 602 603 struct amap_i_t_dpdu_cqe_v2 { 604 u8 db_addr_hi[32]; /* DWORD 0 */ 605 u8 db_addr_lo[32]; /* DWORD 1 */ 606 u8 code[6]; /* DWORD 2 */ 607 u8 num_cons; /* DWORD 2*/ 608 u8 rsvd0[8]; /* DWORD 2 */ 609 u8 dpl[17]; /* DWORD 2 */ 610 u8 index[16]; /* DWORD 3 */ 611 u8 cid[13]; /* DWORD 3 */ 612 u8 rsvd1; /* DWORD 3 */ 613 u8 final; /* DWORD 3 */ 614 u8 valid; /* DWORD 3 */ 615 } __packed; 616 617 #define CQE_VALID_MASK 0x80000000 618 #define CQE_CODE_MASK 0x0000003F 619 #define CQE_CID_MASK 0x0000FFC0 620 621 #define EQE_VALID_MASK 0x00000001 622 #define EQE_MAJORCODE_MASK 0x0000000E 623 #define EQE_RESID_MASK 0xFFFF0000 624 625 struct be_eq_entry { 626 u32 dw[1]; 627 } __packed; 628 629 /** 630 * Pseudo amap definition in which each bit of the actual structure is defined 631 * as a byte: used to calculate offset/shift/mask of each field 632 */ 633 struct amap_eq_entry { 634 u8 valid; /* DWORD 0 */ 635 u8 major_code[3]; /* DWORD 0 */ 636 u8 minor_code[12]; /* DWORD 0 */ 637 u8 resource_id[16]; /* DWORD 0 */ 638 639 } __packed; 640 641 struct cq_db { 642 u32 dw[1]; 643 } __packed; 644 645 /** 646 * Pseudo amap definition in which each bit of the actual structure is defined 647 * as a byte: used to calculate offset/shift/mask of each field 648 */ 649 struct amap_cq_db { 650 u8 qid[10]; 651 u8 event[1]; 652 u8 rsvd0[5]; 653 u8 num_popped[13]; 654 u8 rearm[1]; 655 u8 rsvd1[2]; 656 } __packed; 657 658 void beiscsi_process_eq(struct beiscsi_hba *phba); 659 660 struct iscsi_wrb { 661 u32 dw[16]; 662 } __packed; 663 664 #define WRB_TYPE_MASK 0xF0000000 665 #define SKH_WRB_TYPE_OFFSET 27 666 #define BE_WRB_TYPE_OFFSET 28 667 668 #define ADAPTER_SET_WRB_TYPE(pwrb, wrb_type, type_offset) \ 669 (pwrb->dw[0] |= (wrb_type << type_offset)) 670 671 /** 672 * Pseudo amap definition in which each bit of the actual structure is defined 673 * as a byte: used to calculate offset/shift/mask of each field 674 */ 675 struct amap_iscsi_wrb { 676 u8 lun[14]; /* DWORD 0 */ 677 u8 lt; /* DWORD 0 */ 678 u8 invld; /* DWORD 0 */ 679 u8 wrb_idx[8]; /* DWORD 0 */ 680 u8 dsp; /* DWORD 0 */ 681 u8 dmsg; /* DWORD 0 */ 682 u8 undr_run; /* DWORD 0 */ 683 u8 over_run; /* DWORD 0 */ 684 u8 type[4]; /* DWORD 0 */ 685 u8 ptr2nextwrb[8]; /* DWORD 1 */ 686 u8 r2t_exp_dtl[24]; /* DWORD 1 */ 687 u8 sgl_icd_idx[12]; /* DWORD 2 */ 688 u8 rsvd0[20]; /* DWORD 2 */ 689 u8 exp_data_sn[32]; /* DWORD 3 */ 690 u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */ 691 u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */ 692 u8 cmdsn_itt[32]; /* DWORD 6 */ 693 u8 dif_ref_tag[32]; /* DWORD 7 */ 694 u8 sge0_addr_hi[32]; /* DWORD 8 */ 695 u8 sge0_addr_lo[32]; /* DWORD 9 */ 696 u8 sge0_offset[22]; /* DWORD 10 */ 697 u8 pbs; /* DWORD 10 */ 698 u8 dif_mode[2]; /* DWORD 10 */ 699 u8 rsvd1[6]; /* DWORD 10 */ 700 u8 sge0_last; /* DWORD 10 */ 701 u8 sge0_len[17]; /* DWORD 11 */ 702 u8 dif_meta_tag[14]; /* DWORD 11 */ 703 u8 sge0_in_ddr; /* DWORD 11 */ 704 u8 sge1_addr_hi[32]; /* DWORD 12 */ 705 u8 sge1_addr_lo[32]; /* DWORD 13 */ 706 u8 sge1_r2t_offset[22]; /* DWORD 14 */ 707 u8 rsvd2[9]; /* DWORD 14 */ 708 u8 sge1_last; /* DWORD 14 */ 709 u8 sge1_len[17]; /* DWORD 15 */ 710 u8 ref_sgl_icd_idx[12]; /* DWORD 15 */ 711 u8 rsvd3[2]; /* DWORD 15 */ 712 u8 sge1_in_ddr; /* DWORD 15 */ 713 714 } __packed; 715 716 struct amap_iscsi_wrb_v2 { 717 u8 r2t_exp_dtl[25]; /* DWORD 0 */ 718 u8 rsvd0[2]; /* DWORD 0*/ 719 u8 type[5]; /* DWORD 0 */ 720 u8 ptr2nextwrb[8]; /* DWORD 1 */ 721 u8 wrb_idx[8]; /* DWORD 1 */ 722 u8 lun[16]; /* DWORD 1 */ 723 u8 sgl_idx[16]; /* DWORD 2 */ 724 u8 ref_sgl_icd_idx[16]; /* DWORD 2 */ 725 u8 exp_data_sn[32]; /* DWORD 3 */ 726 u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */ 727 u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */ 728 u8 cq_id[16]; /* DWORD 6 */ 729 u8 rsvd1[16]; /* DWORD 6 */ 730 u8 cmdsn_itt[32]; /* DWORD 7 */ 731 u8 sge0_addr_hi[32]; /* DWORD 8 */ 732 u8 sge0_addr_lo[32]; /* DWORD 9 */ 733 u8 sge0_offset[24]; /* DWORD 10 */ 734 u8 rsvd2[7]; /* DWORD 10 */ 735 u8 sge0_last; /* DWORD 10 */ 736 u8 sge0_len[17]; /* DWORD 11 */ 737 u8 rsvd3[7]; /* DWORD 11 */ 738 u8 diff_enbl; /* DWORD 11 */ 739 u8 u_run; /* DWORD 11 */ 740 u8 o_run; /* DWORD 11 */ 741 u8 invalid; /* DWORD 11 */ 742 u8 dsp; /* DWORD 11 */ 743 u8 dmsg; /* DWORD 11 */ 744 u8 rsvd4; /* DWORD 11 */ 745 u8 lt; /* DWORD 11 */ 746 u8 sge1_addr_hi[32]; /* DWORD 12 */ 747 u8 sge1_addr_lo[32]; /* DWORD 13 */ 748 u8 sge1_r2t_offset[24]; /* DWORD 14 */ 749 u8 rsvd5[7]; /* DWORD 14 */ 750 u8 sge1_last; /* DWORD 14 */ 751 u8 sge1_len[17]; /* DWORD 15 */ 752 u8 rsvd6[15]; /* DWORD 15 */ 753 } __packed; 754 755 756 struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid); 757 void 758 free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle); 759 760 void beiscsi_process_all_cqs(struct work_struct *work); 761 void beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn, 762 struct iscsi_task *task); 763 764 static inline bool beiscsi_error(struct beiscsi_hba *phba) 765 { 766 return phba->ue_detected || phba->fw_timeout; 767 } 768 769 struct pdu_nop_out { 770 u32 dw[12]; 771 }; 772 773 /** 774 * Pseudo amap definition in which each bit of the actual structure is defined 775 * as a byte: used to calculate offset/shift/mask of each field 776 */ 777 struct amap_pdu_nop_out { 778 u8 opcode[6]; /* opcode 0x00 */ 779 u8 i_bit; /* I Bit */ 780 u8 x_bit; /* reserved; should be 0 */ 781 u8 fp_bit_filler1[7]; 782 u8 f_bit; /* always 1 */ 783 u8 reserved1[16]; 784 u8 ahs_length[8]; /* no AHS */ 785 u8 data_len_hi[8]; 786 u8 data_len_lo[16]; /* DataSegmentLength */ 787 u8 lun[64]; 788 u8 itt[32]; /* initiator id for ping or 0xffffffff */ 789 u8 ttt[32]; /* target id for ping or 0xffffffff */ 790 u8 cmd_sn[32]; 791 u8 exp_stat_sn[32]; 792 u8 reserved5[128]; 793 }; 794 795 #define PDUBASE_OPCODE_MASK 0x0000003F 796 #define PDUBASE_DATALENHI_MASK 0x0000FF00 797 #define PDUBASE_DATALENLO_MASK 0xFFFF0000 798 799 struct pdu_base { 800 u32 dw[16]; 801 } __packed; 802 803 /** 804 * Pseudo amap definition in which each bit of the actual structure is defined 805 * as a byte: used to calculate offset/shift/mask of each field 806 */ 807 struct amap_pdu_base { 808 u8 opcode[6]; 809 u8 i_bit; /* immediate bit */ 810 u8 x_bit; /* reserved, always 0 */ 811 u8 reserved1[24]; /* opcode-specific fields */ 812 u8 ahs_length[8]; /* length units is 4 byte words */ 813 u8 data_len_hi[8]; 814 u8 data_len_lo[16]; /* DatasegmentLength */ 815 u8 lun[64]; /* lun or opcode-specific fields */ 816 u8 itt[32]; /* initiator task tag */ 817 u8 reserved4[224]; 818 }; 819 820 struct iscsi_target_context_update_wrb { 821 u32 dw[16]; 822 } __packed; 823 824 /** 825 * Pseudo amap definition in which each bit of the actual structure is defined 826 * as a byte: used to calculate offset/shift/mask of each field 827 */ 828 #define BE_TGT_CTX_UPDT_CMD 0x07 829 struct amap_iscsi_target_context_update_wrb { 830 u8 lun[14]; /* DWORD 0 */ 831 u8 lt; /* DWORD 0 */ 832 u8 invld; /* DWORD 0 */ 833 u8 wrb_idx[8]; /* DWORD 0 */ 834 u8 dsp; /* DWORD 0 */ 835 u8 dmsg; /* DWORD 0 */ 836 u8 undr_run; /* DWORD 0 */ 837 u8 over_run; /* DWORD 0 */ 838 u8 type[4]; /* DWORD 0 */ 839 u8 ptr2nextwrb[8]; /* DWORD 1 */ 840 u8 max_burst_length[19]; /* DWORD 1 */ 841 u8 rsvd0[5]; /* DWORD 1 */ 842 u8 rsvd1[15]; /* DWORD 2 */ 843 u8 max_send_data_segment_length[17]; /* DWORD 2 */ 844 u8 first_burst_length[14]; /* DWORD 3 */ 845 u8 rsvd2[2]; /* DWORD 3 */ 846 u8 tx_wrbindex_drv_msg[8]; /* DWORD 3 */ 847 u8 rsvd3[5]; /* DWORD 3 */ 848 u8 session_state[3]; /* DWORD 3 */ 849 u8 rsvd4[16]; /* DWORD 4 */ 850 u8 tx_jumbo; /* DWORD 4 */ 851 u8 hde; /* DWORD 4 */ 852 u8 dde; /* DWORD 4 */ 853 u8 erl[2]; /* DWORD 4 */ 854 u8 domain_id[5]; /* DWORD 4 */ 855 u8 mode; /* DWORD 4 */ 856 u8 imd; /* DWORD 4 */ 857 u8 ir2t; /* DWORD 4 */ 858 u8 notpredblq[2]; /* DWORD 4 */ 859 u8 compltonack; /* DWORD 4 */ 860 u8 stat_sn[32]; /* DWORD 5 */ 861 u8 pad_buffer_addr_hi[32]; /* DWORD 6 */ 862 u8 pad_buffer_addr_lo[32]; /* DWORD 7 */ 863 u8 pad_addr_hi[32]; /* DWORD 8 */ 864 u8 pad_addr_lo[32]; /* DWORD 9 */ 865 u8 rsvd5[32]; /* DWORD 10 */ 866 u8 rsvd6[32]; /* DWORD 11 */ 867 u8 rsvd7[32]; /* DWORD 12 */ 868 u8 rsvd8[32]; /* DWORD 13 */ 869 u8 rsvd9[32]; /* DWORD 14 */ 870 u8 rsvd10[32]; /* DWORD 15 */ 871 872 } __packed; 873 874 #define BEISCSI_MAX_RECV_DATASEG_LEN (64 * 1024) 875 #define BEISCSI_MAX_CXNS 1 876 struct amap_iscsi_target_context_update_wrb_v2 { 877 u8 max_burst_length[24]; /* DWORD 0 */ 878 u8 rsvd0[3]; /* DWORD 0 */ 879 u8 type[5]; /* DWORD 0 */ 880 u8 ptr2nextwrb[8]; /* DWORD 1 */ 881 u8 wrb_idx[8]; /* DWORD 1 */ 882 u8 rsvd1[16]; /* DWORD 1 */ 883 u8 max_send_data_segment_length[24]; /* DWORD 2 */ 884 u8 rsvd2[8]; /* DWORD 2 */ 885 u8 first_burst_length[24]; /* DWORD 3 */ 886 u8 rsvd3[8]; /* DOWRD 3 */ 887 u8 max_r2t[16]; /* DWORD 4 */ 888 u8 rsvd4[10]; /* DWORD 4 */ 889 u8 hde; /* DWORD 4 */ 890 u8 dde; /* DWORD 4 */ 891 u8 erl[2]; /* DWORD 4 */ 892 u8 imd; /* DWORD 4 */ 893 u8 ir2t; /* DWORD 4 */ 894 u8 stat_sn[32]; /* DWORD 5 */ 895 u8 rsvd5[32]; /* DWORD 6 */ 896 u8 rsvd6[32]; /* DWORD 7 */ 897 u8 max_recv_dataseg_len[24]; /* DWORD 8 */ 898 u8 rsvd7[8]; /* DWORD 8 */ 899 u8 rsvd8[32]; /* DWORD 9 */ 900 u8 rsvd9[32]; /* DWORD 10 */ 901 u8 max_cxns[16]; /* DWORD 11 */ 902 u8 rsvd10[11]; /* DWORD 11*/ 903 u8 invld; /* DWORD 11 */ 904 u8 rsvd11;/* DWORD 11*/ 905 u8 dmsg; /* DWORD 11 */ 906 u8 data_seq_inorder; /* DWORD 11 */ 907 u8 pdu_seq_inorder; /* DWORD 11 */ 908 u8 rsvd12[32]; /*DWORD 12 */ 909 u8 rsvd13[32]; /* DWORD 13 */ 910 u8 rsvd14[32]; /* DWORD 14 */ 911 u8 rsvd15[32]; /* DWORD 15 */ 912 } __packed; 913 914 915 struct be_ring { 916 u32 pages; /* queue size in pages */ 917 u32 id; /* queue id assigned by beklib */ 918 u32 num; /* number of elements in queue */ 919 u32 cidx; /* consumer index */ 920 u32 pidx; /* producer index -- not used by most rings */ 921 u32 item_size; /* size in bytes of one object */ 922 923 void *va; /* The virtual address of the ring. This 924 * should be last to allow 32 & 64 bit debugger 925 * extensions to work. 926 */ 927 }; 928 929 struct hwi_wrb_context { 930 struct list_head wrb_handle_list; 931 struct list_head wrb_handle_drvr_list; 932 struct wrb_handle **pwrb_handle_base; 933 struct wrb_handle **pwrb_handle_basestd; 934 struct iscsi_wrb *plast_wrb; 935 unsigned short alloc_index; 936 unsigned short free_index; 937 unsigned short wrb_handles_available; 938 unsigned short cid; 939 }; 940 941 struct hwi_controller { 942 struct list_head io_sgl_list; 943 struct list_head eh_sgl_list; 944 struct sgl_handle *psgl_handle_base; 945 unsigned int wrb_mem_index; 946 947 struct hwi_wrb_context *wrb_context; 948 struct mcc_wrb *pmcc_wrb_base; 949 struct be_ring default_pdu_hdr; 950 struct be_ring default_pdu_data; 951 struct hwi_context_memory *phwi_ctxt; 952 }; 953 954 enum hwh_type_enum { 955 HWH_TYPE_IO = 1, 956 HWH_TYPE_LOGOUT = 2, 957 HWH_TYPE_TMF = 3, 958 HWH_TYPE_NOP = 4, 959 HWH_TYPE_IO_RD = 5, 960 HWH_TYPE_LOGIN = 11, 961 HWH_TYPE_INVALID = 0xFFFFFFFF 962 }; 963 964 struct wrb_handle { 965 enum hwh_type_enum type; 966 unsigned short wrb_index; 967 unsigned short nxt_wrb_index; 968 969 struct iscsi_task *pio_handle; 970 struct iscsi_wrb *pwrb; 971 }; 972 973 struct hwi_context_memory { 974 /* Adaptive interrupt coalescing (AIC) info */ 975 u16 min_eqd; /* in usecs */ 976 u16 max_eqd; /* in usecs */ 977 u16 cur_eqd; /* in usecs */ 978 struct be_eq_obj be_eq[MAX_CPUS]; 979 struct be_queue_info be_cq[MAX_CPUS - 1]; 980 981 struct be_queue_info be_def_hdrq; 982 struct be_queue_info be_def_dataq; 983 984 struct be_queue_info *be_wrbq; 985 struct hwi_async_pdu_context *pasync_ctx; 986 }; 987 988 /* Logging related definitions */ 989 #define BEISCSI_LOG_INIT 0x0001 /* Initialization events */ 990 #define BEISCSI_LOG_MBOX 0x0002 /* Mailbox Events */ 991 #define BEISCSI_LOG_MISC 0x0004 /* Miscllaneous Events */ 992 #define BEISCSI_LOG_EH 0x0008 /* Error Handler */ 993 #define BEISCSI_LOG_IO 0x0010 /* IO Code Path */ 994 #define BEISCSI_LOG_CONFIG 0x0020 /* CONFIG Code Path */ 995 996 #define beiscsi_log(phba, level, mask, fmt, arg...) \ 997 do { \ 998 uint32_t log_value = phba->attr_log_enable; \ 999 if (((mask) & log_value) || (level[1] <= '3')) \ 1000 shost_printk(level, phba->shost, \ 1001 fmt, __LINE__, ##arg); \ 1002 } while (0) 1003 1004 #endif 1005