1 /** 2 * Copyright (C) 2005 - 2013 Emulex 3 * All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License version 2 7 * as published by the Free Software Foundation. The full GNU General 8 * Public License is included in this distribution in the file called COPYING. 9 * 10 * Contact Information: 11 * linux-drivers@emulex.com 12 * 13 * Emulex 14 * 3333 Susan Street 15 * Costa Mesa, CA 92626 16 */ 17 18 #include <scsi/iscsi_proto.h> 19 20 #include "be_main.h" 21 #include "be.h" 22 #include "be_mgmt.h" 23 24 int beiscsi_pci_soft_reset(struct beiscsi_hba *phba) 25 { 26 u32 sreset; 27 u8 *pci_reset_offset = 0; 28 u8 *pci_online0_offset = 0; 29 u8 *pci_online1_offset = 0; 30 u32 pconline0 = 0; 31 u32 pconline1 = 0; 32 u32 i; 33 34 pci_reset_offset = (u8 *)phba->pci_va + BE2_SOFT_RESET; 35 pci_online0_offset = (u8 *)phba->pci_va + BE2_PCI_ONLINE0; 36 pci_online1_offset = (u8 *)phba->pci_va + BE2_PCI_ONLINE1; 37 sreset = readl((void *)pci_reset_offset); 38 sreset |= BE2_SET_RESET; 39 writel(sreset, (void *)pci_reset_offset); 40 41 i = 0; 42 while (sreset & BE2_SET_RESET) { 43 if (i > 64) 44 break; 45 msleep(100); 46 sreset = readl((void *)pci_reset_offset); 47 i++; 48 } 49 50 if (sreset & BE2_SET_RESET) { 51 printk(KERN_ERR DRV_NAME 52 " Soft Reset did not deassert\n"); 53 return -EIO; 54 } 55 pconline1 = BE2_MPU_IRAM_ONLINE; 56 writel(pconline0, (void *)pci_online0_offset); 57 writel(pconline1, (void *)pci_online1_offset); 58 59 sreset |= BE2_SET_RESET; 60 writel(sreset, (void *)pci_reset_offset); 61 62 i = 0; 63 while (sreset & BE2_SET_RESET) { 64 if (i > 64) 65 break; 66 msleep(1); 67 sreset = readl((void *)pci_reset_offset); 68 i++; 69 } 70 if (sreset & BE2_SET_RESET) { 71 printk(KERN_ERR DRV_NAME 72 " MPU Online Soft Reset did not deassert\n"); 73 return -EIO; 74 } 75 return 0; 76 } 77 78 int be_chk_reset_complete(struct beiscsi_hba *phba) 79 { 80 unsigned int num_loop; 81 u8 *mpu_sem = 0; 82 u32 status; 83 84 num_loop = 1000; 85 mpu_sem = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE; 86 msleep(5000); 87 88 while (num_loop) { 89 status = readl((void *)mpu_sem); 90 91 if ((status & 0x80000000) || (status & 0x0000FFFF) == 0xC000) 92 break; 93 msleep(60); 94 num_loop--; 95 } 96 97 if ((status & 0x80000000) || (!num_loop)) { 98 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 99 "BC_%d : Failed in be_chk_reset_complete" 100 "status = 0x%x\n", status); 101 return -EIO; 102 } 103 104 return 0; 105 } 106 107 void be_mcc_notify(struct beiscsi_hba *phba) 108 { 109 struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q; 110 u32 val = 0; 111 112 val |= mccq->id & DB_MCCQ_RING_ID_MASK; 113 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT; 114 iowrite32(val, phba->db_va + DB_MCCQ_OFFSET); 115 } 116 117 unsigned int alloc_mcc_tag(struct beiscsi_hba *phba) 118 { 119 unsigned int tag = 0; 120 121 if (phba->ctrl.mcc_tag_available) { 122 tag = phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index]; 123 phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index] = 0; 124 phba->ctrl.mcc_numtag[tag] = 0; 125 } 126 if (tag) { 127 phba->ctrl.mcc_tag_available--; 128 if (phba->ctrl.mcc_alloc_index == (MAX_MCC_CMD - 1)) 129 phba->ctrl.mcc_alloc_index = 0; 130 else 131 phba->ctrl.mcc_alloc_index++; 132 } 133 return tag; 134 } 135 136 /* 137 * beiscsi_mccq_compl()- Wait for completion of MBX 138 * @phba: Driver private structure 139 * @tag: Tag for the MBX Command 140 * @wrb: the WRB used for the MBX Command 141 * @mbx_cmd_mem: ptr to memory allocated for MBX Cmd 142 * 143 * Waits for MBX completion with the passed TAG. 144 * 145 * return 146 * Success: 0 147 * Failure: Non-Zero 148 **/ 149 int beiscsi_mccq_compl(struct beiscsi_hba *phba, 150 uint32_t tag, struct be_mcc_wrb **wrb, 151 struct be_dma_mem *mbx_cmd_mem) 152 { 153 int rc = 0; 154 uint32_t mcc_tag_response; 155 uint16_t status = 0, addl_status = 0, wrb_num = 0; 156 struct be_mcc_wrb *temp_wrb; 157 struct be_cmd_req_hdr *mbx_hdr; 158 struct be_cmd_resp_hdr *mbx_resp_hdr; 159 struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q; 160 161 if (beiscsi_error(phba)) { 162 free_mcc_tag(&phba->ctrl, tag); 163 return -EPERM; 164 } 165 166 /* Set MBX Tag state to Active */ 167 spin_lock(&phba->ctrl.mbox_lock); 168 phba->ctrl.ptag_state[tag].tag_state = MCC_TAG_STATE_RUNNING; 169 spin_unlock(&phba->ctrl.mbox_lock); 170 171 /* wait for the mccq completion */ 172 rc = wait_event_interruptible_timeout( 173 phba->ctrl.mcc_wait[tag], 174 phba->ctrl.mcc_numtag[tag], 175 msecs_to_jiffies( 176 BEISCSI_HOST_MBX_TIMEOUT)); 177 178 if (rc <= 0) { 179 struct be_dma_mem *tag_mem; 180 /* Set MBX Tag state to timeout */ 181 spin_lock(&phba->ctrl.mbox_lock); 182 phba->ctrl.ptag_state[tag].tag_state = MCC_TAG_STATE_TIMEOUT; 183 spin_unlock(&phba->ctrl.mbox_lock); 184 185 /* Store resource addr to be freed later */ 186 tag_mem = &phba->ctrl.ptag_state[tag].tag_mem_state; 187 if (mbx_cmd_mem) { 188 tag_mem->size = mbx_cmd_mem->size; 189 tag_mem->va = mbx_cmd_mem->va; 190 tag_mem->dma = mbx_cmd_mem->dma; 191 } else 192 tag_mem->size = 0; 193 194 beiscsi_log(phba, KERN_ERR, 195 BEISCSI_LOG_INIT | BEISCSI_LOG_EH | 196 BEISCSI_LOG_CONFIG, 197 "BC_%d : MBX Cmd Completion timed out\n"); 198 return -EBUSY; 199 } else { 200 rc = 0; 201 /* Set MBX Tag state to completed */ 202 spin_lock(&phba->ctrl.mbox_lock); 203 phba->ctrl.ptag_state[tag].tag_state = MCC_TAG_STATE_COMPLETED; 204 spin_unlock(&phba->ctrl.mbox_lock); 205 } 206 207 mcc_tag_response = phba->ctrl.mcc_numtag[tag]; 208 status = (mcc_tag_response & CQE_STATUS_MASK); 209 addl_status = ((mcc_tag_response & CQE_STATUS_ADDL_MASK) >> 210 CQE_STATUS_ADDL_SHIFT); 211 212 if (mbx_cmd_mem) { 213 mbx_hdr = (struct be_cmd_req_hdr *)mbx_cmd_mem->va; 214 } else { 215 wrb_num = (mcc_tag_response & CQE_STATUS_WRB_MASK) >> 216 CQE_STATUS_WRB_SHIFT; 217 temp_wrb = (struct be_mcc_wrb *)queue_get_wrb(mccq, wrb_num); 218 mbx_hdr = embedded_payload(temp_wrb); 219 220 if (wrb) 221 *wrb = temp_wrb; 222 } 223 224 if (status || addl_status) { 225 beiscsi_log(phba, KERN_WARNING, 226 BEISCSI_LOG_INIT | BEISCSI_LOG_EH | 227 BEISCSI_LOG_CONFIG, 228 "BC_%d : MBX Cmd Failed for " 229 "Subsys : %d Opcode : %d with " 230 "Status : %d and Extd_Status : %d\n", 231 mbx_hdr->subsystem, 232 mbx_hdr->opcode, 233 status, addl_status); 234 235 if (status == MCC_STATUS_INSUFFICIENT_BUFFER) { 236 mbx_resp_hdr = (struct be_cmd_resp_hdr *) mbx_hdr; 237 beiscsi_log(phba, KERN_WARNING, 238 BEISCSI_LOG_INIT | BEISCSI_LOG_EH | 239 BEISCSI_LOG_CONFIG, 240 "BC_%d : Insufficent Buffer Error " 241 "Resp_Len : %d Actual_Resp_Len : %d\n", 242 mbx_resp_hdr->response_length, 243 mbx_resp_hdr->actual_resp_len); 244 245 rc = -EAGAIN; 246 goto release_mcc_tag; 247 } 248 rc = -EIO; 249 } 250 251 release_mcc_tag: 252 /* Release the MCC entry */ 253 free_mcc_tag(&phba->ctrl, tag); 254 255 return rc; 256 } 257 258 void free_mcc_tag(struct be_ctrl_info *ctrl, unsigned int tag) 259 { 260 spin_lock(&ctrl->mbox_lock); 261 tag = tag & 0x000000FF; 262 ctrl->mcc_tag[ctrl->mcc_free_index] = tag; 263 if (ctrl->mcc_free_index == (MAX_MCC_CMD - 1)) 264 ctrl->mcc_free_index = 0; 265 else 266 ctrl->mcc_free_index++; 267 ctrl->mcc_tag_available++; 268 spin_unlock(&ctrl->mbox_lock); 269 } 270 271 bool is_link_state_evt(u32 trailer) 272 { 273 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) & 274 ASYNC_TRAILER_EVENT_CODE_MASK) == 275 ASYNC_EVENT_CODE_LINK_STATE); 276 } 277 278 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl) 279 { 280 if (compl->flags != 0) { 281 compl->flags = le32_to_cpu(compl->flags); 282 WARN_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0); 283 return true; 284 } else 285 return false; 286 } 287 288 static inline void be_mcc_compl_use(struct be_mcc_compl *compl) 289 { 290 compl->flags = 0; 291 } 292 293 /* 294 * be_mcc_compl_process()- Check the MBX comapletion status 295 * @ctrl: Function specific MBX data structure 296 * @compl: Completion status of MBX Command 297 * 298 * Check for the MBX completion status when BMBX method used 299 * 300 * return 301 * Success: Zero 302 * Failure: Non-Zero 303 **/ 304 static int be_mcc_compl_process(struct be_ctrl_info *ctrl, 305 struct be_mcc_compl *compl) 306 { 307 u16 compl_status, extd_status; 308 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); 309 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); 310 struct be_cmd_req_hdr *hdr = embedded_payload(wrb); 311 struct be_cmd_resp_hdr *resp_hdr; 312 313 be_dws_le_to_cpu(compl, 4); 314 315 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) & 316 CQE_STATUS_COMPL_MASK; 317 if (compl_status != MCC_STATUS_SUCCESS) { 318 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) & 319 CQE_STATUS_EXTD_MASK; 320 321 beiscsi_log(phba, KERN_ERR, 322 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX, 323 "BC_%d : error in cmd completion: " 324 "Subsystem : %d Opcode : %d " 325 "status(compl/extd)=%d/%d\n", 326 hdr->subsystem, hdr->opcode, 327 compl_status, extd_status); 328 329 if (compl_status == MCC_STATUS_INSUFFICIENT_BUFFER) { 330 resp_hdr = (struct be_cmd_resp_hdr *) hdr; 331 if (resp_hdr->response_length) 332 return 0; 333 } 334 return -EBUSY; 335 } 336 return 0; 337 } 338 339 int be_mcc_compl_process_isr(struct be_ctrl_info *ctrl, 340 struct be_mcc_compl *compl) 341 { 342 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); 343 u16 compl_status, extd_status; 344 unsigned short tag; 345 346 be_dws_le_to_cpu(compl, 4); 347 348 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) & 349 CQE_STATUS_COMPL_MASK; 350 /* The ctrl.mcc_numtag[tag] is filled with 351 * [31] = valid, [30:24] = Rsvd, [23:16] = wrb, [15:8] = extd_status, 352 * [7:0] = compl_status 353 */ 354 tag = (compl->tag0 & 0x000000FF); 355 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) & 356 CQE_STATUS_EXTD_MASK; 357 358 ctrl->mcc_numtag[tag] = 0x80000000; 359 ctrl->mcc_numtag[tag] |= (compl->tag0 & 0x00FF0000); 360 ctrl->mcc_numtag[tag] |= (extd_status & 0x000000FF) << 8; 361 ctrl->mcc_numtag[tag] |= (compl_status & 0x000000FF); 362 363 if (ctrl->ptag_state[tag].tag_state == MCC_TAG_STATE_RUNNING) { 364 wake_up_interruptible(&ctrl->mcc_wait[tag]); 365 } else if (ctrl->ptag_state[tag].tag_state == MCC_TAG_STATE_TIMEOUT) { 366 struct be_dma_mem *tag_mem; 367 tag_mem = &ctrl->ptag_state[tag].tag_mem_state; 368 369 beiscsi_log(phba, KERN_WARNING, 370 BEISCSI_LOG_MBOX | BEISCSI_LOG_INIT | 371 BEISCSI_LOG_CONFIG, 372 "BC_%d : MBX Completion for timeout Command " 373 "from FW\n"); 374 /* Check if memory needs to be freed */ 375 if (tag_mem->size) 376 pci_free_consistent(ctrl->pdev, tag_mem->size, 377 tag_mem->va, tag_mem->dma); 378 379 /* Change tag state */ 380 spin_lock(&phba->ctrl.mbox_lock); 381 ctrl->ptag_state[tag].tag_state = MCC_TAG_STATE_COMPLETED; 382 spin_unlock(&phba->ctrl.mbox_lock); 383 384 /* Free MCC Tag */ 385 free_mcc_tag(ctrl, tag); 386 } 387 388 return 0; 389 } 390 391 static struct be_mcc_compl *be_mcc_compl_get(struct beiscsi_hba *phba) 392 { 393 struct be_queue_info *mcc_cq = &phba->ctrl.mcc_obj.cq; 394 struct be_mcc_compl *compl = queue_tail_node(mcc_cq); 395 396 if (be_mcc_compl_is_new(compl)) { 397 queue_tail_inc(mcc_cq); 398 return compl; 399 } 400 return NULL; 401 } 402 403 /** 404 * be2iscsi_fail_session(): Closing session with appropriate error 405 * @cls_session: ptr to session 406 * 407 * Depending on adapter state appropriate error flag is passed. 408 **/ 409 void be2iscsi_fail_session(struct iscsi_cls_session *cls_session) 410 { 411 struct Scsi_Host *shost = iscsi_session_to_shost(cls_session); 412 struct beiscsi_hba *phba = iscsi_host_priv(shost); 413 uint32_t iscsi_err_flag; 414 415 if (phba->state & BE_ADAPTER_STATE_SHUTDOWN) 416 iscsi_err_flag = ISCSI_ERR_INVALID_HOST; 417 else 418 iscsi_err_flag = ISCSI_ERR_CONN_FAILED; 419 420 iscsi_session_failure(cls_session->dd_data, ISCSI_ERR_CONN_FAILED); 421 } 422 423 void beiscsi_async_link_state_process(struct beiscsi_hba *phba, 424 struct be_async_event_link_state *evt) 425 { 426 if ((evt->port_link_status == ASYNC_EVENT_LINK_DOWN) || 427 ((evt->port_link_status & ASYNC_EVENT_LOGICAL) && 428 (evt->port_fault != BEISCSI_PHY_LINK_FAULT_NONE))) { 429 phba->state = BE_ADAPTER_LINK_DOWN; 430 431 beiscsi_log(phba, KERN_ERR, 432 BEISCSI_LOG_CONFIG | BEISCSI_LOG_INIT, 433 "BC_%d : Link Down on Port %d\n", 434 evt->physical_port); 435 436 iscsi_host_for_each_session(phba->shost, 437 be2iscsi_fail_session); 438 } else if ((evt->port_link_status & ASYNC_EVENT_LINK_UP) || 439 ((evt->port_link_status & ASYNC_EVENT_LOGICAL) && 440 (evt->port_fault == BEISCSI_PHY_LINK_FAULT_NONE))) { 441 phba->state = BE_ADAPTER_LINK_UP; 442 443 beiscsi_log(phba, KERN_ERR, 444 BEISCSI_LOG_CONFIG | BEISCSI_LOG_INIT, 445 "BC_%d : Link UP on Port %d\n", 446 evt->physical_port); 447 } 448 } 449 450 int beiscsi_process_mcc(struct beiscsi_hba *phba) 451 { 452 struct be_mcc_compl *compl; 453 int num = 0, status = 0; 454 struct be_ctrl_info *ctrl = &phba->ctrl; 455 456 spin_lock_bh(&phba->ctrl.mcc_cq_lock); 457 while ((compl = be_mcc_compl_get(phba))) { 458 if (compl->flags & CQE_FLAGS_ASYNC_MASK) { 459 /* Interpret flags as an async trailer */ 460 if (is_link_state_evt(compl->flags)) 461 /* Interpret compl as a async link evt */ 462 beiscsi_async_link_state_process(phba, 463 (struct be_async_event_link_state *) compl); 464 else 465 beiscsi_log(phba, KERN_ERR, 466 BEISCSI_LOG_CONFIG | 467 BEISCSI_LOG_MBOX, 468 "BC_%d : Unsupported Async Event, flags" 469 " = 0x%08x\n", compl->flags); 470 471 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) { 472 status = be_mcc_compl_process(ctrl, compl); 473 atomic_dec(&phba->ctrl.mcc_obj.q.used); 474 } 475 be_mcc_compl_use(compl); 476 num++; 477 } 478 479 if (num) 480 hwi_ring_cq_db(phba, phba->ctrl.mcc_obj.cq.id, num, 1, 0); 481 482 spin_unlock_bh(&phba->ctrl.mcc_cq_lock); 483 return status; 484 } 485 486 /* 487 * be_mcc_wait_compl()- Wait for MBX completion 488 * @phba: driver private structure 489 * 490 * Wait till no more pending mcc requests are present 491 * 492 * return 493 * Success: 0 494 * Failure: Non-Zero 495 * 496 **/ 497 static int be_mcc_wait_compl(struct beiscsi_hba *phba) 498 { 499 int i, status; 500 for (i = 0; i < mcc_timeout; i++) { 501 if (beiscsi_error(phba)) 502 return -EIO; 503 504 status = beiscsi_process_mcc(phba); 505 if (status) 506 return status; 507 508 if (atomic_read(&phba->ctrl.mcc_obj.q.used) == 0) 509 break; 510 udelay(100); 511 } 512 if (i == mcc_timeout) { 513 beiscsi_log(phba, KERN_ERR, 514 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX, 515 "BC_%d : FW Timed Out\n"); 516 phba->fw_timeout = true; 517 beiscsi_ue_detect(phba); 518 return -EBUSY; 519 } 520 return 0; 521 } 522 523 /* 524 * be_mcc_notify_wait()- Notify and wait for Compl 525 * @phba: driver private structure 526 * 527 * Notify MCC requests and wait for completion 528 * 529 * return 530 * Success: 0 531 * Failure: Non-Zero 532 **/ 533 int be_mcc_notify_wait(struct beiscsi_hba *phba) 534 { 535 be_mcc_notify(phba); 536 return be_mcc_wait_compl(phba); 537 } 538 539 /* 540 * be_mbox_db_ready_wait()- Check ready status 541 * @ctrl: Function specific MBX data structure 542 * 543 * Check for the ready status of FW to send BMBX 544 * commands to adapter. 545 * 546 * return 547 * Success: 0 548 * Failure: Non-Zero 549 **/ 550 static int be_mbox_db_ready_wait(struct be_ctrl_info *ctrl) 551 { 552 #define BEISCSI_MBX_RDY_BIT_TIMEOUT 4000 /* 4sec */ 553 void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET; 554 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); 555 unsigned long timeout; 556 bool read_flag = false; 557 int ret = 0, i; 558 u32 ready; 559 DECLARE_WAIT_QUEUE_HEAD_ONSTACK(rdybit_check_q); 560 561 if (beiscsi_error(phba)) 562 return -EIO; 563 564 timeout = jiffies + (HZ * 110); 565 566 do { 567 for (i = 0; i < BEISCSI_MBX_RDY_BIT_TIMEOUT; i++) { 568 ready = ioread32(db) & MPU_MAILBOX_DB_RDY_MASK; 569 if (ready) { 570 read_flag = true; 571 break; 572 } 573 mdelay(1); 574 } 575 576 if (!read_flag) { 577 wait_event_timeout(rdybit_check_q, 578 (read_flag != true), 579 HZ * 5); 580 } 581 } while ((time_before(jiffies, timeout)) && !read_flag); 582 583 if (!read_flag) { 584 beiscsi_log(phba, KERN_ERR, 585 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX, 586 "BC_%d : FW Timed Out\n"); 587 phba->fw_timeout = true; 588 beiscsi_ue_detect(phba); 589 ret = -EBUSY; 590 } 591 592 return ret; 593 } 594 595 /* 596 * be_mbox_notify: Notify adapter of new BMBX command 597 * @ctrl: Function specific MBX data structure 598 * 599 * Ring doorbell to inform adapter of a BMBX command 600 * to process 601 * 602 * return 603 * Success: 0 604 * Failure: Non-Zero 605 **/ 606 int be_mbox_notify(struct be_ctrl_info *ctrl) 607 { 608 int status; 609 u32 val = 0; 610 void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET; 611 struct be_dma_mem *mbox_mem = &ctrl->mbox_mem; 612 struct be_mcc_mailbox *mbox = mbox_mem->va; 613 struct be_mcc_compl *compl = &mbox->compl; 614 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); 615 616 status = be_mbox_db_ready_wait(ctrl); 617 if (status) 618 return status; 619 620 val &= ~MPU_MAILBOX_DB_RDY_MASK; 621 val |= MPU_MAILBOX_DB_HI_MASK; 622 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2; 623 iowrite32(val, db); 624 625 status = be_mbox_db_ready_wait(ctrl); 626 if (status) 627 return status; 628 629 val = 0; 630 val &= ~MPU_MAILBOX_DB_RDY_MASK; 631 val &= ~MPU_MAILBOX_DB_HI_MASK; 632 val |= (u32) (mbox_mem->dma >> 4) << 2; 633 iowrite32(val, db); 634 635 status = be_mbox_db_ready_wait(ctrl); 636 if (status) 637 return status; 638 639 if (be_mcc_compl_is_new(compl)) { 640 status = be_mcc_compl_process(ctrl, &mbox->compl); 641 be_mcc_compl_use(compl); 642 if (status) { 643 beiscsi_log(phba, KERN_ERR, 644 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX, 645 "BC_%d : After be_mcc_compl_process\n"); 646 647 return status; 648 } 649 } else { 650 beiscsi_log(phba, KERN_ERR, 651 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX, 652 "BC_%d : Invalid Mailbox Completion\n"); 653 654 return -EBUSY; 655 } 656 return 0; 657 } 658 659 /* 660 * Insert the mailbox address into the doorbell in two steps 661 * Polls on the mbox doorbell till a command completion (or a timeout) occurs 662 */ 663 static int be_mbox_notify_wait(struct beiscsi_hba *phba) 664 { 665 int status; 666 u32 val = 0; 667 void __iomem *db = phba->ctrl.db + MPU_MAILBOX_DB_OFFSET; 668 struct be_dma_mem *mbox_mem = &phba->ctrl.mbox_mem; 669 struct be_mcc_mailbox *mbox = mbox_mem->va; 670 struct be_mcc_compl *compl = &mbox->compl; 671 struct be_ctrl_info *ctrl = &phba->ctrl; 672 673 status = be_mbox_db_ready_wait(ctrl); 674 if (status) 675 return status; 676 677 val |= MPU_MAILBOX_DB_HI_MASK; 678 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */ 679 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2; 680 iowrite32(val, db); 681 682 /* wait for ready to be set */ 683 status = be_mbox_db_ready_wait(ctrl); 684 if (status != 0) 685 return status; 686 687 val = 0; 688 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */ 689 val |= (u32)(mbox_mem->dma >> 4) << 2; 690 iowrite32(val, db); 691 692 status = be_mbox_db_ready_wait(ctrl); 693 if (status != 0) 694 return status; 695 696 /* A cq entry has been made now */ 697 if (be_mcc_compl_is_new(compl)) { 698 status = be_mcc_compl_process(ctrl, &mbox->compl); 699 be_mcc_compl_use(compl); 700 if (status) 701 return status; 702 } else { 703 beiscsi_log(phba, KERN_ERR, 704 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX, 705 "BC_%d : invalid mailbox completion\n"); 706 707 return -EBUSY; 708 } 709 return 0; 710 } 711 712 void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len, 713 bool embedded, u8 sge_cnt) 714 { 715 if (embedded) 716 wrb->embedded |= MCC_WRB_EMBEDDED_MASK; 717 else 718 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) << 719 MCC_WRB_SGE_CNT_SHIFT; 720 wrb->payload_length = payload_len; 721 be_dws_cpu_to_le(wrb, 8); 722 } 723 724 void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr, 725 u8 subsystem, u8 opcode, int cmd_len) 726 { 727 req_hdr->opcode = opcode; 728 req_hdr->subsystem = subsystem; 729 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr)); 730 req_hdr->timeout = BEISCSI_FW_MBX_TIMEOUT; 731 } 732 733 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages, 734 struct be_dma_mem *mem) 735 { 736 int i, buf_pages; 737 u64 dma = (u64) mem->dma; 738 739 buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages); 740 for (i = 0; i < buf_pages; i++) { 741 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF); 742 pages[i].hi = cpu_to_le32(upper_32_bits(dma)); 743 dma += PAGE_SIZE_4K; 744 } 745 } 746 747 static u32 eq_delay_to_mult(u32 usec_delay) 748 { 749 #define MAX_INTR_RATE 651042 750 const u32 round = 10; 751 u32 multiplier; 752 753 if (usec_delay == 0) 754 multiplier = 0; 755 else { 756 u32 interrupt_rate = 1000000 / usec_delay; 757 if (interrupt_rate == 0) 758 multiplier = 1023; 759 else { 760 multiplier = (MAX_INTR_RATE - interrupt_rate) * round; 761 multiplier /= interrupt_rate; 762 multiplier = (multiplier + round / 2) / round; 763 multiplier = min(multiplier, (u32) 1023); 764 } 765 } 766 return multiplier; 767 } 768 769 struct be_mcc_wrb *wrb_from_mbox(struct be_dma_mem *mbox_mem) 770 { 771 return &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb; 772 } 773 774 struct be_mcc_wrb *wrb_from_mccq(struct beiscsi_hba *phba) 775 { 776 struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q; 777 struct be_mcc_wrb *wrb; 778 779 WARN_ON(atomic_read(&mccq->used) >= mccq->len); 780 wrb = queue_head_node(mccq); 781 memset(wrb, 0, sizeof(*wrb)); 782 wrb->tag0 = (mccq->head & 0x000000FF) << 16; 783 queue_head_inc(mccq); 784 atomic_inc(&mccq->used); 785 return wrb; 786 } 787 788 789 int beiscsi_cmd_eq_create(struct be_ctrl_info *ctrl, 790 struct be_queue_info *eq, int eq_delay) 791 { 792 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); 793 struct be_cmd_req_eq_create *req = embedded_payload(wrb); 794 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb); 795 struct be_dma_mem *q_mem = &eq->dma_mem; 796 int status; 797 798 spin_lock(&ctrl->mbox_lock); 799 memset(wrb, 0, sizeof(*wrb)); 800 801 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 802 803 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 804 OPCODE_COMMON_EQ_CREATE, sizeof(*req)); 805 806 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); 807 808 AMAP_SET_BITS(struct amap_eq_context, func, req->context, 809 PCI_FUNC(ctrl->pdev->devfn)); 810 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1); 811 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0); 812 AMAP_SET_BITS(struct amap_eq_context, count, req->context, 813 __ilog2_u32(eq->len / 256)); 814 AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context, 815 eq_delay_to_mult(eq_delay)); 816 be_dws_cpu_to_le(req->context, sizeof(req->context)); 817 818 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 819 820 status = be_mbox_notify(ctrl); 821 if (!status) { 822 eq->id = le16_to_cpu(resp->eq_id); 823 eq->created = true; 824 } 825 spin_unlock(&ctrl->mbox_lock); 826 return status; 827 } 828 829 /** 830 * be_cmd_fw_initialize()- Initialize FW 831 * @ctrl: Pointer to function control structure 832 * 833 * Send FW initialize pattern for the function. 834 * 835 * return 836 * Success: 0 837 * Failure: Non-Zero value 838 **/ 839 int be_cmd_fw_initialize(struct be_ctrl_info *ctrl) 840 { 841 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); 842 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); 843 int status; 844 u8 *endian_check; 845 846 spin_lock(&ctrl->mbox_lock); 847 memset(wrb, 0, sizeof(*wrb)); 848 849 endian_check = (u8 *) wrb; 850 *endian_check++ = 0xFF; 851 *endian_check++ = 0x12; 852 *endian_check++ = 0x34; 853 *endian_check++ = 0xFF; 854 *endian_check++ = 0xFF; 855 *endian_check++ = 0x56; 856 *endian_check++ = 0x78; 857 *endian_check++ = 0xFF; 858 be_dws_cpu_to_le(wrb, sizeof(*wrb)); 859 860 status = be_mbox_notify(ctrl); 861 if (status) 862 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 863 "BC_%d : be_cmd_fw_initialize Failed\n"); 864 865 spin_unlock(&ctrl->mbox_lock); 866 return status; 867 } 868 869 /** 870 * be_cmd_fw_uninit()- Uinitialize FW 871 * @ctrl: Pointer to function control structure 872 * 873 * Send FW uninitialize pattern for the function 874 * 875 * return 876 * Success: 0 877 * Failure: Non-Zero value 878 **/ 879 int be_cmd_fw_uninit(struct be_ctrl_info *ctrl) 880 { 881 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); 882 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); 883 int status; 884 u8 *endian_check; 885 886 spin_lock(&ctrl->mbox_lock); 887 memset(wrb, 0, sizeof(*wrb)); 888 889 endian_check = (u8 *) wrb; 890 *endian_check++ = 0xFF; 891 *endian_check++ = 0xAA; 892 *endian_check++ = 0xBB; 893 *endian_check++ = 0xFF; 894 *endian_check++ = 0xFF; 895 *endian_check++ = 0xCC; 896 *endian_check++ = 0xDD; 897 *endian_check = 0xFF; 898 899 be_dws_cpu_to_le(wrb, sizeof(*wrb)); 900 901 status = be_mbox_notify(ctrl); 902 if (status) 903 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 904 "BC_%d : be_cmd_fw_uninit Failed\n"); 905 906 spin_unlock(&ctrl->mbox_lock); 907 return status; 908 } 909 910 int beiscsi_cmd_cq_create(struct be_ctrl_info *ctrl, 911 struct be_queue_info *cq, struct be_queue_info *eq, 912 bool sol_evts, bool no_delay, int coalesce_wm) 913 { 914 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); 915 struct be_cmd_req_cq_create *req = embedded_payload(wrb); 916 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb); 917 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); 918 struct be_dma_mem *q_mem = &cq->dma_mem; 919 void *ctxt = &req->context; 920 int status; 921 922 spin_lock(&ctrl->mbox_lock); 923 memset(wrb, 0, sizeof(*wrb)); 924 925 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 926 927 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 928 OPCODE_COMMON_CQ_CREATE, sizeof(*req)); 929 930 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); 931 if (is_chip_be2_be3r(phba)) { 932 AMAP_SET_BITS(struct amap_cq_context, coalescwm, 933 ctxt, coalesce_wm); 934 AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay); 935 AMAP_SET_BITS(struct amap_cq_context, count, ctxt, 936 __ilog2_u32(cq->len / 256)); 937 AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1); 938 AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts); 939 AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1); 940 AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id); 941 AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1); 942 AMAP_SET_BITS(struct amap_cq_context, func, ctxt, 943 PCI_FUNC(ctrl->pdev->devfn)); 944 } else { 945 req->hdr.version = MBX_CMD_VER2; 946 req->page_size = 1; 947 AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm, 948 ctxt, coalesce_wm); 949 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, 950 ctxt, no_delay); 951 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt, 952 __ilog2_u32(cq->len / 256)); 953 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1); 954 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1); 955 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id); 956 AMAP_SET_BITS(struct amap_cq_context_v2, armed, ctxt, 1); 957 } 958 959 be_dws_cpu_to_le(ctxt, sizeof(req->context)); 960 961 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 962 963 status = be_mbox_notify(ctrl); 964 if (!status) { 965 cq->id = le16_to_cpu(resp->cq_id); 966 cq->created = true; 967 } else 968 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 969 "BC_%d : In be_cmd_cq_create, status=ox%08x\n", 970 status); 971 972 spin_unlock(&ctrl->mbox_lock); 973 974 return status; 975 } 976 977 static u32 be_encoded_q_len(int q_len) 978 { 979 u32 len_encoded = fls(q_len); /* log2(len) + 1 */ 980 if (len_encoded == 16) 981 len_encoded = 0; 982 return len_encoded; 983 } 984 985 int beiscsi_cmd_mccq_create(struct beiscsi_hba *phba, 986 struct be_queue_info *mccq, 987 struct be_queue_info *cq) 988 { 989 struct be_mcc_wrb *wrb; 990 struct be_cmd_req_mcc_create *req; 991 struct be_dma_mem *q_mem = &mccq->dma_mem; 992 struct be_ctrl_info *ctrl; 993 void *ctxt; 994 int status; 995 996 spin_lock(&phba->ctrl.mbox_lock); 997 ctrl = &phba->ctrl; 998 wrb = wrb_from_mbox(&ctrl->mbox_mem); 999 memset(wrb, 0, sizeof(*wrb)); 1000 req = embedded_payload(wrb); 1001 ctxt = &req->context; 1002 1003 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 1004 1005 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1006 OPCODE_COMMON_MCC_CREATE, sizeof(*req)); 1007 1008 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size); 1009 1010 AMAP_SET_BITS(struct amap_mcc_context, fid, ctxt, 1011 PCI_FUNC(phba->pcidev->devfn)); 1012 AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1); 1013 AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt, 1014 be_encoded_q_len(mccq->len)); 1015 AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id); 1016 1017 be_dws_cpu_to_le(ctxt, sizeof(req->context)); 1018 1019 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 1020 1021 status = be_mbox_notify_wait(phba); 1022 if (!status) { 1023 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb); 1024 mccq->id = le16_to_cpu(resp->id); 1025 mccq->created = true; 1026 } 1027 spin_unlock(&phba->ctrl.mbox_lock); 1028 1029 return status; 1030 } 1031 1032 int beiscsi_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q, 1033 int queue_type) 1034 { 1035 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); 1036 struct be_cmd_req_q_destroy *req = embedded_payload(wrb); 1037 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); 1038 u8 subsys = 0, opcode = 0; 1039 int status; 1040 1041 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 1042 "BC_%d : In beiscsi_cmd_q_destroy " 1043 "queue_type : %d\n", queue_type); 1044 1045 spin_lock(&ctrl->mbox_lock); 1046 memset(wrb, 0, sizeof(*wrb)); 1047 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 1048 1049 switch (queue_type) { 1050 case QTYPE_EQ: 1051 subsys = CMD_SUBSYSTEM_COMMON; 1052 opcode = OPCODE_COMMON_EQ_DESTROY; 1053 break; 1054 case QTYPE_CQ: 1055 subsys = CMD_SUBSYSTEM_COMMON; 1056 opcode = OPCODE_COMMON_CQ_DESTROY; 1057 break; 1058 case QTYPE_MCCQ: 1059 subsys = CMD_SUBSYSTEM_COMMON; 1060 opcode = OPCODE_COMMON_MCC_DESTROY; 1061 break; 1062 case QTYPE_WRBQ: 1063 subsys = CMD_SUBSYSTEM_ISCSI; 1064 opcode = OPCODE_COMMON_ISCSI_WRBQ_DESTROY; 1065 break; 1066 case QTYPE_DPDUQ: 1067 subsys = CMD_SUBSYSTEM_ISCSI; 1068 opcode = OPCODE_COMMON_ISCSI_DEFQ_DESTROY; 1069 break; 1070 case QTYPE_SGL: 1071 subsys = CMD_SUBSYSTEM_ISCSI; 1072 opcode = OPCODE_COMMON_ISCSI_CFG_REMOVE_SGL_PAGES; 1073 break; 1074 default: 1075 spin_unlock(&ctrl->mbox_lock); 1076 BUG(); 1077 return -ENXIO; 1078 } 1079 be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req)); 1080 if (queue_type != QTYPE_SGL) 1081 req->id = cpu_to_le16(q->id); 1082 1083 status = be_mbox_notify(ctrl); 1084 1085 spin_unlock(&ctrl->mbox_lock); 1086 return status; 1087 } 1088 1089 /** 1090 * be_cmd_create_default_pdu_queue()- Create DEFQ for the adapter 1091 * @ctrl: ptr to ctrl_info 1092 * @cq: Completion Queue 1093 * @dq: Default Queue 1094 * @lenght: ring size 1095 * @entry_size: size of each entry in DEFQ 1096 * @is_header: Header or Data DEFQ 1097 * @ulp_num: Bind to which ULP 1098 * 1099 * Create HDR/Data DEFQ for the passed ULP. Unsol PDU are posted 1100 * on this queue by the FW 1101 * 1102 * return 1103 * Success: 0 1104 * Failure: Non-Zero Value 1105 * 1106 **/ 1107 int be_cmd_create_default_pdu_queue(struct be_ctrl_info *ctrl, 1108 struct be_queue_info *cq, 1109 struct be_queue_info *dq, int length, 1110 int entry_size, uint8_t is_header, 1111 uint8_t ulp_num) 1112 { 1113 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); 1114 struct be_defq_create_req *req = embedded_payload(wrb); 1115 struct be_dma_mem *q_mem = &dq->dma_mem; 1116 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); 1117 void *ctxt = &req->context; 1118 int status; 1119 1120 spin_lock(&ctrl->mbox_lock); 1121 memset(wrb, 0, sizeof(*wrb)); 1122 1123 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 1124 1125 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI, 1126 OPCODE_COMMON_ISCSI_DEFQ_CREATE, sizeof(*req)); 1127 1128 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size); 1129 if (phba->fw_config.dual_ulp_aware) { 1130 req->ulp_num = ulp_num; 1131 req->dua_feature |= (1 << BEISCSI_DUAL_ULP_AWARE_BIT); 1132 req->dua_feature |= (1 << BEISCSI_BIND_Q_TO_ULP_BIT); 1133 } 1134 1135 if (is_chip_be2_be3r(phba)) { 1136 AMAP_SET_BITS(struct amap_be_default_pdu_context, 1137 rx_pdid, ctxt, 0); 1138 AMAP_SET_BITS(struct amap_be_default_pdu_context, 1139 rx_pdid_valid, ctxt, 1); 1140 AMAP_SET_BITS(struct amap_be_default_pdu_context, 1141 pci_func_id, ctxt, PCI_FUNC(ctrl->pdev->devfn)); 1142 AMAP_SET_BITS(struct amap_be_default_pdu_context, 1143 ring_size, ctxt, 1144 be_encoded_q_len(length / 1145 sizeof(struct phys_addr))); 1146 AMAP_SET_BITS(struct amap_be_default_pdu_context, 1147 default_buffer_size, ctxt, entry_size); 1148 AMAP_SET_BITS(struct amap_be_default_pdu_context, 1149 cq_id_recv, ctxt, cq->id); 1150 } else { 1151 AMAP_SET_BITS(struct amap_default_pdu_context_ext, 1152 rx_pdid, ctxt, 0); 1153 AMAP_SET_BITS(struct amap_default_pdu_context_ext, 1154 rx_pdid_valid, ctxt, 1); 1155 AMAP_SET_BITS(struct amap_default_pdu_context_ext, 1156 ring_size, ctxt, 1157 be_encoded_q_len(length / 1158 sizeof(struct phys_addr))); 1159 AMAP_SET_BITS(struct amap_default_pdu_context_ext, 1160 default_buffer_size, ctxt, entry_size); 1161 AMAP_SET_BITS(struct amap_default_pdu_context_ext, 1162 cq_id_recv, ctxt, cq->id); 1163 } 1164 1165 be_dws_cpu_to_le(ctxt, sizeof(req->context)); 1166 1167 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 1168 1169 status = be_mbox_notify(ctrl); 1170 if (!status) { 1171 struct be_ring *defq_ring; 1172 struct be_defq_create_resp *resp = embedded_payload(wrb); 1173 1174 dq->id = le16_to_cpu(resp->id); 1175 dq->created = true; 1176 if (is_header) 1177 defq_ring = &phba->phwi_ctrlr->default_pdu_hdr[ulp_num]; 1178 else 1179 defq_ring = &phba->phwi_ctrlr-> 1180 default_pdu_data[ulp_num]; 1181 1182 defq_ring->id = dq->id; 1183 1184 if (!phba->fw_config.dual_ulp_aware) { 1185 defq_ring->ulp_num = BEISCSI_ULP0; 1186 defq_ring->doorbell_offset = DB_RXULP0_OFFSET; 1187 } else { 1188 defq_ring->ulp_num = resp->ulp_num; 1189 defq_ring->doorbell_offset = resp->doorbell_offset; 1190 } 1191 } 1192 spin_unlock(&ctrl->mbox_lock); 1193 1194 return status; 1195 } 1196 1197 /** 1198 * be_cmd_wrbq_create()- Create WRBQ 1199 * @ctrl: ptr to ctrl_info 1200 * @q_mem: memory details for the queue 1201 * @wrbq: queue info 1202 * @pwrb_context: ptr to wrb_context 1203 * @ulp_num: ULP on which the WRBQ is to be created 1204 * 1205 * Create WRBQ on the passed ULP_NUM. 1206 * 1207 **/ 1208 int be_cmd_wrbq_create(struct be_ctrl_info *ctrl, 1209 struct be_dma_mem *q_mem, 1210 struct be_queue_info *wrbq, 1211 struct hwi_wrb_context *pwrb_context, 1212 uint8_t ulp_num) 1213 { 1214 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); 1215 struct be_wrbq_create_req *req = embedded_payload(wrb); 1216 struct be_wrbq_create_resp *resp = embedded_payload(wrb); 1217 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); 1218 int status; 1219 1220 spin_lock(&ctrl->mbox_lock); 1221 memset(wrb, 0, sizeof(*wrb)); 1222 1223 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 1224 1225 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI, 1226 OPCODE_COMMON_ISCSI_WRBQ_CREATE, sizeof(*req)); 1227 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size); 1228 1229 if (phba->fw_config.dual_ulp_aware) { 1230 req->ulp_num = ulp_num; 1231 req->dua_feature |= (1 << BEISCSI_DUAL_ULP_AWARE_BIT); 1232 req->dua_feature |= (1 << BEISCSI_BIND_Q_TO_ULP_BIT); 1233 } 1234 1235 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 1236 1237 status = be_mbox_notify(ctrl); 1238 if (!status) { 1239 wrbq->id = le16_to_cpu(resp->cid); 1240 wrbq->created = true; 1241 1242 pwrb_context->cid = wrbq->id; 1243 if (!phba->fw_config.dual_ulp_aware) { 1244 pwrb_context->doorbell_offset = DB_TXULP0_OFFSET; 1245 pwrb_context->ulp_num = BEISCSI_ULP0; 1246 } else { 1247 pwrb_context->ulp_num = resp->ulp_num; 1248 pwrb_context->doorbell_offset = resp->doorbell_offset; 1249 } 1250 } 1251 spin_unlock(&ctrl->mbox_lock); 1252 return status; 1253 } 1254 1255 int be_cmd_iscsi_post_template_hdr(struct be_ctrl_info *ctrl, 1256 struct be_dma_mem *q_mem) 1257 { 1258 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); 1259 struct be_post_template_pages_req *req = embedded_payload(wrb); 1260 int status; 1261 1262 spin_lock(&ctrl->mbox_lock); 1263 1264 memset(wrb, 0, sizeof(*wrb)); 1265 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 1266 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1267 OPCODE_COMMON_ADD_TEMPLATE_HEADER_BUFFERS, 1268 sizeof(*req)); 1269 1270 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size); 1271 req->type = BEISCSI_TEMPLATE_HDR_TYPE_ISCSI; 1272 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 1273 1274 status = be_mbox_notify(ctrl); 1275 spin_unlock(&ctrl->mbox_lock); 1276 return status; 1277 } 1278 1279 int be_cmd_iscsi_remove_template_hdr(struct be_ctrl_info *ctrl) 1280 { 1281 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); 1282 struct be_remove_template_pages_req *req = embedded_payload(wrb); 1283 int status; 1284 1285 spin_lock(&ctrl->mbox_lock); 1286 1287 memset(wrb, 0, sizeof(*wrb)); 1288 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 1289 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1290 OPCODE_COMMON_REMOVE_TEMPLATE_HEADER_BUFFERS, 1291 sizeof(*req)); 1292 1293 req->type = BEISCSI_TEMPLATE_HDR_TYPE_ISCSI; 1294 1295 status = be_mbox_notify(ctrl); 1296 spin_unlock(&ctrl->mbox_lock); 1297 return status; 1298 } 1299 1300 int be_cmd_iscsi_post_sgl_pages(struct be_ctrl_info *ctrl, 1301 struct be_dma_mem *q_mem, 1302 u32 page_offset, u32 num_pages) 1303 { 1304 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); 1305 struct be_post_sgl_pages_req *req = embedded_payload(wrb); 1306 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); 1307 int status; 1308 unsigned int curr_pages; 1309 u32 internal_page_offset = 0; 1310 u32 temp_num_pages = num_pages; 1311 1312 if (num_pages == 0xff) 1313 num_pages = 1; 1314 1315 spin_lock(&ctrl->mbox_lock); 1316 do { 1317 memset(wrb, 0, sizeof(*wrb)); 1318 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 1319 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI, 1320 OPCODE_COMMON_ISCSI_CFG_POST_SGL_PAGES, 1321 sizeof(*req)); 1322 curr_pages = BE_NUMBER_OF_FIELD(struct be_post_sgl_pages_req, 1323 pages); 1324 req->num_pages = min(num_pages, curr_pages); 1325 req->page_offset = page_offset; 1326 be_cmd_page_addrs_prepare(req->pages, req->num_pages, q_mem); 1327 q_mem->dma = q_mem->dma + (req->num_pages * PAGE_SIZE); 1328 internal_page_offset += req->num_pages; 1329 page_offset += req->num_pages; 1330 num_pages -= req->num_pages; 1331 1332 if (temp_num_pages == 0xff) 1333 req->num_pages = temp_num_pages; 1334 1335 status = be_mbox_notify(ctrl); 1336 if (status) { 1337 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 1338 "BC_%d : FW CMD to map iscsi frags failed.\n"); 1339 1340 goto error; 1341 } 1342 } while (num_pages > 0); 1343 error: 1344 spin_unlock(&ctrl->mbox_lock); 1345 if (status != 0) 1346 beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL); 1347 return status; 1348 } 1349 1350 int beiscsi_cmd_reset_function(struct beiscsi_hba *phba) 1351 { 1352 struct be_ctrl_info *ctrl = &phba->ctrl; 1353 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); 1354 struct be_post_sgl_pages_req *req = embedded_payload(wrb); 1355 int status; 1356 1357 spin_lock(&ctrl->mbox_lock); 1358 1359 req = embedded_payload(wrb); 1360 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 1361 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1362 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req)); 1363 status = be_mbox_notify_wait(phba); 1364 1365 spin_unlock(&ctrl->mbox_lock); 1366 return status; 1367 } 1368 1369 /** 1370 * be_cmd_set_vlan()- Configure VLAN paramters on the adapter 1371 * @phba: device priv structure instance 1372 * @vlan_tag: TAG to be set 1373 * 1374 * Set the VLAN_TAG for the adapter or Disable VLAN on adapter 1375 * 1376 * returns 1377 * TAG for the MBX Cmd 1378 * **/ 1379 int be_cmd_set_vlan(struct beiscsi_hba *phba, 1380 uint16_t vlan_tag) 1381 { 1382 unsigned int tag = 0; 1383 struct be_mcc_wrb *wrb; 1384 struct be_cmd_set_vlan_req *req; 1385 struct be_ctrl_info *ctrl = &phba->ctrl; 1386 1387 spin_lock(&ctrl->mbox_lock); 1388 tag = alloc_mcc_tag(phba); 1389 if (!tag) { 1390 spin_unlock(&ctrl->mbox_lock); 1391 return tag; 1392 } 1393 1394 wrb = wrb_from_mccq(phba); 1395 req = embedded_payload(wrb); 1396 wrb->tag0 |= tag; 1397 be_wrb_hdr_prepare(wrb, sizeof(*wrb), true, 0); 1398 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI, 1399 OPCODE_COMMON_ISCSI_NTWK_SET_VLAN, 1400 sizeof(*req)); 1401 1402 req->interface_hndl = phba->interface_handle; 1403 req->vlan_priority = vlan_tag; 1404 1405 be_mcc_notify(phba); 1406 spin_unlock(&ctrl->mbox_lock); 1407 1408 return tag; 1409 } 1410