1 /** 2 * Copyright (C) 2005 - 2013 Emulex 3 * All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License version 2 7 * as published by the Free Software Foundation. The full GNU General 8 * Public License is included in this distribution in the file called COPYING. 9 * 10 * Contact Information: 11 * linux-drivers@emulex.com 12 * 13 * Emulex 14 * 3333 Susan Street 15 * Costa Mesa, CA 92626 16 */ 17 18 #include <scsi/iscsi_proto.h> 19 20 #include "be.h" 21 #include "be_mgmt.h" 22 #include "be_main.h" 23 24 int beiscsi_pci_soft_reset(struct beiscsi_hba *phba) 25 { 26 u32 sreset; 27 u8 *pci_reset_offset = 0; 28 u8 *pci_online0_offset = 0; 29 u8 *pci_online1_offset = 0; 30 u32 pconline0 = 0; 31 u32 pconline1 = 0; 32 u32 i; 33 34 pci_reset_offset = (u8 *)phba->pci_va + BE2_SOFT_RESET; 35 pci_online0_offset = (u8 *)phba->pci_va + BE2_PCI_ONLINE0; 36 pci_online1_offset = (u8 *)phba->pci_va + BE2_PCI_ONLINE1; 37 sreset = readl((void *)pci_reset_offset); 38 sreset |= BE2_SET_RESET; 39 writel(sreset, (void *)pci_reset_offset); 40 41 i = 0; 42 while (sreset & BE2_SET_RESET) { 43 if (i > 64) 44 break; 45 msleep(100); 46 sreset = readl((void *)pci_reset_offset); 47 i++; 48 } 49 50 if (sreset & BE2_SET_RESET) { 51 printk(KERN_ERR DRV_NAME 52 " Soft Reset did not deassert\n"); 53 return -EIO; 54 } 55 pconline1 = BE2_MPU_IRAM_ONLINE; 56 writel(pconline0, (void *)pci_online0_offset); 57 writel(pconline1, (void *)pci_online1_offset); 58 59 sreset |= BE2_SET_RESET; 60 writel(sreset, (void *)pci_reset_offset); 61 62 i = 0; 63 while (sreset & BE2_SET_RESET) { 64 if (i > 64) 65 break; 66 msleep(1); 67 sreset = readl((void *)pci_reset_offset); 68 i++; 69 } 70 if (sreset & BE2_SET_RESET) { 71 printk(KERN_ERR DRV_NAME 72 " MPU Online Soft Reset did not deassert\n"); 73 return -EIO; 74 } 75 return 0; 76 } 77 78 int be_chk_reset_complete(struct beiscsi_hba *phba) 79 { 80 unsigned int num_loop; 81 u8 *mpu_sem = 0; 82 u32 status; 83 84 num_loop = 1000; 85 mpu_sem = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE; 86 msleep(5000); 87 88 while (num_loop) { 89 status = readl((void *)mpu_sem); 90 91 if ((status & 0x80000000) || (status & 0x0000FFFF) == 0xC000) 92 break; 93 msleep(60); 94 num_loop--; 95 } 96 97 if ((status & 0x80000000) || (!num_loop)) { 98 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 99 "BC_%d : Failed in be_chk_reset_complete" 100 "status = 0x%x\n", status); 101 return -EIO; 102 } 103 104 return 0; 105 } 106 107 void be_mcc_notify(struct beiscsi_hba *phba) 108 { 109 struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q; 110 u32 val = 0; 111 112 val |= mccq->id & DB_MCCQ_RING_ID_MASK; 113 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT; 114 iowrite32(val, phba->db_va + DB_MCCQ_OFFSET); 115 } 116 117 unsigned int alloc_mcc_tag(struct beiscsi_hba *phba) 118 { 119 unsigned int tag = 0; 120 121 if (phba->ctrl.mcc_tag_available) { 122 tag = phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index]; 123 phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index] = 0; 124 phba->ctrl.mcc_numtag[tag] = 0; 125 } 126 if (tag) { 127 phba->ctrl.mcc_tag_available--; 128 if (phba->ctrl.mcc_alloc_index == (MAX_MCC_CMD - 1)) 129 phba->ctrl.mcc_alloc_index = 0; 130 else 131 phba->ctrl.mcc_alloc_index++; 132 } 133 return tag; 134 } 135 136 /* 137 * beiscsi_mccq_compl()- Wait for completion of MBX 138 * @phba: Driver private structure 139 * @tag: Tag for the MBX Command 140 * @wrb: the WRB used for the MBX Command 141 * @cmd_hdr: IOCTL Hdr for the MBX Cmd 142 * 143 * Waits for MBX completion with the passed TAG. 144 * 145 * return 146 * Success: 0 147 * Failure: Non-Zero 148 **/ 149 int beiscsi_mccq_compl(struct beiscsi_hba *phba, 150 uint32_t tag, struct be_mcc_wrb **wrb, 151 void *cmd_hdr) 152 { 153 int rc = 0; 154 uint32_t mcc_tag_response; 155 uint16_t status = 0, addl_status = 0, wrb_num = 0; 156 struct be_mcc_wrb *temp_wrb; 157 struct be_cmd_req_hdr *ioctl_hdr; 158 struct be_cmd_resp_hdr *ioctl_resp_hdr; 159 struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q; 160 161 if (beiscsi_error(phba)) 162 return -EIO; 163 164 /* wait for the mccq completion */ 165 rc = wait_event_interruptible_timeout( 166 phba->ctrl.mcc_wait[tag], 167 phba->ctrl.mcc_numtag[tag], 168 msecs_to_jiffies( 169 BEISCSI_HOST_MBX_TIMEOUT)); 170 171 if (rc <= 0) { 172 beiscsi_log(phba, KERN_ERR, 173 BEISCSI_LOG_INIT | BEISCSI_LOG_EH | 174 BEISCSI_LOG_CONFIG, 175 "BC_%d : MBX Cmd Completion timed out\n"); 176 rc = -EAGAIN; 177 goto release_mcc_tag; 178 } else 179 rc = 0; 180 181 mcc_tag_response = phba->ctrl.mcc_numtag[tag]; 182 status = (mcc_tag_response & CQE_STATUS_MASK); 183 addl_status = ((mcc_tag_response & CQE_STATUS_ADDL_MASK) >> 184 CQE_STATUS_ADDL_SHIFT); 185 186 if (cmd_hdr) { 187 ioctl_hdr = (struct be_cmd_req_hdr *)cmd_hdr; 188 } else { 189 wrb_num = (mcc_tag_response & CQE_STATUS_WRB_MASK) >> 190 CQE_STATUS_WRB_SHIFT; 191 temp_wrb = (struct be_mcc_wrb *)queue_get_wrb(mccq, wrb_num); 192 ioctl_hdr = embedded_payload(temp_wrb); 193 194 if (wrb) 195 *wrb = temp_wrb; 196 } 197 198 if (status || addl_status) { 199 beiscsi_log(phba, KERN_ERR, 200 BEISCSI_LOG_INIT | BEISCSI_LOG_EH | 201 BEISCSI_LOG_CONFIG, 202 "BC_%d : MBX Cmd Failed for " 203 "Subsys : %d Opcode : %d with " 204 "Status : %d and Extd_Status : %d\n", 205 ioctl_hdr->subsystem, 206 ioctl_hdr->opcode, 207 status, addl_status); 208 209 if (status == MCC_STATUS_INSUFFICIENT_BUFFER) { 210 ioctl_resp_hdr = (struct be_cmd_resp_hdr *) ioctl_hdr; 211 if (ioctl_resp_hdr->response_length) 212 goto release_mcc_tag; 213 } 214 rc = -EAGAIN; 215 } 216 217 release_mcc_tag: 218 /* Release the MCC entry */ 219 free_mcc_tag(&phba->ctrl, tag); 220 221 return rc; 222 } 223 224 void free_mcc_tag(struct be_ctrl_info *ctrl, unsigned int tag) 225 { 226 spin_lock(&ctrl->mbox_lock); 227 tag = tag & 0x000000FF; 228 ctrl->mcc_tag[ctrl->mcc_free_index] = tag; 229 if (ctrl->mcc_free_index == (MAX_MCC_CMD - 1)) 230 ctrl->mcc_free_index = 0; 231 else 232 ctrl->mcc_free_index++; 233 ctrl->mcc_tag_available++; 234 spin_unlock(&ctrl->mbox_lock); 235 } 236 237 bool is_link_state_evt(u32 trailer) 238 { 239 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) & 240 ASYNC_TRAILER_EVENT_CODE_MASK) == 241 ASYNC_EVENT_CODE_LINK_STATE); 242 } 243 244 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl) 245 { 246 if (compl->flags != 0) { 247 compl->flags = le32_to_cpu(compl->flags); 248 WARN_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0); 249 return true; 250 } else 251 return false; 252 } 253 254 static inline void be_mcc_compl_use(struct be_mcc_compl *compl) 255 { 256 compl->flags = 0; 257 } 258 259 /* 260 * be_mcc_compl_process()- Check the MBX comapletion status 261 * @ctrl: Function specific MBX data structure 262 * @compl: Completion status of MBX Command 263 * 264 * Check for the MBX completion status when BMBX method used 265 * 266 * return 267 * Success: Zero 268 * Failure: Non-Zero 269 **/ 270 static int be_mcc_compl_process(struct be_ctrl_info *ctrl, 271 struct be_mcc_compl *compl) 272 { 273 u16 compl_status, extd_status; 274 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); 275 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); 276 struct be_cmd_req_hdr *hdr = embedded_payload(wrb); 277 struct be_cmd_resp_hdr *resp_hdr; 278 279 be_dws_le_to_cpu(compl, 4); 280 281 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) & 282 CQE_STATUS_COMPL_MASK; 283 if (compl_status != MCC_STATUS_SUCCESS) { 284 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) & 285 CQE_STATUS_EXTD_MASK; 286 287 beiscsi_log(phba, KERN_ERR, 288 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX, 289 "BC_%d : error in cmd completion: " 290 "Subsystem : %d Opcode : %d " 291 "status(compl/extd)=%d/%d\n", 292 hdr->subsystem, hdr->opcode, 293 compl_status, extd_status); 294 295 if (compl_status == MCC_STATUS_INSUFFICIENT_BUFFER) { 296 resp_hdr = (struct be_cmd_resp_hdr *) hdr; 297 if (resp_hdr->response_length) 298 return 0; 299 } 300 return -EBUSY; 301 } 302 return 0; 303 } 304 305 int be_mcc_compl_process_isr(struct be_ctrl_info *ctrl, 306 struct be_mcc_compl *compl) 307 { 308 u16 compl_status, extd_status; 309 unsigned short tag; 310 311 be_dws_le_to_cpu(compl, 4); 312 313 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) & 314 CQE_STATUS_COMPL_MASK; 315 /* The ctrl.mcc_numtag[tag] is filled with 316 * [31] = valid, [30:24] = Rsvd, [23:16] = wrb, [15:8] = extd_status, 317 * [7:0] = compl_status 318 */ 319 tag = (compl->tag0 & 0x000000FF); 320 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) & 321 CQE_STATUS_EXTD_MASK; 322 323 ctrl->mcc_numtag[tag] = 0x80000000; 324 ctrl->mcc_numtag[tag] |= (compl->tag0 & 0x00FF0000); 325 ctrl->mcc_numtag[tag] |= (extd_status & 0x000000FF) << 8; 326 ctrl->mcc_numtag[tag] |= (compl_status & 0x000000FF); 327 wake_up_interruptible(&ctrl->mcc_wait[tag]); 328 return 0; 329 } 330 331 static struct be_mcc_compl *be_mcc_compl_get(struct beiscsi_hba *phba) 332 { 333 struct be_queue_info *mcc_cq = &phba->ctrl.mcc_obj.cq; 334 struct be_mcc_compl *compl = queue_tail_node(mcc_cq); 335 336 if (be_mcc_compl_is_new(compl)) { 337 queue_tail_inc(mcc_cq); 338 return compl; 339 } 340 return NULL; 341 } 342 343 static void be2iscsi_fail_session(struct iscsi_cls_session *cls_session) 344 { 345 iscsi_session_failure(cls_session->dd_data, ISCSI_ERR_CONN_FAILED); 346 } 347 348 void beiscsi_async_link_state_process(struct beiscsi_hba *phba, 349 struct be_async_event_link_state *evt) 350 { 351 if ((evt->port_link_status == ASYNC_EVENT_LINK_DOWN) || 352 ((evt->port_link_status & ASYNC_EVENT_LOGICAL) && 353 (evt->port_fault != BEISCSI_PHY_LINK_FAULT_NONE))) { 354 phba->state = BE_ADAPTER_LINK_DOWN; 355 356 beiscsi_log(phba, KERN_ERR, 357 BEISCSI_LOG_CONFIG | BEISCSI_LOG_INIT, 358 "BC_%d : Link Down on Port %d\n", 359 evt->physical_port); 360 361 iscsi_host_for_each_session(phba->shost, 362 be2iscsi_fail_session); 363 } else if ((evt->port_link_status & ASYNC_EVENT_LINK_UP) || 364 ((evt->port_link_status & ASYNC_EVENT_LOGICAL) && 365 (evt->port_fault == BEISCSI_PHY_LINK_FAULT_NONE))) { 366 phba->state = BE_ADAPTER_UP; 367 368 beiscsi_log(phba, KERN_ERR, 369 BEISCSI_LOG_CONFIG | BEISCSI_LOG_INIT, 370 "BC_%d : Link UP on Port %d\n", 371 evt->physical_port); 372 } 373 } 374 375 static void beiscsi_cq_notify(struct beiscsi_hba *phba, u16 qid, bool arm, 376 u16 num_popped) 377 { 378 u32 val = 0; 379 val |= qid & DB_CQ_RING_ID_MASK; 380 if (arm) 381 val |= 1 << DB_CQ_REARM_SHIFT; 382 val |= num_popped << DB_CQ_NUM_POPPED_SHIFT; 383 iowrite32(val, phba->db_va + DB_CQ_OFFSET); 384 } 385 386 387 int beiscsi_process_mcc(struct beiscsi_hba *phba) 388 { 389 struct be_mcc_compl *compl; 390 int num = 0, status = 0; 391 struct be_ctrl_info *ctrl = &phba->ctrl; 392 393 spin_lock_bh(&phba->ctrl.mcc_cq_lock); 394 while ((compl = be_mcc_compl_get(phba))) { 395 if (compl->flags & CQE_FLAGS_ASYNC_MASK) { 396 /* Interpret flags as an async trailer */ 397 if (is_link_state_evt(compl->flags)) 398 /* Interpret compl as a async link evt */ 399 beiscsi_async_link_state_process(phba, 400 (struct be_async_event_link_state *) compl); 401 else 402 beiscsi_log(phba, KERN_ERR, 403 BEISCSI_LOG_CONFIG | 404 BEISCSI_LOG_MBOX, 405 "BC_%d : Unsupported Async Event, flags" 406 " = 0x%08x\n", compl->flags); 407 408 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) { 409 status = be_mcc_compl_process(ctrl, compl); 410 atomic_dec(&phba->ctrl.mcc_obj.q.used); 411 } 412 be_mcc_compl_use(compl); 413 num++; 414 } 415 416 if (num) 417 beiscsi_cq_notify(phba, phba->ctrl.mcc_obj.cq.id, true, num); 418 419 spin_unlock_bh(&phba->ctrl.mcc_cq_lock); 420 return status; 421 } 422 423 /* 424 * be_mcc_wait_compl()- Wait for MBX completion 425 * @phba: driver private structure 426 * 427 * Wait till no more pending mcc requests are present 428 * 429 * return 430 * Success: 0 431 * Failure: Non-Zero 432 * 433 **/ 434 static int be_mcc_wait_compl(struct beiscsi_hba *phba) 435 { 436 int i, status; 437 for (i = 0; i < mcc_timeout; i++) { 438 if (beiscsi_error(phba)) 439 return -EIO; 440 441 status = beiscsi_process_mcc(phba); 442 if (status) 443 return status; 444 445 if (atomic_read(&phba->ctrl.mcc_obj.q.used) == 0) 446 break; 447 udelay(100); 448 } 449 if (i == mcc_timeout) { 450 beiscsi_log(phba, KERN_ERR, 451 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX, 452 "BC_%d : FW Timed Out\n"); 453 phba->fw_timeout = true; 454 beiscsi_ue_detect(phba); 455 return -EBUSY; 456 } 457 return 0; 458 } 459 460 /* 461 * be_mcc_notify_wait()- Notify and wait for Compl 462 * @phba: driver private structure 463 * 464 * Notify MCC requests and wait for completion 465 * 466 * return 467 * Success: 0 468 * Failure: Non-Zero 469 **/ 470 int be_mcc_notify_wait(struct beiscsi_hba *phba) 471 { 472 be_mcc_notify(phba); 473 return be_mcc_wait_compl(phba); 474 } 475 476 /* 477 * be_mbox_db_ready_wait()- Check ready status 478 * @ctrl: Function specific MBX data structure 479 * 480 * Check for the ready status of FW to send BMBX 481 * commands to adapter. 482 * 483 * return 484 * Success: 0 485 * Failure: Non-Zero 486 **/ 487 static int be_mbox_db_ready_wait(struct be_ctrl_info *ctrl) 488 { 489 void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET; 490 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); 491 uint32_t wait = 0; 492 u32 ready; 493 494 do { 495 496 if (beiscsi_error(phba)) 497 return -EIO; 498 499 ready = ioread32(db) & MPU_MAILBOX_DB_RDY_MASK; 500 if (ready) 501 break; 502 503 if (wait > BEISCSI_HOST_MBX_TIMEOUT) { 504 beiscsi_log(phba, KERN_ERR, 505 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX, 506 "BC_%d : FW Timed Out\n"); 507 phba->fw_timeout = true; 508 beiscsi_ue_detect(phba); 509 return -EBUSY; 510 } 511 512 mdelay(1); 513 wait++; 514 } while (true); 515 return 0; 516 } 517 518 /* 519 * be_mbox_notify: Notify adapter of new BMBX command 520 * @ctrl: Function specific MBX data structure 521 * 522 * Ring doorbell to inform adapter of a BMBX command 523 * to process 524 * 525 * return 526 * Success: 0 527 * Failure: Non-Zero 528 **/ 529 int be_mbox_notify(struct be_ctrl_info *ctrl) 530 { 531 int status; 532 u32 val = 0; 533 void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET; 534 struct be_dma_mem *mbox_mem = &ctrl->mbox_mem; 535 struct be_mcc_mailbox *mbox = mbox_mem->va; 536 struct be_mcc_compl *compl = &mbox->compl; 537 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); 538 539 status = be_mbox_db_ready_wait(ctrl); 540 if (status) 541 return status; 542 543 val &= ~MPU_MAILBOX_DB_RDY_MASK; 544 val |= MPU_MAILBOX_DB_HI_MASK; 545 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2; 546 iowrite32(val, db); 547 548 status = be_mbox_db_ready_wait(ctrl); 549 if (status) 550 return status; 551 552 val = 0; 553 val &= ~MPU_MAILBOX_DB_RDY_MASK; 554 val &= ~MPU_MAILBOX_DB_HI_MASK; 555 val |= (u32) (mbox_mem->dma >> 4) << 2; 556 iowrite32(val, db); 557 558 status = be_mbox_db_ready_wait(ctrl); 559 if (status) 560 return status; 561 562 if (be_mcc_compl_is_new(compl)) { 563 status = be_mcc_compl_process(ctrl, &mbox->compl); 564 be_mcc_compl_use(compl); 565 if (status) { 566 beiscsi_log(phba, KERN_ERR, 567 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX, 568 "BC_%d : After be_mcc_compl_process\n"); 569 570 return status; 571 } 572 } else { 573 beiscsi_log(phba, KERN_ERR, 574 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX, 575 "BC_%d : Invalid Mailbox Completion\n"); 576 577 return -EBUSY; 578 } 579 return 0; 580 } 581 582 /* 583 * Insert the mailbox address into the doorbell in two steps 584 * Polls on the mbox doorbell till a command completion (or a timeout) occurs 585 */ 586 static int be_mbox_notify_wait(struct beiscsi_hba *phba) 587 { 588 int status; 589 u32 val = 0; 590 void __iomem *db = phba->ctrl.db + MPU_MAILBOX_DB_OFFSET; 591 struct be_dma_mem *mbox_mem = &phba->ctrl.mbox_mem; 592 struct be_mcc_mailbox *mbox = mbox_mem->va; 593 struct be_mcc_compl *compl = &mbox->compl; 594 struct be_ctrl_info *ctrl = &phba->ctrl; 595 596 status = be_mbox_db_ready_wait(ctrl); 597 if (status) 598 return status; 599 600 val |= MPU_MAILBOX_DB_HI_MASK; 601 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */ 602 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2; 603 iowrite32(val, db); 604 605 /* wait for ready to be set */ 606 status = be_mbox_db_ready_wait(ctrl); 607 if (status != 0) 608 return status; 609 610 val = 0; 611 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */ 612 val |= (u32)(mbox_mem->dma >> 4) << 2; 613 iowrite32(val, db); 614 615 status = be_mbox_db_ready_wait(ctrl); 616 if (status != 0) 617 return status; 618 619 /* A cq entry has been made now */ 620 if (be_mcc_compl_is_new(compl)) { 621 status = be_mcc_compl_process(ctrl, &mbox->compl); 622 be_mcc_compl_use(compl); 623 if (status) 624 return status; 625 } else { 626 beiscsi_log(phba, KERN_ERR, 627 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX, 628 "BC_%d : invalid mailbox completion\n"); 629 630 return -EBUSY; 631 } 632 return 0; 633 } 634 635 void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len, 636 bool embedded, u8 sge_cnt) 637 { 638 if (embedded) 639 wrb->embedded |= MCC_WRB_EMBEDDED_MASK; 640 else 641 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) << 642 MCC_WRB_SGE_CNT_SHIFT; 643 wrb->payload_length = payload_len; 644 be_dws_cpu_to_le(wrb, 8); 645 } 646 647 void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr, 648 u8 subsystem, u8 opcode, int cmd_len) 649 { 650 req_hdr->opcode = opcode; 651 req_hdr->subsystem = subsystem; 652 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr)); 653 req_hdr->timeout = BEISCSI_FW_MBX_TIMEOUT; 654 } 655 656 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages, 657 struct be_dma_mem *mem) 658 { 659 int i, buf_pages; 660 u64 dma = (u64) mem->dma; 661 662 buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages); 663 for (i = 0; i < buf_pages; i++) { 664 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF); 665 pages[i].hi = cpu_to_le32(upper_32_bits(dma)); 666 dma += PAGE_SIZE_4K; 667 } 668 } 669 670 static u32 eq_delay_to_mult(u32 usec_delay) 671 { 672 #define MAX_INTR_RATE 651042 673 const u32 round = 10; 674 u32 multiplier; 675 676 if (usec_delay == 0) 677 multiplier = 0; 678 else { 679 u32 interrupt_rate = 1000000 / usec_delay; 680 if (interrupt_rate == 0) 681 multiplier = 1023; 682 else { 683 multiplier = (MAX_INTR_RATE - interrupt_rate) * round; 684 multiplier /= interrupt_rate; 685 multiplier = (multiplier + round / 2) / round; 686 multiplier = min(multiplier, (u32) 1023); 687 } 688 } 689 return multiplier; 690 } 691 692 struct be_mcc_wrb *wrb_from_mbox(struct be_dma_mem *mbox_mem) 693 { 694 return &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb; 695 } 696 697 struct be_mcc_wrb *wrb_from_mccq(struct beiscsi_hba *phba) 698 { 699 struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q; 700 struct be_mcc_wrb *wrb; 701 702 BUG_ON(atomic_read(&mccq->used) >= mccq->len); 703 wrb = queue_head_node(mccq); 704 memset(wrb, 0, sizeof(*wrb)); 705 wrb->tag0 = (mccq->head & 0x000000FF) << 16; 706 queue_head_inc(mccq); 707 atomic_inc(&mccq->used); 708 return wrb; 709 } 710 711 712 int beiscsi_cmd_eq_create(struct be_ctrl_info *ctrl, 713 struct be_queue_info *eq, int eq_delay) 714 { 715 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); 716 struct be_cmd_req_eq_create *req = embedded_payload(wrb); 717 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb); 718 struct be_dma_mem *q_mem = &eq->dma_mem; 719 int status; 720 721 spin_lock(&ctrl->mbox_lock); 722 memset(wrb, 0, sizeof(*wrb)); 723 724 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 725 726 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 727 OPCODE_COMMON_EQ_CREATE, sizeof(*req)); 728 729 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); 730 731 AMAP_SET_BITS(struct amap_eq_context, func, req->context, 732 PCI_FUNC(ctrl->pdev->devfn)); 733 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1); 734 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0); 735 AMAP_SET_BITS(struct amap_eq_context, count, req->context, 736 __ilog2_u32(eq->len / 256)); 737 AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context, 738 eq_delay_to_mult(eq_delay)); 739 be_dws_cpu_to_le(req->context, sizeof(req->context)); 740 741 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 742 743 status = be_mbox_notify(ctrl); 744 if (!status) { 745 eq->id = le16_to_cpu(resp->eq_id); 746 eq->created = true; 747 } 748 spin_unlock(&ctrl->mbox_lock); 749 return status; 750 } 751 752 /** 753 * be_cmd_fw_initialize()- Initialize FW 754 * @ctrl: Pointer to function control structure 755 * 756 * Send FW initialize pattern for the function. 757 * 758 * return 759 * Success: 0 760 * Failure: Non-Zero value 761 **/ 762 int be_cmd_fw_initialize(struct be_ctrl_info *ctrl) 763 { 764 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); 765 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); 766 int status; 767 u8 *endian_check; 768 769 spin_lock(&ctrl->mbox_lock); 770 memset(wrb, 0, sizeof(*wrb)); 771 772 endian_check = (u8 *) wrb; 773 *endian_check++ = 0xFF; 774 *endian_check++ = 0x12; 775 *endian_check++ = 0x34; 776 *endian_check++ = 0xFF; 777 *endian_check++ = 0xFF; 778 *endian_check++ = 0x56; 779 *endian_check++ = 0x78; 780 *endian_check++ = 0xFF; 781 be_dws_cpu_to_le(wrb, sizeof(*wrb)); 782 783 status = be_mbox_notify(ctrl); 784 if (status) 785 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 786 "BC_%d : be_cmd_fw_initialize Failed\n"); 787 788 spin_unlock(&ctrl->mbox_lock); 789 return status; 790 } 791 792 /** 793 * be_cmd_fw_uninit()- Uinitialize FW 794 * @ctrl: Pointer to function control structure 795 * 796 * Send FW uninitialize pattern for the function 797 * 798 * return 799 * Success: 0 800 * Failure: Non-Zero value 801 **/ 802 int be_cmd_fw_uninit(struct be_ctrl_info *ctrl) 803 { 804 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); 805 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); 806 int status; 807 u8 *endian_check; 808 809 spin_lock(&ctrl->mbox_lock); 810 memset(wrb, 0, sizeof(*wrb)); 811 812 endian_check = (u8 *) wrb; 813 *endian_check++ = 0xFF; 814 *endian_check++ = 0xAA; 815 *endian_check++ = 0xBB; 816 *endian_check++ = 0xFF; 817 *endian_check++ = 0xFF; 818 *endian_check++ = 0xCC; 819 *endian_check++ = 0xDD; 820 *endian_check = 0xFF; 821 822 be_dws_cpu_to_le(wrb, sizeof(*wrb)); 823 824 status = be_mbox_notify(ctrl); 825 if (status) 826 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 827 "BC_%d : be_cmd_fw_uninit Failed\n"); 828 829 spin_unlock(&ctrl->mbox_lock); 830 return status; 831 } 832 833 int beiscsi_cmd_cq_create(struct be_ctrl_info *ctrl, 834 struct be_queue_info *cq, struct be_queue_info *eq, 835 bool sol_evts, bool no_delay, int coalesce_wm) 836 { 837 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); 838 struct be_cmd_req_cq_create *req = embedded_payload(wrb); 839 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb); 840 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); 841 struct be_dma_mem *q_mem = &cq->dma_mem; 842 void *ctxt = &req->context; 843 int status; 844 845 spin_lock(&ctrl->mbox_lock); 846 memset(wrb, 0, sizeof(*wrb)); 847 848 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 849 850 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 851 OPCODE_COMMON_CQ_CREATE, sizeof(*req)); 852 853 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); 854 if (is_chip_be2_be3r(phba)) { 855 AMAP_SET_BITS(struct amap_cq_context, coalescwm, 856 ctxt, coalesce_wm); 857 AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay); 858 AMAP_SET_BITS(struct amap_cq_context, count, ctxt, 859 __ilog2_u32(cq->len / 256)); 860 AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1); 861 AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts); 862 AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1); 863 AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id); 864 AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1); 865 AMAP_SET_BITS(struct amap_cq_context, func, ctxt, 866 PCI_FUNC(ctrl->pdev->devfn)); 867 } else { 868 req->hdr.version = MBX_CMD_VER2; 869 req->page_size = 1; 870 AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm, 871 ctxt, coalesce_wm); 872 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, 873 ctxt, no_delay); 874 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt, 875 __ilog2_u32(cq->len / 256)); 876 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1); 877 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1); 878 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id); 879 AMAP_SET_BITS(struct amap_cq_context_v2, armed, ctxt, 1); 880 } 881 882 be_dws_cpu_to_le(ctxt, sizeof(req->context)); 883 884 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 885 886 status = be_mbox_notify(ctrl); 887 if (!status) { 888 cq->id = le16_to_cpu(resp->cq_id); 889 cq->created = true; 890 } else 891 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 892 "BC_%d : In be_cmd_cq_create, status=ox%08x\n", 893 status); 894 895 spin_unlock(&ctrl->mbox_lock); 896 897 return status; 898 } 899 900 static u32 be_encoded_q_len(int q_len) 901 { 902 u32 len_encoded = fls(q_len); /* log2(len) + 1 */ 903 if (len_encoded == 16) 904 len_encoded = 0; 905 return len_encoded; 906 } 907 908 int beiscsi_cmd_mccq_create(struct beiscsi_hba *phba, 909 struct be_queue_info *mccq, 910 struct be_queue_info *cq) 911 { 912 struct be_mcc_wrb *wrb; 913 struct be_cmd_req_mcc_create *req; 914 struct be_dma_mem *q_mem = &mccq->dma_mem; 915 struct be_ctrl_info *ctrl; 916 void *ctxt; 917 int status; 918 919 spin_lock(&phba->ctrl.mbox_lock); 920 ctrl = &phba->ctrl; 921 wrb = wrb_from_mbox(&ctrl->mbox_mem); 922 memset(wrb, 0, sizeof(*wrb)); 923 req = embedded_payload(wrb); 924 ctxt = &req->context; 925 926 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 927 928 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 929 OPCODE_COMMON_MCC_CREATE, sizeof(*req)); 930 931 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size); 932 933 AMAP_SET_BITS(struct amap_mcc_context, fid, ctxt, 934 PCI_FUNC(phba->pcidev->devfn)); 935 AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1); 936 AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt, 937 be_encoded_q_len(mccq->len)); 938 AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id); 939 940 be_dws_cpu_to_le(ctxt, sizeof(req->context)); 941 942 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 943 944 status = be_mbox_notify_wait(phba); 945 if (!status) { 946 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb); 947 mccq->id = le16_to_cpu(resp->id); 948 mccq->created = true; 949 } 950 spin_unlock(&phba->ctrl.mbox_lock); 951 952 return status; 953 } 954 955 int beiscsi_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q, 956 int queue_type) 957 { 958 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); 959 struct be_cmd_req_q_destroy *req = embedded_payload(wrb); 960 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); 961 u8 subsys = 0, opcode = 0; 962 int status; 963 964 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, 965 "BC_%d : In beiscsi_cmd_q_destroy " 966 "queue_type : %d\n", queue_type); 967 968 spin_lock(&ctrl->mbox_lock); 969 memset(wrb, 0, sizeof(*wrb)); 970 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 971 972 switch (queue_type) { 973 case QTYPE_EQ: 974 subsys = CMD_SUBSYSTEM_COMMON; 975 opcode = OPCODE_COMMON_EQ_DESTROY; 976 break; 977 case QTYPE_CQ: 978 subsys = CMD_SUBSYSTEM_COMMON; 979 opcode = OPCODE_COMMON_CQ_DESTROY; 980 break; 981 case QTYPE_MCCQ: 982 subsys = CMD_SUBSYSTEM_COMMON; 983 opcode = OPCODE_COMMON_MCC_DESTROY; 984 break; 985 case QTYPE_WRBQ: 986 subsys = CMD_SUBSYSTEM_ISCSI; 987 opcode = OPCODE_COMMON_ISCSI_WRBQ_DESTROY; 988 break; 989 case QTYPE_DPDUQ: 990 subsys = CMD_SUBSYSTEM_ISCSI; 991 opcode = OPCODE_COMMON_ISCSI_DEFQ_DESTROY; 992 break; 993 case QTYPE_SGL: 994 subsys = CMD_SUBSYSTEM_ISCSI; 995 opcode = OPCODE_COMMON_ISCSI_CFG_REMOVE_SGL_PAGES; 996 break; 997 default: 998 spin_unlock(&ctrl->mbox_lock); 999 BUG(); 1000 return -ENXIO; 1001 } 1002 be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req)); 1003 if (queue_type != QTYPE_SGL) 1004 req->id = cpu_to_le16(q->id); 1005 1006 status = be_mbox_notify(ctrl); 1007 1008 spin_unlock(&ctrl->mbox_lock); 1009 return status; 1010 } 1011 1012 int be_cmd_create_default_pdu_queue(struct be_ctrl_info *ctrl, 1013 struct be_queue_info *cq, 1014 struct be_queue_info *dq, int length, 1015 int entry_size) 1016 { 1017 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); 1018 struct be_defq_create_req *req = embedded_payload(wrb); 1019 struct be_dma_mem *q_mem = &dq->dma_mem; 1020 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); 1021 void *ctxt = &req->context; 1022 int status; 1023 1024 spin_lock(&ctrl->mbox_lock); 1025 memset(wrb, 0, sizeof(*wrb)); 1026 1027 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 1028 1029 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI, 1030 OPCODE_COMMON_ISCSI_DEFQ_CREATE, sizeof(*req)); 1031 1032 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size); 1033 1034 if (is_chip_be2_be3r(phba)) { 1035 AMAP_SET_BITS(struct amap_be_default_pdu_context, 1036 rx_pdid, ctxt, 0); 1037 AMAP_SET_BITS(struct amap_be_default_pdu_context, 1038 rx_pdid_valid, ctxt, 1); 1039 AMAP_SET_BITS(struct amap_be_default_pdu_context, 1040 pci_func_id, ctxt, PCI_FUNC(ctrl->pdev->devfn)); 1041 AMAP_SET_BITS(struct amap_be_default_pdu_context, 1042 ring_size, ctxt, 1043 be_encoded_q_len(length / 1044 sizeof(struct phys_addr))); 1045 AMAP_SET_BITS(struct amap_be_default_pdu_context, 1046 default_buffer_size, ctxt, entry_size); 1047 AMAP_SET_BITS(struct amap_be_default_pdu_context, 1048 cq_id_recv, ctxt, cq->id); 1049 } else { 1050 AMAP_SET_BITS(struct amap_default_pdu_context_ext, 1051 rx_pdid, ctxt, 0); 1052 AMAP_SET_BITS(struct amap_default_pdu_context_ext, 1053 rx_pdid_valid, ctxt, 1); 1054 AMAP_SET_BITS(struct amap_default_pdu_context_ext, 1055 ring_size, ctxt, 1056 be_encoded_q_len(length / 1057 sizeof(struct phys_addr))); 1058 AMAP_SET_BITS(struct amap_default_pdu_context_ext, 1059 default_buffer_size, ctxt, entry_size); 1060 AMAP_SET_BITS(struct amap_default_pdu_context_ext, 1061 cq_id_recv, ctxt, cq->id); 1062 } 1063 1064 be_dws_cpu_to_le(ctxt, sizeof(req->context)); 1065 1066 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 1067 1068 status = be_mbox_notify(ctrl); 1069 if (!status) { 1070 struct be_defq_create_resp *resp = embedded_payload(wrb); 1071 1072 dq->id = le16_to_cpu(resp->id); 1073 dq->created = true; 1074 } 1075 spin_unlock(&ctrl->mbox_lock); 1076 1077 return status; 1078 } 1079 1080 int be_cmd_wrbq_create(struct be_ctrl_info *ctrl, struct be_dma_mem *q_mem, 1081 struct be_queue_info *wrbq) 1082 { 1083 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); 1084 struct be_wrbq_create_req *req = embedded_payload(wrb); 1085 struct be_wrbq_create_resp *resp = embedded_payload(wrb); 1086 int status; 1087 1088 spin_lock(&ctrl->mbox_lock); 1089 memset(wrb, 0, sizeof(*wrb)); 1090 1091 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 1092 1093 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI, 1094 OPCODE_COMMON_ISCSI_WRBQ_CREATE, sizeof(*req)); 1095 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size); 1096 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); 1097 1098 status = be_mbox_notify(ctrl); 1099 if (!status) { 1100 wrbq->id = le16_to_cpu(resp->cid); 1101 wrbq->created = true; 1102 } 1103 spin_unlock(&ctrl->mbox_lock); 1104 return status; 1105 } 1106 1107 int be_cmd_iscsi_post_sgl_pages(struct be_ctrl_info *ctrl, 1108 struct be_dma_mem *q_mem, 1109 u32 page_offset, u32 num_pages) 1110 { 1111 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); 1112 struct be_post_sgl_pages_req *req = embedded_payload(wrb); 1113 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev); 1114 int status; 1115 unsigned int curr_pages; 1116 u32 internal_page_offset = 0; 1117 u32 temp_num_pages = num_pages; 1118 1119 if (num_pages == 0xff) 1120 num_pages = 1; 1121 1122 spin_lock(&ctrl->mbox_lock); 1123 do { 1124 memset(wrb, 0, sizeof(*wrb)); 1125 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 1126 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI, 1127 OPCODE_COMMON_ISCSI_CFG_POST_SGL_PAGES, 1128 sizeof(*req)); 1129 curr_pages = BE_NUMBER_OF_FIELD(struct be_post_sgl_pages_req, 1130 pages); 1131 req->num_pages = min(num_pages, curr_pages); 1132 req->page_offset = page_offset; 1133 be_cmd_page_addrs_prepare(req->pages, req->num_pages, q_mem); 1134 q_mem->dma = q_mem->dma + (req->num_pages * PAGE_SIZE); 1135 internal_page_offset += req->num_pages; 1136 page_offset += req->num_pages; 1137 num_pages -= req->num_pages; 1138 1139 if (temp_num_pages == 0xff) 1140 req->num_pages = temp_num_pages; 1141 1142 status = be_mbox_notify(ctrl); 1143 if (status) { 1144 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, 1145 "BC_%d : FW CMD to map iscsi frags failed.\n"); 1146 1147 goto error; 1148 } 1149 } while (num_pages > 0); 1150 error: 1151 spin_unlock(&ctrl->mbox_lock); 1152 if (status != 0) 1153 beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL); 1154 return status; 1155 } 1156 1157 int beiscsi_cmd_reset_function(struct beiscsi_hba *phba) 1158 { 1159 struct be_ctrl_info *ctrl = &phba->ctrl; 1160 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); 1161 struct be_post_sgl_pages_req *req = embedded_payload(wrb); 1162 int status; 1163 1164 spin_lock(&ctrl->mbox_lock); 1165 1166 req = embedded_payload(wrb); 1167 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); 1168 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1169 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req)); 1170 status = be_mbox_notify_wait(phba); 1171 1172 spin_unlock(&ctrl->mbox_lock); 1173 return status; 1174 } 1175 1176 /** 1177 * be_cmd_set_vlan()- Configure VLAN paramters on the adapter 1178 * @phba: device priv structure instance 1179 * @vlan_tag: TAG to be set 1180 * 1181 * Set the VLAN_TAG for the adapter or Disable VLAN on adapter 1182 * 1183 * returns 1184 * TAG for the MBX Cmd 1185 * **/ 1186 int be_cmd_set_vlan(struct beiscsi_hba *phba, 1187 uint16_t vlan_tag) 1188 { 1189 unsigned int tag = 0; 1190 struct be_mcc_wrb *wrb; 1191 struct be_cmd_set_vlan_req *req; 1192 struct be_ctrl_info *ctrl = &phba->ctrl; 1193 1194 spin_lock(&ctrl->mbox_lock); 1195 tag = alloc_mcc_tag(phba); 1196 if (!tag) { 1197 spin_unlock(&ctrl->mbox_lock); 1198 return tag; 1199 } 1200 1201 wrb = wrb_from_mccq(phba); 1202 req = embedded_payload(wrb); 1203 wrb->tag0 |= tag; 1204 be_wrb_hdr_prepare(wrb, sizeof(*wrb), true, 0); 1205 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI, 1206 OPCODE_COMMON_ISCSI_NTWK_SET_VLAN, 1207 sizeof(*req)); 1208 1209 req->interface_hndl = phba->interface_handle; 1210 req->vlan_priority = vlan_tag; 1211 1212 be_mcc_notify(phba); 1213 spin_unlock(&ctrl->mbox_lock); 1214 1215 return tag; 1216 } 1217