1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright 2017 Broadcom. All Rights Reserved. 4 * The term "Broadcom" refers to Broadcom Limited and/or its subsidiaries. 5 * 6 * Contact Information: 7 * linux-drivers@broadcom.com 8 */ 9 10 #ifndef BEISCSI_H 11 #define BEISCSI_H 12 13 #include <linux/pci.h> 14 #include <linux/if_vlan.h> 15 #include <linux/irq_poll.h> 16 #define FW_VER_LEN 32 17 #define MCC_Q_LEN 128 18 #define MCC_CQ_LEN 256 19 #define MAX_MCC_CMD 16 20 /* BladeEngine Generation numbers */ 21 #define BE_GEN2 2 22 #define BE_GEN3 3 23 #define BE_GEN4 4 24 struct be_dma_mem { 25 void *va; 26 dma_addr_t dma; 27 u32 size; 28 }; 29 30 struct be_queue_info { 31 struct be_dma_mem dma_mem; 32 u16 len; 33 u16 entry_size; /* Size of an element in the queue */ 34 u16 id; 35 u16 tail, head; 36 bool created; 37 u16 used; /* Number of valid elements in the queue */ 38 }; 39 40 static inline u32 MODULO(u16 val, u16 limit) 41 { 42 WARN_ON(limit & (limit - 1)); 43 return val & (limit - 1); 44 } 45 46 static inline void index_inc(u16 *index, u16 limit) 47 { 48 *index = MODULO((*index + 1), limit); 49 } 50 51 static inline void *queue_head_node(struct be_queue_info *q) 52 { 53 return q->dma_mem.va + q->head * q->entry_size; 54 } 55 56 static inline void *queue_get_wrb(struct be_queue_info *q, unsigned int wrb_num) 57 { 58 return q->dma_mem.va + wrb_num * q->entry_size; 59 } 60 61 static inline void *queue_tail_node(struct be_queue_info *q) 62 { 63 return q->dma_mem.va + q->tail * q->entry_size; 64 } 65 66 static inline void queue_head_inc(struct be_queue_info *q) 67 { 68 index_inc(&q->head, q->len); 69 } 70 71 static inline void queue_tail_inc(struct be_queue_info *q) 72 { 73 index_inc(&q->tail, q->len); 74 } 75 76 /*ISCSI */ 77 78 struct be_aic_obj { /* Adaptive interrupt coalescing (AIC) info */ 79 unsigned long jiffies; 80 u32 eq_prev; /* Used to calculate eqe */ 81 u32 prev_eqd; 82 #define BEISCSI_EQ_DELAY_MIN 0 83 #define BEISCSI_EQ_DELAY_DEF 32 84 #define BEISCSI_EQ_DELAY_MAX 128 85 }; 86 87 struct be_eq_obj { 88 u32 cq_count; 89 struct be_queue_info q; 90 struct beiscsi_hba *phba; 91 struct be_queue_info *cq; 92 struct work_struct mcc_work; /* Work Item */ 93 struct irq_poll iopoll; 94 }; 95 96 struct be_mcc_obj { 97 struct be_queue_info q; 98 struct be_queue_info cq; 99 }; 100 101 struct beiscsi_mcc_tag_state { 102 unsigned long tag_state; 103 #define MCC_TAG_STATE_RUNNING 0 104 #define MCC_TAG_STATE_TIMEOUT 1 105 #define MCC_TAG_STATE_ASYNC 2 106 #define MCC_TAG_STATE_IGNORE 3 107 void (*cbfn)(struct beiscsi_hba *, unsigned int); 108 struct be_dma_mem tag_mem_state; 109 }; 110 111 struct be_ctrl_info { 112 u8 __iomem *csr; 113 u8 __iomem *db; /* Door Bell */ 114 u8 __iomem *pcicfg; /* PCI config space */ 115 struct pci_dev *pdev; 116 117 /* Mbox used for cmd request/response */ 118 struct mutex mbox_lock; /* For serializing mbox cmds to BE card */ 119 struct be_dma_mem mbox_mem; 120 /* Mbox mem is adjusted to align to 16 bytes. The allocated addr 121 * is stored for freeing purpose */ 122 struct be_dma_mem mbox_mem_alloced; 123 124 /* MCC Rings */ 125 struct be_mcc_obj mcc_obj; 126 spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */ 127 128 wait_queue_head_t mcc_wait[MAX_MCC_CMD + 1]; 129 unsigned int mcc_tag[MAX_MCC_CMD]; 130 unsigned int mcc_tag_status[MAX_MCC_CMD + 1]; 131 unsigned short mcc_alloc_index; 132 unsigned short mcc_free_index; 133 unsigned int mcc_tag_available; 134 135 struct beiscsi_mcc_tag_state ptag_state[MAX_MCC_CMD + 1]; 136 }; 137 138 #include "be_cmds.h" 139 140 /* WRB index mask for MCC_Q_LEN queue entries */ 141 #define MCC_Q_WRB_IDX_MASK CQE_STATUS_WRB_MASK 142 #define MCC_Q_WRB_IDX_SHIFT CQE_STATUS_WRB_SHIFT 143 /* TAG is from 1...MAX_MCC_CMD, MASK includes MAX_MCC_CMD */ 144 #define MCC_Q_CMD_TAG_MASK ((MAX_MCC_CMD << 1) - 1) 145 146 #define PAGE_SHIFT_4K 12 147 #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K) 148 149 /* Returns number of pages spanned by the data starting at the given addr */ 150 #define PAGES_4K_SPANNED(_address, size) \ 151 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \ 152 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K)) 153 154 /* Returns bit offset within a DWORD of a bitfield */ 155 #define AMAP_BIT_OFFSET(_struct, field) \ 156 (((size_t)&(((_struct *)0)->field))%32) 157 158 /* Returns the bit mask of the field that is NOT shifted into location. */ 159 static inline u32 amap_mask(u32 bitsize) 160 { 161 return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1); 162 } 163 164 static inline void amap_set(void *ptr, u32 dw_offset, u32 mask, 165 u32 offset, u32 value) 166 { 167 u32 *dw = (u32 *) ptr + dw_offset; 168 *dw &= ~(mask << offset); 169 *dw |= (mask & value) << offset; 170 } 171 172 #define AMAP_SET_BITS(_struct, field, ptr, val) \ 173 amap_set(ptr, \ 174 offsetof(_struct, field)/32, \ 175 amap_mask(sizeof(((_struct *)0)->field)), \ 176 AMAP_BIT_OFFSET(_struct, field), \ 177 val) 178 179 static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset) 180 { 181 u32 *dw = ptr; 182 return mask & (*(dw + dw_offset) >> offset); 183 } 184 185 #define AMAP_GET_BITS(_struct, field, ptr) \ 186 amap_get(ptr, \ 187 offsetof(_struct, field)/32, \ 188 amap_mask(sizeof(((_struct *)0)->field)), \ 189 AMAP_BIT_OFFSET(_struct, field)) 190 191 #define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len) 192 #define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len) 193 static inline void swap_dws(void *wrb, int len) 194 { 195 #ifdef __BIG_ENDIAN 196 u32 *dw = wrb; 197 WARN_ON(len % 4); 198 do { 199 *dw = cpu_to_le32(*dw); 200 dw++; 201 len -= 4; 202 } while (len); 203 #endif /* __BIG_ENDIAN */ 204 } 205 #endif /* BEISCSI_H */ 206