1 /* 2 * Copyright 2017 Broadcom. All Rights Reserved. 3 * The term "Broadcom" refers to Broadcom Limited and/or its subsidiaries. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License version 2 7 * as published by the Free Software Foundation. The full GNU General 8 * Public License is included in this distribution in the file called COPYING. 9 * 10 * Contact Information: 11 * linux-drivers@broadcom.com 12 * 13 */ 14 15 #ifndef BEISCSI_H 16 #define BEISCSI_H 17 18 #include <linux/pci.h> 19 #include <linux/if_vlan.h> 20 #include <linux/irq_poll.h> 21 #define FW_VER_LEN 32 22 #define MCC_Q_LEN 128 23 #define MCC_CQ_LEN 256 24 #define MAX_MCC_CMD 16 25 /* BladeEngine Generation numbers */ 26 #define BE_GEN2 2 27 #define BE_GEN3 3 28 #define BE_GEN4 4 29 struct be_dma_mem { 30 void *va; 31 dma_addr_t dma; 32 u32 size; 33 }; 34 35 struct be_queue_info { 36 struct be_dma_mem dma_mem; 37 u16 len; 38 u16 entry_size; /* Size of an element in the queue */ 39 u16 id; 40 u16 tail, head; 41 bool created; 42 u16 used; /* Number of valid elements in the queue */ 43 }; 44 45 static inline u32 MODULO(u16 val, u16 limit) 46 { 47 WARN_ON(limit & (limit - 1)); 48 return val & (limit - 1); 49 } 50 51 static inline void index_inc(u16 *index, u16 limit) 52 { 53 *index = MODULO((*index + 1), limit); 54 } 55 56 static inline void *queue_head_node(struct be_queue_info *q) 57 { 58 return q->dma_mem.va + q->head * q->entry_size; 59 } 60 61 static inline void *queue_get_wrb(struct be_queue_info *q, unsigned int wrb_num) 62 { 63 return q->dma_mem.va + wrb_num * q->entry_size; 64 } 65 66 static inline void *queue_tail_node(struct be_queue_info *q) 67 { 68 return q->dma_mem.va + q->tail * q->entry_size; 69 } 70 71 static inline void queue_head_inc(struct be_queue_info *q) 72 { 73 index_inc(&q->head, q->len); 74 } 75 76 static inline void queue_tail_inc(struct be_queue_info *q) 77 { 78 index_inc(&q->tail, q->len); 79 } 80 81 /*ISCSI */ 82 83 struct be_aic_obj { /* Adaptive interrupt coalescing (AIC) info */ 84 u32 min_eqd; /* in usecs */ 85 u32 max_eqd; /* in usecs */ 86 u32 prev_eqd; /* in usecs */ 87 u32 et_eqd; /* configured val when aic is off */ 88 ulong jiffies; 89 u64 eq_prev; /* Used to calculate eqe */ 90 }; 91 92 struct be_eq_obj { 93 u32 cq_count; 94 struct be_queue_info q; 95 struct beiscsi_hba *phba; 96 struct be_queue_info *cq; 97 struct work_struct mcc_work; /* Work Item */ 98 struct irq_poll iopoll; 99 }; 100 101 struct be_mcc_obj { 102 struct be_queue_info q; 103 struct be_queue_info cq; 104 }; 105 106 struct beiscsi_mcc_tag_state { 107 unsigned long tag_state; 108 #define MCC_TAG_STATE_RUNNING 0 109 #define MCC_TAG_STATE_TIMEOUT 1 110 #define MCC_TAG_STATE_ASYNC 2 111 #define MCC_TAG_STATE_IGNORE 3 112 void (*cbfn)(struct beiscsi_hba *, unsigned int); 113 struct be_dma_mem tag_mem_state; 114 }; 115 116 struct be_ctrl_info { 117 u8 __iomem *csr; 118 u8 __iomem *db; /* Door Bell */ 119 u8 __iomem *pcicfg; /* PCI config space */ 120 struct pci_dev *pdev; 121 122 /* Mbox used for cmd request/response */ 123 struct mutex mbox_lock; /* For serializing mbox cmds to BE card */ 124 struct be_dma_mem mbox_mem; 125 /* Mbox mem is adjusted to align to 16 bytes. The allocated addr 126 * is stored for freeing purpose */ 127 struct be_dma_mem mbox_mem_alloced; 128 129 /* MCC Rings */ 130 struct be_mcc_obj mcc_obj; 131 spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */ 132 133 wait_queue_head_t mcc_wait[MAX_MCC_CMD + 1]; 134 unsigned int mcc_tag[MAX_MCC_CMD]; 135 unsigned int mcc_tag_status[MAX_MCC_CMD + 1]; 136 unsigned short mcc_alloc_index; 137 unsigned short mcc_free_index; 138 unsigned int mcc_tag_available; 139 140 struct beiscsi_mcc_tag_state ptag_state[MAX_MCC_CMD + 1]; 141 }; 142 143 #include "be_cmds.h" 144 145 /* WRB index mask for MCC_Q_LEN queue entries */ 146 #define MCC_Q_WRB_IDX_MASK CQE_STATUS_WRB_MASK 147 #define MCC_Q_WRB_IDX_SHIFT CQE_STATUS_WRB_SHIFT 148 /* TAG is from 1...MAX_MCC_CMD, MASK includes MAX_MCC_CMD */ 149 #define MCC_Q_CMD_TAG_MASK ((MAX_MCC_CMD << 1) - 1) 150 151 #define PAGE_SHIFT_4K 12 152 #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K) 153 #define mcc_timeout 120000 /* 12s timeout */ 154 155 /* Returns number of pages spanned by the data starting at the given addr */ 156 #define PAGES_4K_SPANNED(_address, size) \ 157 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \ 158 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K)) 159 160 /* Returns bit offset within a DWORD of a bitfield */ 161 #define AMAP_BIT_OFFSET(_struct, field) \ 162 (((size_t)&(((_struct *)0)->field))%32) 163 164 /* Returns the bit mask of the field that is NOT shifted into location. */ 165 static inline u32 amap_mask(u32 bitsize) 166 { 167 return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1); 168 } 169 170 static inline void amap_set(void *ptr, u32 dw_offset, u32 mask, 171 u32 offset, u32 value) 172 { 173 u32 *dw = (u32 *) ptr + dw_offset; 174 *dw &= ~(mask << offset); 175 *dw |= (mask & value) << offset; 176 } 177 178 #define AMAP_SET_BITS(_struct, field, ptr, val) \ 179 amap_set(ptr, \ 180 offsetof(_struct, field)/32, \ 181 amap_mask(sizeof(((_struct *)0)->field)), \ 182 AMAP_BIT_OFFSET(_struct, field), \ 183 val) 184 185 static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset) 186 { 187 u32 *dw = ptr; 188 return mask & (*(dw + dw_offset) >> offset); 189 } 190 191 #define AMAP_GET_BITS(_struct, field, ptr) \ 192 amap_get(ptr, \ 193 offsetof(_struct, field)/32, \ 194 amap_mask(sizeof(((_struct *)0)->field)), \ 195 AMAP_BIT_OFFSET(_struct, field)) 196 197 #define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len) 198 #define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len) 199 static inline void swap_dws(void *wrb, int len) 200 { 201 #ifdef __BIG_ENDIAN 202 u32 *dw = wrb; 203 WARN_ON(len % 4); 204 do { 205 *dw = cpu_to_le32(*dw); 206 dw++; 207 len -= 4; 208 } while (len); 209 #endif /* __BIG_ENDIAN */ 210 } 211 #endif /* BEISCSI_H */ 212