1 /** 2 * Copyright (C) 2005 - 2015 Emulex 3 * All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License version 2 7 * as published by the Free Software Foundation. The full GNU General 8 * Public License is included in this distribution in the file called COPYING. 9 * 10 * Contact Information: 11 * linux-drivers@avagotech.com 12 * 13 * Emulex 14 * 3333 Susan Street 15 * Costa Mesa, CA 92626 16 */ 17 18 #ifndef BEISCSI_H 19 #define BEISCSI_H 20 21 #include <linux/pci.h> 22 #include <linux/if_vlan.h> 23 #include <linux/irq_poll.h> 24 #define FW_VER_LEN 32 25 #define MCC_Q_LEN 128 26 #define MCC_CQ_LEN 256 27 #define MAX_MCC_CMD 16 28 /* BladeEngine Generation numbers */ 29 #define BE_GEN2 2 30 #define BE_GEN3 3 31 #define BE_GEN4 4 32 struct be_dma_mem { 33 void *va; 34 dma_addr_t dma; 35 u32 size; 36 }; 37 38 struct be_queue_info { 39 struct be_dma_mem dma_mem; 40 u16 len; 41 u16 entry_size; /* Size of an element in the queue */ 42 u16 id; 43 u16 tail, head; 44 bool created; 45 u16 used; /* Number of valid elements in the queue */ 46 }; 47 48 static inline u32 MODULO(u16 val, u16 limit) 49 { 50 WARN_ON(limit & (limit - 1)); 51 return val & (limit - 1); 52 } 53 54 static inline void index_inc(u16 *index, u16 limit) 55 { 56 *index = MODULO((*index + 1), limit); 57 } 58 59 static inline void *queue_head_node(struct be_queue_info *q) 60 { 61 return q->dma_mem.va + q->head * q->entry_size; 62 } 63 64 static inline void *queue_get_wrb(struct be_queue_info *q, unsigned int wrb_num) 65 { 66 return q->dma_mem.va + wrb_num * q->entry_size; 67 } 68 69 static inline void *queue_tail_node(struct be_queue_info *q) 70 { 71 return q->dma_mem.va + q->tail * q->entry_size; 72 } 73 74 static inline void queue_head_inc(struct be_queue_info *q) 75 { 76 index_inc(&q->head, q->len); 77 } 78 79 static inline void queue_tail_inc(struct be_queue_info *q) 80 { 81 index_inc(&q->tail, q->len); 82 } 83 84 /*ISCSI */ 85 86 struct be_aic_obj { /* Adaptive interrupt coalescing (AIC) info */ 87 bool enable; 88 u32 min_eqd; /* in usecs */ 89 u32 max_eqd; /* in usecs */ 90 u32 prev_eqd; /* in usecs */ 91 u32 et_eqd; /* configured val when aic is off */ 92 ulong jiffies; 93 u64 eq_prev; /* Used to calculate eqe */ 94 }; 95 96 struct be_eq_obj { 97 bool todo_mcc_cq; 98 bool todo_cq; 99 u32 cq_count; 100 struct be_queue_info q; 101 struct beiscsi_hba *phba; 102 struct be_queue_info *cq; 103 struct work_struct mcc_work; /* Work Item */ 104 struct irq_poll iopoll; 105 }; 106 107 struct be_mcc_obj { 108 struct be_queue_info q; 109 struct be_queue_info cq; 110 }; 111 112 struct beiscsi_mcc_tag_state { 113 unsigned long tag_state; 114 #define MCC_TAG_STATE_RUNNING 0 115 #define MCC_TAG_STATE_TIMEOUT 1 116 #define MCC_TAG_STATE_ASYNC 2 117 #define MCC_TAG_STATE_IGNORE 3 118 void (*cbfn)(struct beiscsi_hba *, unsigned int); 119 struct be_dma_mem tag_mem_state; 120 }; 121 122 struct be_ctrl_info { 123 u8 __iomem *csr; 124 u8 __iomem *db; /* Door Bell */ 125 u8 __iomem *pcicfg; /* PCI config space */ 126 struct pci_dev *pdev; 127 128 /* Mbox used for cmd request/response */ 129 struct mutex mbox_lock; /* For serializing mbox cmds to BE card */ 130 struct be_dma_mem mbox_mem; 131 /* Mbox mem is adjusted to align to 16 bytes. The allocated addr 132 * is stored for freeing purpose */ 133 struct be_dma_mem mbox_mem_alloced; 134 135 /* MCC Rings */ 136 struct be_mcc_obj mcc_obj; 137 spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */ 138 139 wait_queue_head_t mcc_wait[MAX_MCC_CMD + 1]; 140 unsigned int mcc_tag[MAX_MCC_CMD]; 141 unsigned int mcc_tag_status[MAX_MCC_CMD + 1]; 142 unsigned short mcc_alloc_index; 143 unsigned short mcc_free_index; 144 unsigned int mcc_tag_available; 145 146 struct beiscsi_mcc_tag_state ptag_state[MAX_MCC_CMD + 1]; 147 }; 148 149 #include "be_cmds.h" 150 151 /* WRB index mask for MCC_Q_LEN queue entries */ 152 #define MCC_Q_WRB_IDX_MASK CQE_STATUS_WRB_MASK 153 #define MCC_Q_WRB_IDX_SHIFT CQE_STATUS_WRB_SHIFT 154 /* TAG is from 1...MAX_MCC_CMD, MASK includes MAX_MCC_CMD */ 155 #define MCC_Q_CMD_TAG_MASK ((MAX_MCC_CMD << 1) - 1) 156 157 #define PAGE_SHIFT_4K 12 158 #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K) 159 #define mcc_timeout 120000 /* 12s timeout */ 160 #define BEISCSI_LOGOUT_SYNC_DELAY 250 161 162 /* Returns number of pages spanned by the data starting at the given addr */ 163 #define PAGES_4K_SPANNED(_address, size) \ 164 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \ 165 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K)) 166 167 /* Returns bit offset within a DWORD of a bitfield */ 168 #define AMAP_BIT_OFFSET(_struct, field) \ 169 (((size_t)&(((_struct *)0)->field))%32) 170 171 /* Returns the bit mask of the field that is NOT shifted into location. */ 172 static inline u32 amap_mask(u32 bitsize) 173 { 174 return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1); 175 } 176 177 static inline void amap_set(void *ptr, u32 dw_offset, u32 mask, 178 u32 offset, u32 value) 179 { 180 u32 *dw = (u32 *) ptr + dw_offset; 181 *dw &= ~(mask << offset); 182 *dw |= (mask & value) << offset; 183 } 184 185 #define AMAP_SET_BITS(_struct, field, ptr, val) \ 186 amap_set(ptr, \ 187 offsetof(_struct, field)/32, \ 188 amap_mask(sizeof(((_struct *)0)->field)), \ 189 AMAP_BIT_OFFSET(_struct, field), \ 190 val) 191 192 static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset) 193 { 194 u32 *dw = ptr; 195 return mask & (*(dw + dw_offset) >> offset); 196 } 197 198 #define AMAP_GET_BITS(_struct, field, ptr) \ 199 amap_get(ptr, \ 200 offsetof(_struct, field)/32, \ 201 amap_mask(sizeof(((_struct *)0)->field)), \ 202 AMAP_BIT_OFFSET(_struct, field)) 203 204 #define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len) 205 #define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len) 206 static inline void swap_dws(void *wrb, int len) 207 { 208 #ifdef __BIG_ENDIAN 209 u32 *dw = wrb; 210 WARN_ON(len % 4); 211 do { 212 *dw = cpu_to_le32(*dw); 213 dw++; 214 len -= 4; 215 } while (len); 216 #endif /* __BIG_ENDIAN */ 217 } 218 #endif /* BEISCSI_H */ 219