1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 1997 Wu Ching Chen 4 * 2.1.x update (C) 1998 Krzysztof G. Baranowski 5 * 2.5.x update (C) 2002 Red Hat 6 * 2.6.x update (C) 2004 Red Hat 7 * 8 * Marcelo Tosatti <marcelo@conectiva.com.br> : SMP fixes 9 * 10 * Wu Ching Chen : NULL pointer fixes 2000/06/02 11 * support atp876 chip 12 * enable 32 bit fifo transfer 13 * support cdrom & remove device run ultra speed 14 * fix disconnect bug 2000/12/21 15 * support atp880 chip lvd u160 2001/05/15 16 * fix prd table bug 2001/09/12 (7.1) 17 * 18 * atp885 support add by ACARD Hao Ping Lian 2005/01/05 19 */ 20 #include <linux/module.h> 21 #include <linux/init.h> 22 #include <linux/interrupt.h> 23 #include <linux/kernel.h> 24 #include <linux/types.h> 25 #include <linux/string.h> 26 #include <linux/ioport.h> 27 #include <linux/delay.h> 28 #include <linux/proc_fs.h> 29 #include <linux/spinlock.h> 30 #include <linux/pci.h> 31 #include <linux/blkdev.h> 32 #include <linux/dma-mapping.h> 33 #include <linux/slab.h> 34 #include <asm/io.h> 35 36 #include <scsi/scsi.h> 37 #include <scsi/scsi_cmnd.h> 38 #include <scsi/scsi_device.h> 39 #include <scsi/scsi_host.h> 40 41 #include "atp870u.h" 42 43 static struct scsi_host_template atp870u_template; 44 static void send_s870(struct atp_unit *dev,unsigned char c); 45 static void atp_is(struct atp_unit *dev, unsigned char c, bool wide_chip, 46 unsigned char lvdmode); 47 48 static inline void atp_writeb_base(struct atp_unit *atp, u8 reg, u8 val) 49 { 50 outb(val, atp->baseport + reg); 51 } 52 53 static inline void atp_writew_base(struct atp_unit *atp, u8 reg, u16 val) 54 { 55 outw(val, atp->baseport + reg); 56 } 57 58 static inline void atp_writeb_io(struct atp_unit *atp, u8 channel, u8 reg, u8 val) 59 { 60 outb(val, atp->ioport[channel] + reg); 61 } 62 63 static inline void atp_writew_io(struct atp_unit *atp, u8 channel, u8 reg, u16 val) 64 { 65 outw(val, atp->ioport[channel] + reg); 66 } 67 68 static inline void atp_writeb_pci(struct atp_unit *atp, u8 channel, u8 reg, u8 val) 69 { 70 outb(val, atp->pciport[channel] + reg); 71 } 72 73 static inline void atp_writel_pci(struct atp_unit *atp, u8 channel, u8 reg, u32 val) 74 { 75 outl(val, atp->pciport[channel] + reg); 76 } 77 78 static inline u8 atp_readb_base(struct atp_unit *atp, u8 reg) 79 { 80 return inb(atp->baseport + reg); 81 } 82 83 static inline u16 atp_readw_base(struct atp_unit *atp, u8 reg) 84 { 85 return inw(atp->baseport + reg); 86 } 87 88 static inline u32 atp_readl_base(struct atp_unit *atp, u8 reg) 89 { 90 return inl(atp->baseport + reg); 91 } 92 93 static inline u8 atp_readb_io(struct atp_unit *atp, u8 channel, u8 reg) 94 { 95 return inb(atp->ioport[channel] + reg); 96 } 97 98 static inline u16 atp_readw_io(struct atp_unit *atp, u8 channel, u8 reg) 99 { 100 return inw(atp->ioport[channel] + reg); 101 } 102 103 static inline u8 atp_readb_pci(struct atp_unit *atp, u8 channel, u8 reg) 104 { 105 return inb(atp->pciport[channel] + reg); 106 } 107 108 static inline bool is880(struct atp_unit *atp) 109 { 110 return atp->pdev->device == ATP880_DEVID1 || 111 atp->pdev->device == ATP880_DEVID2; 112 } 113 114 static inline bool is885(struct atp_unit *atp) 115 { 116 return atp->pdev->device == ATP885_DEVID; 117 } 118 119 static irqreturn_t atp870u_intr_handle(int irq, void *dev_id) 120 { 121 unsigned long flags; 122 unsigned short int id; 123 unsigned char i, j, c, target_id, lun,cmdp; 124 unsigned char *prd; 125 struct scsi_cmnd *workreq; 126 unsigned long adrcnt, k; 127 #ifdef ED_DBGP 128 unsigned long l; 129 #endif 130 struct Scsi_Host *host = dev_id; 131 struct atp_unit *dev = (struct atp_unit *)&host->hostdata; 132 133 for (c = 0; c < 2; c++) { 134 j = atp_readb_io(dev, c, 0x1f); 135 if ((j & 0x80) != 0) 136 break; 137 dev->in_int[c] = 0; 138 } 139 if ((j & 0x80) == 0) 140 return IRQ_NONE; 141 #ifdef ED_DBGP 142 printk("atp870u_intr_handle enter\n"); 143 #endif 144 dev->in_int[c] = 1; 145 cmdp = atp_readb_io(dev, c, 0x10); 146 if (dev->working[c] != 0) { 147 if (is885(dev)) { 148 if ((atp_readb_io(dev, c, 0x16) & 0x80) == 0) 149 atp_writeb_io(dev, c, 0x16, 150 (atp_readb_io(dev, c, 0x16) | 0x80)); 151 } 152 if ((atp_readb_pci(dev, c, 0x00) & 0x08) != 0) 153 { 154 for (k=0; k < 1000; k++) { 155 if ((atp_readb_pci(dev, c, 2) & 0x08) == 0) 156 break; 157 if ((atp_readb_pci(dev, c, 2) & 0x01) == 0) 158 break; 159 } 160 } 161 atp_writeb_pci(dev, c, 0, 0x00); 162 163 i = atp_readb_io(dev, c, 0x17); 164 165 if (is885(dev)) 166 atp_writeb_pci(dev, c, 2, 0x06); 167 168 target_id = atp_readb_io(dev, c, 0x15); 169 170 /* 171 * Remap wide devices onto id numbers 172 */ 173 174 if ((target_id & 0x40) != 0) { 175 target_id = (target_id & 0x07) | 0x08; 176 } else { 177 target_id &= 0x07; 178 } 179 180 if ((j & 0x40) != 0) { 181 if (dev->last_cmd[c] == 0xff) { 182 dev->last_cmd[c] = target_id; 183 } 184 dev->last_cmd[c] |= 0x40; 185 } 186 if (is885(dev)) 187 dev->r1f[c][target_id] |= j; 188 #ifdef ED_DBGP 189 printk("atp870u_intr_handle status = %x\n",i); 190 #endif 191 if (i == 0x85) { 192 if ((dev->last_cmd[c] & 0xf0) != 0x40) { 193 dev->last_cmd[c] = 0xff; 194 } 195 if (is885(dev)) { 196 adrcnt = 0; 197 ((unsigned char *) &adrcnt)[2] = 198 atp_readb_io(dev, c, 0x12); 199 ((unsigned char *) &adrcnt)[1] = 200 atp_readb_io(dev, c, 0x13); 201 ((unsigned char *) &adrcnt)[0] = 202 atp_readb_io(dev, c, 0x14); 203 if (dev->id[c][target_id].last_len != adrcnt) { 204 k = dev->id[c][target_id].last_len; 205 k -= adrcnt; 206 dev->id[c][target_id].tran_len = k; 207 dev->id[c][target_id].last_len = adrcnt; 208 } 209 #ifdef ED_DBGP 210 printk("dev->id[c][target_id].last_len = %d " 211 "dev->id[c][target_id].tran_len = %d\n", 212 dev->id[c][target_id].last_len, 213 dev->id[c][target_id].tran_len); 214 #endif 215 } 216 217 /* 218 * Flip wide 219 */ 220 if (dev->wide_id[c] != 0) { 221 atp_writeb_io(dev, c, 0x1b, 0x01); 222 while ((atp_readb_io(dev, c, 0x1b) & 0x01) != 0x01) 223 atp_writeb_io(dev, c, 0x1b, 0x01); 224 } 225 /* 226 * Issue more commands 227 */ 228 spin_lock_irqsave(dev->host->host_lock, flags); 229 if (((dev->quhd[c] != dev->quend[c]) || 230 (dev->last_cmd[c] != 0xff)) && 231 (dev->in_snd[c] == 0)) { 232 #ifdef ED_DBGP 233 printk("Call sent_s870\n"); 234 #endif 235 send_s870(dev,c); 236 } 237 spin_unlock_irqrestore(dev->host->host_lock, flags); 238 /* 239 * Done 240 */ 241 dev->in_int[c] = 0; 242 #ifdef ED_DBGP 243 printk("Status 0x85 return\n"); 244 #endif 245 return IRQ_HANDLED; 246 } 247 248 if (i == 0x40) { 249 dev->last_cmd[c] |= 0x40; 250 dev->in_int[c] = 0; 251 return IRQ_HANDLED; 252 } 253 254 if (i == 0x21) { 255 if ((dev->last_cmd[c] & 0xf0) != 0x40) { 256 dev->last_cmd[c] = 0xff; 257 } 258 adrcnt = 0; 259 ((unsigned char *) &adrcnt)[2] = 260 atp_readb_io(dev, c, 0x12); 261 ((unsigned char *) &adrcnt)[1] = 262 atp_readb_io(dev, c, 0x13); 263 ((unsigned char *) &adrcnt)[0] = 264 atp_readb_io(dev, c, 0x14); 265 k = dev->id[c][target_id].last_len; 266 k -= adrcnt; 267 dev->id[c][target_id].tran_len = k; 268 dev->id[c][target_id].last_len = adrcnt; 269 atp_writeb_io(dev, c, 0x10, 0x41); 270 atp_writeb_io(dev, c, 0x18, 0x08); 271 dev->in_int[c] = 0; 272 return IRQ_HANDLED; 273 } 274 275 if (is885(dev)) { 276 if ((i == 0x4c) || (i == 0x4d) || (i == 0x8c) || (i == 0x8d)) { 277 if ((i == 0x4c) || (i == 0x8c)) 278 i=0x48; 279 else 280 i=0x49; 281 } 282 } 283 if ((i == 0x80) || (i == 0x8f)) { 284 #ifdef ED_DBGP 285 printk(KERN_DEBUG "Device reselect\n"); 286 #endif 287 lun = 0; 288 if (cmdp == 0x44 || i == 0x80) 289 lun = atp_readb_io(dev, c, 0x1d) & 0x07; 290 else { 291 if ((dev->last_cmd[c] & 0xf0) != 0x40) { 292 dev->last_cmd[c] = 0xff; 293 } 294 if (cmdp == 0x41) { 295 #ifdef ED_DBGP 296 printk("cmdp = 0x41\n"); 297 #endif 298 adrcnt = 0; 299 ((unsigned char *) &adrcnt)[2] = 300 atp_readb_io(dev, c, 0x12); 301 ((unsigned char *) &adrcnt)[1] = 302 atp_readb_io(dev, c, 0x13); 303 ((unsigned char *) &adrcnt)[0] = 304 atp_readb_io(dev, c, 0x14); 305 k = dev->id[c][target_id].last_len; 306 k -= adrcnt; 307 dev->id[c][target_id].tran_len = k; 308 dev->id[c][target_id].last_len = adrcnt; 309 atp_writeb_io(dev, c, 0x18, 0x08); 310 dev->in_int[c] = 0; 311 return IRQ_HANDLED; 312 } else { 313 #ifdef ED_DBGP 314 printk("cmdp != 0x41\n"); 315 #endif 316 atp_writeb_io(dev, c, 0x10, 0x46); 317 dev->id[c][target_id].dirct = 0x00; 318 atp_writeb_io(dev, c, 0x12, 0x00); 319 atp_writeb_io(dev, c, 0x13, 0x00); 320 atp_writeb_io(dev, c, 0x14, 0x00); 321 atp_writeb_io(dev, c, 0x18, 0x08); 322 dev->in_int[c] = 0; 323 return IRQ_HANDLED; 324 } 325 } 326 if (dev->last_cmd[c] != 0xff) { 327 dev->last_cmd[c] |= 0x40; 328 } 329 if (is885(dev)) { 330 j = atp_readb_base(dev, 0x29) & 0xfe; 331 atp_writeb_base(dev, 0x29, j); 332 } else 333 atp_writeb_io(dev, c, 0x10, 0x45); 334 335 target_id = atp_readb_io(dev, c, 0x16); 336 /* 337 * Remap wide identifiers 338 */ 339 if ((target_id & 0x10) != 0) { 340 target_id = (target_id & 0x07) | 0x08; 341 } else { 342 target_id &= 0x07; 343 } 344 if (is885(dev)) 345 atp_writeb_io(dev, c, 0x10, 0x45); 346 workreq = dev->id[c][target_id].curr_req; 347 #ifdef ED_DBGP 348 scmd_printk(KERN_DEBUG, workreq, "CDB"); 349 for (l = 0; l < workreq->cmd_len; l++) 350 printk(KERN_DEBUG " %x",workreq->cmnd[l]); 351 printk("\n"); 352 #endif 353 354 atp_writeb_io(dev, c, 0x0f, lun); 355 atp_writeb_io(dev, c, 0x11, dev->id[c][target_id].devsp); 356 adrcnt = dev->id[c][target_id].tran_len; 357 k = dev->id[c][target_id].last_len; 358 359 atp_writeb_io(dev, c, 0x12, ((unsigned char *) &k)[2]); 360 atp_writeb_io(dev, c, 0x13, ((unsigned char *) &k)[1]); 361 atp_writeb_io(dev, c, 0x14, ((unsigned char *) &k)[0]); 362 #ifdef ED_DBGP 363 printk("k %x, k[0] 0x%x k[1] 0x%x k[2] 0x%x\n", k, 364 atp_readb_io(dev, c, 0x14), 365 atp_readb_io(dev, c, 0x13), 366 atp_readb_io(dev, c, 0x12)); 367 #endif 368 /* Remap wide */ 369 j = target_id; 370 if (target_id > 7) { 371 j = (j & 0x07) | 0x40; 372 } 373 /* Add direction */ 374 j |= dev->id[c][target_id].dirct; 375 atp_writeb_io(dev, c, 0x15, j); 376 atp_writeb_io(dev, c, 0x16, 0x80); 377 378 /* enable 32 bit fifo transfer */ 379 if (is885(dev)) { 380 i = atp_readb_pci(dev, c, 1) & 0xf3; 381 //j=workreq->cmnd[0]; 382 if ((workreq->cmnd[0] == READ_6) || 383 (workreq->cmnd[0] == READ_10) || 384 (workreq->cmnd[0] == WRITE_6) || 385 (workreq->cmnd[0] == WRITE_10)) { 386 i |= 0x0c; 387 } 388 atp_writeb_pci(dev, c, 1, i); 389 } else if (is880(dev)) { 390 if ((workreq->cmnd[0] == READ_6) || 391 (workreq->cmnd[0] == READ_10) || 392 (workreq->cmnd[0] == WRITE_6) || 393 (workreq->cmnd[0] == WRITE_10)) 394 atp_writeb_base(dev, 0x3b, 395 (atp_readb_base(dev, 0x3b) & 0x3f) | 0xc0); 396 else 397 atp_writeb_base(dev, 0x3b, 398 atp_readb_base(dev, 0x3b) & 0x3f); 399 } else { 400 if ((workreq->cmnd[0] == READ_6) || 401 (workreq->cmnd[0] == READ_10) || 402 (workreq->cmnd[0] == WRITE_6) || 403 (workreq->cmnd[0] == WRITE_10)) 404 atp_writeb_base(dev, 0x3a, 405 (atp_readb_base(dev, 0x3a) & 0xf3) | 0x08); 406 else 407 atp_writeb_base(dev, 0x3a, 408 atp_readb_base(dev, 0x3a) & 0xf3); 409 } 410 j = 0; 411 id = 1; 412 id = id << target_id; 413 /* 414 * Is this a wide device 415 */ 416 if ((id & dev->wide_id[c]) != 0) { 417 j |= 0x01; 418 } 419 atp_writeb_io(dev, c, 0x1b, j); 420 while ((atp_readb_io(dev, c, 0x1b) & 0x01) != j) 421 atp_writeb_io(dev, c, 0x1b, j); 422 if (dev->id[c][target_id].last_len == 0) { 423 atp_writeb_io(dev, c, 0x18, 0x08); 424 dev->in_int[c] = 0; 425 #ifdef ED_DBGP 426 printk("dev->id[c][target_id].last_len = 0\n"); 427 #endif 428 return IRQ_HANDLED; 429 } 430 #ifdef ED_DBGP 431 printk("target_id = %d adrcnt = %d\n",target_id,adrcnt); 432 #endif 433 prd = dev->id[c][target_id].prd_pos; 434 while (adrcnt != 0) { 435 id = ((unsigned short int *)prd)[2]; 436 if (id == 0) { 437 k = 0x10000; 438 } else { 439 k = id; 440 } 441 if (k > adrcnt) { 442 ((unsigned short int *)prd)[2] = 443 (unsigned short int)(k - adrcnt); 444 ((unsigned long *)prd)[0] += adrcnt; 445 adrcnt = 0; 446 dev->id[c][target_id].prd_pos = prd; 447 } else { 448 adrcnt -= k; 449 dev->id[c][target_id].prdaddr += 0x08; 450 prd += 0x08; 451 if (adrcnt == 0) { 452 dev->id[c][target_id].prd_pos = prd; 453 } 454 } 455 } 456 atp_writel_pci(dev, c, 0x04, dev->id[c][target_id].prdaddr); 457 #ifdef ED_DBGP 458 printk("dev->id[%d][%d].prdaddr 0x%8x\n", 459 c, target_id, dev->id[c][target_id].prdaddr); 460 #endif 461 if (!is885(dev)) { 462 atp_writeb_pci(dev, c, 2, 0x06); 463 atp_writeb_pci(dev, c, 2, 0x00); 464 } 465 /* 466 * Check transfer direction 467 */ 468 if (dev->id[c][target_id].dirct != 0) { 469 atp_writeb_io(dev, c, 0x18, 0x08); 470 atp_writeb_pci(dev, c, 0, 0x01); 471 dev->in_int[c] = 0; 472 #ifdef ED_DBGP 473 printk("status 0x80 return dirct != 0\n"); 474 #endif 475 return IRQ_HANDLED; 476 } 477 atp_writeb_io(dev, c, 0x18, 0x08); 478 atp_writeb_pci(dev, c, 0, 0x09); 479 dev->in_int[c] = 0; 480 #ifdef ED_DBGP 481 printk("status 0x80 return dirct = 0\n"); 482 #endif 483 return IRQ_HANDLED; 484 } 485 486 /* 487 * Current scsi request on this target 488 */ 489 490 workreq = dev->id[c][target_id].curr_req; 491 492 if (i == 0x42 || i == 0x16) { 493 if ((dev->last_cmd[c] & 0xf0) != 0x40) { 494 dev->last_cmd[c] = 0xff; 495 } 496 if (i == 0x16) { 497 workreq->result = atp_readb_io(dev, c, 0x0f); 498 if (((dev->r1f[c][target_id] & 0x10) != 0) && is885(dev)) { 499 printk(KERN_WARNING "AEC67162 CRC ERROR !\n"); 500 workreq->result = SAM_STAT_CHECK_CONDITION; 501 } 502 } else 503 workreq->result = SAM_STAT_CHECK_CONDITION; 504 505 if (is885(dev)) { 506 j = atp_readb_base(dev, 0x29) | 0x01; 507 atp_writeb_base(dev, 0x29, j); 508 } 509 /* 510 * Complete the command 511 */ 512 scsi_dma_unmap(workreq); 513 514 spin_lock_irqsave(dev->host->host_lock, flags); 515 (*workreq->scsi_done) (workreq); 516 #ifdef ED_DBGP 517 printk("workreq->scsi_done\n"); 518 #endif 519 /* 520 * Clear it off the queue 521 */ 522 dev->id[c][target_id].curr_req = NULL; 523 dev->working[c]--; 524 spin_unlock_irqrestore(dev->host->host_lock, flags); 525 /* 526 * Take it back wide 527 */ 528 if (dev->wide_id[c] != 0) { 529 atp_writeb_io(dev, c, 0x1b, 0x01); 530 while ((atp_readb_io(dev, c, 0x1b) & 0x01) != 0x01) 531 atp_writeb_io(dev, c, 0x1b, 0x01); 532 } 533 /* 534 * If there is stuff to send and nothing going then send it 535 */ 536 spin_lock_irqsave(dev->host->host_lock, flags); 537 if (((dev->last_cmd[c] != 0xff) || 538 (dev->quhd[c] != dev->quend[c])) && 539 (dev->in_snd[c] == 0)) { 540 #ifdef ED_DBGP 541 printk("Call sent_s870(scsi_done)\n"); 542 #endif 543 send_s870(dev,c); 544 } 545 spin_unlock_irqrestore(dev->host->host_lock, flags); 546 dev->in_int[c] = 0; 547 return IRQ_HANDLED; 548 } 549 if ((dev->last_cmd[c] & 0xf0) != 0x40) { 550 dev->last_cmd[c] = 0xff; 551 } 552 if (i == 0x4f) { 553 i = 0x89; 554 } 555 i &= 0x0f; 556 if (i == 0x09) { 557 atp_writel_pci(dev, c, 4, dev->id[c][target_id].prdaddr); 558 atp_writeb_pci(dev, c, 2, 0x06); 559 atp_writeb_pci(dev, c, 2, 0x00); 560 atp_writeb_io(dev, c, 0x10, 0x41); 561 if (is885(dev)) { 562 k = dev->id[c][target_id].last_len; 563 atp_writeb_io(dev, c, 0x12, 564 ((unsigned char *) (&k))[2]); 565 atp_writeb_io(dev, c, 0x13, 566 ((unsigned char *) (&k))[1]); 567 atp_writeb_io(dev, c, 0x14, 568 ((unsigned char *) (&k))[0]); 569 dev->id[c][target_id].dirct = 0x00; 570 } else { 571 dev->id[c][target_id].dirct = 0x00; 572 } 573 atp_writeb_io(dev, c, 0x18, 0x08); 574 atp_writeb_pci(dev, c, 0, 0x09); 575 dev->in_int[c] = 0; 576 return IRQ_HANDLED; 577 } 578 if (i == 0x08) { 579 atp_writel_pci(dev, c, 4, dev->id[c][target_id].prdaddr); 580 atp_writeb_pci(dev, c, 2, 0x06); 581 atp_writeb_pci(dev, c, 2, 0x00); 582 atp_writeb_io(dev, c, 0x10, 0x41); 583 if (is885(dev)) { 584 k = dev->id[c][target_id].last_len; 585 atp_writeb_io(dev, c, 0x12, 586 ((unsigned char *) (&k))[2]); 587 atp_writeb_io(dev, c, 0x13, 588 ((unsigned char *) (&k))[1]); 589 atp_writeb_io(dev, c, 0x14, 590 ((unsigned char *) (&k))[0]); 591 } 592 atp_writeb_io(dev, c, 0x15, 593 atp_readb_io(dev, c, 0x15) | 0x20); 594 dev->id[c][target_id].dirct = 0x20; 595 atp_writeb_io(dev, c, 0x18, 0x08); 596 atp_writeb_pci(dev, c, 0, 0x01); 597 dev->in_int[c] = 0; 598 return IRQ_HANDLED; 599 } 600 if (i == 0x0a) 601 atp_writeb_io(dev, c, 0x10, 0x30); 602 else 603 atp_writeb_io(dev, c, 0x10, 0x46); 604 dev->id[c][target_id].dirct = 0x00; 605 atp_writeb_io(dev, c, 0x12, 0x00); 606 atp_writeb_io(dev, c, 0x13, 0x00); 607 atp_writeb_io(dev, c, 0x14, 0x00); 608 atp_writeb_io(dev, c, 0x18, 0x08); 609 } 610 dev->in_int[c] = 0; 611 612 return IRQ_HANDLED; 613 } 614 /** 615 * atp870u_queuecommand - Queue SCSI command 616 * @req_p: request block 617 * @done: completion function 618 * 619 * Queue a command to the ATP queue. Called with the host lock held. 620 */ 621 static int atp870u_queuecommand_lck(struct scsi_cmnd *req_p, 622 void (*done) (struct scsi_cmnd *)) 623 { 624 unsigned char c; 625 unsigned int m; 626 struct atp_unit *dev; 627 struct Scsi_Host *host; 628 629 c = scmd_channel(req_p); 630 req_p->sense_buffer[0]=0; 631 scsi_set_resid(req_p, 0); 632 if (scmd_channel(req_p) > 1) { 633 req_p->result = DID_BAD_TARGET << 16; 634 done(req_p); 635 #ifdef ED_DBGP 636 printk("atp870u_queuecommand : req_p->device->channel > 1\n"); 637 #endif 638 return 0; 639 } 640 641 host = req_p->device->host; 642 dev = (struct atp_unit *)&host->hostdata; 643 644 m = 1; 645 m = m << scmd_id(req_p); 646 647 /* 648 * Fake a timeout for missing targets 649 */ 650 651 if ((m & dev->active_id[c]) == 0) { 652 req_p->result = DID_BAD_TARGET << 16; 653 done(req_p); 654 return 0; 655 } 656 657 if (done) { 658 req_p->scsi_done = done; 659 } else { 660 #ifdef ED_DBGP 661 printk( "atp870u_queuecommand: done can't be NULL\n"); 662 #endif 663 req_p->result = 0; 664 done(req_p); 665 return 0; 666 } 667 668 /* 669 * Count new command 670 */ 671 dev->quend[c]++; 672 if (dev->quend[c] >= qcnt) { 673 dev->quend[c] = 0; 674 } 675 676 /* 677 * Check queue state 678 */ 679 if (dev->quhd[c] == dev->quend[c]) { 680 if (dev->quend[c] == 0) { 681 dev->quend[c] = qcnt; 682 } 683 #ifdef ED_DBGP 684 printk("atp870u_queuecommand : dev->quhd[c] == dev->quend[c]\n"); 685 #endif 686 dev->quend[c]--; 687 req_p->result = DID_BUS_BUSY << 16; 688 done(req_p); 689 return 0; 690 } 691 dev->quereq[c][dev->quend[c]] = req_p; 692 #ifdef ED_DBGP 693 printk("dev->ioport[c] = %x atp_readb_io(dev, c, 0x1c) = %x " 694 "dev->in_int[%d] = %d dev->in_snd[%d] = %d\n", 695 dev->ioport[c], atp_readb_io(dev, c, 0x1c), c, 696 dev->in_int[c],c,dev->in_snd[c]); 697 #endif 698 if ((atp_readb_io(dev, c, 0x1c) == 0) && 699 (dev->in_int[c] == 0) && 700 (dev->in_snd[c] == 0)) { 701 #ifdef ED_DBGP 702 printk("Call sent_s870(atp870u_queuecommand)\n"); 703 #endif 704 send_s870(dev,c); 705 } 706 #ifdef ED_DBGP 707 printk("atp870u_queuecommand : exit\n"); 708 #endif 709 return 0; 710 } 711 712 static DEF_SCSI_QCMD(atp870u_queuecommand) 713 714 /** 715 * send_s870 - send a command to the controller 716 * @host: host 717 * 718 * On entry there is work queued to be done. We move some of that work to the 719 * controller itself. 720 * 721 * Caller holds the host lock. 722 */ 723 static void send_s870(struct atp_unit *dev,unsigned char c) 724 { 725 struct scsi_cmnd *workreq = NULL; 726 unsigned int i;//,k; 727 unsigned char j, target_id; 728 unsigned char *prd; 729 unsigned short int w; 730 unsigned long l, bttl = 0; 731 unsigned long sg_count; 732 733 if (dev->in_snd[c] != 0) { 734 #ifdef ED_DBGP 735 printk("cmnd in_snd\n"); 736 #endif 737 return; 738 } 739 #ifdef ED_DBGP 740 printk("Sent_s870 enter\n"); 741 #endif 742 dev->in_snd[c] = 1; 743 if ((dev->last_cmd[c] != 0xff) && ((dev->last_cmd[c] & 0x40) != 0)) { 744 dev->last_cmd[c] &= 0x0f; 745 workreq = dev->id[c][dev->last_cmd[c]].curr_req; 746 if (!workreq) { 747 dev->last_cmd[c] = 0xff; 748 if (dev->quhd[c] == dev->quend[c]) { 749 dev->in_snd[c] = 0; 750 return; 751 } 752 } 753 } 754 if (!workreq) { 755 if ((dev->last_cmd[c] != 0xff) && (dev->working[c] != 0)) { 756 dev->in_snd[c] = 0; 757 return; 758 } 759 dev->working[c]++; 760 j = dev->quhd[c]; 761 dev->quhd[c]++; 762 if (dev->quhd[c] >= qcnt) 763 dev->quhd[c] = 0; 764 workreq = dev->quereq[c][dev->quhd[c]]; 765 if (dev->id[c][scmd_id(workreq)].curr_req != NULL) { 766 dev->quhd[c] = j; 767 dev->working[c]--; 768 dev->in_snd[c] = 0; 769 return; 770 } 771 dev->id[c][scmd_id(workreq)].curr_req = workreq; 772 dev->last_cmd[c] = scmd_id(workreq); 773 } 774 if ((atp_readb_io(dev, c, 0x1f) & 0xb0) != 0 || 775 atp_readb_io(dev, c, 0x1c) != 0) { 776 #ifdef ED_DBGP 777 printk("Abort to Send\n"); 778 #endif 779 dev->last_cmd[c] |= 0x40; 780 dev->in_snd[c] = 0; 781 return; 782 } 783 #ifdef ED_DBGP 784 printk("OK to Send\n"); 785 scmd_printk(KERN_DEBUG, workreq, "CDB"); 786 for(i=0;i<workreq->cmd_len;i++) { 787 printk(" %x",workreq->cmnd[i]); 788 } 789 printk("\n"); 790 #endif 791 l = scsi_bufflen(workreq); 792 793 if (is885(dev)) { 794 j = atp_readb_base(dev, 0x29) & 0xfe; 795 atp_writeb_base(dev, 0x29, j); 796 dev->r1f[c][scmd_id(workreq)] = 0; 797 } 798 799 if (workreq->cmnd[0] == READ_CAPACITY) { 800 if (l > 8) 801 l = 8; 802 } 803 if (workreq->cmnd[0] == TEST_UNIT_READY) { 804 l = 0; 805 } 806 807 j = 0; 808 target_id = scmd_id(workreq); 809 810 /* 811 * Wide ? 812 */ 813 w = 1; 814 w = w << target_id; 815 if ((w & dev->wide_id[c]) != 0) { 816 j |= 0x01; 817 } 818 atp_writeb_io(dev, c, 0x1b, j); 819 while ((atp_readb_io(dev, c, 0x1b) & 0x01) != j) { 820 atp_writeb_pci(dev, c, 0x1b, j); 821 #ifdef ED_DBGP 822 printk("send_s870 while loop 1\n"); 823 #endif 824 } 825 /* 826 * Write the command 827 */ 828 829 atp_writeb_io(dev, c, 0x00, workreq->cmd_len); 830 atp_writeb_io(dev, c, 0x01, 0x2c); 831 if (is885(dev)) 832 atp_writeb_io(dev, c, 0x02, 0x7f); 833 else 834 atp_writeb_io(dev, c, 0x02, 0xcf); 835 for (i = 0; i < workreq->cmd_len; i++) 836 atp_writeb_io(dev, c, 0x03 + i, workreq->cmnd[i]); 837 atp_writeb_io(dev, c, 0x0f, workreq->device->lun); 838 /* 839 * Write the target 840 */ 841 atp_writeb_io(dev, c, 0x11, dev->id[c][target_id].devsp); 842 #ifdef ED_DBGP 843 printk("dev->id[%d][%d].devsp = %2x\n",c,target_id, 844 dev->id[c][target_id].devsp); 845 #endif 846 847 sg_count = scsi_dma_map(workreq); 848 /* 849 * Write transfer size 850 */ 851 atp_writeb_io(dev, c, 0x12, ((unsigned char *) (&l))[2]); 852 atp_writeb_io(dev, c, 0x13, ((unsigned char *) (&l))[1]); 853 atp_writeb_io(dev, c, 0x14, ((unsigned char *) (&l))[0]); 854 j = target_id; 855 dev->id[c][j].last_len = l; 856 dev->id[c][j].tran_len = 0; 857 #ifdef ED_DBGP 858 printk("dev->id[%2d][%2d].last_len = %d\n",c,j,dev->id[c][j].last_len); 859 #endif 860 /* 861 * Flip the wide bits 862 */ 863 if ((j & 0x08) != 0) { 864 j = (j & 0x07) | 0x40; 865 } 866 /* 867 * Check transfer direction 868 */ 869 if (workreq->sc_data_direction == DMA_TO_DEVICE) 870 atp_writeb_io(dev, c, 0x15, j | 0x20); 871 else 872 atp_writeb_io(dev, c, 0x15, j); 873 atp_writeb_io(dev, c, 0x16, atp_readb_io(dev, c, 0x16) | 0x80); 874 atp_writeb_io(dev, c, 0x16, 0x80); 875 dev->id[c][target_id].dirct = 0; 876 if (l == 0) { 877 if (atp_readb_io(dev, c, 0x1c) == 0) { 878 #ifdef ED_DBGP 879 printk("change SCSI_CMD_REG 0x08\n"); 880 #endif 881 atp_writeb_io(dev, c, 0x18, 0x08); 882 } else 883 dev->last_cmd[c] |= 0x40; 884 dev->in_snd[c] = 0; 885 return; 886 } 887 prd = dev->id[c][target_id].prd_table; 888 dev->id[c][target_id].prd_pos = prd; 889 890 /* 891 * Now write the request list. Either as scatter/gather or as 892 * a linear chain. 893 */ 894 895 if (l) { 896 struct scatterlist *sgpnt; 897 i = 0; 898 scsi_for_each_sg(workreq, sgpnt, sg_count, j) { 899 bttl = sg_dma_address(sgpnt); 900 l=sg_dma_len(sgpnt); 901 #ifdef ED_DBGP 902 printk("1. bttl %x, l %x\n",bttl, l); 903 #endif 904 while (l > 0x10000) { 905 (((u16 *) (prd))[i + 3]) = 0x0000; 906 (((u16 *) (prd))[i + 2]) = 0x0000; 907 (((u32 *) (prd))[i >> 1]) = cpu_to_le32(bttl); 908 l -= 0x10000; 909 bttl += 0x10000; 910 i += 0x04; 911 } 912 (((u32 *) (prd))[i >> 1]) = cpu_to_le32(bttl); 913 (((u16 *) (prd))[i + 2]) = cpu_to_le16(l); 914 (((u16 *) (prd))[i + 3]) = 0; 915 i += 0x04; 916 } 917 (((u16 *) (prd))[i - 1]) = cpu_to_le16(0x8000); 918 #ifdef ED_DBGP 919 printk("prd %4x %4x %4x %4x\n", 920 (((unsigned short int *)prd)[0]), 921 (((unsigned short int *)prd)[1]), 922 (((unsigned short int *)prd)[2]), 923 (((unsigned short int *)prd)[3])); 924 printk("2. bttl %x, l %x\n",bttl, l); 925 #endif 926 } 927 #ifdef ED_DBGP 928 printk("send_s870: prdaddr_2 0x%8x target_id %d\n", 929 dev->id[c][target_id].prdaddr,target_id); 930 #endif 931 dev->id[c][target_id].prdaddr = dev->id[c][target_id].prd_bus; 932 atp_writel_pci(dev, c, 4, dev->id[c][target_id].prdaddr); 933 atp_writeb_pci(dev, c, 2, 0x06); 934 atp_writeb_pci(dev, c, 2, 0x00); 935 if (is885(dev)) { 936 j = atp_readb_pci(dev, c, 1) & 0xf3; 937 if ((workreq->cmnd[0] == READ_6) || 938 (workreq->cmnd[0] == READ_10) || 939 (workreq->cmnd[0] == WRITE_6) || 940 (workreq->cmnd[0] == WRITE_10)) { 941 j |= 0x0c; 942 } 943 atp_writeb_pci(dev, c, 1, j); 944 } else if (is880(dev)) { 945 if ((workreq->cmnd[0] == READ_6) || 946 (workreq->cmnd[0] == READ_10) || 947 (workreq->cmnd[0] == WRITE_6) || 948 (workreq->cmnd[0] == WRITE_10)) 949 atp_writeb_base(dev, 0x3b, 950 (atp_readb_base(dev, 0x3b) & 0x3f) | 0xc0); 951 else 952 atp_writeb_base(dev, 0x3b, 953 atp_readb_base(dev, 0x3b) & 0x3f); 954 } else { 955 if ((workreq->cmnd[0] == READ_6) || 956 (workreq->cmnd[0] == READ_10) || 957 (workreq->cmnd[0] == WRITE_6) || 958 (workreq->cmnd[0] == WRITE_10)) 959 atp_writeb_base(dev, 0x3a, 960 (atp_readb_base(dev, 0x3a) & 0xf3) | 0x08); 961 else 962 atp_writeb_base(dev, 0x3a, 963 atp_readb_base(dev, 0x3a) & 0xf3); 964 } 965 966 if(workreq->sc_data_direction == DMA_TO_DEVICE) { 967 dev->id[c][target_id].dirct = 0x20; 968 if (atp_readb_io(dev, c, 0x1c) == 0) { 969 atp_writeb_io(dev, c, 0x18, 0x08); 970 atp_writeb_pci(dev, c, 0, 0x01); 971 #ifdef ED_DBGP 972 printk( "start DMA(to target)\n"); 973 #endif 974 } else { 975 dev->last_cmd[c] |= 0x40; 976 } 977 dev->in_snd[c] = 0; 978 return; 979 } 980 if (atp_readb_io(dev, c, 0x1c) == 0) { 981 atp_writeb_io(dev, c, 0x18, 0x08); 982 atp_writeb_pci(dev, c, 0, 0x09); 983 #ifdef ED_DBGP 984 printk( "start DMA(to host)\n"); 985 #endif 986 } else { 987 dev->last_cmd[c] |= 0x40; 988 } 989 dev->in_snd[c] = 0; 990 return; 991 992 } 993 994 static unsigned char fun_scam(struct atp_unit *dev, unsigned short int *val) 995 { 996 unsigned short int i, k; 997 unsigned char j; 998 999 atp_writew_io(dev, 0, 0x1c, *val); 1000 for (i = 0; i < 10; i++) { /* stable >= bus settle delay(400 ns) */ 1001 k = atp_readw_io(dev, 0, 0x1c); 1002 j = (unsigned char) (k >> 8); 1003 if ((k & 0x8000) != 0) /* DB7 all release? */ 1004 i = 0; 1005 } 1006 *val |= 0x4000; /* assert DB6 */ 1007 atp_writew_io(dev, 0, 0x1c, *val); 1008 *val &= 0xdfff; /* assert DB5 */ 1009 atp_writew_io(dev, 0, 0x1c, *val); 1010 for (i = 0; i < 10; i++) { /* stable >= bus settle delay(400 ns) */ 1011 if ((atp_readw_io(dev, 0, 0x1c) & 0x2000) != 0) /* DB5 all release? */ 1012 i = 0; 1013 } 1014 *val |= 0x8000; /* no DB4-0, assert DB7 */ 1015 *val &= 0xe0ff; 1016 atp_writew_io(dev, 0, 0x1c, *val); 1017 *val &= 0xbfff; /* release DB6 */ 1018 atp_writew_io(dev, 0, 0x1c, *val); 1019 for (i = 0; i < 10; i++) { /* stable >= bus settle delay(400 ns) */ 1020 if ((atp_readw_io(dev, 0, 0x1c) & 0x4000) != 0) /* DB6 all release? */ 1021 i = 0; 1022 } 1023 1024 return j; 1025 } 1026 1027 static void tscam(struct Scsi_Host *host, bool wide_chip, u8 scam_on) 1028 { 1029 1030 unsigned char i, j, k; 1031 unsigned long n; 1032 unsigned short int m, assignid_map, val; 1033 unsigned char mbuf[33], quintet[2]; 1034 struct atp_unit *dev = (struct atp_unit *)&host->hostdata; 1035 static unsigned char g2q_tab[8] = { 1036 0x38, 0x31, 0x32, 0x2b, 0x34, 0x2d, 0x2e, 0x27 1037 }; 1038 1039 /* I can't believe we need this before we've even done anything. Remove it 1040 * and see if anyone bitches. 1041 for (i = 0; i < 0x10; i++) { 1042 udelay(0xffff); 1043 } 1044 */ 1045 1046 atp_writeb_io(dev, 0, 1, 0x08); 1047 atp_writeb_io(dev, 0, 2, 0x7f); 1048 atp_writeb_io(dev, 0, 0x11, 0x20); 1049 1050 if ((scam_on & 0x40) == 0) { 1051 return; 1052 } 1053 m = 1; 1054 m <<= dev->host_id[0]; 1055 j = 16; 1056 if (!wide_chip) { 1057 m |= 0xff00; 1058 j = 8; 1059 } 1060 assignid_map = m; 1061 atp_writeb_io(dev, 0, 0x02, 0x02); /* 2*2=4ms,3EH 2/32*3E=3.9ms */ 1062 atp_writeb_io(dev, 0, 0x03, 0); 1063 atp_writeb_io(dev, 0, 0x04, 0); 1064 atp_writeb_io(dev, 0, 0x05, 0); 1065 atp_writeb_io(dev, 0, 0x06, 0); 1066 atp_writeb_io(dev, 0, 0x07, 0); 1067 atp_writeb_io(dev, 0, 0x08, 0); 1068 1069 for (i = 0; i < j; i++) { 1070 m = 1; 1071 m = m << i; 1072 if ((m & assignid_map) != 0) { 1073 continue; 1074 } 1075 atp_writeb_io(dev, 0, 0x0f, 0); 1076 atp_writeb_io(dev, 0, 0x12, 0); 1077 atp_writeb_io(dev, 0, 0x13, 0); 1078 atp_writeb_io(dev, 0, 0x14, 0); 1079 if (i > 7) { 1080 k = (i & 0x07) | 0x40; 1081 } else { 1082 k = i; 1083 } 1084 atp_writeb_io(dev, 0, 0x15, k); 1085 if (wide_chip) 1086 atp_writeb_io(dev, 0, 0x1b, 0x01); 1087 else 1088 atp_writeb_io(dev, 0, 0x1b, 0x00); 1089 do { 1090 atp_writeb_io(dev, 0, 0x18, 0x09); 1091 1092 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0x00) 1093 cpu_relax(); 1094 k = atp_readb_io(dev, 0, 0x17); 1095 if ((k == 0x85) || (k == 0x42)) 1096 break; 1097 if (k != 0x16) 1098 atp_writeb_io(dev, 0, 0x10, 0x41); 1099 } while (k != 0x16); 1100 if ((k == 0x85) || (k == 0x42)) 1101 continue; 1102 assignid_map |= m; 1103 1104 } 1105 atp_writeb_io(dev, 0, 0x02, 0x7f); 1106 atp_writeb_io(dev, 0, 0x1b, 0x02); 1107 1108 udelay(2); 1109 1110 val = 0x0080; /* bsy */ 1111 atp_writew_io(dev, 0, 0x1c, val); 1112 val |= 0x0040; /* sel */ 1113 atp_writew_io(dev, 0, 0x1c, val); 1114 val |= 0x0004; /* msg */ 1115 atp_writew_io(dev, 0, 0x1c, val); 1116 udelay(2); /* 2 deskew delay(45ns*2=90ns) */ 1117 val &= 0x007f; /* no bsy */ 1118 atp_writew_io(dev, 0, 0x1c, val); 1119 msleep(128); 1120 val &= 0x00fb; /* after 1ms no msg */ 1121 atp_writew_io(dev, 0, 0x1c, val); 1122 while ((atp_readb_io(dev, 0, 0x1c) & 0x04) != 0) 1123 ; 1124 udelay(2); 1125 udelay(100); 1126 for (n = 0; n < 0x30000; n++) 1127 if ((atp_readb_io(dev, 0, 0x1c) & 0x80) != 0) /* bsy ? */ 1128 break; 1129 if (n < 0x30000) 1130 for (n = 0; n < 0x30000; n++) 1131 if ((atp_readb_io(dev, 0, 0x1c) & 0x81) == 0x0081) { 1132 udelay(2); 1133 val |= 0x8003; /* io,cd,db7 */ 1134 atp_writew_io(dev, 0, 0x1c, val); 1135 udelay(2); 1136 val &= 0x00bf; /* no sel */ 1137 atp_writew_io(dev, 0, 0x1c, val); 1138 udelay(2); 1139 break; 1140 } 1141 while (1) { 1142 /* 1143 * The funny division into multiple delays is to accomodate 1144 * arches like ARM where udelay() multiplies its argument by 1145 * a large number to initialize a loop counter. To avoid 1146 * overflow, the maximum supported udelay is 2000 microseconds. 1147 * 1148 * XXX it would be more polite to find a way to use msleep() 1149 */ 1150 mdelay(2); 1151 udelay(48); 1152 if ((atp_readb_io(dev, 0, 0x1c) & 0x80) == 0x00) { /* bsy ? */ 1153 atp_writew_io(dev, 0, 0x1c, 0); 1154 atp_writeb_io(dev, 0, 0x1b, 0); 1155 atp_writeb_io(dev, 0, 0x15, 0); 1156 atp_writeb_io(dev, 0, 0x18, 0x09); 1157 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0) 1158 cpu_relax(); 1159 atp_readb_io(dev, 0, 0x17); 1160 return; 1161 } 1162 val &= 0x00ff; /* synchronization */ 1163 val |= 0x3f00; 1164 fun_scam(dev, &val); 1165 udelay(2); 1166 val &= 0x00ff; /* isolation */ 1167 val |= 0x2000; 1168 fun_scam(dev, &val); 1169 udelay(2); 1170 i = 8; 1171 j = 0; 1172 1173 while (1) { 1174 if ((atp_readw_io(dev, 0, 0x1c) & 0x2000) == 0) 1175 continue; 1176 udelay(2); 1177 val &= 0x00ff; /* get ID_STRING */ 1178 val |= 0x2000; 1179 k = fun_scam(dev, &val); 1180 if ((k & 0x03) == 0) 1181 break; 1182 mbuf[j] <<= 0x01; 1183 mbuf[j] &= 0xfe; 1184 if ((k & 0x02) != 0) 1185 mbuf[j] |= 0x01; 1186 i--; 1187 if (i > 0) 1188 continue; 1189 j++; 1190 i = 8; 1191 } 1192 1193 /* isolation complete.. */ 1194 /* mbuf[32]=0; 1195 printk(" \n%x %x %x %s\n ",assignid_map,mbuf[0],mbuf[1],&mbuf[2]); */ 1196 i = 15; 1197 j = mbuf[0]; 1198 if ((j & 0x20) != 0) { /* bit5=1:ID up to 7 */ 1199 i = 7; 1200 } 1201 if ((j & 0x06) != 0) { /* IDvalid? */ 1202 k = mbuf[1]; 1203 while (1) { 1204 m = 1; 1205 m <<= k; 1206 if ((m & assignid_map) == 0) 1207 break; 1208 if (k > 0) 1209 k--; 1210 else 1211 break; 1212 } 1213 } 1214 if ((m & assignid_map) != 0) { /* srch from max acceptable ID# */ 1215 k = i; /* max acceptable ID# */ 1216 while (1) { 1217 m = 1; 1218 m <<= k; 1219 if ((m & assignid_map) == 0) 1220 break; 1221 if (k > 0) 1222 k--; 1223 else 1224 break; 1225 } 1226 } 1227 /* k=binID#, */ 1228 assignid_map |= m; 1229 if (k < 8) { 1230 quintet[0] = 0x38; /* 1st dft ID<8 */ 1231 } else { 1232 quintet[0] = 0x31; /* 1st ID>=8 */ 1233 } 1234 k &= 0x07; 1235 quintet[1] = g2q_tab[k]; 1236 1237 val &= 0x00ff; /* AssignID 1stQuintet,AH=001xxxxx */ 1238 m = quintet[0] << 8; 1239 val |= m; 1240 fun_scam(dev, &val); 1241 val &= 0x00ff; /* AssignID 2ndQuintet,AH=001xxxxx */ 1242 m = quintet[1] << 8; 1243 val |= m; 1244 fun_scam(dev, &val); 1245 1246 } 1247 } 1248 1249 static void atp870u_free_tables(struct Scsi_Host *host) 1250 { 1251 struct atp_unit *atp_dev = (struct atp_unit *)&host->hostdata; 1252 int j, k; 1253 for (j=0; j < 2; j++) { 1254 for (k = 0; k < 16; k++) { 1255 if (!atp_dev->id[j][k].prd_table) 1256 continue; 1257 dma_free_coherent(&atp_dev->pdev->dev, 1024, 1258 atp_dev->id[j][k].prd_table, 1259 atp_dev->id[j][k].prd_bus); 1260 atp_dev->id[j][k].prd_table = NULL; 1261 } 1262 } 1263 } 1264 1265 static int atp870u_init_tables(struct Scsi_Host *host) 1266 { 1267 struct atp_unit *atp_dev = (struct atp_unit *)&host->hostdata; 1268 int c,k; 1269 for(c=0;c < 2;c++) { 1270 for(k=0;k<16;k++) { 1271 atp_dev->id[c][k].prd_table = 1272 dma_alloc_coherent(&atp_dev->pdev->dev, 1024, 1273 &(atp_dev->id[c][k].prd_bus), 1274 GFP_KERNEL); 1275 if (!atp_dev->id[c][k].prd_table) { 1276 printk("atp870u_init_tables fail\n"); 1277 atp870u_free_tables(host); 1278 return -ENOMEM; 1279 } 1280 atp_dev->id[c][k].prdaddr = atp_dev->id[c][k].prd_bus; 1281 atp_dev->id[c][k].devsp=0x20; 1282 atp_dev->id[c][k].devtype = 0x7f; 1283 atp_dev->id[c][k].curr_req = NULL; 1284 } 1285 1286 atp_dev->active_id[c] = 0; 1287 atp_dev->wide_id[c] = 0; 1288 atp_dev->host_id[c] = 0x07; 1289 atp_dev->quhd[c] = 0; 1290 atp_dev->quend[c] = 0; 1291 atp_dev->last_cmd[c] = 0xff; 1292 atp_dev->in_snd[c] = 0; 1293 atp_dev->in_int[c] = 0; 1294 1295 for (k = 0; k < qcnt; k++) { 1296 atp_dev->quereq[c][k] = NULL; 1297 } 1298 for (k = 0; k < 16; k++) { 1299 atp_dev->id[c][k].curr_req = NULL; 1300 atp_dev->sp[c][k] = 0x04; 1301 } 1302 } 1303 return 0; 1304 } 1305 1306 static void atp_set_host_id(struct atp_unit *atp, u8 c, u8 host_id) 1307 { 1308 atp_writeb_io(atp, c, 0, host_id | 0x08); 1309 atp_writeb_io(atp, c, 0x18, 0); 1310 while ((atp_readb_io(atp, c, 0x1f) & 0x80) == 0) 1311 mdelay(1); 1312 atp_readb_io(atp, c, 0x17); 1313 atp_writeb_io(atp, c, 1, 8); 1314 atp_writeb_io(atp, c, 2, 0x7f); 1315 atp_writeb_io(atp, c, 0x11, 0x20); 1316 } 1317 1318 static void atp870_init(struct Scsi_Host *shpnt) 1319 { 1320 struct atp_unit *atpdev = shost_priv(shpnt); 1321 struct pci_dev *pdev = atpdev->pdev; 1322 unsigned char k, host_id; 1323 u8 scam_on; 1324 bool wide_chip = 1325 (pdev->device == PCI_DEVICE_ID_ARTOP_AEC7610 && 1326 pdev->revision == 4) || 1327 (pdev->device == PCI_DEVICE_ID_ARTOP_AEC7612UW) || 1328 (pdev->device == PCI_DEVICE_ID_ARTOP_AEC7612SUW); 1329 1330 pci_read_config_byte(pdev, 0x49, &host_id); 1331 1332 dev_info(&pdev->dev, "ACARD AEC-671X PCI Ultra/W SCSI-2/3 " 1333 "Host Adapter: IO:%lx, IRQ:%d.\n", 1334 shpnt->io_port, shpnt->irq); 1335 1336 atpdev->ioport[0] = shpnt->io_port; 1337 atpdev->pciport[0] = shpnt->io_port + 0x20; 1338 host_id &= 0x07; 1339 atpdev->host_id[0] = host_id; 1340 scam_on = atp_readb_pci(atpdev, 0, 2); 1341 atpdev->global_map[0] = atp_readb_base(atpdev, 0x2d); 1342 atpdev->ultra_map[0] = atp_readw_base(atpdev, 0x2e); 1343 1344 if (atpdev->ultra_map[0] == 0) { 1345 scam_on = 0x00; 1346 atpdev->global_map[0] = 0x20; 1347 atpdev->ultra_map[0] = 0xffff; 1348 } 1349 1350 if (pdev->revision > 0x07) /* check if atp876 chip */ 1351 atp_writeb_base(atpdev, 0x3e, 0x00); /* enable terminator */ 1352 1353 k = (atp_readb_base(atpdev, 0x3a) & 0xf3) | 0x10; 1354 atp_writeb_base(atpdev, 0x3a, k); 1355 atp_writeb_base(atpdev, 0x3a, k & 0xdf); 1356 msleep(32); 1357 atp_writeb_base(atpdev, 0x3a, k); 1358 msleep(32); 1359 atp_set_host_id(atpdev, 0, host_id); 1360 1361 tscam(shpnt, wide_chip, scam_on); 1362 atp_writeb_base(atpdev, 0x3a, atp_readb_base(atpdev, 0x3a) | 0x10); 1363 atp_is(atpdev, 0, wide_chip, 0); 1364 atp_writeb_base(atpdev, 0x3a, atp_readb_base(atpdev, 0x3a) & 0xef); 1365 atp_writeb_base(atpdev, 0x3b, atp_readb_base(atpdev, 0x3b) | 0x20); 1366 shpnt->max_id = wide_chip ? 16 : 8; 1367 shpnt->this_id = host_id; 1368 } 1369 1370 static void atp880_init(struct Scsi_Host *shpnt) 1371 { 1372 struct atp_unit *atpdev = shost_priv(shpnt); 1373 struct pci_dev *pdev = atpdev->pdev; 1374 unsigned char k, m, host_id; 1375 unsigned int n; 1376 1377 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80); 1378 1379 atpdev->ioport[0] = shpnt->io_port + 0x40; 1380 atpdev->pciport[0] = shpnt->io_port + 0x28; 1381 1382 host_id = atp_readb_base(atpdev, 0x39) >> 4; 1383 1384 dev_info(&pdev->dev, "ACARD AEC-67160 PCI Ultra3 LVD " 1385 "Host Adapter: IO:%lx, IRQ:%d.\n", 1386 shpnt->io_port, shpnt->irq); 1387 atpdev->host_id[0] = host_id; 1388 1389 atpdev->global_map[0] = atp_readb_base(atpdev, 0x35); 1390 atpdev->ultra_map[0] = atp_readw_base(atpdev, 0x3c); 1391 1392 n = 0x3f09; 1393 while (n < 0x4000) { 1394 m = 0; 1395 atp_writew_base(atpdev, 0x34, n); 1396 n += 0x0002; 1397 if (atp_readb_base(atpdev, 0x30) == 0xff) 1398 break; 1399 1400 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x30); 1401 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x31); 1402 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x32); 1403 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x33); 1404 atp_writew_base(atpdev, 0x34, n); 1405 n += 0x0002; 1406 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x30); 1407 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x31); 1408 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x32); 1409 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x33); 1410 atp_writew_base(atpdev, 0x34, n); 1411 n += 0x0002; 1412 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x30); 1413 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x31); 1414 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x32); 1415 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x33); 1416 atp_writew_base(atpdev, 0x34, n); 1417 n += 0x0002; 1418 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x30); 1419 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x31); 1420 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x32); 1421 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x33); 1422 n += 0x0018; 1423 } 1424 atp_writew_base(atpdev, 0x34, 0); 1425 atpdev->ultra_map[0] = 0; 1426 atpdev->async[0] = 0; 1427 for (k = 0; k < 16; k++) { 1428 n = 1 << k; 1429 if (atpdev->sp[0][k] > 1) 1430 atpdev->ultra_map[0] |= n; 1431 else 1432 if (atpdev->sp[0][k] == 0) 1433 atpdev->async[0] |= n; 1434 } 1435 atpdev->async[0] = ~(atpdev->async[0]); 1436 atp_writeb_base(atpdev, 0x35, atpdev->global_map[0]); 1437 1438 k = atp_readb_base(atpdev, 0x38) & 0x80; 1439 atp_writeb_base(atpdev, 0x38, k); 1440 atp_writeb_base(atpdev, 0x3b, 0x20); 1441 msleep(32); 1442 atp_writeb_base(atpdev, 0x3b, 0); 1443 msleep(32); 1444 atp_readb_io(atpdev, 0, 0x1b); 1445 atp_readb_io(atpdev, 0, 0x17); 1446 1447 atp_set_host_id(atpdev, 0, host_id); 1448 1449 tscam(shpnt, true, atp_readb_base(atpdev, 0x22)); 1450 atp_is(atpdev, 0, true, atp_readb_base(atpdev, 0x3f) & 0x40); 1451 atp_writeb_base(atpdev, 0x38, 0xb0); 1452 shpnt->max_id = 16; 1453 shpnt->this_id = host_id; 1454 } 1455 1456 static void atp885_init(struct Scsi_Host *shpnt) 1457 { 1458 struct atp_unit *atpdev = shost_priv(shpnt); 1459 struct pci_dev *pdev = atpdev->pdev; 1460 unsigned char k, m, c; 1461 unsigned int n; 1462 unsigned char setupdata[2][16]; 1463 1464 dev_info(&pdev->dev, "ACARD AEC-67162 PCI Ultra3 LVD " 1465 "Host Adapter: IO:%lx, IRQ:%d.\n", 1466 shpnt->io_port, shpnt->irq); 1467 1468 atpdev->ioport[0] = shpnt->io_port + 0x80; 1469 atpdev->ioport[1] = shpnt->io_port + 0xc0; 1470 atpdev->pciport[0] = shpnt->io_port + 0x40; 1471 atpdev->pciport[1] = shpnt->io_port + 0x50; 1472 1473 c = atp_readb_base(atpdev, 0x29); 1474 atp_writeb_base(atpdev, 0x29, c | 0x04); 1475 1476 n = 0x1f80; 1477 while (n < 0x2000) { 1478 atp_writew_base(atpdev, 0x3c, n); 1479 if (atp_readl_base(atpdev, 0x38) == 0xffffffff) 1480 break; 1481 for (m = 0; m < 2; m++) { 1482 atpdev->global_map[m] = 0; 1483 for (k = 0; k < 4; k++) { 1484 atp_writew_base(atpdev, 0x3c, n++); 1485 ((u32 *)&setupdata[m][0])[k] = 1486 atp_readl_base(atpdev, 0x38); 1487 } 1488 for (k = 0; k < 4; k++) { 1489 atp_writew_base(atpdev, 0x3c, n++); 1490 ((u32 *)&atpdev->sp[m][0])[k] = 1491 atp_readl_base(atpdev, 0x38); 1492 } 1493 n += 8; 1494 } 1495 } 1496 c = atp_readb_base(atpdev, 0x29); 1497 atp_writeb_base(atpdev, 0x29, c & 0xfb); 1498 for (c = 0; c < 2; c++) { 1499 atpdev->ultra_map[c] = 0; 1500 atpdev->async[c] = 0; 1501 for (k = 0; k < 16; k++) { 1502 n = 1 << k; 1503 if (atpdev->sp[c][k] > 1) 1504 atpdev->ultra_map[c] |= n; 1505 else 1506 if (atpdev->sp[c][k] == 0) 1507 atpdev->async[c] |= n; 1508 } 1509 atpdev->async[c] = ~(atpdev->async[c]); 1510 1511 if (atpdev->global_map[c] == 0) { 1512 k = setupdata[c][1]; 1513 if ((k & 0x40) != 0) 1514 atpdev->global_map[c] |= 0x20; 1515 k &= 0x07; 1516 atpdev->global_map[c] |= k; 1517 if ((setupdata[c][2] & 0x04) != 0) 1518 atpdev->global_map[c] |= 0x08; 1519 atpdev->host_id[c] = setupdata[c][0] & 0x07; 1520 } 1521 } 1522 1523 k = atp_readb_base(atpdev, 0x28) & 0x8f; 1524 k |= 0x10; 1525 atp_writeb_base(atpdev, 0x28, k); 1526 atp_writeb_pci(atpdev, 0, 1, 0x80); 1527 atp_writeb_pci(atpdev, 1, 1, 0x80); 1528 msleep(100); 1529 atp_writeb_pci(atpdev, 0, 1, 0); 1530 atp_writeb_pci(atpdev, 1, 1, 0); 1531 msleep(1000); 1532 atp_readb_io(atpdev, 0, 0x1b); 1533 atp_readb_io(atpdev, 0, 0x17); 1534 atp_readb_io(atpdev, 1, 0x1b); 1535 atp_readb_io(atpdev, 1, 0x17); 1536 1537 k = atpdev->host_id[0]; 1538 if (k > 7) 1539 k = (k & 0x07) | 0x40; 1540 atp_set_host_id(atpdev, 0, k); 1541 1542 k = atpdev->host_id[1]; 1543 if (k > 7) 1544 k = (k & 0x07) | 0x40; 1545 atp_set_host_id(atpdev, 1, k); 1546 1547 msleep(600); /* this delay used to be called tscam_885() */ 1548 dev_info(&pdev->dev, "Scanning Channel A SCSI Device ...\n"); 1549 atp_is(atpdev, 0, true, atp_readb_io(atpdev, 0, 0x1b) >> 7); 1550 atp_writeb_io(atpdev, 0, 0x16, 0x80); 1551 dev_info(&pdev->dev, "Scanning Channel B SCSI Device ...\n"); 1552 atp_is(atpdev, 1, true, atp_readb_io(atpdev, 1, 0x1b) >> 7); 1553 atp_writeb_io(atpdev, 1, 0x16, 0x80); 1554 k = atp_readb_base(atpdev, 0x28) & 0xcf; 1555 k |= 0xc0; 1556 atp_writeb_base(atpdev, 0x28, k); 1557 k = atp_readb_base(atpdev, 0x1f) | 0x80; 1558 atp_writeb_base(atpdev, 0x1f, k); 1559 k = atp_readb_base(atpdev, 0x29) | 0x01; 1560 atp_writeb_base(atpdev, 0x29, k); 1561 shpnt->max_id = 16; 1562 shpnt->max_lun = (atpdev->global_map[0] & 0x07) + 1; 1563 shpnt->max_channel = 1; 1564 shpnt->this_id = atpdev->host_id[0]; 1565 } 1566 1567 /* return non-zero on detection */ 1568 static int atp870u_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1569 { 1570 struct Scsi_Host *shpnt = NULL; 1571 struct atp_unit *atpdev; 1572 int err; 1573 1574 if (ent->device == PCI_DEVICE_ID_ARTOP_AEC7610 && pdev->revision < 2) { 1575 dev_err(&pdev->dev, "ATP850S chips (AEC6710L/F cards) are not supported.\n"); 1576 return -ENODEV; 1577 } 1578 1579 err = pci_enable_device(pdev); 1580 if (err) 1581 goto fail; 1582 1583 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) { 1584 printk(KERN_ERR "atp870u: DMA mask required but not available.\n"); 1585 err = -EIO; 1586 goto disable_device; 1587 } 1588 1589 err = pci_request_regions(pdev, "atp870u"); 1590 if (err) 1591 goto disable_device; 1592 pci_set_master(pdev); 1593 1594 err = -ENOMEM; 1595 shpnt = scsi_host_alloc(&atp870u_template, sizeof(struct atp_unit)); 1596 if (!shpnt) 1597 goto release_region; 1598 1599 atpdev = shost_priv(shpnt); 1600 1601 atpdev->host = shpnt; 1602 atpdev->pdev = pdev; 1603 pci_set_drvdata(pdev, atpdev); 1604 1605 shpnt->io_port = pci_resource_start(pdev, 0); 1606 shpnt->io_port &= 0xfffffff8; 1607 shpnt->n_io_port = pci_resource_len(pdev, 0); 1608 atpdev->baseport = shpnt->io_port; 1609 shpnt->unique_id = shpnt->io_port; 1610 shpnt->irq = pdev->irq; 1611 1612 err = atp870u_init_tables(shpnt); 1613 if (err) { 1614 dev_err(&pdev->dev, "Unable to allocate tables for Acard controller\n"); 1615 goto unregister; 1616 } 1617 1618 if (is880(atpdev)) 1619 atp880_init(shpnt); 1620 else if (is885(atpdev)) 1621 atp885_init(shpnt); 1622 else 1623 atp870_init(shpnt); 1624 1625 err = request_irq(shpnt->irq, atp870u_intr_handle, IRQF_SHARED, "atp870u", shpnt); 1626 if (err) { 1627 dev_err(&pdev->dev, "Unable to allocate IRQ %d.\n", shpnt->irq); 1628 goto free_tables; 1629 } 1630 1631 err = scsi_add_host(shpnt, &pdev->dev); 1632 if (err) 1633 goto scsi_add_fail; 1634 scsi_scan_host(shpnt); 1635 1636 return 0; 1637 1638 scsi_add_fail: 1639 free_irq(shpnt->irq, shpnt); 1640 free_tables: 1641 atp870u_free_tables(shpnt); 1642 unregister: 1643 scsi_host_put(shpnt); 1644 release_region: 1645 pci_release_regions(pdev); 1646 disable_device: 1647 pci_disable_device(pdev); 1648 fail: 1649 return err; 1650 } 1651 1652 /* The abort command does not leave the device in a clean state where 1653 it is available to be used again. Until this gets worked out, we will 1654 leave it commented out. */ 1655 1656 static int atp870u_abort(struct scsi_cmnd * SCpnt) 1657 { 1658 unsigned char j, k, c; 1659 struct scsi_cmnd *workrequ; 1660 struct atp_unit *dev; 1661 struct Scsi_Host *host; 1662 host = SCpnt->device->host; 1663 1664 dev = (struct atp_unit *)&host->hostdata; 1665 c = scmd_channel(SCpnt); 1666 printk(" atp870u: abort Channel = %x \n", c); 1667 printk("working=%x last_cmd=%x ", dev->working[c], dev->last_cmd[c]); 1668 printk(" quhdu=%x quendu=%x ", dev->quhd[c], dev->quend[c]); 1669 for (j = 0; j < 0x18; j++) { 1670 printk(" r%2x=%2x", j, atp_readb_io(dev, c, j)); 1671 } 1672 printk(" r1c=%2x", atp_readb_io(dev, c, 0x1c)); 1673 printk(" r1f=%2x in_snd=%2x ", atp_readb_io(dev, c, 0x1f), dev->in_snd[c]); 1674 printk(" d00=%2x", atp_readb_pci(dev, c, 0x00)); 1675 printk(" d02=%2x", atp_readb_pci(dev, c, 0x02)); 1676 for(j=0;j<16;j++) { 1677 if (dev->id[c][j].curr_req != NULL) { 1678 workrequ = dev->id[c][j].curr_req; 1679 printk("\n que cdb= "); 1680 for (k=0; k < workrequ->cmd_len; k++) { 1681 printk(" %2x ",workrequ->cmnd[k]); 1682 } 1683 printk(" last_lenu= %x ",(unsigned int)dev->id[c][j].last_len); 1684 } 1685 } 1686 return SUCCESS; 1687 } 1688 1689 static const char *atp870u_info(struct Scsi_Host *notused) 1690 { 1691 static char buffer[128]; 1692 1693 strcpy(buffer, "ACARD AEC-6710/6712/67160 PCI Ultra/W/LVD SCSI-3 Adapter Driver V2.6+ac "); 1694 1695 return buffer; 1696 } 1697 1698 static int atp870u_show_info(struct seq_file *m, struct Scsi_Host *HBAptr) 1699 { 1700 seq_puts(m, "ACARD AEC-671X Driver Version: 2.6+ac\n\n" 1701 "Adapter Configuration:\n"); 1702 seq_printf(m, " Base IO: %#.4lx\n", HBAptr->io_port); 1703 seq_printf(m, " IRQ: %d\n", HBAptr->irq); 1704 return 0; 1705 } 1706 1707 1708 static int atp870u_biosparam(struct scsi_device *disk, struct block_device *dev, 1709 sector_t capacity, int *ip) 1710 { 1711 int heads, sectors, cylinders; 1712 1713 heads = 64; 1714 sectors = 32; 1715 cylinders = (unsigned long)capacity / (heads * sectors); 1716 if (cylinders > 1024) { 1717 heads = 255; 1718 sectors = 63; 1719 cylinders = (unsigned long)capacity / (heads * sectors); 1720 } 1721 ip[0] = heads; 1722 ip[1] = sectors; 1723 ip[2] = cylinders; 1724 1725 return 0; 1726 } 1727 1728 static void atp870u_remove (struct pci_dev *pdev) 1729 { 1730 struct atp_unit *devext = pci_get_drvdata(pdev); 1731 struct Scsi_Host *pshost = devext->host; 1732 1733 scsi_remove_host(pshost); 1734 free_irq(pshost->irq, pshost); 1735 pci_release_regions(pdev); 1736 pci_disable_device(pdev); 1737 atp870u_free_tables(pshost); 1738 scsi_host_put(pshost); 1739 } 1740 MODULE_LICENSE("GPL"); 1741 1742 static struct scsi_host_template atp870u_template = { 1743 .module = THIS_MODULE, 1744 .name = "atp870u" /* name */, 1745 .proc_name = "atp870u", 1746 .show_info = atp870u_show_info, 1747 .info = atp870u_info /* info */, 1748 .queuecommand = atp870u_queuecommand /* queuecommand */, 1749 .eh_abort_handler = atp870u_abort /* abort */, 1750 .bios_param = atp870u_biosparam /* biosparm */, 1751 .can_queue = qcnt /* can_queue */, 1752 .this_id = 7 /* SCSI ID */, 1753 .sg_tablesize = ATP870U_SCATTER /*SG_ALL*/, 1754 .max_sectors = ATP870U_MAX_SECTORS, 1755 }; 1756 1757 static struct pci_device_id atp870u_id_table[] = { 1758 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, ATP885_DEVID) }, 1759 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, ATP880_DEVID1) }, 1760 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, ATP880_DEVID2) }, 1761 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7610) }, 1762 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612UW) }, 1763 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612U) }, 1764 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612S) }, 1765 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612D) }, 1766 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612SUW) }, 1767 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_8060) }, 1768 { 0, }, 1769 }; 1770 1771 MODULE_DEVICE_TABLE(pci, atp870u_id_table); 1772 1773 static struct pci_driver atp870u_driver = { 1774 .id_table = atp870u_id_table, 1775 .name = "atp870u", 1776 .probe = atp870u_probe, 1777 .remove = atp870u_remove, 1778 }; 1779 1780 module_pci_driver(atp870u_driver); 1781 1782 static void atp_is(struct atp_unit *dev, unsigned char c, bool wide_chip, 1783 unsigned char lvdmode) 1784 { 1785 unsigned char i, j, k, rmb, n; 1786 unsigned short int m; 1787 static unsigned char mbuf[512]; 1788 static unsigned char satn[9] = { 0, 0, 0, 0, 0, 0, 0, 6, 6 }; 1789 static unsigned char inqd[9] = { 0x12, 0, 0, 0, 0x24, 0, 0, 0x24, 6 }; 1790 static unsigned char synn[6] = { 0x80, 1, 3, 1, 0x19, 0x0e }; 1791 unsigned char synu[6] = { 0x80, 1, 3, 1, 0x0a, 0x0e }; 1792 static unsigned char synw[6] = { 0x80, 1, 3, 1, 0x19, 0x0e }; 1793 static unsigned char synw_870[6] = { 0x80, 1, 3, 1, 0x0c, 0x07 }; 1794 unsigned char synuw[6] = { 0x80, 1, 3, 1, 0x0a, 0x0e }; 1795 static unsigned char wide[6] = { 0x80, 1, 2, 3, 1, 0 }; 1796 static unsigned char u3[9] = { 0x80, 1, 6, 4, 0x09, 00, 0x0e, 0x01, 0x02 }; 1797 1798 for (i = 0; i < 16; i++) { 1799 if (!wide_chip && (i > 7)) 1800 break; 1801 m = 1; 1802 m = m << i; 1803 if ((m & dev->active_id[c]) != 0) { 1804 continue; 1805 } 1806 if (i == dev->host_id[c]) { 1807 printk(KERN_INFO " ID: %2d Host Adapter\n", dev->host_id[c]); 1808 continue; 1809 } 1810 atp_writeb_io(dev, c, 0x1b, wide_chip ? 0x01 : 0x00); 1811 atp_writeb_io(dev, c, 1, 0x08); 1812 atp_writeb_io(dev, c, 2, 0x7f); 1813 atp_writeb_io(dev, c, 3, satn[0]); 1814 atp_writeb_io(dev, c, 4, satn[1]); 1815 atp_writeb_io(dev, c, 5, satn[2]); 1816 atp_writeb_io(dev, c, 6, satn[3]); 1817 atp_writeb_io(dev, c, 7, satn[4]); 1818 atp_writeb_io(dev, c, 8, satn[5]); 1819 atp_writeb_io(dev, c, 0x0f, 0); 1820 atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp); 1821 atp_writeb_io(dev, c, 0x12, 0); 1822 atp_writeb_io(dev, c, 0x13, satn[6]); 1823 atp_writeb_io(dev, c, 0x14, satn[7]); 1824 j = i; 1825 if ((j & 0x08) != 0) { 1826 j = (j & 0x07) | 0x40; 1827 } 1828 atp_writeb_io(dev, c, 0x15, j); 1829 atp_writeb_io(dev, c, 0x18, satn[8]); 1830 1831 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00) 1832 cpu_relax(); 1833 1834 if (atp_readb_io(dev, c, 0x17) != 0x11 && atp_readb_io(dev, c, 0x17) != 0x8e) 1835 continue; 1836 1837 while (atp_readb_io(dev, c, 0x17) != 0x8e) 1838 cpu_relax(); 1839 1840 dev->active_id[c] |= m; 1841 1842 atp_writeb_io(dev, c, 0x10, 0x30); 1843 if (is885(dev) || is880(dev)) 1844 atp_writeb_io(dev, c, 0x14, 0x00); 1845 else /* result of is870() merge - is this a bug? */ 1846 atp_writeb_io(dev, c, 0x04, 0x00); 1847 1848 phase_cmd: 1849 atp_writeb_io(dev, c, 0x18, 0x08); 1850 1851 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00) 1852 cpu_relax(); 1853 1854 j = atp_readb_io(dev, c, 0x17); 1855 if (j != 0x16) { 1856 atp_writeb_io(dev, c, 0x10, 0x41); 1857 goto phase_cmd; 1858 } 1859 sel_ok: 1860 atp_writeb_io(dev, c, 3, inqd[0]); 1861 atp_writeb_io(dev, c, 4, inqd[1]); 1862 atp_writeb_io(dev, c, 5, inqd[2]); 1863 atp_writeb_io(dev, c, 6, inqd[3]); 1864 atp_writeb_io(dev, c, 7, inqd[4]); 1865 atp_writeb_io(dev, c, 8, inqd[5]); 1866 atp_writeb_io(dev, c, 0x0f, 0); 1867 atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp); 1868 atp_writeb_io(dev, c, 0x12, 0); 1869 atp_writeb_io(dev, c, 0x13, inqd[6]); 1870 atp_writeb_io(dev, c, 0x14, inqd[7]); 1871 atp_writeb_io(dev, c, 0x18, inqd[8]); 1872 1873 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00) 1874 cpu_relax(); 1875 1876 if (atp_readb_io(dev, c, 0x17) != 0x11 && atp_readb_io(dev, c, 0x17) != 0x8e) 1877 continue; 1878 1879 while (atp_readb_io(dev, c, 0x17) != 0x8e) 1880 cpu_relax(); 1881 1882 if (wide_chip) 1883 atp_writeb_io(dev, c, 0x1b, 0x00); 1884 1885 atp_writeb_io(dev, c, 0x18, 0x08); 1886 j = 0; 1887 rd_inq_data: 1888 k = atp_readb_io(dev, c, 0x1f); 1889 if ((k & 0x01) != 0) { 1890 mbuf[j++] = atp_readb_io(dev, c, 0x19); 1891 goto rd_inq_data; 1892 } 1893 if ((k & 0x80) == 0) { 1894 goto rd_inq_data; 1895 } 1896 j = atp_readb_io(dev, c, 0x17); 1897 if (j == 0x16) { 1898 goto inq_ok; 1899 } 1900 atp_writeb_io(dev, c, 0x10, 0x46); 1901 atp_writeb_io(dev, c, 0x12, 0); 1902 atp_writeb_io(dev, c, 0x13, 0); 1903 atp_writeb_io(dev, c, 0x14, 0); 1904 atp_writeb_io(dev, c, 0x18, 0x08); 1905 1906 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00) 1907 cpu_relax(); 1908 1909 if (atp_readb_io(dev, c, 0x17) != 0x16) 1910 goto sel_ok; 1911 1912 inq_ok: 1913 mbuf[36] = 0; 1914 printk(KERN_INFO " ID: %2d %s\n", i, &mbuf[8]); 1915 dev->id[c][i].devtype = mbuf[0]; 1916 rmb = mbuf[1]; 1917 n = mbuf[7]; 1918 if (!wide_chip) 1919 goto not_wide; 1920 if ((mbuf[7] & 0x60) == 0) { 1921 goto not_wide; 1922 } 1923 if (is885(dev) || is880(dev)) { 1924 if ((i < 8) && ((dev->global_map[c] & 0x20) == 0)) 1925 goto not_wide; 1926 } else { /* result of is870() merge - is this a bug? */ 1927 if ((dev->global_map[c] & 0x20) == 0) 1928 goto not_wide; 1929 } 1930 if (lvdmode == 0) { 1931 goto chg_wide; 1932 } 1933 if (dev->sp[c][i] != 0x04) // force u2 1934 { 1935 goto chg_wide; 1936 } 1937 1938 atp_writeb_io(dev, c, 0x1b, 0x01); 1939 atp_writeb_io(dev, c, 3, satn[0]); 1940 atp_writeb_io(dev, c, 4, satn[1]); 1941 atp_writeb_io(dev, c, 5, satn[2]); 1942 atp_writeb_io(dev, c, 6, satn[3]); 1943 atp_writeb_io(dev, c, 7, satn[4]); 1944 atp_writeb_io(dev, c, 8, satn[5]); 1945 atp_writeb_io(dev, c, 0x0f, 0); 1946 atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp); 1947 atp_writeb_io(dev, c, 0x12, 0); 1948 atp_writeb_io(dev, c, 0x13, satn[6]); 1949 atp_writeb_io(dev, c, 0x14, satn[7]); 1950 atp_writeb_io(dev, c, 0x18, satn[8]); 1951 1952 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00) 1953 cpu_relax(); 1954 1955 if (atp_readb_io(dev, c, 0x17) != 0x11 && atp_readb_io(dev, c, 0x17) != 0x8e) 1956 continue; 1957 1958 while (atp_readb_io(dev, c, 0x17) != 0x8e) 1959 cpu_relax(); 1960 1961 try_u3: 1962 j = 0; 1963 atp_writeb_io(dev, c, 0x14, 0x09); 1964 atp_writeb_io(dev, c, 0x18, 0x20); 1965 1966 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) { 1967 if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0) 1968 atp_writeb_io(dev, c, 0x19, u3[j++]); 1969 cpu_relax(); 1970 } 1971 1972 while ((atp_readb_io(dev, c, 0x17) & 0x80) == 0x00) 1973 cpu_relax(); 1974 1975 j = atp_readb_io(dev, c, 0x17) & 0x0f; 1976 if (j == 0x0f) { 1977 goto u3p_in; 1978 } 1979 if (j == 0x0a) { 1980 goto u3p_cmd; 1981 } 1982 if (j == 0x0e) { 1983 goto try_u3; 1984 } 1985 continue; 1986 u3p_out: 1987 atp_writeb_io(dev, c, 0x18, 0x20); 1988 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) { 1989 if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0) 1990 atp_writeb_io(dev, c, 0x19, 0); 1991 cpu_relax(); 1992 } 1993 j = atp_readb_io(dev, c, 0x17) & 0x0f; 1994 if (j == 0x0f) { 1995 goto u3p_in; 1996 } 1997 if (j == 0x0a) { 1998 goto u3p_cmd; 1999 } 2000 if (j == 0x0e) { 2001 goto u3p_out; 2002 } 2003 continue; 2004 u3p_in: 2005 atp_writeb_io(dev, c, 0x14, 0x09); 2006 atp_writeb_io(dev, c, 0x18, 0x20); 2007 k = 0; 2008 u3p_in1: 2009 j = atp_readb_io(dev, c, 0x1f); 2010 if ((j & 0x01) != 0) { 2011 mbuf[k++] = atp_readb_io(dev, c, 0x19); 2012 goto u3p_in1; 2013 } 2014 if ((j & 0x80) == 0x00) { 2015 goto u3p_in1; 2016 } 2017 j = atp_readb_io(dev, c, 0x17) & 0x0f; 2018 if (j == 0x0f) { 2019 goto u3p_in; 2020 } 2021 if (j == 0x0a) { 2022 goto u3p_cmd; 2023 } 2024 if (j == 0x0e) { 2025 goto u3p_out; 2026 } 2027 continue; 2028 u3p_cmd: 2029 atp_writeb_io(dev, c, 0x10, 0x30); 2030 atp_writeb_io(dev, c, 0x14, 0x00); 2031 atp_writeb_io(dev, c, 0x18, 0x08); 2032 2033 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00); 2034 2035 j = atp_readb_io(dev, c, 0x17); 2036 if (j != 0x16) { 2037 if (j == 0x4e) { 2038 goto u3p_out; 2039 } 2040 continue; 2041 } 2042 if (mbuf[0] != 0x01) { 2043 goto chg_wide; 2044 } 2045 if (mbuf[1] != 0x06) { 2046 goto chg_wide; 2047 } 2048 if (mbuf[2] != 0x04) { 2049 goto chg_wide; 2050 } 2051 if (mbuf[3] == 0x09) { 2052 m = 1; 2053 m = m << i; 2054 dev->wide_id[c] |= m; 2055 dev->id[c][i].devsp = 0xce; 2056 #ifdef ED_DBGP 2057 printk("dev->id[%2d][%2d].devsp = %2x\n", 2058 c, i, dev->id[c][i].devsp); 2059 #endif 2060 continue; 2061 } 2062 chg_wide: 2063 atp_writeb_io(dev, c, 0x1b, 0x01); 2064 atp_writeb_io(dev, c, 3, satn[0]); 2065 atp_writeb_io(dev, c, 4, satn[1]); 2066 atp_writeb_io(dev, c, 5, satn[2]); 2067 atp_writeb_io(dev, c, 6, satn[3]); 2068 atp_writeb_io(dev, c, 7, satn[4]); 2069 atp_writeb_io(dev, c, 8, satn[5]); 2070 atp_writeb_io(dev, c, 0x0f, 0); 2071 atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp); 2072 atp_writeb_io(dev, c, 0x12, 0); 2073 atp_writeb_io(dev, c, 0x13, satn[6]); 2074 atp_writeb_io(dev, c, 0x14, satn[7]); 2075 atp_writeb_io(dev, c, 0x18, satn[8]); 2076 2077 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00) 2078 cpu_relax(); 2079 2080 if (atp_readb_io(dev, c, 0x17) != 0x11 && 2081 atp_readb_io(dev, c, 0x17) != 0x8e) 2082 continue; 2083 2084 while (atp_readb_io(dev, c, 0x17) != 0x8e) 2085 cpu_relax(); 2086 2087 try_wide: 2088 j = 0; 2089 atp_writeb_io(dev, c, 0x14, 0x05); 2090 atp_writeb_io(dev, c, 0x18, 0x20); 2091 2092 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) { 2093 if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0) 2094 atp_writeb_io(dev, c, 0x19, wide[j++]); 2095 cpu_relax(); 2096 } 2097 2098 while ((atp_readb_io(dev, c, 0x17) & 0x80) == 0x00) 2099 cpu_relax(); 2100 2101 j = atp_readb_io(dev, c, 0x17) & 0x0f; 2102 if (j == 0x0f) { 2103 goto widep_in; 2104 } 2105 if (j == 0x0a) { 2106 goto widep_cmd; 2107 } 2108 if (j == 0x0e) { 2109 goto try_wide; 2110 } 2111 continue; 2112 widep_out: 2113 atp_writeb_io(dev, c, 0x18, 0x20); 2114 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) { 2115 if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0) 2116 atp_writeb_io(dev, c, 0x19, 0); 2117 cpu_relax(); 2118 } 2119 j = atp_readb_io(dev, c, 0x17) & 0x0f; 2120 if (j == 0x0f) { 2121 goto widep_in; 2122 } 2123 if (j == 0x0a) { 2124 goto widep_cmd; 2125 } 2126 if (j == 0x0e) { 2127 goto widep_out; 2128 } 2129 continue; 2130 widep_in: 2131 atp_writeb_io(dev, c, 0x14, 0xff); 2132 atp_writeb_io(dev, c, 0x18, 0x20); 2133 k = 0; 2134 widep_in1: 2135 j = atp_readb_io(dev, c, 0x1f); 2136 if ((j & 0x01) != 0) { 2137 mbuf[k++] = atp_readb_io(dev, c, 0x19); 2138 goto widep_in1; 2139 } 2140 if ((j & 0x80) == 0x00) { 2141 goto widep_in1; 2142 } 2143 j = atp_readb_io(dev, c, 0x17) & 0x0f; 2144 if (j == 0x0f) { 2145 goto widep_in; 2146 } 2147 if (j == 0x0a) { 2148 goto widep_cmd; 2149 } 2150 if (j == 0x0e) { 2151 goto widep_out; 2152 } 2153 continue; 2154 widep_cmd: 2155 atp_writeb_io(dev, c, 0x10, 0x30); 2156 atp_writeb_io(dev, c, 0x14, 0x00); 2157 atp_writeb_io(dev, c, 0x18, 0x08); 2158 2159 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00) 2160 cpu_relax(); 2161 2162 j = atp_readb_io(dev, c, 0x17); 2163 if (j != 0x16) { 2164 if (j == 0x4e) { 2165 goto widep_out; 2166 } 2167 continue; 2168 } 2169 if (mbuf[0] != 0x01) { 2170 goto not_wide; 2171 } 2172 if (mbuf[1] != 0x02) { 2173 goto not_wide; 2174 } 2175 if (mbuf[2] != 0x03) { 2176 goto not_wide; 2177 } 2178 if (mbuf[3] != 0x01) { 2179 goto not_wide; 2180 } 2181 m = 1; 2182 m = m << i; 2183 dev->wide_id[c] |= m; 2184 not_wide: 2185 if ((dev->id[c][i].devtype == 0x00) || 2186 (dev->id[c][i].devtype == 0x07) || 2187 ((dev->id[c][i].devtype == 0x05) && ((n & 0x10) != 0))) { 2188 m = 1; 2189 m = m << i; 2190 if ((dev->async[c] & m) != 0) { 2191 goto set_sync; 2192 } 2193 } 2194 continue; 2195 set_sync: 2196 if ((!is885(dev) && !is880(dev)) || (dev->sp[c][i] == 0x02)) { 2197 synu[4] = 0x0c; 2198 synuw[4] = 0x0c; 2199 } else { 2200 if (dev->sp[c][i] >= 0x03) { 2201 synu[4] = 0x0a; 2202 synuw[4] = 0x0a; 2203 } 2204 } 2205 j = 0; 2206 if ((m & dev->wide_id[c]) != 0) { 2207 j |= 0x01; 2208 } 2209 atp_writeb_io(dev, c, 0x1b, j); 2210 atp_writeb_io(dev, c, 3, satn[0]); 2211 atp_writeb_io(dev, c, 4, satn[1]); 2212 atp_writeb_io(dev, c, 5, satn[2]); 2213 atp_writeb_io(dev, c, 6, satn[3]); 2214 atp_writeb_io(dev, c, 7, satn[4]); 2215 atp_writeb_io(dev, c, 8, satn[5]); 2216 atp_writeb_io(dev, c, 0x0f, 0); 2217 atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp); 2218 atp_writeb_io(dev, c, 0x12, 0); 2219 atp_writeb_io(dev, c, 0x13, satn[6]); 2220 atp_writeb_io(dev, c, 0x14, satn[7]); 2221 atp_writeb_io(dev, c, 0x18, satn[8]); 2222 2223 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00) 2224 cpu_relax(); 2225 2226 if (atp_readb_io(dev, c, 0x17) != 0x11 && 2227 atp_readb_io(dev, c, 0x17) != 0x8e) 2228 continue; 2229 2230 while (atp_readb_io(dev, c, 0x17) != 0x8e) 2231 cpu_relax(); 2232 2233 try_sync: 2234 j = 0; 2235 atp_writeb_io(dev, c, 0x14, 0x06); 2236 atp_writeb_io(dev, c, 0x18, 0x20); 2237 2238 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) { 2239 if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0) { 2240 if ((m & dev->wide_id[c]) != 0) { 2241 if (is885(dev) || is880(dev)) { 2242 if ((m & dev->ultra_map[c]) != 0) { 2243 atp_writeb_io(dev, c, 0x19, synuw[j++]); 2244 } else { 2245 atp_writeb_io(dev, c, 0x19, synw[j++]); 2246 } 2247 } else 2248 atp_writeb_io(dev, c, 0x19, synw_870[j++]); 2249 } else { 2250 if ((m & dev->ultra_map[c]) != 0) { 2251 atp_writeb_io(dev, c, 0x19, synu[j++]); 2252 } else { 2253 atp_writeb_io(dev, c, 0x19, synn[j++]); 2254 } 2255 } 2256 } 2257 } 2258 2259 while ((atp_readb_io(dev, c, 0x17) & 0x80) == 0x00) 2260 cpu_relax(); 2261 2262 j = atp_readb_io(dev, c, 0x17) & 0x0f; 2263 if (j == 0x0f) { 2264 goto phase_ins; 2265 } 2266 if (j == 0x0a) { 2267 goto phase_cmds; 2268 } 2269 if (j == 0x0e) { 2270 goto try_sync; 2271 } 2272 continue; 2273 phase_outs: 2274 atp_writeb_io(dev, c, 0x18, 0x20); 2275 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00) { 2276 if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0x00) 2277 atp_writeb_io(dev, c, 0x19, 0x00); 2278 cpu_relax(); 2279 } 2280 j = atp_readb_io(dev, c, 0x17); 2281 if (j == 0x85) { 2282 goto tar_dcons; 2283 } 2284 j &= 0x0f; 2285 if (j == 0x0f) { 2286 goto phase_ins; 2287 } 2288 if (j == 0x0a) { 2289 goto phase_cmds; 2290 } 2291 if (j == 0x0e) { 2292 goto phase_outs; 2293 } 2294 continue; 2295 phase_ins: 2296 if (is885(dev) || is880(dev)) 2297 atp_writeb_io(dev, c, 0x14, 0x06); 2298 else 2299 atp_writeb_io(dev, c, 0x14, 0xff); 2300 atp_writeb_io(dev, c, 0x18, 0x20); 2301 k = 0; 2302 phase_ins1: 2303 j = atp_readb_io(dev, c, 0x1f); 2304 if ((j & 0x01) != 0x00) { 2305 mbuf[k++] = atp_readb_io(dev, c, 0x19); 2306 goto phase_ins1; 2307 } 2308 if ((j & 0x80) == 0x00) { 2309 goto phase_ins1; 2310 } 2311 2312 while ((atp_readb_io(dev, c, 0x17) & 0x80) == 0x00); 2313 2314 j = atp_readb_io(dev, c, 0x17); 2315 if (j == 0x85) { 2316 goto tar_dcons; 2317 } 2318 j &= 0x0f; 2319 if (j == 0x0f) { 2320 goto phase_ins; 2321 } 2322 if (j == 0x0a) { 2323 goto phase_cmds; 2324 } 2325 if (j == 0x0e) { 2326 goto phase_outs; 2327 } 2328 continue; 2329 phase_cmds: 2330 atp_writeb_io(dev, c, 0x10, 0x30); 2331 tar_dcons: 2332 atp_writeb_io(dev, c, 0x14, 0x00); 2333 atp_writeb_io(dev, c, 0x18, 0x08); 2334 2335 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00) 2336 cpu_relax(); 2337 2338 j = atp_readb_io(dev, c, 0x17); 2339 if (j != 0x16) { 2340 continue; 2341 } 2342 if (mbuf[0] != 0x01) { 2343 continue; 2344 } 2345 if (mbuf[1] != 0x03) { 2346 continue; 2347 } 2348 if (mbuf[4] == 0x00) { 2349 continue; 2350 } 2351 if (mbuf[3] > 0x64) { 2352 continue; 2353 } 2354 if (is885(dev) || is880(dev)) { 2355 if (mbuf[4] > 0x0e) { 2356 mbuf[4] = 0x0e; 2357 } 2358 } else { 2359 if (mbuf[4] > 0x0c) { 2360 mbuf[4] = 0x0c; 2361 } 2362 } 2363 dev->id[c][i].devsp = mbuf[4]; 2364 if (is885(dev) || is880(dev)) 2365 if (mbuf[3] < 0x0c) { 2366 j = 0xb0; 2367 goto set_syn_ok; 2368 } 2369 if ((mbuf[3] < 0x0d) && (rmb == 0)) { 2370 j = 0xa0; 2371 goto set_syn_ok; 2372 } 2373 if (mbuf[3] < 0x1a) { 2374 j = 0x20; 2375 goto set_syn_ok; 2376 } 2377 if (mbuf[3] < 0x33) { 2378 j = 0x40; 2379 goto set_syn_ok; 2380 } 2381 if (mbuf[3] < 0x4c) { 2382 j = 0x50; 2383 goto set_syn_ok; 2384 } 2385 j = 0x60; 2386 set_syn_ok: 2387 dev->id[c][i].devsp = (dev->id[c][i].devsp & 0x0f) | j; 2388 #ifdef ED_DBGP 2389 printk("dev->id[%2d][%2d].devsp = %2x\n", 2390 c,i,dev->id[c][i].devsp); 2391 #endif 2392 } 2393 } 2394