1 /* 2 * Copyright (C) 1997 Wu Ching Chen 3 * 2.1.x update (C) 1998 Krzysztof G. Baranowski 4 * 2.5.x update (C) 2002 Red Hat 5 * 2.6.x update (C) 2004 Red Hat 6 * 7 * Marcelo Tosatti <marcelo@conectiva.com.br> : SMP fixes 8 * 9 * Wu Ching Chen : NULL pointer fixes 2000/06/02 10 * support atp876 chip 11 * enable 32 bit fifo transfer 12 * support cdrom & remove device run ultra speed 13 * fix disconnect bug 2000/12/21 14 * support atp880 chip lvd u160 2001/05/15 15 * fix prd table bug 2001/09/12 (7.1) 16 * 17 * atp885 support add by ACARD Hao Ping Lian 2005/01/05 18 */ 19 #include <linux/module.h> 20 #include <linux/init.h> 21 #include <linux/interrupt.h> 22 #include <linux/kernel.h> 23 #include <linux/types.h> 24 #include <linux/string.h> 25 #include <linux/ioport.h> 26 #include <linux/delay.h> 27 #include <linux/proc_fs.h> 28 #include <linux/spinlock.h> 29 #include <linux/pci.h> 30 #include <linux/blkdev.h> 31 #include <linux/dma-mapping.h> 32 #include <linux/slab.h> 33 #include <asm/io.h> 34 35 #include <scsi/scsi.h> 36 #include <scsi/scsi_cmnd.h> 37 #include <scsi/scsi_device.h> 38 #include <scsi/scsi_host.h> 39 40 #include "atp870u.h" 41 42 static struct scsi_host_template atp870u_template; 43 static void send_s870(struct atp_unit *dev,unsigned char c); 44 static void atp_is(struct atp_unit *dev, unsigned char c, bool wide_chip, unsigned char lvdmode); 45 46 static inline void atp_writeb_base(struct atp_unit *atp, u8 reg, u8 val) 47 { 48 outb(val, atp->baseport + reg); 49 } 50 51 static inline void atp_writew_base(struct atp_unit *atp, u8 reg, u16 val) 52 { 53 outw(val, atp->baseport + reg); 54 } 55 56 static inline void atp_writeb_io(struct atp_unit *atp, u8 channel, u8 reg, u8 val) 57 { 58 outb(val, atp->ioport[channel] + reg); 59 } 60 61 static inline void atp_writew_io(struct atp_unit *atp, u8 channel, u8 reg, u16 val) 62 { 63 outw(val, atp->ioport[channel] + reg); 64 } 65 66 static inline void atp_writeb_pci(struct atp_unit *atp, u8 channel, u8 reg, u8 val) 67 { 68 outb(val, atp->pciport[channel] + reg); 69 } 70 71 static inline void atp_writel_pci(struct atp_unit *atp, u8 channel, u8 reg, u32 val) 72 { 73 outl(val, atp->pciport[channel] + reg); 74 } 75 76 static inline u8 atp_readb_base(struct atp_unit *atp, u8 reg) 77 { 78 return inb(atp->baseport + reg); 79 } 80 81 static inline u16 atp_readw_base(struct atp_unit *atp, u8 reg) 82 { 83 return inw(atp->baseport + reg); 84 } 85 86 static inline u32 atp_readl_base(struct atp_unit *atp, u8 reg) 87 { 88 return inl(atp->baseport + reg); 89 } 90 91 static inline u8 atp_readb_io(struct atp_unit *atp, u8 channel, u8 reg) 92 { 93 return inb(atp->ioport[channel] + reg); 94 } 95 96 static inline u16 atp_readw_io(struct atp_unit *atp, u8 channel, u8 reg) 97 { 98 return inw(atp->ioport[channel] + reg); 99 } 100 101 static inline u8 atp_readb_pci(struct atp_unit *atp, u8 channel, u8 reg) 102 { 103 return inb(atp->pciport[channel] + reg); 104 } 105 106 static inline bool is880(struct atp_unit *atp) 107 { 108 return atp->pdev->device == ATP880_DEVID1 || 109 atp->pdev->device == ATP880_DEVID2; 110 } 111 112 static inline bool is885(struct atp_unit *atp) 113 { 114 return atp->pdev->device == ATP885_DEVID; 115 } 116 117 static irqreturn_t atp870u_intr_handle(int irq, void *dev_id) 118 { 119 unsigned long flags; 120 unsigned short int id; 121 unsigned char i, j, c, target_id, lun,cmdp; 122 unsigned char *prd; 123 struct scsi_cmnd *workreq; 124 unsigned long adrcnt, k; 125 #ifdef ED_DBGP 126 unsigned long l; 127 #endif 128 struct Scsi_Host *host = dev_id; 129 struct atp_unit *dev = (struct atp_unit *)&host->hostdata; 130 131 for (c = 0; c < 2; c++) { 132 j = atp_readb_io(dev, c, 0x1f); 133 if ((j & 0x80) != 0) 134 break; 135 dev->in_int[c] = 0; 136 } 137 if ((j & 0x80) == 0) 138 return IRQ_NONE; 139 #ifdef ED_DBGP 140 printk("atp870u_intr_handle enter\n"); 141 #endif 142 dev->in_int[c] = 1; 143 cmdp = atp_readb_io(dev, c, 0x10); 144 if (dev->working[c] != 0) { 145 if (is885(dev)) { 146 if ((atp_readb_io(dev, c, 0x16) & 0x80) == 0) 147 atp_writeb_io(dev, c, 0x16, (atp_readb_io(dev, c, 0x16) | 0x80)); 148 } 149 if ((atp_readb_pci(dev, c, 0x00) & 0x08) != 0) 150 { 151 for (k=0; k < 1000; k++) { 152 if ((atp_readb_pci(dev, c, 2) & 0x08) == 0) 153 break; 154 if ((atp_readb_pci(dev, c, 2) & 0x01) == 0) 155 break; 156 } 157 } 158 atp_writeb_pci(dev, c, 0, 0x00); 159 160 i = atp_readb_io(dev, c, 0x17); 161 162 if (is885(dev)) 163 atp_writeb_pci(dev, c, 2, 0x06); 164 165 target_id = atp_readb_io(dev, c, 0x15); 166 167 /* 168 * Remap wide devices onto id numbers 169 */ 170 171 if ((target_id & 0x40) != 0) { 172 target_id = (target_id & 0x07) | 0x08; 173 } else { 174 target_id &= 0x07; 175 } 176 177 if ((j & 0x40) != 0) { 178 if (dev->last_cmd[c] == 0xff) { 179 dev->last_cmd[c] = target_id; 180 } 181 dev->last_cmd[c] |= 0x40; 182 } 183 if (is885(dev)) 184 dev->r1f[c][target_id] |= j; 185 #ifdef ED_DBGP 186 printk("atp870u_intr_handle status = %x\n",i); 187 #endif 188 if (i == 0x85) { 189 if ((dev->last_cmd[c] & 0xf0) != 0x40) { 190 dev->last_cmd[c] = 0xff; 191 } 192 if (is885(dev)) { 193 adrcnt = 0; 194 ((unsigned char *) &adrcnt)[2] = atp_readb_io(dev, c, 0x12); 195 ((unsigned char *) &adrcnt)[1] = atp_readb_io(dev, c, 0x13); 196 ((unsigned char *) &adrcnt)[0] = atp_readb_io(dev, c, 0x14); 197 if (dev->id[c][target_id].last_len != adrcnt) { 198 k = dev->id[c][target_id].last_len; 199 k -= adrcnt; 200 dev->id[c][target_id].tran_len = k; 201 dev->id[c][target_id].last_len = adrcnt; 202 } 203 #ifdef ED_DBGP 204 printk("dev->id[c][target_id].last_len = %d dev->id[c][target_id].tran_len = %d\n",dev->id[c][target_id].last_len,dev->id[c][target_id].tran_len); 205 #endif 206 } 207 208 /* 209 * Flip wide 210 */ 211 if (dev->wide_id[c] != 0) { 212 atp_writeb_io(dev, c, 0x1b, 0x01); 213 while ((atp_readb_io(dev, c, 0x1b) & 0x01) != 0x01) 214 atp_writeb_io(dev, c, 0x1b, 0x01); 215 } 216 /* 217 * Issue more commands 218 */ 219 spin_lock_irqsave(dev->host->host_lock, flags); 220 if (((dev->quhd[c] != dev->quend[c]) || (dev->last_cmd[c] != 0xff)) && 221 (dev->in_snd[c] == 0)) { 222 #ifdef ED_DBGP 223 printk("Call sent_s870\n"); 224 #endif 225 send_s870(dev,c); 226 } 227 spin_unlock_irqrestore(dev->host->host_lock, flags); 228 /* 229 * Done 230 */ 231 dev->in_int[c] = 0; 232 #ifdef ED_DBGP 233 printk("Status 0x85 return\n"); 234 #endif 235 return IRQ_HANDLED; 236 } 237 238 if (i == 0x40) { 239 dev->last_cmd[c] |= 0x40; 240 dev->in_int[c] = 0; 241 return IRQ_HANDLED; 242 } 243 244 if (i == 0x21) { 245 if ((dev->last_cmd[c] & 0xf0) != 0x40) { 246 dev->last_cmd[c] = 0xff; 247 } 248 adrcnt = 0; 249 ((unsigned char *) &adrcnt)[2] = atp_readb_io(dev, c, 0x12); 250 ((unsigned char *) &adrcnt)[1] = atp_readb_io(dev, c, 0x13); 251 ((unsigned char *) &adrcnt)[0] = atp_readb_io(dev, c, 0x14); 252 k = dev->id[c][target_id].last_len; 253 k -= adrcnt; 254 dev->id[c][target_id].tran_len = k; 255 dev->id[c][target_id].last_len = adrcnt; 256 atp_writeb_io(dev, c, 0x10, 0x41); 257 atp_writeb_io(dev, c, 0x18, 0x08); 258 dev->in_int[c] = 0; 259 return IRQ_HANDLED; 260 } 261 262 if (is885(dev)) { 263 if ((i == 0x4c) || (i == 0x4d) || (i == 0x8c) || (i == 0x8d)) { 264 if ((i == 0x4c) || (i == 0x8c)) 265 i=0x48; 266 else 267 i=0x49; 268 } 269 270 } 271 if ((i == 0x80) || (i == 0x8f)) { 272 #ifdef ED_DBGP 273 printk(KERN_DEBUG "Device reselect\n"); 274 #endif 275 lun = 0; 276 if (cmdp == 0x44 || i == 0x80) 277 lun = atp_readb_io(dev, c, 0x1d) & 0x07; 278 else { 279 if ((dev->last_cmd[c] & 0xf0) != 0x40) { 280 dev->last_cmd[c] = 0xff; 281 } 282 if (cmdp == 0x41) { 283 #ifdef ED_DBGP 284 printk("cmdp = 0x41\n"); 285 #endif 286 adrcnt = 0; 287 ((unsigned char *) &adrcnt)[2] = atp_readb_io(dev, c, 0x12); 288 ((unsigned char *) &adrcnt)[1] = atp_readb_io(dev, c, 0x13); 289 ((unsigned char *) &adrcnt)[0] = atp_readb_io(dev, c, 0x14); 290 k = dev->id[c][target_id].last_len; 291 k -= adrcnt; 292 dev->id[c][target_id].tran_len = k; 293 dev->id[c][target_id].last_len = adrcnt; 294 atp_writeb_io(dev, c, 0x18, 0x08); 295 dev->in_int[c] = 0; 296 return IRQ_HANDLED; 297 } else { 298 #ifdef ED_DBGP 299 printk("cmdp != 0x41\n"); 300 #endif 301 atp_writeb_io(dev, c, 0x10, 0x46); 302 dev->id[c][target_id].dirct = 0x00; 303 atp_writeb_io(dev, c, 0x12, 0x00); 304 atp_writeb_io(dev, c, 0x13, 0x00); 305 atp_writeb_io(dev, c, 0x14, 0x00); 306 atp_writeb_io(dev, c, 0x18, 0x08); 307 dev->in_int[c] = 0; 308 return IRQ_HANDLED; 309 } 310 } 311 if (dev->last_cmd[c] != 0xff) { 312 dev->last_cmd[c] |= 0x40; 313 } 314 if (is885(dev)) { 315 j = atp_readb_base(dev, 0x29) & 0xfe; 316 atp_writeb_base(dev, 0x29, j); 317 } else 318 atp_writeb_io(dev, c, 0x10, 0x45); 319 320 target_id = atp_readb_io(dev, c, 0x16); 321 /* 322 * Remap wide identifiers 323 */ 324 if ((target_id & 0x10) != 0) { 325 target_id = (target_id & 0x07) | 0x08; 326 } else { 327 target_id &= 0x07; 328 } 329 if (is885(dev)) 330 atp_writeb_io(dev, c, 0x10, 0x45); 331 workreq = dev->id[c][target_id].curr_req; 332 #ifdef ED_DBGP 333 scmd_printk(KERN_DEBUG, workreq, "CDB"); 334 for (l = 0; l < workreq->cmd_len; l++) 335 printk(KERN_DEBUG " %x",workreq->cmnd[l]); 336 printk("\n"); 337 #endif 338 339 atp_writeb_io(dev, c, 0x0f, lun); 340 atp_writeb_io(dev, c, 0x11, dev->id[c][target_id].devsp); 341 adrcnt = dev->id[c][target_id].tran_len; 342 k = dev->id[c][target_id].last_len; 343 344 atp_writeb_io(dev, c, 0x12, ((unsigned char *) &k)[2]); 345 atp_writeb_io(dev, c, 0x13, ((unsigned char *) &k)[1]); 346 atp_writeb_io(dev, c, 0x14, ((unsigned char *) &k)[0]); 347 #ifdef ED_DBGP 348 printk("k %x, k[0] 0x%x k[1] 0x%x k[2] 0x%x\n", k, atp_readb_io(dev, c, 0x14), atp_readb_io(dev, c, 0x13), atp_readb_io(dev, c, 0x12)); 349 #endif 350 /* Remap wide */ 351 j = target_id; 352 if (target_id > 7) { 353 j = (j & 0x07) | 0x40; 354 } 355 /* Add direction */ 356 j |= dev->id[c][target_id].dirct; 357 atp_writeb_io(dev, c, 0x15, j); 358 atp_writeb_io(dev, c, 0x16, 0x80); 359 360 /* enable 32 bit fifo transfer */ 361 if (is885(dev)) { 362 i = atp_readb_pci(dev, c, 1) & 0xf3; 363 //j=workreq->cmnd[0]; 364 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) { 365 i |= 0x0c; 366 } 367 atp_writeb_pci(dev, c, 1, i); 368 } else if (is880(dev)) { 369 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) 370 atp_writeb_base(dev, 0x3b, (atp_readb_base(dev, 0x3b) & 0x3f) | 0xc0); 371 else 372 atp_writeb_base(dev, 0x3b, atp_readb_base(dev, 0x3b) & 0x3f); 373 } else { 374 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) 375 atp_writeb_base(dev, 0x3a, (atp_readb_base(dev, 0x3a) & 0xf3) | 0x08); 376 else 377 atp_writeb_base(dev, 0x3a, atp_readb_base(dev, 0x3a) & 0xf3); 378 } 379 j = 0; 380 id = 1; 381 id = id << target_id; 382 /* 383 * Is this a wide device 384 */ 385 if ((id & dev->wide_id[c]) != 0) { 386 j |= 0x01; 387 } 388 atp_writeb_io(dev, c, 0x1b, j); 389 while ((atp_readb_io(dev, c, 0x1b) & 0x01) != j) 390 atp_writeb_io(dev, c, 0x1b, j); 391 if (dev->id[c][target_id].last_len == 0) { 392 atp_writeb_io(dev, c, 0x18, 0x08); 393 dev->in_int[c] = 0; 394 #ifdef ED_DBGP 395 printk("dev->id[c][target_id].last_len = 0\n"); 396 #endif 397 return IRQ_HANDLED; 398 } 399 #ifdef ED_DBGP 400 printk("target_id = %d adrcnt = %d\n",target_id,adrcnt); 401 #endif 402 prd = dev->id[c][target_id].prd_pos; 403 while (adrcnt != 0) { 404 id = ((unsigned short int *)prd)[2]; 405 if (id == 0) { 406 k = 0x10000; 407 } else { 408 k = id; 409 } 410 if (k > adrcnt) { 411 ((unsigned short int *)prd)[2] = (unsigned short int) 412 (k - adrcnt); 413 ((unsigned long *)prd)[0] += adrcnt; 414 adrcnt = 0; 415 dev->id[c][target_id].prd_pos = prd; 416 } else { 417 adrcnt -= k; 418 dev->id[c][target_id].prdaddr += 0x08; 419 prd += 0x08; 420 if (adrcnt == 0) { 421 dev->id[c][target_id].prd_pos = prd; 422 } 423 } 424 } 425 atp_writel_pci(dev, c, 0x04, dev->id[c][target_id].prdaddr); 426 #ifdef ED_DBGP 427 printk("dev->id[%d][%d].prdaddr 0x%8x\n", c, target_id, dev->id[c][target_id].prdaddr); 428 #endif 429 if (!is885(dev)) { 430 atp_writeb_pci(dev, c, 2, 0x06); 431 atp_writeb_pci(dev, c, 2, 0x00); 432 } 433 /* 434 * Check transfer direction 435 */ 436 if (dev->id[c][target_id].dirct != 0) { 437 atp_writeb_io(dev, c, 0x18, 0x08); 438 atp_writeb_pci(dev, c, 0, 0x01); 439 dev->in_int[c] = 0; 440 #ifdef ED_DBGP 441 printk("status 0x80 return dirct != 0\n"); 442 #endif 443 return IRQ_HANDLED; 444 } 445 atp_writeb_io(dev, c, 0x18, 0x08); 446 atp_writeb_pci(dev, c, 0, 0x09); 447 dev->in_int[c] = 0; 448 #ifdef ED_DBGP 449 printk("status 0x80 return dirct = 0\n"); 450 #endif 451 return IRQ_HANDLED; 452 } 453 454 /* 455 * Current scsi request on this target 456 */ 457 458 workreq = dev->id[c][target_id].curr_req; 459 460 if (i == 0x42 || i == 0x16) { 461 if ((dev->last_cmd[c] & 0xf0) != 0x40) { 462 dev->last_cmd[c] = 0xff; 463 } 464 if (i == 0x16) { 465 workreq->result = atp_readb_io(dev, c, 0x0f); 466 if (((dev->r1f[c][target_id] & 0x10) != 0) && is885(dev)) { 467 printk(KERN_WARNING "AEC67162 CRC ERROR !\n"); 468 workreq->result = 0x02; 469 } 470 } else 471 workreq->result = 0x02; 472 473 if (is885(dev)) { 474 j = atp_readb_base(dev, 0x29) | 0x01; 475 atp_writeb_base(dev, 0x29, j); 476 } 477 /* 478 * Complete the command 479 */ 480 scsi_dma_unmap(workreq); 481 482 spin_lock_irqsave(dev->host->host_lock, flags); 483 (*workreq->scsi_done) (workreq); 484 #ifdef ED_DBGP 485 printk("workreq->scsi_done\n"); 486 #endif 487 /* 488 * Clear it off the queue 489 */ 490 dev->id[c][target_id].curr_req = NULL; 491 dev->working[c]--; 492 spin_unlock_irqrestore(dev->host->host_lock, flags); 493 /* 494 * Take it back wide 495 */ 496 if (dev->wide_id[c] != 0) { 497 atp_writeb_io(dev, c, 0x1b, 0x01); 498 while ((atp_readb_io(dev, c, 0x1b) & 0x01) != 0x01) 499 atp_writeb_io(dev, c, 0x1b, 0x01); 500 } 501 /* 502 * If there is stuff to send and nothing going then send it 503 */ 504 spin_lock_irqsave(dev->host->host_lock, flags); 505 if (((dev->last_cmd[c] != 0xff) || (dev->quhd[c] != dev->quend[c])) && 506 (dev->in_snd[c] == 0)) { 507 #ifdef ED_DBGP 508 printk("Call sent_s870(scsi_done)\n"); 509 #endif 510 send_s870(dev,c); 511 } 512 spin_unlock_irqrestore(dev->host->host_lock, flags); 513 dev->in_int[c] = 0; 514 return IRQ_HANDLED; 515 } 516 if ((dev->last_cmd[c] & 0xf0) != 0x40) { 517 dev->last_cmd[c] = 0xff; 518 } 519 if (i == 0x4f) { 520 i = 0x89; 521 } 522 i &= 0x0f; 523 if (i == 0x09) { 524 atp_writel_pci(dev, c, 4, dev->id[c][target_id].prdaddr); 525 atp_writeb_pci(dev, c, 2, 0x06); 526 atp_writeb_pci(dev, c, 2, 0x00); 527 atp_writeb_io(dev, c, 0x10, 0x41); 528 if (is885(dev)) { 529 k = dev->id[c][target_id].last_len; 530 atp_writeb_io(dev, c, 0x12, ((unsigned char *) (&k))[2]); 531 atp_writeb_io(dev, c, 0x13, ((unsigned char *) (&k))[1]); 532 atp_writeb_io(dev, c, 0x14, ((unsigned char *) (&k))[0]); 533 dev->id[c][target_id].dirct = 0x00; 534 } else { 535 dev->id[c][target_id].dirct = 0x00; 536 } 537 atp_writeb_io(dev, c, 0x18, 0x08); 538 atp_writeb_pci(dev, c, 0, 0x09); 539 dev->in_int[c] = 0; 540 return IRQ_HANDLED; 541 } 542 if (i == 0x08) { 543 atp_writel_pci(dev, c, 4, dev->id[c][target_id].prdaddr); 544 atp_writeb_pci(dev, c, 2, 0x06); 545 atp_writeb_pci(dev, c, 2, 0x00); 546 atp_writeb_io(dev, c, 0x10, 0x41); 547 if (is885(dev)) { 548 k = dev->id[c][target_id].last_len; 549 atp_writeb_io(dev, c, 0x12, ((unsigned char *) (&k))[2]); 550 atp_writeb_io(dev, c, 0x13, ((unsigned char *) (&k))[1]); 551 atp_writeb_io(dev, c, 0x14, ((unsigned char *) (&k))[0]); 552 } 553 atp_writeb_io(dev, c, 0x15, atp_readb_io(dev, c, 0x15) | 0x20); 554 dev->id[c][target_id].dirct = 0x20; 555 atp_writeb_io(dev, c, 0x18, 0x08); 556 atp_writeb_pci(dev, c, 0, 0x01); 557 dev->in_int[c] = 0; 558 return IRQ_HANDLED; 559 } 560 if (i == 0x0a) 561 atp_writeb_io(dev, c, 0x10, 0x30); 562 else 563 atp_writeb_io(dev, c, 0x10, 0x46); 564 dev->id[c][target_id].dirct = 0x00; 565 atp_writeb_io(dev, c, 0x12, 0x00); 566 atp_writeb_io(dev, c, 0x13, 0x00); 567 atp_writeb_io(dev, c, 0x14, 0x00); 568 atp_writeb_io(dev, c, 0x18, 0x08); 569 } 570 dev->in_int[c] = 0; 571 572 return IRQ_HANDLED; 573 } 574 /** 575 * atp870u_queuecommand - Queue SCSI command 576 * @req_p: request block 577 * @done: completion function 578 * 579 * Queue a command to the ATP queue. Called with the host lock held. 580 */ 581 static int atp870u_queuecommand_lck(struct scsi_cmnd *req_p, 582 void (*done) (struct scsi_cmnd *)) 583 { 584 unsigned char c; 585 unsigned int m; 586 struct atp_unit *dev; 587 struct Scsi_Host *host; 588 589 c = scmd_channel(req_p); 590 req_p->sense_buffer[0]=0; 591 scsi_set_resid(req_p, 0); 592 if (scmd_channel(req_p) > 1) { 593 req_p->result = 0x00040000; 594 done(req_p); 595 #ifdef ED_DBGP 596 printk("atp870u_queuecommand : req_p->device->channel > 1\n"); 597 #endif 598 return 0; 599 } 600 601 host = req_p->device->host; 602 dev = (struct atp_unit *)&host->hostdata; 603 604 605 606 m = 1; 607 m = m << scmd_id(req_p); 608 609 /* 610 * Fake a timeout for missing targets 611 */ 612 613 if ((m & dev->active_id[c]) == 0) { 614 req_p->result = 0x00040000; 615 done(req_p); 616 return 0; 617 } 618 619 if (done) { 620 req_p->scsi_done = done; 621 } else { 622 #ifdef ED_DBGP 623 printk( "atp870u_queuecommand: done can't be NULL\n"); 624 #endif 625 req_p->result = 0; 626 done(req_p); 627 return 0; 628 } 629 630 /* 631 * Count new command 632 */ 633 dev->quend[c]++; 634 if (dev->quend[c] >= qcnt) { 635 dev->quend[c] = 0; 636 } 637 638 /* 639 * Check queue state 640 */ 641 if (dev->quhd[c] == dev->quend[c]) { 642 if (dev->quend[c] == 0) { 643 dev->quend[c] = qcnt; 644 } 645 #ifdef ED_DBGP 646 printk("atp870u_queuecommand : dev->quhd[c] == dev->quend[c]\n"); 647 #endif 648 dev->quend[c]--; 649 req_p->result = 0x00020000; 650 done(req_p); 651 return 0; 652 } 653 dev->quereq[c][dev->quend[c]] = req_p; 654 #ifdef ED_DBGP 655 printk("dev->ioport[c] = %x atp_readb_io(dev, c, 0x1c) = %x dev->in_int[%d] = %d dev->in_snd[%d] = %d\n",dev->ioport[c],atp_readb_io(dev, c, 0x1c),c,dev->in_int[c],c,dev->in_snd[c]); 656 #endif 657 if ((atp_readb_io(dev, c, 0x1c) == 0) && (dev->in_int[c] == 0) && (dev->in_snd[c] == 0)) { 658 #ifdef ED_DBGP 659 printk("Call sent_s870(atp870u_queuecommand)\n"); 660 #endif 661 send_s870(dev,c); 662 } 663 #ifdef ED_DBGP 664 printk("atp870u_queuecommand : exit\n"); 665 #endif 666 return 0; 667 } 668 669 static DEF_SCSI_QCMD(atp870u_queuecommand) 670 671 /** 672 * send_s870 - send a command to the controller 673 * @host: host 674 * 675 * On entry there is work queued to be done. We move some of that work to the 676 * controller itself. 677 * 678 * Caller holds the host lock. 679 */ 680 static void send_s870(struct atp_unit *dev,unsigned char c) 681 { 682 struct scsi_cmnd *workreq = NULL; 683 unsigned int i;//,k; 684 unsigned char j, target_id; 685 unsigned char *prd; 686 unsigned short int w; 687 unsigned long l, bttl = 0; 688 unsigned long sg_count; 689 690 if (dev->in_snd[c] != 0) { 691 #ifdef ED_DBGP 692 printk("cmnd in_snd\n"); 693 #endif 694 return; 695 } 696 #ifdef ED_DBGP 697 printk("Sent_s870 enter\n"); 698 #endif 699 dev->in_snd[c] = 1; 700 if ((dev->last_cmd[c] != 0xff) && ((dev->last_cmd[c] & 0x40) != 0)) { 701 dev->last_cmd[c] &= 0x0f; 702 workreq = dev->id[c][dev->last_cmd[c]].curr_req; 703 if (!workreq) { 704 dev->last_cmd[c] = 0xff; 705 if (dev->quhd[c] == dev->quend[c]) { 706 dev->in_snd[c] = 0; 707 return; 708 } 709 } 710 } 711 if (!workreq) { 712 if ((dev->last_cmd[c] != 0xff) && (dev->working[c] != 0)) { 713 dev->in_snd[c] = 0; 714 return; 715 } 716 dev->working[c]++; 717 j = dev->quhd[c]; 718 dev->quhd[c]++; 719 if (dev->quhd[c] >= qcnt) 720 dev->quhd[c] = 0; 721 workreq = dev->quereq[c][dev->quhd[c]]; 722 if (dev->id[c][scmd_id(workreq)].curr_req != NULL) { 723 dev->quhd[c] = j; 724 dev->working[c]--; 725 dev->in_snd[c] = 0; 726 return; 727 } 728 dev->id[c][scmd_id(workreq)].curr_req = workreq; 729 dev->last_cmd[c] = scmd_id(workreq); 730 } 731 if ((atp_readb_io(dev, c, 0x1f) & 0xb0) != 0 || atp_readb_io(dev, c, 0x1c) != 0) { 732 #ifdef ED_DBGP 733 printk("Abort to Send\n"); 734 #endif 735 dev->last_cmd[c] |= 0x40; 736 dev->in_snd[c] = 0; 737 return; 738 } 739 #ifdef ED_DBGP 740 printk("OK to Send\n"); 741 scmd_printk(KERN_DEBUG, workreq, "CDB"); 742 for(i=0;i<workreq->cmd_len;i++) { 743 printk(" %x",workreq->cmnd[i]); 744 } 745 printk("\n"); 746 #endif 747 l = scsi_bufflen(workreq); 748 749 if (is885(dev)) { 750 j = atp_readb_base(dev, 0x29) & 0xfe; 751 atp_writeb_base(dev, 0x29, j); 752 dev->r1f[c][scmd_id(workreq)] = 0; 753 } 754 755 if (workreq->cmnd[0] == READ_CAPACITY) { 756 if (l > 8) 757 l = 8; 758 } 759 if (workreq->cmnd[0] == 0x00) { 760 l = 0; 761 } 762 763 j = 0; 764 target_id = scmd_id(workreq); 765 766 /* 767 * Wide ? 768 */ 769 w = 1; 770 w = w << target_id; 771 if ((w & dev->wide_id[c]) != 0) { 772 j |= 0x01; 773 } 774 atp_writeb_io(dev, c, 0x1b, j); 775 while ((atp_readb_io(dev, c, 0x1b) & 0x01) != j) { 776 atp_writeb_pci(dev, c, 0x1b, j); 777 #ifdef ED_DBGP 778 printk("send_s870 while loop 1\n"); 779 #endif 780 } 781 /* 782 * Write the command 783 */ 784 785 atp_writeb_io(dev, c, 0x00, workreq->cmd_len); 786 atp_writeb_io(dev, c, 0x01, 0x2c); 787 if (is885(dev)) 788 atp_writeb_io(dev, c, 0x02, 0x7f); 789 else 790 atp_writeb_io(dev, c, 0x02, 0xcf); 791 for (i = 0; i < workreq->cmd_len; i++) 792 atp_writeb_io(dev, c, 0x03 + i, workreq->cmnd[i]); 793 atp_writeb_io(dev, c, 0x0f, workreq->device->lun); 794 /* 795 * Write the target 796 */ 797 atp_writeb_io(dev, c, 0x11, dev->id[c][target_id].devsp); 798 #ifdef ED_DBGP 799 printk("dev->id[%d][%d].devsp = %2x\n",c,target_id,dev->id[c][target_id].devsp); 800 #endif 801 802 sg_count = scsi_dma_map(workreq); 803 /* 804 * Write transfer size 805 */ 806 atp_writeb_io(dev, c, 0x12, ((unsigned char *) (&l))[2]); 807 atp_writeb_io(dev, c, 0x13, ((unsigned char *) (&l))[1]); 808 atp_writeb_io(dev, c, 0x14, ((unsigned char *) (&l))[0]); 809 j = target_id; 810 dev->id[c][j].last_len = l; 811 dev->id[c][j].tran_len = 0; 812 #ifdef ED_DBGP 813 printk("dev->id[%2d][%2d].last_len = %d\n",c,j,dev->id[c][j].last_len); 814 #endif 815 /* 816 * Flip the wide bits 817 */ 818 if ((j & 0x08) != 0) { 819 j = (j & 0x07) | 0x40; 820 } 821 /* 822 * Check transfer direction 823 */ 824 if (workreq->sc_data_direction == DMA_TO_DEVICE) 825 atp_writeb_io(dev, c, 0x15, j | 0x20); 826 else 827 atp_writeb_io(dev, c, 0x15, j); 828 atp_writeb_io(dev, c, 0x16, atp_readb_io(dev, c, 0x16) | 0x80); 829 atp_writeb_io(dev, c, 0x16, 0x80); 830 dev->id[c][target_id].dirct = 0; 831 if (l == 0) { 832 if (atp_readb_io(dev, c, 0x1c) == 0) { 833 #ifdef ED_DBGP 834 printk("change SCSI_CMD_REG 0x08\n"); 835 #endif 836 atp_writeb_io(dev, c, 0x18, 0x08); 837 } else 838 dev->last_cmd[c] |= 0x40; 839 dev->in_snd[c] = 0; 840 return; 841 } 842 prd = dev->id[c][target_id].prd_table; 843 dev->id[c][target_id].prd_pos = prd; 844 845 /* 846 * Now write the request list. Either as scatter/gather or as 847 * a linear chain. 848 */ 849 850 if (l) { 851 struct scatterlist *sgpnt; 852 i = 0; 853 scsi_for_each_sg(workreq, sgpnt, sg_count, j) { 854 bttl = sg_dma_address(sgpnt); 855 l=sg_dma_len(sgpnt); 856 #ifdef ED_DBGP 857 printk("1. bttl %x, l %x\n",bttl, l); 858 #endif 859 while (l > 0x10000) { 860 (((u16 *) (prd))[i + 3]) = 0x0000; 861 (((u16 *) (prd))[i + 2]) = 0x0000; 862 (((u32 *) (prd))[i >> 1]) = cpu_to_le32(bttl); 863 l -= 0x10000; 864 bttl += 0x10000; 865 i += 0x04; 866 } 867 (((u32 *) (prd))[i >> 1]) = cpu_to_le32(bttl); 868 (((u16 *) (prd))[i + 2]) = cpu_to_le16(l); 869 (((u16 *) (prd))[i + 3]) = 0; 870 i += 0x04; 871 } 872 (((u16 *) (prd))[i - 1]) = cpu_to_le16(0x8000); 873 #ifdef ED_DBGP 874 printk("prd %4x %4x %4x %4x\n",(((unsigned short int *)prd)[0]),(((unsigned short int *)prd)[1]),(((unsigned short int *)prd)[2]),(((unsigned short int *)prd)[3])); 875 printk("2. bttl %x, l %x\n",bttl, l); 876 #endif 877 } 878 #ifdef ED_DBGP 879 printk("send_s870: prdaddr_2 0x%8x target_id %d\n", dev->id[c][target_id].prdaddr,target_id); 880 #endif 881 dev->id[c][target_id].prdaddr = dev->id[c][target_id].prd_bus; 882 atp_writel_pci(dev, c, 4, dev->id[c][target_id].prdaddr); 883 atp_writeb_pci(dev, c, 2, 0x06); 884 atp_writeb_pci(dev, c, 2, 0x00); 885 if (is885(dev)) { 886 j = atp_readb_pci(dev, c, 1) & 0xf3; 887 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || 888 (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) { 889 j |= 0x0c; 890 } 891 atp_writeb_pci(dev, c, 1, j); 892 } else if (is880(dev)) { 893 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) 894 atp_writeb_base(dev, 0x3b, (atp_readb_base(dev, 0x3b) & 0x3f) | 0xc0); 895 else 896 atp_writeb_base(dev, 0x3b, atp_readb_base(dev, 0x3b) & 0x3f); 897 } else { 898 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) 899 atp_writeb_base(dev, 0x3a, (atp_readb_base(dev, 0x3a) & 0xf3) | 0x08); 900 else 901 atp_writeb_base(dev, 0x3a, atp_readb_base(dev, 0x3a) & 0xf3); 902 } 903 904 if(workreq->sc_data_direction == DMA_TO_DEVICE) { 905 dev->id[c][target_id].dirct = 0x20; 906 if (atp_readb_io(dev, c, 0x1c) == 0) { 907 atp_writeb_io(dev, c, 0x18, 0x08); 908 atp_writeb_pci(dev, c, 0, 0x01); 909 #ifdef ED_DBGP 910 printk( "start DMA(to target)\n"); 911 #endif 912 } else { 913 dev->last_cmd[c] |= 0x40; 914 } 915 dev->in_snd[c] = 0; 916 return; 917 } 918 if (atp_readb_io(dev, c, 0x1c) == 0) { 919 atp_writeb_io(dev, c, 0x18, 0x08); 920 atp_writeb_pci(dev, c, 0, 0x09); 921 #ifdef ED_DBGP 922 printk( "start DMA(to host)\n"); 923 #endif 924 } else { 925 dev->last_cmd[c] |= 0x40; 926 } 927 dev->in_snd[c] = 0; 928 return; 929 930 } 931 932 static unsigned char fun_scam(struct atp_unit *dev, unsigned short int *val) 933 { 934 unsigned short int i, k; 935 unsigned char j; 936 937 atp_writew_io(dev, 0, 0x1c, *val); 938 for (i = 0; i < 10; i++) { /* stable >= bus settle delay(400 ns) */ 939 k = atp_readw_io(dev, 0, 0x1c); 940 j = (unsigned char) (k >> 8); 941 if ((k & 0x8000) != 0) /* DB7 all release? */ 942 i = 0; 943 } 944 *val |= 0x4000; /* assert DB6 */ 945 atp_writew_io(dev, 0, 0x1c, *val); 946 *val &= 0xdfff; /* assert DB5 */ 947 atp_writew_io(dev, 0, 0x1c, *val); 948 for (i = 0; i < 10; i++) { /* stable >= bus settle delay(400 ns) */ 949 if ((atp_readw_io(dev, 0, 0x1c) & 0x2000) != 0) /* DB5 all release? */ 950 i = 0; 951 } 952 *val |= 0x8000; /* no DB4-0, assert DB7 */ 953 *val &= 0xe0ff; 954 atp_writew_io(dev, 0, 0x1c, *val); 955 *val &= 0xbfff; /* release DB6 */ 956 atp_writew_io(dev, 0, 0x1c, *val); 957 for (i = 0; i < 10; i++) { /* stable >= bus settle delay(400 ns) */ 958 if ((atp_readw_io(dev, 0, 0x1c) & 0x4000) != 0) /* DB6 all release? */ 959 i = 0; 960 } 961 962 return j; 963 } 964 965 static void tscam(struct Scsi_Host *host, bool wide_chip, u8 scam_on) 966 { 967 968 unsigned char i, j, k; 969 unsigned long n; 970 unsigned short int m, assignid_map, val; 971 unsigned char mbuf[33], quintet[2]; 972 struct atp_unit *dev = (struct atp_unit *)&host->hostdata; 973 static unsigned char g2q_tab[8] = { 974 0x38, 0x31, 0x32, 0x2b, 0x34, 0x2d, 0x2e, 0x27 975 }; 976 977 /* I can't believe we need this before we've even done anything. Remove it 978 * and see if anyone bitches. 979 for (i = 0; i < 0x10; i++) { 980 udelay(0xffff); 981 } 982 */ 983 984 atp_writeb_io(dev, 0, 1, 0x08); 985 atp_writeb_io(dev, 0, 2, 0x7f); 986 atp_writeb_io(dev, 0, 0x11, 0x20); 987 988 if ((scam_on & 0x40) == 0) { 989 return; 990 } 991 m = 1; 992 m <<= dev->host_id[0]; 993 j = 16; 994 if (!wide_chip) { 995 m |= 0xff00; 996 j = 8; 997 } 998 assignid_map = m; 999 atp_writeb_io(dev, 0, 0x02, 0x02); /* 2*2=4ms,3EH 2/32*3E=3.9ms */ 1000 atp_writeb_io(dev, 0, 0x03, 0); 1001 atp_writeb_io(dev, 0, 0x04, 0); 1002 atp_writeb_io(dev, 0, 0x05, 0); 1003 atp_writeb_io(dev, 0, 0x06, 0); 1004 atp_writeb_io(dev, 0, 0x07, 0); 1005 atp_writeb_io(dev, 0, 0x08, 0); 1006 1007 for (i = 0; i < j; i++) { 1008 m = 1; 1009 m = m << i; 1010 if ((m & assignid_map) != 0) { 1011 continue; 1012 } 1013 atp_writeb_io(dev, 0, 0x0f, 0); 1014 atp_writeb_io(dev, 0, 0x12, 0); 1015 atp_writeb_io(dev, 0, 0x13, 0); 1016 atp_writeb_io(dev, 0, 0x14, 0); 1017 if (i > 7) { 1018 k = (i & 0x07) | 0x40; 1019 } else { 1020 k = i; 1021 } 1022 atp_writeb_io(dev, 0, 0x15, k); 1023 if (wide_chip) 1024 atp_writeb_io(dev, 0, 0x1b, 0x01); 1025 else 1026 atp_writeb_io(dev, 0, 0x1b, 0x00); 1027 do { 1028 atp_writeb_io(dev, 0, 0x18, 0x09); 1029 1030 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0x00) 1031 cpu_relax(); 1032 k = atp_readb_io(dev, 0, 0x17); 1033 if ((k == 0x85) || (k == 0x42)) 1034 break; 1035 if (k != 0x16) 1036 atp_writeb_io(dev, 0, 0x10, 0x41); 1037 } while (k != 0x16); 1038 if ((k == 0x85) || (k == 0x42)) 1039 continue; 1040 assignid_map |= m; 1041 1042 } 1043 atp_writeb_io(dev, 0, 0x02, 0x7f); 1044 atp_writeb_io(dev, 0, 0x1b, 0x02); 1045 1046 udelay(2); 1047 1048 val = 0x0080; /* bsy */ 1049 atp_writew_io(dev, 0, 0x1c, val); 1050 val |= 0x0040; /* sel */ 1051 atp_writew_io(dev, 0, 0x1c, val); 1052 val |= 0x0004; /* msg */ 1053 atp_writew_io(dev, 0, 0x1c, val); 1054 udelay(2); /* 2 deskew delay(45ns*2=90ns) */ 1055 val &= 0x007f; /* no bsy */ 1056 atp_writew_io(dev, 0, 0x1c, val); 1057 msleep(128); 1058 val &= 0x00fb; /* after 1ms no msg */ 1059 atp_writew_io(dev, 0, 0x1c, val); 1060 while ((atp_readb_io(dev, 0, 0x1c) & 0x04) != 0) 1061 ; 1062 udelay(2); 1063 udelay(100); 1064 for (n = 0; n < 0x30000; n++) 1065 if ((atp_readb_io(dev, 0, 0x1c) & 0x80) != 0) /* bsy ? */ 1066 break; 1067 if (n < 0x30000) 1068 for (n = 0; n < 0x30000; n++) 1069 if ((atp_readb_io(dev, 0, 0x1c) & 0x81) == 0x0081) { 1070 udelay(2); 1071 val |= 0x8003; /* io,cd,db7 */ 1072 atp_writew_io(dev, 0, 0x1c, val); 1073 udelay(2); 1074 val &= 0x00bf; /* no sel */ 1075 atp_writew_io(dev, 0, 0x1c, val); 1076 udelay(2); 1077 break; 1078 } 1079 while (1) { 1080 /* 1081 * The funny division into multiple delays is to accomodate 1082 * arches like ARM where udelay() multiplies its argument by 1083 * a large number to initialize a loop counter. To avoid 1084 * overflow, the maximum supported udelay is 2000 microseconds. 1085 * 1086 * XXX it would be more polite to find a way to use msleep() 1087 */ 1088 mdelay(2); 1089 udelay(48); 1090 if ((atp_readb_io(dev, 0, 0x1c) & 0x80) == 0x00) { /* bsy ? */ 1091 atp_writew_io(dev, 0, 0x1c, 0); 1092 atp_writeb_io(dev, 0, 0x1b, 0); 1093 atp_writeb_io(dev, 0, 0x15, 0); 1094 atp_writeb_io(dev, 0, 0x18, 0x09); 1095 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0) 1096 cpu_relax(); 1097 atp_readb_io(dev, 0, 0x17); 1098 return; 1099 } 1100 val &= 0x00ff; /* synchronization */ 1101 val |= 0x3f00; 1102 fun_scam(dev, &val); 1103 udelay(2); 1104 val &= 0x00ff; /* isolation */ 1105 val |= 0x2000; 1106 fun_scam(dev, &val); 1107 udelay(2); 1108 i = 8; 1109 j = 0; 1110 1111 while (1) { 1112 if ((atp_readw_io(dev, 0, 0x1c) & 0x2000) == 0) 1113 continue; 1114 udelay(2); 1115 val &= 0x00ff; /* get ID_STRING */ 1116 val |= 0x2000; 1117 k = fun_scam(dev, &val); 1118 if ((k & 0x03) == 0) 1119 break; 1120 mbuf[j] <<= 0x01; 1121 mbuf[j] &= 0xfe; 1122 if ((k & 0x02) != 0) 1123 mbuf[j] |= 0x01; 1124 i--; 1125 if (i > 0) 1126 continue; 1127 j++; 1128 i = 8; 1129 } 1130 1131 /* isolation complete.. */ 1132 /* mbuf[32]=0; 1133 printk(" \n%x %x %x %s\n ",assignid_map,mbuf[0],mbuf[1],&mbuf[2]); */ 1134 i = 15; 1135 j = mbuf[0]; 1136 if ((j & 0x20) != 0) { /* bit5=1:ID up to 7 */ 1137 i = 7; 1138 } 1139 if ((j & 0x06) != 0) { /* IDvalid? */ 1140 k = mbuf[1]; 1141 while (1) { 1142 m = 1; 1143 m <<= k; 1144 if ((m & assignid_map) == 0) 1145 break; 1146 if (k > 0) 1147 k--; 1148 else 1149 break; 1150 } 1151 } 1152 if ((m & assignid_map) != 0) { /* srch from max acceptable ID# */ 1153 k = i; /* max acceptable ID# */ 1154 while (1) { 1155 m = 1; 1156 m <<= k; 1157 if ((m & assignid_map) == 0) 1158 break; 1159 if (k > 0) 1160 k--; 1161 else 1162 break; 1163 } 1164 } 1165 /* k=binID#, */ 1166 assignid_map |= m; 1167 if (k < 8) { 1168 quintet[0] = 0x38; /* 1st dft ID<8 */ 1169 } else { 1170 quintet[0] = 0x31; /* 1st ID>=8 */ 1171 } 1172 k &= 0x07; 1173 quintet[1] = g2q_tab[k]; 1174 1175 val &= 0x00ff; /* AssignID 1stQuintet,AH=001xxxxx */ 1176 m = quintet[0] << 8; 1177 val |= m; 1178 fun_scam(dev, &val); 1179 val &= 0x00ff; /* AssignID 2ndQuintet,AH=001xxxxx */ 1180 m = quintet[1] << 8; 1181 val |= m; 1182 fun_scam(dev, &val); 1183 1184 } 1185 } 1186 1187 static void atp870u_free_tables(struct Scsi_Host *host) 1188 { 1189 struct atp_unit *atp_dev = (struct atp_unit *)&host->hostdata; 1190 int j, k; 1191 for (j=0; j < 2; j++) { 1192 for (k = 0; k < 16; k++) { 1193 if (!atp_dev->id[j][k].prd_table) 1194 continue; 1195 dma_free_coherent(&atp_dev->pdev->dev, 1024, atp_dev->id[j][k].prd_table, atp_dev->id[j][k].prd_bus); 1196 atp_dev->id[j][k].prd_table = NULL; 1197 } 1198 } 1199 } 1200 1201 static int atp870u_init_tables(struct Scsi_Host *host) 1202 { 1203 struct atp_unit *atp_dev = (struct atp_unit *)&host->hostdata; 1204 int c,k; 1205 for(c=0;c < 2;c++) { 1206 for(k=0;k<16;k++) { 1207 atp_dev->id[c][k].prd_table = dma_alloc_coherent(&atp_dev->pdev->dev, 1024, &(atp_dev->id[c][k].prd_bus), GFP_KERNEL); 1208 if (!atp_dev->id[c][k].prd_table) { 1209 printk("atp870u_init_tables fail\n"); 1210 atp870u_free_tables(host); 1211 return -ENOMEM; 1212 } 1213 atp_dev->id[c][k].prdaddr = atp_dev->id[c][k].prd_bus; 1214 atp_dev->id[c][k].devsp=0x20; 1215 atp_dev->id[c][k].devtype = 0x7f; 1216 atp_dev->id[c][k].curr_req = NULL; 1217 } 1218 1219 atp_dev->active_id[c] = 0; 1220 atp_dev->wide_id[c] = 0; 1221 atp_dev->host_id[c] = 0x07; 1222 atp_dev->quhd[c] = 0; 1223 atp_dev->quend[c] = 0; 1224 atp_dev->last_cmd[c] = 0xff; 1225 atp_dev->in_snd[c] = 0; 1226 atp_dev->in_int[c] = 0; 1227 1228 for (k = 0; k < qcnt; k++) { 1229 atp_dev->quereq[c][k] = NULL; 1230 } 1231 for (k = 0; k < 16; k++) { 1232 atp_dev->id[c][k].curr_req = NULL; 1233 atp_dev->sp[c][k] = 0x04; 1234 } 1235 } 1236 return 0; 1237 } 1238 1239 static void atp_set_host_id(struct atp_unit *atp, u8 c, u8 host_id) 1240 { 1241 atp_writeb_io(atp, c, 0, host_id | 0x08); 1242 atp_writeb_io(atp, c, 0x18, 0); 1243 while ((atp_readb_io(atp, c, 0x1f) & 0x80) == 0) 1244 mdelay(1); 1245 atp_readb_io(atp, c, 0x17); 1246 atp_writeb_io(atp, c, 1, 8); 1247 atp_writeb_io(atp, c, 2, 0x7f); 1248 atp_writeb_io(atp, c, 0x11, 0x20); 1249 } 1250 1251 static void atp870_init(struct Scsi_Host *shpnt) 1252 { 1253 struct atp_unit *atpdev = shost_priv(shpnt); 1254 struct pci_dev *pdev = atpdev->pdev; 1255 unsigned char k, host_id; 1256 u8 scam_on; 1257 bool wide_chip = 1258 (pdev->device == PCI_DEVICE_ID_ARTOP_AEC7610 && 1259 pdev->revision == 4) || 1260 (pdev->device == PCI_DEVICE_ID_ARTOP_AEC7612UW) || 1261 (pdev->device == PCI_DEVICE_ID_ARTOP_AEC7612SUW); 1262 1263 pci_read_config_byte(pdev, 0x49, &host_id); 1264 1265 dev_info(&pdev->dev, "ACARD AEC-671X PCI Ultra/W SCSI-2/3 Host Adapter: IO:%lx, IRQ:%d.\n", 1266 shpnt->io_port, shpnt->irq); 1267 1268 atpdev->ioport[0] = shpnt->io_port; 1269 atpdev->pciport[0] = shpnt->io_port + 0x20; 1270 host_id &= 0x07; 1271 atpdev->host_id[0] = host_id; 1272 scam_on = atp_readb_pci(atpdev, 0, 2); 1273 atpdev->global_map[0] = atp_readb_base(atpdev, 0x2d); 1274 atpdev->ultra_map[0] = atp_readw_base(atpdev, 0x2e); 1275 1276 if (atpdev->ultra_map[0] == 0) { 1277 scam_on = 0x00; 1278 atpdev->global_map[0] = 0x20; 1279 atpdev->ultra_map[0] = 0xffff; 1280 } 1281 1282 if (pdev->revision > 0x07) /* check if atp876 chip */ 1283 atp_writeb_base(atpdev, 0x3e, 0x00); /* enable terminator */ 1284 1285 k = (atp_readb_base(atpdev, 0x3a) & 0xf3) | 0x10; 1286 atp_writeb_base(atpdev, 0x3a, k); 1287 atp_writeb_base(atpdev, 0x3a, k & 0xdf); 1288 msleep(32); 1289 atp_writeb_base(atpdev, 0x3a, k); 1290 msleep(32); 1291 atp_set_host_id(atpdev, 0, host_id); 1292 1293 tscam(shpnt, wide_chip, scam_on); 1294 atp_writeb_base(atpdev, 0x3a, atp_readb_base(atpdev, 0x3a) | 0x10); 1295 atp_is(atpdev, 0, wide_chip, 0); 1296 atp_writeb_base(atpdev, 0x3a, atp_readb_base(atpdev, 0x3a) & 0xef); 1297 atp_writeb_base(atpdev, 0x3b, atp_readb_base(atpdev, 0x3b) | 0x20); 1298 shpnt->max_id = wide_chip ? 16 : 8; 1299 shpnt->this_id = host_id; 1300 } 1301 1302 static void atp880_init(struct Scsi_Host *shpnt) 1303 { 1304 struct atp_unit *atpdev = shost_priv(shpnt); 1305 struct pci_dev *pdev = atpdev->pdev; 1306 unsigned char k, m, host_id; 1307 unsigned int n; 1308 1309 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80); 1310 1311 atpdev->ioport[0] = shpnt->io_port + 0x40; 1312 atpdev->pciport[0] = shpnt->io_port + 0x28; 1313 1314 host_id = atp_readb_base(atpdev, 0x39) >> 4; 1315 1316 dev_info(&pdev->dev, "ACARD AEC-67160 PCI Ultra3 LVD Host Adapter: IO:%lx, IRQ:%d.\n", 1317 shpnt->io_port, shpnt->irq); 1318 atpdev->host_id[0] = host_id; 1319 1320 atpdev->global_map[0] = atp_readb_base(atpdev, 0x35); 1321 atpdev->ultra_map[0] = atp_readw_base(atpdev, 0x3c); 1322 1323 n = 0x3f09; 1324 while (n < 0x4000) { 1325 m = 0; 1326 atp_writew_base(atpdev, 0x34, n); 1327 n += 0x0002; 1328 if (atp_readb_base(atpdev, 0x30) == 0xff) 1329 break; 1330 1331 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x30); 1332 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x31); 1333 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x32); 1334 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x33); 1335 atp_writew_base(atpdev, 0x34, n); 1336 n += 0x0002; 1337 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x30); 1338 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x31); 1339 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x32); 1340 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x33); 1341 atp_writew_base(atpdev, 0x34, n); 1342 n += 0x0002; 1343 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x30); 1344 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x31); 1345 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x32); 1346 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x33); 1347 atp_writew_base(atpdev, 0x34, n); 1348 n += 0x0002; 1349 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x30); 1350 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x31); 1351 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x32); 1352 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x33); 1353 n += 0x0018; 1354 } 1355 atp_writew_base(atpdev, 0x34, 0); 1356 atpdev->ultra_map[0] = 0; 1357 atpdev->async[0] = 0; 1358 for (k = 0; k < 16; k++) { 1359 n = 1 << k; 1360 if (atpdev->sp[0][k] > 1) 1361 atpdev->ultra_map[0] |= n; 1362 else 1363 if (atpdev->sp[0][k] == 0) 1364 atpdev->async[0] |= n; 1365 } 1366 atpdev->async[0] = ~(atpdev->async[0]); 1367 atp_writeb_base(atpdev, 0x35, atpdev->global_map[0]); 1368 1369 k = atp_readb_base(atpdev, 0x38) & 0x80; 1370 atp_writeb_base(atpdev, 0x38, k); 1371 atp_writeb_base(atpdev, 0x3b, 0x20); 1372 msleep(32); 1373 atp_writeb_base(atpdev, 0x3b, 0); 1374 msleep(32); 1375 atp_readb_io(atpdev, 0, 0x1b); 1376 atp_readb_io(atpdev, 0, 0x17); 1377 1378 atp_set_host_id(atpdev, 0, host_id); 1379 1380 tscam(shpnt, true, atp_readb_base(atpdev, 0x22)); 1381 atp_is(atpdev, 0, true, atp_readb_base(atpdev, 0x3f) & 0x40); 1382 atp_writeb_base(atpdev, 0x38, 0xb0); 1383 shpnt->max_id = 16; 1384 shpnt->this_id = host_id; 1385 } 1386 1387 static void atp885_init(struct Scsi_Host *shpnt) 1388 { 1389 struct atp_unit *atpdev = shost_priv(shpnt); 1390 struct pci_dev *pdev = atpdev->pdev; 1391 unsigned char k, m, c; 1392 unsigned int n; 1393 unsigned char setupdata[2][16]; 1394 1395 dev_info(&pdev->dev, "ACARD AEC-67162 PCI Ultra3 LVD Host Adapter: IO:%lx, IRQ:%d.\n", 1396 shpnt->io_port, shpnt->irq); 1397 1398 atpdev->ioport[0] = shpnt->io_port + 0x80; 1399 atpdev->ioport[1] = shpnt->io_port + 0xc0; 1400 atpdev->pciport[0] = shpnt->io_port + 0x40; 1401 atpdev->pciport[1] = shpnt->io_port + 0x50; 1402 1403 c = atp_readb_base(atpdev, 0x29); 1404 atp_writeb_base(atpdev, 0x29, c | 0x04); 1405 1406 n = 0x1f80; 1407 while (n < 0x2000) { 1408 atp_writew_base(atpdev, 0x3c, n); 1409 if (atp_readl_base(atpdev, 0x38) == 0xffffffff) 1410 break; 1411 for (m = 0; m < 2; m++) { 1412 atpdev->global_map[m] = 0; 1413 for (k = 0; k < 4; k++) { 1414 atp_writew_base(atpdev, 0x3c, n++); 1415 ((u32 *)&setupdata[m][0])[k] = atp_readl_base(atpdev, 0x38); 1416 } 1417 for (k = 0; k < 4; k++) { 1418 atp_writew_base(atpdev, 0x3c, n++); 1419 ((u32 *)&atpdev->sp[m][0])[k] = atp_readl_base(atpdev, 0x38); 1420 } 1421 n += 8; 1422 } 1423 } 1424 c = atp_readb_base(atpdev, 0x29); 1425 atp_writeb_base(atpdev, 0x29, c & 0xfb); 1426 for (c = 0; c < 2; c++) { 1427 atpdev->ultra_map[c] = 0; 1428 atpdev->async[c] = 0; 1429 for (k = 0; k < 16; k++) { 1430 n = 1 << k; 1431 if (atpdev->sp[c][k] > 1) 1432 atpdev->ultra_map[c] |= n; 1433 else 1434 if (atpdev->sp[c][k] == 0) 1435 atpdev->async[c] |= n; 1436 } 1437 atpdev->async[c] = ~(atpdev->async[c]); 1438 1439 if (atpdev->global_map[c] == 0) { 1440 k = setupdata[c][1]; 1441 if ((k & 0x40) != 0) 1442 atpdev->global_map[c] |= 0x20; 1443 k &= 0x07; 1444 atpdev->global_map[c] |= k; 1445 if ((setupdata[c][2] & 0x04) != 0) 1446 atpdev->global_map[c] |= 0x08; 1447 atpdev->host_id[c] = setupdata[c][0] & 0x07; 1448 } 1449 } 1450 1451 k = atp_readb_base(atpdev, 0x28) & 0x8f; 1452 k |= 0x10; 1453 atp_writeb_base(atpdev, 0x28, k); 1454 atp_writeb_pci(atpdev, 0, 1, 0x80); 1455 atp_writeb_pci(atpdev, 1, 1, 0x80); 1456 msleep(100); 1457 atp_writeb_pci(atpdev, 0, 1, 0); 1458 atp_writeb_pci(atpdev, 1, 1, 0); 1459 msleep(1000); 1460 atp_readb_io(atpdev, 0, 0x1b); 1461 atp_readb_io(atpdev, 0, 0x17); 1462 atp_readb_io(atpdev, 1, 0x1b); 1463 atp_readb_io(atpdev, 1, 0x17); 1464 1465 k = atpdev->host_id[0]; 1466 if (k > 7) 1467 k = (k & 0x07) | 0x40; 1468 atp_set_host_id(atpdev, 0, k); 1469 1470 k = atpdev->host_id[1]; 1471 if (k > 7) 1472 k = (k & 0x07) | 0x40; 1473 atp_set_host_id(atpdev, 1, k); 1474 1475 msleep(600); /* this delay used to be called tscam_885() */ 1476 dev_info(&pdev->dev, "Scanning Channel A SCSI Device ...\n"); 1477 atp_is(atpdev, 0, true, atp_readb_io(atpdev, 0, 0x1b) >> 7); 1478 atp_writeb_io(atpdev, 0, 0x16, 0x80); 1479 dev_info(&pdev->dev, "Scanning Channel B SCSI Device ...\n"); 1480 atp_is(atpdev, 1, true, atp_readb_io(atpdev, 1, 0x1b) >> 7); 1481 atp_writeb_io(atpdev, 1, 0x16, 0x80); 1482 k = atp_readb_base(atpdev, 0x28) & 0xcf; 1483 k |= 0xc0; 1484 atp_writeb_base(atpdev, 0x28, k); 1485 k = atp_readb_base(atpdev, 0x1f) | 0x80; 1486 atp_writeb_base(atpdev, 0x1f, k); 1487 k = atp_readb_base(atpdev, 0x29) | 0x01; 1488 atp_writeb_base(atpdev, 0x29, k); 1489 shpnt->max_id = 16; 1490 shpnt->max_lun = (atpdev->global_map[0] & 0x07) + 1; 1491 shpnt->max_channel = 1; 1492 shpnt->this_id = atpdev->host_id[0]; 1493 } 1494 1495 /* return non-zero on detection */ 1496 static int atp870u_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1497 { 1498 struct Scsi_Host *shpnt = NULL; 1499 struct atp_unit *atpdev; 1500 int err; 1501 1502 if (ent->device == PCI_DEVICE_ID_ARTOP_AEC7610 && pdev->revision < 2) { 1503 dev_err(&pdev->dev, "ATP850S chips (AEC6710L/F cards) are not supported.\n"); 1504 return -ENODEV; 1505 } 1506 1507 err = pci_enable_device(pdev); 1508 if (err) 1509 goto fail; 1510 1511 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) { 1512 printk(KERN_ERR "atp870u: DMA mask required but not available.\n"); 1513 err = -EIO; 1514 goto disable_device; 1515 } 1516 1517 err = pci_request_regions(pdev, "atp870u"); 1518 if (err) 1519 goto disable_device; 1520 pci_set_master(pdev); 1521 1522 err = -ENOMEM; 1523 shpnt = scsi_host_alloc(&atp870u_template, sizeof(struct atp_unit)); 1524 if (!shpnt) 1525 goto release_region; 1526 1527 atpdev = shost_priv(shpnt); 1528 1529 atpdev->host = shpnt; 1530 atpdev->pdev = pdev; 1531 pci_set_drvdata(pdev, atpdev); 1532 1533 shpnt->io_port = pci_resource_start(pdev, 0); 1534 shpnt->io_port &= 0xfffffff8; 1535 shpnt->n_io_port = pci_resource_len(pdev, 0); 1536 atpdev->baseport = shpnt->io_port; 1537 shpnt->unique_id = shpnt->io_port; 1538 shpnt->irq = pdev->irq; 1539 1540 err = atp870u_init_tables(shpnt); 1541 if (err) { 1542 dev_err(&pdev->dev, "Unable to allocate tables for Acard controller\n"); 1543 goto unregister; 1544 } 1545 1546 if (is880(atpdev)) 1547 atp880_init(shpnt); 1548 else if (is885(atpdev)) 1549 atp885_init(shpnt); 1550 else 1551 atp870_init(shpnt); 1552 1553 err = request_irq(shpnt->irq, atp870u_intr_handle, IRQF_SHARED, "atp870u", shpnt); 1554 if (err) { 1555 dev_err(&pdev->dev, "Unable to allocate IRQ %d.\n", shpnt->irq); 1556 goto free_tables; 1557 } 1558 1559 err = scsi_add_host(shpnt, &pdev->dev); 1560 if (err) 1561 goto scsi_add_fail; 1562 scsi_scan_host(shpnt); 1563 1564 return 0; 1565 1566 scsi_add_fail: 1567 free_irq(shpnt->irq, shpnt); 1568 free_tables: 1569 atp870u_free_tables(shpnt); 1570 unregister: 1571 scsi_host_put(shpnt); 1572 release_region: 1573 pci_release_regions(pdev); 1574 disable_device: 1575 pci_disable_device(pdev); 1576 fail: 1577 return err; 1578 } 1579 1580 /* The abort command does not leave the device in a clean state where 1581 it is available to be used again. Until this gets worked out, we will 1582 leave it commented out. */ 1583 1584 static int atp870u_abort(struct scsi_cmnd * SCpnt) 1585 { 1586 unsigned char j, k, c; 1587 struct scsi_cmnd *workrequ; 1588 struct atp_unit *dev; 1589 struct Scsi_Host *host; 1590 host = SCpnt->device->host; 1591 1592 dev = (struct atp_unit *)&host->hostdata; 1593 c = scmd_channel(SCpnt); 1594 printk(" atp870u: abort Channel = %x \n", c); 1595 printk("working=%x last_cmd=%x ", dev->working[c], dev->last_cmd[c]); 1596 printk(" quhdu=%x quendu=%x ", dev->quhd[c], dev->quend[c]); 1597 for (j = 0; j < 0x18; j++) { 1598 printk(" r%2x=%2x", j, atp_readb_io(dev, c, j)); 1599 } 1600 printk(" r1c=%2x", atp_readb_io(dev, c, 0x1c)); 1601 printk(" r1f=%2x in_snd=%2x ", atp_readb_io(dev, c, 0x1f), dev->in_snd[c]); 1602 printk(" d00=%2x", atp_readb_pci(dev, c, 0x00)); 1603 printk(" d02=%2x", atp_readb_pci(dev, c, 0x02)); 1604 for(j=0;j<16;j++) { 1605 if (dev->id[c][j].curr_req != NULL) { 1606 workrequ = dev->id[c][j].curr_req; 1607 printk("\n que cdb= "); 1608 for (k=0; k < workrequ->cmd_len; k++) { 1609 printk(" %2x ",workrequ->cmnd[k]); 1610 } 1611 printk(" last_lenu= %x ",(unsigned int)dev->id[c][j].last_len); 1612 } 1613 } 1614 return SUCCESS; 1615 } 1616 1617 static const char *atp870u_info(struct Scsi_Host *notused) 1618 { 1619 static char buffer[128]; 1620 1621 strcpy(buffer, "ACARD AEC-6710/6712/67160 PCI Ultra/W/LVD SCSI-3 Adapter Driver V2.6+ac "); 1622 1623 return buffer; 1624 } 1625 1626 static int atp870u_show_info(struct seq_file *m, struct Scsi_Host *HBAptr) 1627 { 1628 seq_puts(m, "ACARD AEC-671X Driver Version: 2.6+ac\n\n" 1629 "Adapter Configuration:\n"); 1630 seq_printf(m, " Base IO: %#.4lx\n", HBAptr->io_port); 1631 seq_printf(m, " IRQ: %d\n", HBAptr->irq); 1632 return 0; 1633 } 1634 1635 1636 static int atp870u_biosparam(struct scsi_device *disk, struct block_device *dev, 1637 sector_t capacity, int *ip) 1638 { 1639 int heads, sectors, cylinders; 1640 1641 heads = 64; 1642 sectors = 32; 1643 cylinders = (unsigned long)capacity / (heads * sectors); 1644 if (cylinders > 1024) { 1645 heads = 255; 1646 sectors = 63; 1647 cylinders = (unsigned long)capacity / (heads * sectors); 1648 } 1649 ip[0] = heads; 1650 ip[1] = sectors; 1651 ip[2] = cylinders; 1652 1653 return 0; 1654 } 1655 1656 static void atp870u_remove (struct pci_dev *pdev) 1657 { 1658 struct atp_unit *devext = pci_get_drvdata(pdev); 1659 struct Scsi_Host *pshost = devext->host; 1660 1661 1662 scsi_remove_host(pshost); 1663 free_irq(pshost->irq, pshost); 1664 pci_release_regions(pdev); 1665 pci_disable_device(pdev); 1666 atp870u_free_tables(pshost); 1667 scsi_host_put(pshost); 1668 } 1669 MODULE_LICENSE("GPL"); 1670 1671 static struct scsi_host_template atp870u_template = { 1672 .module = THIS_MODULE, 1673 .name = "atp870u" /* name */, 1674 .proc_name = "atp870u", 1675 .show_info = atp870u_show_info, 1676 .info = atp870u_info /* info */, 1677 .queuecommand = atp870u_queuecommand /* queuecommand */, 1678 .eh_abort_handler = atp870u_abort /* abort */, 1679 .bios_param = atp870u_biosparam /* biosparm */, 1680 .can_queue = qcnt /* can_queue */, 1681 .this_id = 7 /* SCSI ID */, 1682 .sg_tablesize = ATP870U_SCATTER /*SG_ALL*/ /*SG_NONE*/, 1683 .max_sectors = ATP870U_MAX_SECTORS, 1684 }; 1685 1686 static struct pci_device_id atp870u_id_table[] = { 1687 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, ATP885_DEVID) }, 1688 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, ATP880_DEVID1) }, 1689 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, ATP880_DEVID2) }, 1690 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7610) }, 1691 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612UW) }, 1692 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612U) }, 1693 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612S) }, 1694 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612D) }, 1695 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612SUW) }, 1696 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_8060) }, 1697 { 0, }, 1698 }; 1699 1700 MODULE_DEVICE_TABLE(pci, atp870u_id_table); 1701 1702 static struct pci_driver atp870u_driver = { 1703 .id_table = atp870u_id_table, 1704 .name = "atp870u", 1705 .probe = atp870u_probe, 1706 .remove = atp870u_remove, 1707 }; 1708 1709 module_pci_driver(atp870u_driver); 1710 1711 static void atp_is(struct atp_unit *dev, unsigned char c, bool wide_chip, unsigned char lvdmode) 1712 { 1713 unsigned char i, j, k, rmb, n; 1714 unsigned short int m; 1715 static unsigned char mbuf[512]; 1716 static unsigned char satn[9] = { 0, 0, 0, 0, 0, 0, 0, 6, 6 }; 1717 static unsigned char inqd[9] = { 0x12, 0, 0, 0, 0x24, 0, 0, 0x24, 6 }; 1718 static unsigned char synn[6] = { 0x80, 1, 3, 1, 0x19, 0x0e }; 1719 unsigned char synu[6] = { 0x80, 1, 3, 1, 0x0a, 0x0e }; 1720 static unsigned char synw[6] = { 0x80, 1, 3, 1, 0x19, 0x0e }; 1721 static unsigned char synw_870[6] = { 0x80, 1, 3, 1, 0x0c, 0x07 }; 1722 unsigned char synuw[6] = { 0x80, 1, 3, 1, 0x0a, 0x0e }; 1723 static unsigned char wide[6] = { 0x80, 1, 2, 3, 1, 0 }; 1724 static unsigned char u3[9] = { 0x80, 1, 6, 4, 0x09, 00, 0x0e, 0x01, 0x02 }; 1725 1726 for (i = 0; i < 16; i++) { 1727 if (!wide_chip && (i > 7)) 1728 break; 1729 m = 1; 1730 m = m << i; 1731 if ((m & dev->active_id[c]) != 0) { 1732 continue; 1733 } 1734 if (i == dev->host_id[c]) { 1735 printk(KERN_INFO " ID: %2d Host Adapter\n", dev->host_id[c]); 1736 continue; 1737 } 1738 atp_writeb_io(dev, c, 0x1b, wide_chip ? 0x01 : 0x00); 1739 atp_writeb_io(dev, c, 1, 0x08); 1740 atp_writeb_io(dev, c, 2, 0x7f); 1741 atp_writeb_io(dev, c, 3, satn[0]); 1742 atp_writeb_io(dev, c, 4, satn[1]); 1743 atp_writeb_io(dev, c, 5, satn[2]); 1744 atp_writeb_io(dev, c, 6, satn[3]); 1745 atp_writeb_io(dev, c, 7, satn[4]); 1746 atp_writeb_io(dev, c, 8, satn[5]); 1747 atp_writeb_io(dev, c, 0x0f, 0); 1748 atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp); 1749 atp_writeb_io(dev, c, 0x12, 0); 1750 atp_writeb_io(dev, c, 0x13, satn[6]); 1751 atp_writeb_io(dev, c, 0x14, satn[7]); 1752 j = i; 1753 if ((j & 0x08) != 0) { 1754 j = (j & 0x07) | 0x40; 1755 } 1756 atp_writeb_io(dev, c, 0x15, j); 1757 atp_writeb_io(dev, c, 0x18, satn[8]); 1758 1759 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00) 1760 cpu_relax(); 1761 1762 if (atp_readb_io(dev, c, 0x17) != 0x11 && atp_readb_io(dev, c, 0x17) != 0x8e) 1763 continue; 1764 1765 while (atp_readb_io(dev, c, 0x17) != 0x8e) 1766 cpu_relax(); 1767 1768 dev->active_id[c] |= m; 1769 1770 atp_writeb_io(dev, c, 0x10, 0x30); 1771 if (is885(dev) || is880(dev)) 1772 atp_writeb_io(dev, c, 0x14, 0x00); 1773 else /* result of is870() merge - is this a bug? */ 1774 atp_writeb_io(dev, c, 0x04, 0x00); 1775 1776 phase_cmd: 1777 atp_writeb_io(dev, c, 0x18, 0x08); 1778 1779 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00) 1780 cpu_relax(); 1781 1782 j = atp_readb_io(dev, c, 0x17); 1783 if (j != 0x16) { 1784 atp_writeb_io(dev, c, 0x10, 0x41); 1785 goto phase_cmd; 1786 } 1787 sel_ok: 1788 atp_writeb_io(dev, c, 3, inqd[0]); 1789 atp_writeb_io(dev, c, 4, inqd[1]); 1790 atp_writeb_io(dev, c, 5, inqd[2]); 1791 atp_writeb_io(dev, c, 6, inqd[3]); 1792 atp_writeb_io(dev, c, 7, inqd[4]); 1793 atp_writeb_io(dev, c, 8, inqd[5]); 1794 atp_writeb_io(dev, c, 0x0f, 0); 1795 atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp); 1796 atp_writeb_io(dev, c, 0x12, 0); 1797 atp_writeb_io(dev, c, 0x13, inqd[6]); 1798 atp_writeb_io(dev, c, 0x14, inqd[7]); 1799 atp_writeb_io(dev, c, 0x18, inqd[8]); 1800 1801 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00) 1802 cpu_relax(); 1803 1804 if (atp_readb_io(dev, c, 0x17) != 0x11 && atp_readb_io(dev, c, 0x17) != 0x8e) 1805 continue; 1806 1807 while (atp_readb_io(dev, c, 0x17) != 0x8e) 1808 cpu_relax(); 1809 1810 if (wide_chip) 1811 atp_writeb_io(dev, c, 0x1b, 0x00); 1812 1813 atp_writeb_io(dev, c, 0x18, 0x08); 1814 j = 0; 1815 rd_inq_data: 1816 k = atp_readb_io(dev, c, 0x1f); 1817 if ((k & 0x01) != 0) { 1818 mbuf[j++] = atp_readb_io(dev, c, 0x19); 1819 goto rd_inq_data; 1820 } 1821 if ((k & 0x80) == 0) { 1822 goto rd_inq_data; 1823 } 1824 j = atp_readb_io(dev, c, 0x17); 1825 if (j == 0x16) { 1826 goto inq_ok; 1827 } 1828 atp_writeb_io(dev, c, 0x10, 0x46); 1829 atp_writeb_io(dev, c, 0x12, 0); 1830 atp_writeb_io(dev, c, 0x13, 0); 1831 atp_writeb_io(dev, c, 0x14, 0); 1832 atp_writeb_io(dev, c, 0x18, 0x08); 1833 1834 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00) 1835 cpu_relax(); 1836 1837 if (atp_readb_io(dev, c, 0x17) != 0x16) 1838 goto sel_ok; 1839 1840 inq_ok: 1841 mbuf[36] = 0; 1842 printk(KERN_INFO " ID: %2d %s\n", i, &mbuf[8]); 1843 dev->id[c][i].devtype = mbuf[0]; 1844 rmb = mbuf[1]; 1845 n = mbuf[7]; 1846 if (!wide_chip) 1847 goto not_wide; 1848 if ((mbuf[7] & 0x60) == 0) { 1849 goto not_wide; 1850 } 1851 if (is885(dev) || is880(dev)) { 1852 if ((i < 8) && ((dev->global_map[c] & 0x20) == 0)) 1853 goto not_wide; 1854 } else { /* result of is870() merge - is this a bug? */ 1855 if ((dev->global_map[c] & 0x20) == 0) 1856 goto not_wide; 1857 } 1858 if (lvdmode == 0) { 1859 goto chg_wide; 1860 } 1861 if (dev->sp[c][i] != 0x04) // force u2 1862 { 1863 goto chg_wide; 1864 } 1865 1866 atp_writeb_io(dev, c, 0x1b, 0x01); 1867 atp_writeb_io(dev, c, 3, satn[0]); 1868 atp_writeb_io(dev, c, 4, satn[1]); 1869 atp_writeb_io(dev, c, 5, satn[2]); 1870 atp_writeb_io(dev, c, 6, satn[3]); 1871 atp_writeb_io(dev, c, 7, satn[4]); 1872 atp_writeb_io(dev, c, 8, satn[5]); 1873 atp_writeb_io(dev, c, 0x0f, 0); 1874 atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp); 1875 atp_writeb_io(dev, c, 0x12, 0); 1876 atp_writeb_io(dev, c, 0x13, satn[6]); 1877 atp_writeb_io(dev, c, 0x14, satn[7]); 1878 atp_writeb_io(dev, c, 0x18, satn[8]); 1879 1880 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00) 1881 cpu_relax(); 1882 1883 if (atp_readb_io(dev, c, 0x17) != 0x11 && atp_readb_io(dev, c, 0x17) != 0x8e) 1884 continue; 1885 1886 while (atp_readb_io(dev, c, 0x17) != 0x8e) 1887 cpu_relax(); 1888 1889 try_u3: 1890 j = 0; 1891 atp_writeb_io(dev, c, 0x14, 0x09); 1892 atp_writeb_io(dev, c, 0x18, 0x20); 1893 1894 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) { 1895 if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0) 1896 atp_writeb_io(dev, c, 0x19, u3[j++]); 1897 cpu_relax(); 1898 } 1899 1900 while ((atp_readb_io(dev, c, 0x17) & 0x80) == 0x00) 1901 cpu_relax(); 1902 1903 j = atp_readb_io(dev, c, 0x17) & 0x0f; 1904 if (j == 0x0f) { 1905 goto u3p_in; 1906 } 1907 if (j == 0x0a) { 1908 goto u3p_cmd; 1909 } 1910 if (j == 0x0e) { 1911 goto try_u3; 1912 } 1913 continue; 1914 u3p_out: 1915 atp_writeb_io(dev, c, 0x18, 0x20); 1916 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) { 1917 if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0) 1918 atp_writeb_io(dev, c, 0x19, 0); 1919 cpu_relax(); 1920 } 1921 j = atp_readb_io(dev, c, 0x17) & 0x0f; 1922 if (j == 0x0f) { 1923 goto u3p_in; 1924 } 1925 if (j == 0x0a) { 1926 goto u3p_cmd; 1927 } 1928 if (j == 0x0e) { 1929 goto u3p_out; 1930 } 1931 continue; 1932 u3p_in: 1933 atp_writeb_io(dev, c, 0x14, 0x09); 1934 atp_writeb_io(dev, c, 0x18, 0x20); 1935 k = 0; 1936 u3p_in1: 1937 j = atp_readb_io(dev, c, 0x1f); 1938 if ((j & 0x01) != 0) { 1939 mbuf[k++] = atp_readb_io(dev, c, 0x19); 1940 goto u3p_in1; 1941 } 1942 if ((j & 0x80) == 0x00) { 1943 goto u3p_in1; 1944 } 1945 j = atp_readb_io(dev, c, 0x17) & 0x0f; 1946 if (j == 0x0f) { 1947 goto u3p_in; 1948 } 1949 if (j == 0x0a) { 1950 goto u3p_cmd; 1951 } 1952 if (j == 0x0e) { 1953 goto u3p_out; 1954 } 1955 continue; 1956 u3p_cmd: 1957 atp_writeb_io(dev, c, 0x10, 0x30); 1958 atp_writeb_io(dev, c, 0x14, 0x00); 1959 atp_writeb_io(dev, c, 0x18, 0x08); 1960 1961 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00); 1962 1963 j = atp_readb_io(dev, c, 0x17); 1964 if (j != 0x16) { 1965 if (j == 0x4e) { 1966 goto u3p_out; 1967 } 1968 continue; 1969 } 1970 if (mbuf[0] != 0x01) { 1971 goto chg_wide; 1972 } 1973 if (mbuf[1] != 0x06) { 1974 goto chg_wide; 1975 } 1976 if (mbuf[2] != 0x04) { 1977 goto chg_wide; 1978 } 1979 if (mbuf[3] == 0x09) { 1980 m = 1; 1981 m = m << i; 1982 dev->wide_id[c] |= m; 1983 dev->id[c][i].devsp = 0xce; 1984 #ifdef ED_DBGP 1985 printk("dev->id[%2d][%2d].devsp = %2x\n",c,i,dev->id[c][i].devsp); 1986 #endif 1987 continue; 1988 } 1989 chg_wide: 1990 atp_writeb_io(dev, c, 0x1b, 0x01); 1991 atp_writeb_io(dev, c, 3, satn[0]); 1992 atp_writeb_io(dev, c, 4, satn[1]); 1993 atp_writeb_io(dev, c, 5, satn[2]); 1994 atp_writeb_io(dev, c, 6, satn[3]); 1995 atp_writeb_io(dev, c, 7, satn[4]); 1996 atp_writeb_io(dev, c, 8, satn[5]); 1997 atp_writeb_io(dev, c, 0x0f, 0); 1998 atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp); 1999 atp_writeb_io(dev, c, 0x12, 0); 2000 atp_writeb_io(dev, c, 0x13, satn[6]); 2001 atp_writeb_io(dev, c, 0x14, satn[7]); 2002 atp_writeb_io(dev, c, 0x18, satn[8]); 2003 2004 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00) 2005 cpu_relax(); 2006 2007 if (atp_readb_io(dev, c, 0x17) != 0x11 && atp_readb_io(dev, c, 0x17) != 0x8e) 2008 continue; 2009 2010 while (atp_readb_io(dev, c, 0x17) != 0x8e) 2011 cpu_relax(); 2012 2013 try_wide: 2014 j = 0; 2015 atp_writeb_io(dev, c, 0x14, 0x05); 2016 atp_writeb_io(dev, c, 0x18, 0x20); 2017 2018 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) { 2019 if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0) 2020 atp_writeb_io(dev, c, 0x19, wide[j++]); 2021 cpu_relax(); 2022 } 2023 2024 while ((atp_readb_io(dev, c, 0x17) & 0x80) == 0x00) 2025 cpu_relax(); 2026 2027 j = atp_readb_io(dev, c, 0x17) & 0x0f; 2028 if (j == 0x0f) { 2029 goto widep_in; 2030 } 2031 if (j == 0x0a) { 2032 goto widep_cmd; 2033 } 2034 if (j == 0x0e) { 2035 goto try_wide; 2036 } 2037 continue; 2038 widep_out: 2039 atp_writeb_io(dev, c, 0x18, 0x20); 2040 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) { 2041 if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0) 2042 atp_writeb_io(dev, c, 0x19, 0); 2043 cpu_relax(); 2044 } 2045 j = atp_readb_io(dev, c, 0x17) & 0x0f; 2046 if (j == 0x0f) { 2047 goto widep_in; 2048 } 2049 if (j == 0x0a) { 2050 goto widep_cmd; 2051 } 2052 if (j == 0x0e) { 2053 goto widep_out; 2054 } 2055 continue; 2056 widep_in: 2057 atp_writeb_io(dev, c, 0x14, 0xff); 2058 atp_writeb_io(dev, c, 0x18, 0x20); 2059 k = 0; 2060 widep_in1: 2061 j = atp_readb_io(dev, c, 0x1f); 2062 if ((j & 0x01) != 0) { 2063 mbuf[k++] = atp_readb_io(dev, c, 0x19); 2064 goto widep_in1; 2065 } 2066 if ((j & 0x80) == 0x00) { 2067 goto widep_in1; 2068 } 2069 j = atp_readb_io(dev, c, 0x17) & 0x0f; 2070 if (j == 0x0f) { 2071 goto widep_in; 2072 } 2073 if (j == 0x0a) { 2074 goto widep_cmd; 2075 } 2076 if (j == 0x0e) { 2077 goto widep_out; 2078 } 2079 continue; 2080 widep_cmd: 2081 atp_writeb_io(dev, c, 0x10, 0x30); 2082 atp_writeb_io(dev, c, 0x14, 0x00); 2083 atp_writeb_io(dev, c, 0x18, 0x08); 2084 2085 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00) 2086 cpu_relax(); 2087 2088 j = atp_readb_io(dev, c, 0x17); 2089 if (j != 0x16) { 2090 if (j == 0x4e) { 2091 goto widep_out; 2092 } 2093 continue; 2094 } 2095 if (mbuf[0] != 0x01) { 2096 goto not_wide; 2097 } 2098 if (mbuf[1] != 0x02) { 2099 goto not_wide; 2100 } 2101 if (mbuf[2] != 0x03) { 2102 goto not_wide; 2103 } 2104 if (mbuf[3] != 0x01) { 2105 goto not_wide; 2106 } 2107 m = 1; 2108 m = m << i; 2109 dev->wide_id[c] |= m; 2110 not_wide: 2111 if ((dev->id[c][i].devtype == 0x00) || (dev->id[c][i].devtype == 0x07) || ((dev->id[c][i].devtype == 0x05) && ((n & 0x10) != 0))) { 2112 m = 1; 2113 m = m << i; 2114 if ((dev->async[c] & m) != 0) { 2115 goto set_sync; 2116 } 2117 } 2118 continue; 2119 set_sync: 2120 if ((!is885(dev) && !is880(dev)) || (dev->sp[c][i] == 0x02)) { 2121 synu[4] = 0x0c; 2122 synuw[4] = 0x0c; 2123 } else { 2124 if (dev->sp[c][i] >= 0x03) { 2125 synu[4] = 0x0a; 2126 synuw[4] = 0x0a; 2127 } 2128 } 2129 j = 0; 2130 if ((m & dev->wide_id[c]) != 0) { 2131 j |= 0x01; 2132 } 2133 atp_writeb_io(dev, c, 0x1b, j); 2134 atp_writeb_io(dev, c, 3, satn[0]); 2135 atp_writeb_io(dev, c, 4, satn[1]); 2136 atp_writeb_io(dev, c, 5, satn[2]); 2137 atp_writeb_io(dev, c, 6, satn[3]); 2138 atp_writeb_io(dev, c, 7, satn[4]); 2139 atp_writeb_io(dev, c, 8, satn[5]); 2140 atp_writeb_io(dev, c, 0x0f, 0); 2141 atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp); 2142 atp_writeb_io(dev, c, 0x12, 0); 2143 atp_writeb_io(dev, c, 0x13, satn[6]); 2144 atp_writeb_io(dev, c, 0x14, satn[7]); 2145 atp_writeb_io(dev, c, 0x18, satn[8]); 2146 2147 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00) 2148 cpu_relax(); 2149 2150 if (atp_readb_io(dev, c, 0x17) != 0x11 && atp_readb_io(dev, c, 0x17) != 0x8e) 2151 continue; 2152 2153 while (atp_readb_io(dev, c, 0x17) != 0x8e) 2154 cpu_relax(); 2155 2156 try_sync: 2157 j = 0; 2158 atp_writeb_io(dev, c, 0x14, 0x06); 2159 atp_writeb_io(dev, c, 0x18, 0x20); 2160 2161 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) { 2162 if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0) { 2163 if ((m & dev->wide_id[c]) != 0) { 2164 if (is885(dev) || is880(dev)) { 2165 if ((m & dev->ultra_map[c]) != 0) { 2166 atp_writeb_io(dev, c, 0x19, synuw[j++]); 2167 } else { 2168 atp_writeb_io(dev, c, 0x19, synw[j++]); 2169 } 2170 } else 2171 atp_writeb_io(dev, c, 0x19, synw_870[j++]); 2172 } else { 2173 if ((m & dev->ultra_map[c]) != 0) { 2174 atp_writeb_io(dev, c, 0x19, synu[j++]); 2175 } else { 2176 atp_writeb_io(dev, c, 0x19, synn[j++]); 2177 } 2178 } 2179 } 2180 } 2181 2182 while ((atp_readb_io(dev, c, 0x17) & 0x80) == 0x00) 2183 cpu_relax(); 2184 2185 j = atp_readb_io(dev, c, 0x17) & 0x0f; 2186 if (j == 0x0f) { 2187 goto phase_ins; 2188 } 2189 if (j == 0x0a) { 2190 goto phase_cmds; 2191 } 2192 if (j == 0x0e) { 2193 goto try_sync; 2194 } 2195 continue; 2196 phase_outs: 2197 atp_writeb_io(dev, c, 0x18, 0x20); 2198 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00) { 2199 if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0x00) 2200 atp_writeb_io(dev, c, 0x19, 0x00); 2201 cpu_relax(); 2202 } 2203 j = atp_readb_io(dev, c, 0x17); 2204 if (j == 0x85) { 2205 goto tar_dcons; 2206 } 2207 j &= 0x0f; 2208 if (j == 0x0f) { 2209 goto phase_ins; 2210 } 2211 if (j == 0x0a) { 2212 goto phase_cmds; 2213 } 2214 if (j == 0x0e) { 2215 goto phase_outs; 2216 } 2217 continue; 2218 phase_ins: 2219 if (is885(dev) || is880(dev)) 2220 atp_writeb_io(dev, c, 0x14, 0x06); 2221 else 2222 atp_writeb_io(dev, c, 0x14, 0xff); 2223 atp_writeb_io(dev, c, 0x18, 0x20); 2224 k = 0; 2225 phase_ins1: 2226 j = atp_readb_io(dev, c, 0x1f); 2227 if ((j & 0x01) != 0x00) { 2228 mbuf[k++] = atp_readb_io(dev, c, 0x19); 2229 goto phase_ins1; 2230 } 2231 if ((j & 0x80) == 0x00) { 2232 goto phase_ins1; 2233 } 2234 2235 while ((atp_readb_io(dev, c, 0x17) & 0x80) == 0x00); 2236 2237 j = atp_readb_io(dev, c, 0x17); 2238 if (j == 0x85) { 2239 goto tar_dcons; 2240 } 2241 j &= 0x0f; 2242 if (j == 0x0f) { 2243 goto phase_ins; 2244 } 2245 if (j == 0x0a) { 2246 goto phase_cmds; 2247 } 2248 if (j == 0x0e) { 2249 goto phase_outs; 2250 } 2251 continue; 2252 phase_cmds: 2253 atp_writeb_io(dev, c, 0x10, 0x30); 2254 tar_dcons: 2255 atp_writeb_io(dev, c, 0x14, 0x00); 2256 atp_writeb_io(dev, c, 0x18, 0x08); 2257 2258 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00) 2259 cpu_relax(); 2260 2261 j = atp_readb_io(dev, c, 0x17); 2262 if (j != 0x16) { 2263 continue; 2264 } 2265 if (mbuf[0] != 0x01) { 2266 continue; 2267 } 2268 if (mbuf[1] != 0x03) { 2269 continue; 2270 } 2271 if (mbuf[4] == 0x00) { 2272 continue; 2273 } 2274 if (mbuf[3] > 0x64) { 2275 continue; 2276 } 2277 if (is885(dev) || is880(dev)) { 2278 if (mbuf[4] > 0x0e) { 2279 mbuf[4] = 0x0e; 2280 } 2281 } else { 2282 if (mbuf[4] > 0x0c) { 2283 mbuf[4] = 0x0c; 2284 } 2285 } 2286 dev->id[c][i].devsp = mbuf[4]; 2287 if (is885(dev) || is880(dev)) 2288 if (mbuf[3] < 0x0c) { 2289 j = 0xb0; 2290 goto set_syn_ok; 2291 } 2292 if ((mbuf[3] < 0x0d) && (rmb == 0)) { 2293 j = 0xa0; 2294 goto set_syn_ok; 2295 } 2296 if (mbuf[3] < 0x1a) { 2297 j = 0x20; 2298 goto set_syn_ok; 2299 } 2300 if (mbuf[3] < 0x33) { 2301 j = 0x40; 2302 goto set_syn_ok; 2303 } 2304 if (mbuf[3] < 0x4c) { 2305 j = 0x50; 2306 goto set_syn_ok; 2307 } 2308 j = 0x60; 2309 set_syn_ok: 2310 dev->id[c][i].devsp = (dev->id[c][i].devsp & 0x0f) | j; 2311 #ifdef ED_DBGP 2312 printk("dev->id[%2d][%2d].devsp = %2x\n",c,i,dev->id[c][i].devsp); 2313 #endif 2314 } 2315 } 2316