1 /* 2 * Copyright (C) 1997 Wu Ching Chen 3 * 2.1.x update (C) 1998 Krzysztof G. Baranowski 4 * 2.5.x update (C) 2002 Red Hat 5 * 2.6.x update (C) 2004 Red Hat 6 * 7 * Marcelo Tosatti <marcelo@conectiva.com.br> : SMP fixes 8 * 9 * Wu Ching Chen : NULL pointer fixes 2000/06/02 10 * support atp876 chip 11 * enable 32 bit fifo transfer 12 * support cdrom & remove device run ultra speed 13 * fix disconnect bug 2000/12/21 14 * support atp880 chip lvd u160 2001/05/15 15 * fix prd table bug 2001/09/12 (7.1) 16 * 17 * atp885 support add by ACARD Hao Ping Lian 2005/01/05 18 */ 19 #include <linux/module.h> 20 #include <linux/init.h> 21 #include <linux/interrupt.h> 22 #include <linux/kernel.h> 23 #include <linux/types.h> 24 #include <linux/string.h> 25 #include <linux/ioport.h> 26 #include <linux/delay.h> 27 #include <linux/proc_fs.h> 28 #include <linux/spinlock.h> 29 #include <linux/pci.h> 30 #include <linux/blkdev.h> 31 #include <linux/dma-mapping.h> 32 #include <linux/slab.h> 33 #include <asm/io.h> 34 35 #include <scsi/scsi.h> 36 #include <scsi/scsi_cmnd.h> 37 #include <scsi/scsi_device.h> 38 #include <scsi/scsi_host.h> 39 40 #include "atp870u.h" 41 42 static struct scsi_host_template atp870u_template; 43 static void send_s870(struct atp_unit *dev,unsigned char c); 44 static void atp_is(struct atp_unit *dev, unsigned char c, bool wide_chip, unsigned char lvdmode); 45 46 static inline void atp_writeb_base(struct atp_unit *atp, u8 reg, u8 val) 47 { 48 outb(val, atp->baseport + reg); 49 } 50 51 static inline void atp_writew_base(struct atp_unit *atp, u8 reg, u16 val) 52 { 53 outw(val, atp->baseport + reg); 54 } 55 56 static inline void atp_writeb_io(struct atp_unit *atp, u8 channel, u8 reg, u8 val) 57 { 58 outb(val, atp->ioport[channel] + reg); 59 } 60 61 static inline void atp_writew_io(struct atp_unit *atp, u8 channel, u8 reg, u16 val) 62 { 63 outw(val, atp->ioport[channel] + reg); 64 } 65 66 static inline void atp_writeb_pci(struct atp_unit *atp, u8 channel, u8 reg, u8 val) 67 { 68 outb(val, atp->pciport[channel] + reg); 69 } 70 71 static inline void atp_writel_pci(struct atp_unit *atp, u8 channel, u8 reg, u32 val) 72 { 73 outl(val, atp->pciport[channel] + reg); 74 } 75 76 static inline u8 atp_readb_base(struct atp_unit *atp, u8 reg) 77 { 78 return inb(atp->baseport + reg); 79 } 80 81 static inline u16 atp_readw_base(struct atp_unit *atp, u8 reg) 82 { 83 return inw(atp->baseport + reg); 84 } 85 86 static inline u32 atp_readl_base(struct atp_unit *atp, u8 reg) 87 { 88 return inl(atp->baseport + reg); 89 } 90 91 static inline u8 atp_readb_io(struct atp_unit *atp, u8 channel, u8 reg) 92 { 93 return inb(atp->ioport[channel] + reg); 94 } 95 96 static inline u16 atp_readw_io(struct atp_unit *atp, u8 channel, u8 reg) 97 { 98 return inw(atp->ioport[channel] + reg); 99 } 100 101 static inline u8 atp_readb_pci(struct atp_unit *atp, u8 channel, u8 reg) 102 { 103 return inb(atp->pciport[channel] + reg); 104 } 105 106 static inline bool is880(struct atp_unit *atp) 107 { 108 return atp->pdev->device == ATP880_DEVID1 || 109 atp->pdev->device == ATP880_DEVID2; 110 } 111 112 static inline bool is885(struct atp_unit *atp) 113 { 114 return atp->pdev->device == ATP885_DEVID; 115 } 116 117 static irqreturn_t atp870u_intr_handle(int irq, void *dev_id) 118 { 119 unsigned long flags; 120 unsigned short int id; 121 unsigned char i, j, c, target_id, lun,cmdp; 122 unsigned char *prd; 123 struct scsi_cmnd *workreq; 124 unsigned long adrcnt, k; 125 #ifdef ED_DBGP 126 unsigned long l; 127 #endif 128 struct Scsi_Host *host = dev_id; 129 struct atp_unit *dev = (struct atp_unit *)&host->hostdata; 130 131 for (c = 0; c < 2; c++) { 132 j = atp_readb_io(dev, c, 0x1f); 133 if ((j & 0x80) != 0) 134 break; 135 dev->in_int[c] = 0; 136 } 137 if ((j & 0x80) == 0) 138 return IRQ_NONE; 139 #ifdef ED_DBGP 140 printk("atp870u_intr_handle enter\n"); 141 #endif 142 dev->in_int[c] = 1; 143 cmdp = atp_readb_io(dev, c, 0x10); 144 if (dev->working[c] != 0) { 145 if (is885(dev)) { 146 if ((atp_readb_io(dev, c, 0x16) & 0x80) == 0) 147 atp_writeb_io(dev, c, 0x16, (atp_readb_io(dev, c, 0x16) | 0x80)); 148 } 149 if ((atp_readb_pci(dev, c, 0x00) & 0x08) != 0) 150 { 151 for (k=0; k < 1000; k++) { 152 if ((atp_readb_pci(dev, c, 2) & 0x08) == 0) 153 break; 154 if ((atp_readb_pci(dev, c, 2) & 0x01) == 0) 155 break; 156 } 157 } 158 atp_writeb_pci(dev, c, 0, 0x00); 159 160 i = atp_readb_io(dev, c, 0x17); 161 162 if (is885(dev)) 163 atp_writeb_pci(dev, c, 2, 0x06); 164 165 target_id = atp_readb_io(dev, c, 0x15); 166 167 /* 168 * Remap wide devices onto id numbers 169 */ 170 171 if ((target_id & 0x40) != 0) { 172 target_id = (target_id & 0x07) | 0x08; 173 } else { 174 target_id &= 0x07; 175 } 176 177 if ((j & 0x40) != 0) { 178 if (dev->last_cmd[c] == 0xff) { 179 dev->last_cmd[c] = target_id; 180 } 181 dev->last_cmd[c] |= 0x40; 182 } 183 if (is885(dev)) 184 dev->r1f[c][target_id] |= j; 185 #ifdef ED_DBGP 186 printk("atp870u_intr_handle status = %x\n",i); 187 #endif 188 if (i == 0x85) { 189 if ((dev->last_cmd[c] & 0xf0) != 0x40) { 190 dev->last_cmd[c] = 0xff; 191 } 192 if (is885(dev)) { 193 adrcnt = 0; 194 ((unsigned char *) &adrcnt)[2] = atp_readb_io(dev, c, 0x12); 195 ((unsigned char *) &adrcnt)[1] = atp_readb_io(dev, c, 0x13); 196 ((unsigned char *) &adrcnt)[0] = atp_readb_io(dev, c, 0x14); 197 if (dev->id[c][target_id].last_len != adrcnt) 198 { 199 k = dev->id[c][target_id].last_len; 200 k -= adrcnt; 201 dev->id[c][target_id].tran_len = k; 202 dev->id[c][target_id].last_len = adrcnt; 203 } 204 #ifdef ED_DBGP 205 printk("dev->id[c][target_id].last_len = %d dev->id[c][target_id].tran_len = %d\n",dev->id[c][target_id].last_len,dev->id[c][target_id].tran_len); 206 #endif 207 } 208 209 /* 210 * Flip wide 211 */ 212 if (dev->wide_id[c] != 0) { 213 atp_writeb_io(dev, c, 0x1b, 0x01); 214 while ((atp_readb_io(dev, c, 0x1b) & 0x01) != 0x01) 215 atp_writeb_io(dev, c, 0x1b, 0x01); 216 } 217 /* 218 * Issue more commands 219 */ 220 spin_lock_irqsave(dev->host->host_lock, flags); 221 if (((dev->quhd[c] != dev->quend[c]) || (dev->last_cmd[c] != 0xff)) && 222 (dev->in_snd[c] == 0)) { 223 #ifdef ED_DBGP 224 printk("Call sent_s870\n"); 225 #endif 226 send_s870(dev,c); 227 } 228 spin_unlock_irqrestore(dev->host->host_lock, flags); 229 /* 230 * Done 231 */ 232 dev->in_int[c] = 0; 233 #ifdef ED_DBGP 234 printk("Status 0x85 return\n"); 235 #endif 236 return IRQ_HANDLED; 237 } 238 239 if (i == 0x40) { 240 dev->last_cmd[c] |= 0x40; 241 dev->in_int[c] = 0; 242 return IRQ_HANDLED; 243 } 244 245 if (i == 0x21) { 246 if ((dev->last_cmd[c] & 0xf0) != 0x40) { 247 dev->last_cmd[c] = 0xff; 248 } 249 adrcnt = 0; 250 ((unsigned char *) &adrcnt)[2] = atp_readb_io(dev, c, 0x12); 251 ((unsigned char *) &adrcnt)[1] = atp_readb_io(dev, c, 0x13); 252 ((unsigned char *) &adrcnt)[0] = atp_readb_io(dev, c, 0x14); 253 k = dev->id[c][target_id].last_len; 254 k -= adrcnt; 255 dev->id[c][target_id].tran_len = k; 256 dev->id[c][target_id].last_len = adrcnt; 257 atp_writeb_io(dev, c, 0x10, 0x41); 258 atp_writeb_io(dev, c, 0x18, 0x08); 259 dev->in_int[c] = 0; 260 return IRQ_HANDLED; 261 } 262 263 if (is885(dev)) { 264 if ((i == 0x4c) || (i == 0x4d) || (i == 0x8c) || (i == 0x8d)) { 265 if ((i == 0x4c) || (i == 0x8c)) 266 i=0x48; 267 else 268 i=0x49; 269 } 270 271 } 272 if ((i == 0x80) || (i == 0x8f)) { 273 #ifdef ED_DBGP 274 printk(KERN_DEBUG "Device reselect\n"); 275 #endif 276 lun = 0; 277 if (cmdp == 0x44 || i == 0x80) 278 lun = atp_readb_io(dev, c, 0x1d) & 0x07; 279 else { 280 if ((dev->last_cmd[c] & 0xf0) != 0x40) { 281 dev->last_cmd[c] = 0xff; 282 } 283 if (cmdp == 0x41) { 284 #ifdef ED_DBGP 285 printk("cmdp = 0x41\n"); 286 #endif 287 adrcnt = 0; 288 ((unsigned char *) &adrcnt)[2] = atp_readb_io(dev, c, 0x12); 289 ((unsigned char *) &adrcnt)[1] = atp_readb_io(dev, c, 0x13); 290 ((unsigned char *) &adrcnt)[0] = atp_readb_io(dev, c, 0x14); 291 k = dev->id[c][target_id].last_len; 292 k -= adrcnt; 293 dev->id[c][target_id].tran_len = k; 294 dev->id[c][target_id].last_len = adrcnt; 295 atp_writeb_io(dev, c, 0x18, 0x08); 296 dev->in_int[c] = 0; 297 return IRQ_HANDLED; 298 } else { 299 #ifdef ED_DBGP 300 printk("cmdp != 0x41\n"); 301 #endif 302 atp_writeb_io(dev, c, 0x10, 0x46); 303 dev->id[c][target_id].dirct = 0x00; 304 atp_writeb_io(dev, c, 0x12, 0x00); 305 atp_writeb_io(dev, c, 0x13, 0x00); 306 atp_writeb_io(dev, c, 0x14, 0x00); 307 atp_writeb_io(dev, c, 0x18, 0x08); 308 dev->in_int[c] = 0; 309 return IRQ_HANDLED; 310 } 311 } 312 if (dev->last_cmd[c] != 0xff) { 313 dev->last_cmd[c] |= 0x40; 314 } 315 if (is885(dev)) { 316 j = atp_readb_base(dev, 0x29) & 0xfe; 317 atp_writeb_base(dev, 0x29, j); 318 } else 319 atp_writeb_io(dev, c, 0x10, 0x45); 320 321 target_id = atp_readb_io(dev, c, 0x16); 322 /* 323 * Remap wide identifiers 324 */ 325 if ((target_id & 0x10) != 0) { 326 target_id = (target_id & 0x07) | 0x08; 327 } else { 328 target_id &= 0x07; 329 } 330 if (is885(dev)) 331 atp_writeb_io(dev, c, 0x10, 0x45); 332 workreq = dev->id[c][target_id].curr_req; 333 #ifdef ED_DBGP 334 scmd_printk(KERN_DEBUG, workreq, "CDB"); 335 for (l = 0; l < workreq->cmd_len; l++) 336 printk(KERN_DEBUG " %x",workreq->cmnd[l]); 337 printk("\n"); 338 #endif 339 340 atp_writeb_io(dev, c, 0x0f, lun); 341 atp_writeb_io(dev, c, 0x11, dev->id[c][target_id].devsp); 342 adrcnt = dev->id[c][target_id].tran_len; 343 k = dev->id[c][target_id].last_len; 344 345 atp_writeb_io(dev, c, 0x12, ((unsigned char *) &k)[2]); 346 atp_writeb_io(dev, c, 0x13, ((unsigned char *) &k)[1]); 347 atp_writeb_io(dev, c, 0x14, ((unsigned char *) &k)[0]); 348 #ifdef ED_DBGP 349 printk("k %x, k[0] 0x%x k[1] 0x%x k[2] 0x%x\n", k, atp_readb_io(dev, c, 0x14), atp_readb_io(dev, c, 0x13), atp_readb_io(dev, c, 0x12)); 350 #endif 351 /* Remap wide */ 352 j = target_id; 353 if (target_id > 7) { 354 j = (j & 0x07) | 0x40; 355 } 356 /* Add direction */ 357 j |= dev->id[c][target_id].dirct; 358 atp_writeb_io(dev, c, 0x15, j); 359 atp_writeb_io(dev, c, 0x16, 0x80); 360 361 /* enable 32 bit fifo transfer */ 362 if (is885(dev)) { 363 i = atp_readb_pci(dev, c, 1) & 0xf3; 364 //j=workreq->cmnd[0]; 365 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) { 366 i |= 0x0c; 367 } 368 atp_writeb_pci(dev, c, 1, i); 369 } else if (is880(dev)) { 370 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) 371 atp_writeb_base(dev, 0x3b, (atp_readb_base(dev, 0x3b) & 0x3f) | 0xc0); 372 else 373 atp_writeb_base(dev, 0x3b, atp_readb_base(dev, 0x3b) & 0x3f); 374 } else { 375 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) 376 atp_writeb_base(dev, 0x3a, (atp_readb_base(dev, 0x3a) & 0xf3) | 0x08); 377 else 378 atp_writeb_base(dev, 0x3a, atp_readb_base(dev, 0x3a) & 0xf3); 379 } 380 j = 0; 381 id = 1; 382 id = id << target_id; 383 /* 384 * Is this a wide device 385 */ 386 if ((id & dev->wide_id[c]) != 0) { 387 j |= 0x01; 388 } 389 atp_writeb_io(dev, c, 0x1b, j); 390 while ((atp_readb_io(dev, c, 0x1b) & 0x01) != j) 391 atp_writeb_io(dev, c, 0x1b, j); 392 if (dev->id[c][target_id].last_len == 0) { 393 atp_writeb_io(dev, c, 0x18, 0x08); 394 dev->in_int[c] = 0; 395 #ifdef ED_DBGP 396 printk("dev->id[c][target_id].last_len = 0\n"); 397 #endif 398 return IRQ_HANDLED; 399 } 400 #ifdef ED_DBGP 401 printk("target_id = %d adrcnt = %d\n",target_id,adrcnt); 402 #endif 403 prd = dev->id[c][target_id].prd_pos; 404 while (adrcnt != 0) { 405 id = ((unsigned short int *)prd)[2]; 406 if (id == 0) { 407 k = 0x10000; 408 } else { 409 k = id; 410 } 411 if (k > adrcnt) { 412 ((unsigned short int *)prd)[2] = (unsigned short int) 413 (k - adrcnt); 414 ((unsigned long *)prd)[0] += adrcnt; 415 adrcnt = 0; 416 dev->id[c][target_id].prd_pos = prd; 417 } else { 418 adrcnt -= k; 419 dev->id[c][target_id].prdaddr += 0x08; 420 prd += 0x08; 421 if (adrcnt == 0) { 422 dev->id[c][target_id].prd_pos = prd; 423 } 424 } 425 } 426 atp_writel_pci(dev, c, 0x04, dev->id[c][target_id].prdaddr); 427 #ifdef ED_DBGP 428 printk("dev->id[%d][%d].prdaddr 0x%8x\n", c, target_id, dev->id[c][target_id].prdaddr); 429 #endif 430 if (!is885(dev)) { 431 atp_writeb_pci(dev, c, 2, 0x06); 432 atp_writeb_pci(dev, c, 2, 0x00); 433 } 434 /* 435 * Check transfer direction 436 */ 437 if (dev->id[c][target_id].dirct != 0) { 438 atp_writeb_io(dev, c, 0x18, 0x08); 439 atp_writeb_pci(dev, c, 0, 0x01); 440 dev->in_int[c] = 0; 441 #ifdef ED_DBGP 442 printk("status 0x80 return dirct != 0\n"); 443 #endif 444 return IRQ_HANDLED; 445 } 446 atp_writeb_io(dev, c, 0x18, 0x08); 447 atp_writeb_pci(dev, c, 0, 0x09); 448 dev->in_int[c] = 0; 449 #ifdef ED_DBGP 450 printk("status 0x80 return dirct = 0\n"); 451 #endif 452 return IRQ_HANDLED; 453 } 454 455 /* 456 * Current scsi request on this target 457 */ 458 459 workreq = dev->id[c][target_id].curr_req; 460 461 if (i == 0x42 || i == 0x16) { 462 if ((dev->last_cmd[c] & 0xf0) != 0x40) { 463 dev->last_cmd[c] = 0xff; 464 } 465 if (i == 0x16) { 466 workreq->result = atp_readb_io(dev, c, 0x0f); 467 if (((dev->r1f[c][target_id] & 0x10) != 0) && is885(dev)) { 468 printk(KERN_WARNING "AEC67162 CRC ERROR !\n"); 469 workreq->result = 0x02; 470 } 471 } else 472 workreq->result = 0x02; 473 474 if (is885(dev)) { 475 j = atp_readb_base(dev, 0x29) | 0x01; 476 atp_writeb_base(dev, 0x29, j); 477 } 478 /* 479 * Complete the command 480 */ 481 scsi_dma_unmap(workreq); 482 483 spin_lock_irqsave(dev->host->host_lock, flags); 484 (*workreq->scsi_done) (workreq); 485 #ifdef ED_DBGP 486 printk("workreq->scsi_done\n"); 487 #endif 488 /* 489 * Clear it off the queue 490 */ 491 dev->id[c][target_id].curr_req = NULL; 492 dev->working[c]--; 493 spin_unlock_irqrestore(dev->host->host_lock, flags); 494 /* 495 * Take it back wide 496 */ 497 if (dev->wide_id[c] != 0) { 498 atp_writeb_io(dev, c, 0x1b, 0x01); 499 while ((atp_readb_io(dev, c, 0x1b) & 0x01) != 0x01) 500 atp_writeb_io(dev, c, 0x1b, 0x01); 501 } 502 /* 503 * If there is stuff to send and nothing going then send it 504 */ 505 spin_lock_irqsave(dev->host->host_lock, flags); 506 if (((dev->last_cmd[c] != 0xff) || (dev->quhd[c] != dev->quend[c])) && 507 (dev->in_snd[c] == 0)) { 508 #ifdef ED_DBGP 509 printk("Call sent_s870(scsi_done)\n"); 510 #endif 511 send_s870(dev,c); 512 } 513 spin_unlock_irqrestore(dev->host->host_lock, flags); 514 dev->in_int[c] = 0; 515 return IRQ_HANDLED; 516 } 517 if ((dev->last_cmd[c] & 0xf0) != 0x40) { 518 dev->last_cmd[c] = 0xff; 519 } 520 if (i == 0x4f) { 521 i = 0x89; 522 } 523 i &= 0x0f; 524 if (i == 0x09) { 525 atp_writel_pci(dev, c, 4, dev->id[c][target_id].prdaddr); 526 atp_writeb_pci(dev, c, 2, 0x06); 527 atp_writeb_pci(dev, c, 2, 0x00); 528 atp_writeb_io(dev, c, 0x10, 0x41); 529 if (is885(dev)) { 530 k = dev->id[c][target_id].last_len; 531 atp_writeb_io(dev, c, 0x12, ((unsigned char *) (&k))[2]); 532 atp_writeb_io(dev, c, 0x13, ((unsigned char *) (&k))[1]); 533 atp_writeb_io(dev, c, 0x14, ((unsigned char *) (&k))[0]); 534 dev->id[c][target_id].dirct = 0x00; 535 } else { 536 dev->id[c][target_id].dirct = 0x00; 537 } 538 atp_writeb_io(dev, c, 0x18, 0x08); 539 atp_writeb_pci(dev, c, 0, 0x09); 540 dev->in_int[c] = 0; 541 return IRQ_HANDLED; 542 } 543 if (i == 0x08) { 544 atp_writel_pci(dev, c, 4, dev->id[c][target_id].prdaddr); 545 atp_writeb_pci(dev, c, 2, 0x06); 546 atp_writeb_pci(dev, c, 2, 0x00); 547 atp_writeb_io(dev, c, 0x10, 0x41); 548 if (is885(dev)) { 549 k = dev->id[c][target_id].last_len; 550 atp_writeb_io(dev, c, 0x12, ((unsigned char *) (&k))[2]); 551 atp_writeb_io(dev, c, 0x13, ((unsigned char *) (&k))[1]); 552 atp_writeb_io(dev, c, 0x14, ((unsigned char *) (&k))[0]); 553 } 554 atp_writeb_io(dev, c, 0x15, atp_readb_io(dev, c, 0x15) | 0x20); 555 dev->id[c][target_id].dirct = 0x20; 556 atp_writeb_io(dev, c, 0x18, 0x08); 557 atp_writeb_pci(dev, c, 0, 0x01); 558 dev->in_int[c] = 0; 559 return IRQ_HANDLED; 560 } 561 if (i == 0x0a) 562 atp_writeb_io(dev, c, 0x10, 0x30); 563 else 564 atp_writeb_io(dev, c, 0x10, 0x46); 565 dev->id[c][target_id].dirct = 0x00; 566 atp_writeb_io(dev, c, 0x12, 0x00); 567 atp_writeb_io(dev, c, 0x13, 0x00); 568 atp_writeb_io(dev, c, 0x14, 0x00); 569 atp_writeb_io(dev, c, 0x18, 0x08); 570 } 571 dev->in_int[c] = 0; 572 573 return IRQ_HANDLED; 574 } 575 /** 576 * atp870u_queuecommand - Queue SCSI command 577 * @req_p: request block 578 * @done: completion function 579 * 580 * Queue a command to the ATP queue. Called with the host lock held. 581 */ 582 static int atp870u_queuecommand_lck(struct scsi_cmnd *req_p, 583 void (*done) (struct scsi_cmnd *)) 584 { 585 unsigned char c; 586 unsigned int m; 587 struct atp_unit *dev; 588 struct Scsi_Host *host; 589 590 c = scmd_channel(req_p); 591 req_p->sense_buffer[0]=0; 592 scsi_set_resid(req_p, 0); 593 if (scmd_channel(req_p) > 1) { 594 req_p->result = 0x00040000; 595 done(req_p); 596 #ifdef ED_DBGP 597 printk("atp870u_queuecommand : req_p->device->channel > 1\n"); 598 #endif 599 return 0; 600 } 601 602 host = req_p->device->host; 603 dev = (struct atp_unit *)&host->hostdata; 604 605 606 607 m = 1; 608 m = m << scmd_id(req_p); 609 610 /* 611 * Fake a timeout for missing targets 612 */ 613 614 if ((m & dev->active_id[c]) == 0) { 615 req_p->result = 0x00040000; 616 done(req_p); 617 return 0; 618 } 619 620 if (done) { 621 req_p->scsi_done = done; 622 } else { 623 #ifdef ED_DBGP 624 printk( "atp870u_queuecommand: done can't be NULL\n"); 625 #endif 626 req_p->result = 0; 627 done(req_p); 628 return 0; 629 } 630 631 /* 632 * Count new command 633 */ 634 dev->quend[c]++; 635 if (dev->quend[c] >= qcnt) { 636 dev->quend[c] = 0; 637 } 638 639 /* 640 * Check queue state 641 */ 642 if (dev->quhd[c] == dev->quend[c]) { 643 if (dev->quend[c] == 0) { 644 dev->quend[c] = qcnt; 645 } 646 #ifdef ED_DBGP 647 printk("atp870u_queuecommand : dev->quhd[c] == dev->quend[c]\n"); 648 #endif 649 dev->quend[c]--; 650 req_p->result = 0x00020000; 651 done(req_p); 652 return 0; 653 } 654 dev->quereq[c][dev->quend[c]] = req_p; 655 #ifdef ED_DBGP 656 printk("dev->ioport[c] = %x atp_readb_io(dev, c, 0x1c) = %x dev->in_int[%d] = %d dev->in_snd[%d] = %d\n",dev->ioport[c],atp_readb_io(dev, c, 0x1c),c,dev->in_int[c],c,dev->in_snd[c]); 657 #endif 658 if ((atp_readb_io(dev, c, 0x1c) == 0) && (dev->in_int[c] == 0) && (dev->in_snd[c] == 0)) { 659 #ifdef ED_DBGP 660 printk("Call sent_s870(atp870u_queuecommand)\n"); 661 #endif 662 send_s870(dev,c); 663 } 664 #ifdef ED_DBGP 665 printk("atp870u_queuecommand : exit\n"); 666 #endif 667 return 0; 668 } 669 670 static DEF_SCSI_QCMD(atp870u_queuecommand) 671 672 /** 673 * send_s870 - send a command to the controller 674 * @host: host 675 * 676 * On entry there is work queued to be done. We move some of that work to the 677 * controller itself. 678 * 679 * Caller holds the host lock. 680 */ 681 static void send_s870(struct atp_unit *dev,unsigned char c) 682 { 683 struct scsi_cmnd *workreq = NULL; 684 unsigned int i;//,k; 685 unsigned char j, target_id; 686 unsigned char *prd; 687 unsigned short int w; 688 unsigned long l, bttl = 0; 689 unsigned long sg_count; 690 691 if (dev->in_snd[c] != 0) { 692 #ifdef ED_DBGP 693 printk("cmnd in_snd\n"); 694 #endif 695 return; 696 } 697 #ifdef ED_DBGP 698 printk("Sent_s870 enter\n"); 699 #endif 700 dev->in_snd[c] = 1; 701 if ((dev->last_cmd[c] != 0xff) && ((dev->last_cmd[c] & 0x40) != 0)) { 702 dev->last_cmd[c] &= 0x0f; 703 workreq = dev->id[c][dev->last_cmd[c]].curr_req; 704 if (!workreq) { 705 dev->last_cmd[c] = 0xff; 706 if (dev->quhd[c] == dev->quend[c]) { 707 dev->in_snd[c] = 0; 708 return; 709 } 710 } 711 } 712 if (!workreq) { 713 if ((dev->last_cmd[c] != 0xff) && (dev->working[c] != 0)) { 714 dev->in_snd[c] = 0; 715 return; 716 } 717 dev->working[c]++; 718 j = dev->quhd[c]; 719 dev->quhd[c]++; 720 if (dev->quhd[c] >= qcnt) 721 dev->quhd[c] = 0; 722 workreq = dev->quereq[c][dev->quhd[c]]; 723 if (dev->id[c][scmd_id(workreq)].curr_req != NULL) { 724 dev->quhd[c] = j; 725 dev->working[c]--; 726 dev->in_snd[c] = 0; 727 return; 728 } 729 dev->id[c][scmd_id(workreq)].curr_req = workreq; 730 dev->last_cmd[c] = scmd_id(workreq); 731 } 732 if ((atp_readb_io(dev, c, 0x1f) & 0xb0) != 0 || atp_readb_io(dev, c, 0x1c) != 0) { 733 #ifdef ED_DBGP 734 printk("Abort to Send\n"); 735 #endif 736 dev->last_cmd[c] |= 0x40; 737 dev->in_snd[c] = 0; 738 return; 739 } 740 #ifdef ED_DBGP 741 printk("OK to Send\n"); 742 scmd_printk(KERN_DEBUG, workreq, "CDB"); 743 for(i=0;i<workreq->cmd_len;i++) { 744 printk(" %x",workreq->cmnd[i]); 745 } 746 printk("\n"); 747 #endif 748 l = scsi_bufflen(workreq); 749 750 if (is885(dev)) { 751 j = atp_readb_base(dev, 0x29) & 0xfe; 752 atp_writeb_base(dev, 0x29, j); 753 dev->r1f[c][scmd_id(workreq)] = 0; 754 } 755 756 if (workreq->cmnd[0] == READ_CAPACITY) { 757 if (l > 8) 758 l = 8; 759 } 760 if (workreq->cmnd[0] == 0x00) { 761 l = 0; 762 } 763 764 j = 0; 765 target_id = scmd_id(workreq); 766 767 /* 768 * Wide ? 769 */ 770 w = 1; 771 w = w << target_id; 772 if ((w & dev->wide_id[c]) != 0) { 773 j |= 0x01; 774 } 775 atp_writeb_io(dev, c, 0x1b, j); 776 while ((atp_readb_io(dev, c, 0x1b) & 0x01) != j) { 777 atp_writeb_pci(dev, c, 0x1b, j); 778 #ifdef ED_DBGP 779 printk("send_s870 while loop 1\n"); 780 #endif 781 } 782 /* 783 * Write the command 784 */ 785 786 atp_writeb_io(dev, c, 0x00, workreq->cmd_len); 787 atp_writeb_io(dev, c, 0x01, 0x2c); 788 if (is885(dev)) 789 atp_writeb_io(dev, c, 0x02, 0x7f); 790 else 791 atp_writeb_io(dev, c, 0x02, 0xcf); 792 for (i = 0; i < workreq->cmd_len; i++) 793 atp_writeb_io(dev, c, 0x03 + i, workreq->cmnd[i]); 794 atp_writeb_io(dev, c, 0x0f, workreq->device->lun); 795 /* 796 * Write the target 797 */ 798 atp_writeb_io(dev, c, 0x11, dev->id[c][target_id].devsp); 799 #ifdef ED_DBGP 800 printk("dev->id[%d][%d].devsp = %2x\n",c,target_id,dev->id[c][target_id].devsp); 801 #endif 802 803 sg_count = scsi_dma_map(workreq); 804 /* 805 * Write transfer size 806 */ 807 atp_writeb_io(dev, c, 0x12, ((unsigned char *) (&l))[2]); 808 atp_writeb_io(dev, c, 0x13, ((unsigned char *) (&l))[1]); 809 atp_writeb_io(dev, c, 0x14, ((unsigned char *) (&l))[0]); 810 j = target_id; 811 dev->id[c][j].last_len = l; 812 dev->id[c][j].tran_len = 0; 813 #ifdef ED_DBGP 814 printk("dev->id[%2d][%2d].last_len = %d\n",c,j,dev->id[c][j].last_len); 815 #endif 816 /* 817 * Flip the wide bits 818 */ 819 if ((j & 0x08) != 0) { 820 j = (j & 0x07) | 0x40; 821 } 822 /* 823 * Check transfer direction 824 */ 825 if (workreq->sc_data_direction == DMA_TO_DEVICE) 826 atp_writeb_io(dev, c, 0x15, j | 0x20); 827 else 828 atp_writeb_io(dev, c, 0x15, j); 829 atp_writeb_io(dev, c, 0x16, atp_readb_io(dev, c, 0x16) | 0x80); 830 atp_writeb_io(dev, c, 0x16, 0x80); 831 dev->id[c][target_id].dirct = 0; 832 if (l == 0) { 833 if (atp_readb_io(dev, c, 0x1c) == 0) { 834 #ifdef ED_DBGP 835 printk("change SCSI_CMD_REG 0x08\n"); 836 #endif 837 atp_writeb_io(dev, c, 0x18, 0x08); 838 } else 839 dev->last_cmd[c] |= 0x40; 840 dev->in_snd[c] = 0; 841 return; 842 } 843 prd = dev->id[c][target_id].prd_table; 844 dev->id[c][target_id].prd_pos = prd; 845 846 /* 847 * Now write the request list. Either as scatter/gather or as 848 * a linear chain. 849 */ 850 851 if (l) { 852 struct scatterlist *sgpnt; 853 i = 0; 854 scsi_for_each_sg(workreq, sgpnt, sg_count, j) { 855 bttl = sg_dma_address(sgpnt); 856 l=sg_dma_len(sgpnt); 857 #ifdef ED_DBGP 858 printk("1. bttl %x, l %x\n",bttl, l); 859 #endif 860 while (l > 0x10000) { 861 (((u16 *) (prd))[i + 3]) = 0x0000; 862 (((u16 *) (prd))[i + 2]) = 0x0000; 863 (((u32 *) (prd))[i >> 1]) = cpu_to_le32(bttl); 864 l -= 0x10000; 865 bttl += 0x10000; 866 i += 0x04; 867 } 868 (((u32 *) (prd))[i >> 1]) = cpu_to_le32(bttl); 869 (((u16 *) (prd))[i + 2]) = cpu_to_le16(l); 870 (((u16 *) (prd))[i + 3]) = 0; 871 i += 0x04; 872 } 873 (((u16 *) (prd))[i - 1]) = cpu_to_le16(0x8000); 874 #ifdef ED_DBGP 875 printk("prd %4x %4x %4x %4x\n",(((unsigned short int *)prd)[0]),(((unsigned short int *)prd)[1]),(((unsigned short int *)prd)[2]),(((unsigned short int *)prd)[3])); 876 printk("2. bttl %x, l %x\n",bttl, l); 877 #endif 878 } 879 #ifdef ED_DBGP 880 printk("send_s870: prdaddr_2 0x%8x target_id %d\n", dev->id[c][target_id].prdaddr,target_id); 881 #endif 882 dev->id[c][target_id].prdaddr = dev->id[c][target_id].prd_bus; 883 atp_writel_pci(dev, c, 4, dev->id[c][target_id].prdaddr); 884 atp_writeb_pci(dev, c, 2, 0x06); 885 atp_writeb_pci(dev, c, 2, 0x00); 886 if (is885(dev)) { 887 j = atp_readb_pci(dev, c, 1) & 0xf3; 888 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || 889 (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) { 890 j |= 0x0c; 891 } 892 atp_writeb_pci(dev, c, 1, j); 893 } else if (is880(dev)) { 894 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) 895 atp_writeb_base(dev, 0x3b, (atp_readb_base(dev, 0x3b) & 0x3f) | 0xc0); 896 else 897 atp_writeb_base(dev, 0x3b, atp_readb_base(dev, 0x3b) & 0x3f); 898 } else { 899 if ((workreq->cmnd[0] == 0x08) || (workreq->cmnd[0] == 0x28) || (workreq->cmnd[0] == 0x0a) || (workreq->cmnd[0] == 0x2a)) 900 atp_writeb_base(dev, 0x3a, (atp_readb_base(dev, 0x3a) & 0xf3) | 0x08); 901 else 902 atp_writeb_base(dev, 0x3a, atp_readb_base(dev, 0x3a) & 0xf3); 903 } 904 905 if(workreq->sc_data_direction == DMA_TO_DEVICE) { 906 dev->id[c][target_id].dirct = 0x20; 907 if (atp_readb_io(dev, c, 0x1c) == 0) { 908 atp_writeb_io(dev, c, 0x18, 0x08); 909 atp_writeb_pci(dev, c, 0, 0x01); 910 #ifdef ED_DBGP 911 printk( "start DMA(to target)\n"); 912 #endif 913 } else { 914 dev->last_cmd[c] |= 0x40; 915 } 916 dev->in_snd[c] = 0; 917 return; 918 } 919 if (atp_readb_io(dev, c, 0x1c) == 0) { 920 atp_writeb_io(dev, c, 0x18, 0x08); 921 atp_writeb_pci(dev, c, 0, 0x09); 922 #ifdef ED_DBGP 923 printk( "start DMA(to host)\n"); 924 #endif 925 } else { 926 dev->last_cmd[c] |= 0x40; 927 } 928 dev->in_snd[c] = 0; 929 return; 930 931 } 932 933 static unsigned char fun_scam(struct atp_unit *dev, unsigned short int *val) 934 { 935 unsigned short int i, k; 936 unsigned char j; 937 938 atp_writew_io(dev, 0, 0x1c, *val); 939 for (i = 0; i < 10; i++) { /* stable >= bus settle delay(400 ns) */ 940 k = atp_readw_io(dev, 0, 0x1c); 941 j = (unsigned char) (k >> 8); 942 if ((k & 0x8000) != 0) /* DB7 all release? */ 943 i = 0; 944 } 945 *val |= 0x4000; /* assert DB6 */ 946 atp_writew_io(dev, 0, 0x1c, *val); 947 *val &= 0xdfff; /* assert DB5 */ 948 atp_writew_io(dev, 0, 0x1c, *val); 949 for (i = 0; i < 10; i++) { /* stable >= bus settle delay(400 ns) */ 950 if ((atp_readw_io(dev, 0, 0x1c) & 0x2000) != 0) /* DB5 all release? */ 951 i = 0; 952 } 953 *val |= 0x8000; /* no DB4-0, assert DB7 */ 954 *val &= 0xe0ff; 955 atp_writew_io(dev, 0, 0x1c, *val); 956 *val &= 0xbfff; /* release DB6 */ 957 atp_writew_io(dev, 0, 0x1c, *val); 958 for (i = 0; i < 10; i++) { /* stable >= bus settle delay(400 ns) */ 959 if ((atp_readw_io(dev, 0, 0x1c) & 0x4000) != 0) /* DB6 all release? */ 960 i = 0; 961 } 962 963 return j; 964 } 965 966 static void tscam(struct Scsi_Host *host, bool wide_chip, u8 scam_on) 967 { 968 969 unsigned char i, j, k; 970 unsigned long n; 971 unsigned short int m, assignid_map, val; 972 unsigned char mbuf[33], quintet[2]; 973 struct atp_unit *dev = (struct atp_unit *)&host->hostdata; 974 static unsigned char g2q_tab[8] = { 975 0x38, 0x31, 0x32, 0x2b, 0x34, 0x2d, 0x2e, 0x27 976 }; 977 978 /* I can't believe we need this before we've even done anything. Remove it 979 * and see if anyone bitches. 980 for (i = 0; i < 0x10; i++) { 981 udelay(0xffff); 982 } 983 */ 984 985 atp_writeb_io(dev, 0, 1, 0x08); 986 atp_writeb_io(dev, 0, 2, 0x7f); 987 atp_writeb_io(dev, 0, 0x11, 0x20); 988 989 if ((scam_on & 0x40) == 0) { 990 return; 991 } 992 m = 1; 993 m <<= dev->host_id[0]; 994 j = 16; 995 if (!wide_chip) { 996 m |= 0xff00; 997 j = 8; 998 } 999 assignid_map = m; 1000 atp_writeb_io(dev, 0, 0x02, 0x02); /* 2*2=4ms,3EH 2/32*3E=3.9ms */ 1001 atp_writeb_io(dev, 0, 0x03, 0); 1002 atp_writeb_io(dev, 0, 0x04, 0); 1003 atp_writeb_io(dev, 0, 0x05, 0); 1004 atp_writeb_io(dev, 0, 0x06, 0); 1005 atp_writeb_io(dev, 0, 0x07, 0); 1006 atp_writeb_io(dev, 0, 0x08, 0); 1007 1008 for (i = 0; i < j; i++) { 1009 m = 1; 1010 m = m << i; 1011 if ((m & assignid_map) != 0) { 1012 continue; 1013 } 1014 atp_writeb_io(dev, 0, 0x0f, 0); 1015 atp_writeb_io(dev, 0, 0x12, 0); 1016 atp_writeb_io(dev, 0, 0x13, 0); 1017 atp_writeb_io(dev, 0, 0x14, 0); 1018 if (i > 7) { 1019 k = (i & 0x07) | 0x40; 1020 } else { 1021 k = i; 1022 } 1023 atp_writeb_io(dev, 0, 0x15, k); 1024 if (wide_chip) 1025 atp_writeb_io(dev, 0, 0x1b, 0x01); 1026 else 1027 atp_writeb_io(dev, 0, 0x1b, 0x00); 1028 do { 1029 atp_writeb_io(dev, 0, 0x18, 0x09); 1030 1031 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0x00) 1032 cpu_relax(); 1033 k = atp_readb_io(dev, 0, 0x17); 1034 if ((k == 0x85) || (k == 0x42)) 1035 break; 1036 if (k != 0x16) 1037 atp_writeb_io(dev, 0, 0x10, 0x41); 1038 } while (k != 0x16); 1039 if ((k == 0x85) || (k == 0x42)) 1040 continue; 1041 assignid_map |= m; 1042 1043 } 1044 atp_writeb_io(dev, 0, 0x02, 0x7f); 1045 atp_writeb_io(dev, 0, 0x1b, 0x02); 1046 1047 udelay(2); 1048 1049 val = 0x0080; /* bsy */ 1050 atp_writew_io(dev, 0, 0x1c, val); 1051 val |= 0x0040; /* sel */ 1052 atp_writew_io(dev, 0, 0x1c, val); 1053 val |= 0x0004; /* msg */ 1054 atp_writew_io(dev, 0, 0x1c, val); 1055 udelay(2); /* 2 deskew delay(45ns*2=90ns) */ 1056 val &= 0x007f; /* no bsy */ 1057 atp_writew_io(dev, 0, 0x1c, val); 1058 mdelay(128); 1059 val &= 0x00fb; /* after 1ms no msg */ 1060 atp_writew_io(dev, 0, 0x1c, val); 1061 while ((atp_readb_io(dev, 0, 0x1c) & 0x04) != 0) 1062 ; 1063 udelay(2); 1064 udelay(100); 1065 for (n = 0; n < 0x30000; n++) 1066 if ((atp_readb_io(dev, 0, 0x1c) & 0x80) != 0) /* bsy ? */ 1067 break; 1068 if (n < 0x30000) 1069 for (n = 0; n < 0x30000; n++) 1070 if ((atp_readb_io(dev, 0, 0x1c) & 0x81) == 0x0081) { 1071 udelay(2); 1072 val |= 0x8003; /* io,cd,db7 */ 1073 atp_writew_io(dev, 0, 0x1c, val); 1074 udelay(2); 1075 val &= 0x00bf; /* no sel */ 1076 atp_writew_io(dev, 0, 0x1c, val); 1077 udelay(2); 1078 break; 1079 } 1080 while (1) { 1081 /* 1082 * The funny division into multiple delays is to accomodate 1083 * arches like ARM where udelay() multiplies its argument by 1084 * a large number to initialize a loop counter. To avoid 1085 * overflow, the maximum supported udelay is 2000 microseconds. 1086 * 1087 * XXX it would be more polite to find a way to use msleep() 1088 */ 1089 mdelay(2); 1090 udelay(48); 1091 if ((atp_readb_io(dev, 0, 0x1c) & 0x80) == 0x00) { /* bsy ? */ 1092 atp_writew_io(dev, 0, 0x1c, 0); 1093 atp_writeb_io(dev, 0, 0x1b, 0); 1094 atp_writeb_io(dev, 0, 0x15, 0); 1095 atp_writeb_io(dev, 0, 0x18, 0x09); 1096 while ((atp_readb_io(dev, 0, 0x1f) & 0x80) == 0) 1097 cpu_relax(); 1098 atp_readb_io(dev, 0, 0x17); 1099 return; 1100 } 1101 val &= 0x00ff; /* synchronization */ 1102 val |= 0x3f00; 1103 fun_scam(dev, &val); 1104 udelay(2); 1105 val &= 0x00ff; /* isolation */ 1106 val |= 0x2000; 1107 fun_scam(dev, &val); 1108 udelay(2); 1109 i = 8; 1110 j = 0; 1111 1112 while (1) { 1113 if ((atp_readw_io(dev, 0, 0x1c) & 0x2000) == 0) 1114 continue; 1115 udelay(2); 1116 val &= 0x00ff; /* get ID_STRING */ 1117 val |= 0x2000; 1118 k = fun_scam(dev, &val); 1119 if ((k & 0x03) == 0) 1120 break; 1121 mbuf[j] <<= 0x01; 1122 mbuf[j] &= 0xfe; 1123 if ((k & 0x02) != 0) 1124 mbuf[j] |= 0x01; 1125 i--; 1126 if (i > 0) 1127 continue; 1128 j++; 1129 i = 8; 1130 } 1131 1132 /* isolation complete.. */ 1133 /* mbuf[32]=0; 1134 printk(" \n%x %x %x %s\n ",assignid_map,mbuf[0],mbuf[1],&mbuf[2]); */ 1135 i = 15; 1136 j = mbuf[0]; 1137 if ((j & 0x20) != 0) { /* bit5=1:ID up to 7 */ 1138 i = 7; 1139 } 1140 if ((j & 0x06) != 0) { /* IDvalid? */ 1141 k = mbuf[1]; 1142 while (1) { 1143 m = 1; 1144 m <<= k; 1145 if ((m & assignid_map) == 0) 1146 break; 1147 if (k > 0) 1148 k--; 1149 else 1150 break; 1151 } 1152 } 1153 if ((m & assignid_map) != 0) { /* srch from max acceptable ID# */ 1154 k = i; /* max acceptable ID# */ 1155 while (1) { 1156 m = 1; 1157 m <<= k; 1158 if ((m & assignid_map) == 0) 1159 break; 1160 if (k > 0) 1161 k--; 1162 else 1163 break; 1164 } 1165 } 1166 /* k=binID#, */ 1167 assignid_map |= m; 1168 if (k < 8) { 1169 quintet[0] = 0x38; /* 1st dft ID<8 */ 1170 } else { 1171 quintet[0] = 0x31; /* 1st ID>=8 */ 1172 } 1173 k &= 0x07; 1174 quintet[1] = g2q_tab[k]; 1175 1176 val &= 0x00ff; /* AssignID 1stQuintet,AH=001xxxxx */ 1177 m = quintet[0] << 8; 1178 val |= m; 1179 fun_scam(dev, &val); 1180 val &= 0x00ff; /* AssignID 2ndQuintet,AH=001xxxxx */ 1181 m = quintet[1] << 8; 1182 val |= m; 1183 fun_scam(dev, &val); 1184 1185 } 1186 } 1187 1188 static void atp870u_free_tables(struct Scsi_Host *host) 1189 { 1190 struct atp_unit *atp_dev = (struct atp_unit *)&host->hostdata; 1191 int j, k; 1192 for (j=0; j < 2; j++) { 1193 for (k = 0; k < 16; k++) { 1194 if (!atp_dev->id[j][k].prd_table) 1195 continue; 1196 pci_free_consistent(atp_dev->pdev, 1024, atp_dev->id[j][k].prd_table, atp_dev->id[j][k].prd_bus); 1197 atp_dev->id[j][k].prd_table = NULL; 1198 } 1199 } 1200 } 1201 1202 static int atp870u_init_tables(struct Scsi_Host *host) 1203 { 1204 struct atp_unit *atp_dev = (struct atp_unit *)&host->hostdata; 1205 int c,k; 1206 for(c=0;c < 2;c++) { 1207 for(k=0;k<16;k++) { 1208 atp_dev->id[c][k].prd_table = pci_alloc_consistent(atp_dev->pdev, 1024, &(atp_dev->id[c][k].prd_bus)); 1209 if (!atp_dev->id[c][k].prd_table) { 1210 printk("atp870u_init_tables fail\n"); 1211 atp870u_free_tables(host); 1212 return -ENOMEM; 1213 } 1214 atp_dev->id[c][k].prdaddr = atp_dev->id[c][k].prd_bus; 1215 atp_dev->id[c][k].devsp=0x20; 1216 atp_dev->id[c][k].devtype = 0x7f; 1217 atp_dev->id[c][k].curr_req = NULL; 1218 } 1219 1220 atp_dev->active_id[c] = 0; 1221 atp_dev->wide_id[c] = 0; 1222 atp_dev->host_id[c] = 0x07; 1223 atp_dev->quhd[c] = 0; 1224 atp_dev->quend[c] = 0; 1225 atp_dev->last_cmd[c] = 0xff; 1226 atp_dev->in_snd[c] = 0; 1227 atp_dev->in_int[c] = 0; 1228 1229 for (k = 0; k < qcnt; k++) { 1230 atp_dev->quereq[c][k] = NULL; 1231 } 1232 for (k = 0; k < 16; k++) { 1233 atp_dev->id[c][k].curr_req = NULL; 1234 atp_dev->sp[c][k] = 0x04; 1235 } 1236 } 1237 return 0; 1238 } 1239 1240 static void atp_set_host_id(struct atp_unit *atp, u8 c, u8 host_id) 1241 { 1242 atp_writeb_io(atp, c, 0, host_id | 0x08); 1243 atp_writeb_io(atp, c, 0x18, 0); 1244 while ((atp_readb_io(atp, c, 0x1f) & 0x80) == 0) 1245 mdelay(1); 1246 atp_readb_io(atp, c, 0x17); 1247 atp_writeb_io(atp, c, 1, 8); 1248 atp_writeb_io(atp, c, 2, 0x7f); 1249 atp_writeb_io(atp, c, 0x11, 0x20); 1250 } 1251 1252 static void atp870_init(struct Scsi_Host *shpnt) 1253 { 1254 struct atp_unit *atpdev = shost_priv(shpnt); 1255 struct pci_dev *pdev = atpdev->pdev; 1256 unsigned char k, host_id; 1257 u8 scam_on; 1258 bool wide_chip = 1259 (pdev->device == PCI_DEVICE_ID_ARTOP_AEC7610 && 1260 pdev->revision == 4) || 1261 (pdev->device == PCI_DEVICE_ID_ARTOP_AEC7612UW) || 1262 (pdev->device == PCI_DEVICE_ID_ARTOP_AEC7612SUW); 1263 1264 pci_read_config_byte(pdev, 0x49, &host_id); 1265 1266 dev_info(&pdev->dev, "ACARD AEC-671X PCI Ultra/W SCSI-2/3 Host Adapter: IO:%lx, IRQ:%d.\n", 1267 shpnt->io_port, shpnt->irq); 1268 1269 atpdev->ioport[0] = shpnt->io_port; 1270 atpdev->pciport[0] = shpnt->io_port + 0x20; 1271 host_id &= 0x07; 1272 atpdev->host_id[0] = host_id; 1273 scam_on = atp_readb_pci(atpdev, 0, 2); 1274 atpdev->global_map[0] = atp_readb_base(atpdev, 0x2d); 1275 atpdev->ultra_map[0] = atp_readw_base(atpdev, 0x2e); 1276 1277 if (atpdev->ultra_map[0] == 0) { 1278 scam_on = 0x00; 1279 atpdev->global_map[0] = 0x20; 1280 atpdev->ultra_map[0] = 0xffff; 1281 } 1282 1283 if (pdev->revision > 0x07) /* check if atp876 chip */ 1284 atp_writeb_base(atpdev, 0x3e, 0x00); /* enable terminator */ 1285 1286 k = (atp_readb_base(atpdev, 0x3a) & 0xf3) | 0x10; 1287 atp_writeb_base(atpdev, 0x3a, k); 1288 atp_writeb_base(atpdev, 0x3a, k & 0xdf); 1289 mdelay(32); 1290 atp_writeb_base(atpdev, 0x3a, k); 1291 mdelay(32); 1292 atp_set_host_id(atpdev, 0, host_id); 1293 1294 tscam(shpnt, wide_chip, scam_on); 1295 atp_writeb_base(atpdev, 0x3a, atp_readb_base(atpdev, 0x3a) | 0x10); 1296 atp_is(atpdev, 0, wide_chip, 0); 1297 atp_writeb_base(atpdev, 0x3a, atp_readb_base(atpdev, 0x3a) & 0xef); 1298 atp_writeb_base(atpdev, 0x3b, atp_readb_base(atpdev, 0x3b) | 0x20); 1299 shpnt->max_id = wide_chip ? 16 : 8; 1300 shpnt->this_id = host_id; 1301 } 1302 1303 static void atp880_init(struct Scsi_Host *shpnt) 1304 { 1305 struct atp_unit *atpdev = shost_priv(shpnt); 1306 struct pci_dev *pdev = atpdev->pdev; 1307 unsigned char k, m, host_id; 1308 unsigned int n; 1309 1310 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80); 1311 1312 atpdev->ioport[0] = shpnt->io_port + 0x40; 1313 atpdev->pciport[0] = shpnt->io_port + 0x28; 1314 1315 host_id = atp_readb_base(atpdev, 0x39) >> 4; 1316 1317 dev_info(&pdev->dev, "ACARD AEC-67160 PCI Ultra3 LVD Host Adapter: IO:%lx, IRQ:%d.\n", 1318 shpnt->io_port, shpnt->irq); 1319 atpdev->host_id[0] = host_id; 1320 1321 atpdev->global_map[0] = atp_readb_base(atpdev, 0x35); 1322 atpdev->ultra_map[0] = atp_readw_base(atpdev, 0x3c); 1323 1324 n = 0x3f09; 1325 while (n < 0x4000) { 1326 m = 0; 1327 atp_writew_base(atpdev, 0x34, n); 1328 n += 0x0002; 1329 if (atp_readb_base(atpdev, 0x30) == 0xff) 1330 break; 1331 1332 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x30); 1333 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x31); 1334 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x32); 1335 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x33); 1336 atp_writew_base(atpdev, 0x34, n); 1337 n += 0x0002; 1338 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x30); 1339 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x31); 1340 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x32); 1341 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x33); 1342 atp_writew_base(atpdev, 0x34, n); 1343 n += 0x0002; 1344 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x30); 1345 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x31); 1346 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x32); 1347 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x33); 1348 atp_writew_base(atpdev, 0x34, n); 1349 n += 0x0002; 1350 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x30); 1351 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x31); 1352 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x32); 1353 atpdev->sp[0][m++] = atp_readb_base(atpdev, 0x33); 1354 n += 0x0018; 1355 } 1356 atp_writew_base(atpdev, 0x34, 0); 1357 atpdev->ultra_map[0] = 0; 1358 atpdev->async[0] = 0; 1359 for (k = 0; k < 16; k++) { 1360 n = 1 << k; 1361 if (atpdev->sp[0][k] > 1) 1362 atpdev->ultra_map[0] |= n; 1363 else 1364 if (atpdev->sp[0][k] == 0) 1365 atpdev->async[0] |= n; 1366 } 1367 atpdev->async[0] = ~(atpdev->async[0]); 1368 atp_writeb_base(atpdev, 0x35, atpdev->global_map[0]); 1369 1370 k = atp_readb_base(atpdev, 0x38) & 0x80; 1371 atp_writeb_base(atpdev, 0x38, k); 1372 atp_writeb_base(atpdev, 0x3b, 0x20); 1373 mdelay(32); 1374 atp_writeb_base(atpdev, 0x3b, 0); 1375 mdelay(32); 1376 atp_readb_io(atpdev, 0, 0x1b); 1377 atp_readb_io(atpdev, 0, 0x17); 1378 1379 atp_set_host_id(atpdev, 0, host_id); 1380 1381 tscam(shpnt, true, atp_readb_base(atpdev, 0x22)); 1382 atp_is(atpdev, 0, true, atp_readb_base(atpdev, 0x3f) & 0x40); 1383 atp_writeb_base(atpdev, 0x38, 0xb0); 1384 shpnt->max_id = 16; 1385 shpnt->this_id = host_id; 1386 } 1387 1388 static void atp885_init(struct Scsi_Host *shpnt) 1389 { 1390 struct atp_unit *atpdev = shost_priv(shpnt); 1391 struct pci_dev *pdev = atpdev->pdev; 1392 unsigned char k, m, c; 1393 unsigned int n; 1394 unsigned char setupdata[2][16]; 1395 1396 dev_info(&pdev->dev, "ACARD AEC-67162 PCI Ultra3 LVD Host Adapter: IO:%lx, IRQ:%d.\n", 1397 shpnt->io_port, shpnt->irq); 1398 1399 atpdev->ioport[0] = shpnt->io_port + 0x80; 1400 atpdev->ioport[1] = shpnt->io_port + 0xc0; 1401 atpdev->pciport[0] = shpnt->io_port + 0x40; 1402 atpdev->pciport[1] = shpnt->io_port + 0x50; 1403 1404 c = atp_readb_base(atpdev, 0x29); 1405 atp_writeb_base(atpdev, 0x29, c | 0x04); 1406 1407 n = 0x1f80; 1408 while (n < 0x2000) { 1409 atp_writew_base(atpdev, 0x3c, n); 1410 if (atp_readl_base(atpdev, 0x38) == 0xffffffff) 1411 break; 1412 for (m = 0; m < 2; m++) { 1413 atpdev->global_map[m] = 0; 1414 for (k = 0; k < 4; k++) { 1415 atp_writew_base(atpdev, 0x3c, n++); 1416 ((u32 *)&setupdata[m][0])[k] = atp_readl_base(atpdev, 0x38); 1417 } 1418 for (k = 0; k < 4; k++) { 1419 atp_writew_base(atpdev, 0x3c, n++); 1420 ((u32 *)&atpdev->sp[m][0])[k] = atp_readl_base(atpdev, 0x38); 1421 } 1422 n += 8; 1423 } 1424 } 1425 c = atp_readb_base(atpdev, 0x29); 1426 atp_writeb_base(atpdev, 0x29, c & 0xfb); 1427 for (c = 0; c < 2; c++) { 1428 atpdev->ultra_map[c] = 0; 1429 atpdev->async[c] = 0; 1430 for (k = 0; k < 16; k++) { 1431 n = 1 << k; 1432 if (atpdev->sp[c][k] > 1) 1433 atpdev->ultra_map[c] |= n; 1434 else 1435 if (atpdev->sp[c][k] == 0) 1436 atpdev->async[c] |= n; 1437 } 1438 atpdev->async[c] = ~(atpdev->async[c]); 1439 1440 if (atpdev->global_map[c] == 0) { 1441 k = setupdata[c][1]; 1442 if ((k & 0x40) != 0) 1443 atpdev->global_map[c] |= 0x20; 1444 k &= 0x07; 1445 atpdev->global_map[c] |= k; 1446 if ((setupdata[c][2] & 0x04) != 0) 1447 atpdev->global_map[c] |= 0x08; 1448 atpdev->host_id[c] = setupdata[c][0] & 0x07; 1449 } 1450 } 1451 1452 k = atp_readb_base(atpdev, 0x28) & 0x8f; 1453 k |= 0x10; 1454 atp_writeb_base(atpdev, 0x28, k); 1455 atp_writeb_pci(atpdev, 0, 1, 0x80); 1456 atp_writeb_pci(atpdev, 1, 1, 0x80); 1457 mdelay(100); 1458 atp_writeb_pci(atpdev, 0, 1, 0); 1459 atp_writeb_pci(atpdev, 1, 1, 0); 1460 mdelay(1000); 1461 atp_readb_io(atpdev, 0, 0x1b); 1462 atp_readb_io(atpdev, 0, 0x17); 1463 atp_readb_io(atpdev, 1, 0x1b); 1464 atp_readb_io(atpdev, 1, 0x17); 1465 1466 k = atpdev->host_id[0]; 1467 if (k > 7) 1468 k = (k & 0x07) | 0x40; 1469 atp_set_host_id(atpdev, 0, k); 1470 1471 k = atpdev->host_id[1]; 1472 if (k > 7) 1473 k = (k & 0x07) | 0x40; 1474 atp_set_host_id(atpdev, 1, k); 1475 1476 mdelay(600); /* this delay used to be called tscam_885() */ 1477 dev_info(&pdev->dev, "Scanning Channel A SCSI Device ...\n"); 1478 atp_is(atpdev, 0, true, atp_readb_io(atpdev, 0, 0x1b) >> 7); 1479 atp_writeb_io(atpdev, 0, 0x16, 0x80); 1480 dev_info(&pdev->dev, "Scanning Channel B SCSI Device ...\n"); 1481 atp_is(atpdev, 1, true, atp_readb_io(atpdev, 1, 0x1b) >> 7); 1482 atp_writeb_io(atpdev, 1, 0x16, 0x80); 1483 k = atp_readb_base(atpdev, 0x28) & 0xcf; 1484 k |= 0xc0; 1485 atp_writeb_base(atpdev, 0x28, k); 1486 k = atp_readb_base(atpdev, 0x1f) | 0x80; 1487 atp_writeb_base(atpdev, 0x1f, k); 1488 k = atp_readb_base(atpdev, 0x29) | 0x01; 1489 atp_writeb_base(atpdev, 0x29, k); 1490 shpnt->max_id = 16; 1491 shpnt->max_lun = (atpdev->global_map[0] & 0x07) + 1; 1492 shpnt->max_channel = 1; 1493 shpnt->this_id = atpdev->host_id[0]; 1494 } 1495 1496 /* return non-zero on detection */ 1497 static int atp870u_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1498 { 1499 struct Scsi_Host *shpnt = NULL; 1500 struct atp_unit *atpdev; 1501 int err; 1502 1503 if (ent->device == PCI_DEVICE_ID_ARTOP_AEC7610 && pdev->revision < 2) { 1504 dev_err(&pdev->dev, "ATP850S chips (AEC6710L/F cards) are not supported.\n"); 1505 return -ENODEV; 1506 } 1507 1508 err = pci_enable_device(pdev); 1509 if (err) 1510 goto fail; 1511 1512 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { 1513 printk(KERN_ERR "atp870u: DMA mask required but not available.\n"); 1514 err = -EIO; 1515 goto disable_device; 1516 } 1517 1518 err = pci_request_regions(pdev, "atp870u"); 1519 if (err) 1520 goto disable_device; 1521 pci_set_master(pdev); 1522 1523 err = -ENOMEM; 1524 shpnt = scsi_host_alloc(&atp870u_template, sizeof(struct atp_unit)); 1525 if (!shpnt) 1526 goto release_region; 1527 1528 atpdev = shost_priv(shpnt); 1529 1530 atpdev->host = shpnt; 1531 atpdev->pdev = pdev; 1532 pci_set_drvdata(pdev, atpdev); 1533 1534 shpnt->io_port = pci_resource_start(pdev, 0); 1535 shpnt->io_port &= 0xfffffff8; 1536 shpnt->n_io_port = pci_resource_len(pdev, 0); 1537 atpdev->baseport = shpnt->io_port; 1538 shpnt->unique_id = shpnt->io_port; 1539 shpnt->irq = pdev->irq; 1540 1541 err = atp870u_init_tables(shpnt); 1542 if (err) { 1543 dev_err(&pdev->dev, "Unable to allocate tables for Acard controller\n"); 1544 goto unregister; 1545 } 1546 1547 if (is880(atpdev)) 1548 atp880_init(shpnt); 1549 else if (is885(atpdev)) 1550 atp885_init(shpnt); 1551 else 1552 atp870_init(shpnt); 1553 1554 err = request_irq(shpnt->irq, atp870u_intr_handle, IRQF_SHARED, "atp870u", shpnt); 1555 if (err) { 1556 dev_err(&pdev->dev, "Unable to allocate IRQ %d.\n", shpnt->irq); 1557 goto free_tables; 1558 } 1559 1560 err = scsi_add_host(shpnt, &pdev->dev); 1561 if (err) 1562 goto scsi_add_fail; 1563 scsi_scan_host(shpnt); 1564 1565 return 0; 1566 1567 scsi_add_fail: 1568 free_irq(shpnt->irq, shpnt); 1569 free_tables: 1570 atp870u_free_tables(shpnt); 1571 unregister: 1572 scsi_host_put(shpnt); 1573 release_region: 1574 pci_release_regions(pdev); 1575 disable_device: 1576 pci_disable_device(pdev); 1577 fail: 1578 return err; 1579 } 1580 1581 /* The abort command does not leave the device in a clean state where 1582 it is available to be used again. Until this gets worked out, we will 1583 leave it commented out. */ 1584 1585 static int atp870u_abort(struct scsi_cmnd * SCpnt) 1586 { 1587 unsigned char j, k, c; 1588 struct scsi_cmnd *workrequ; 1589 struct atp_unit *dev; 1590 struct Scsi_Host *host; 1591 host = SCpnt->device->host; 1592 1593 dev = (struct atp_unit *)&host->hostdata; 1594 c = scmd_channel(SCpnt); 1595 printk(" atp870u: abort Channel = %x \n", c); 1596 printk("working=%x last_cmd=%x ", dev->working[c], dev->last_cmd[c]); 1597 printk(" quhdu=%x quendu=%x ", dev->quhd[c], dev->quend[c]); 1598 for (j = 0; j < 0x18; j++) { 1599 printk(" r%2x=%2x", j, atp_readb_io(dev, c, j)); 1600 } 1601 printk(" r1c=%2x", atp_readb_io(dev, c, 0x1c)); 1602 printk(" r1f=%2x in_snd=%2x ", atp_readb_io(dev, c, 0x1f), dev->in_snd[c]); 1603 printk(" d00=%2x", atp_readb_pci(dev, c, 0x00)); 1604 printk(" d02=%2x", atp_readb_pci(dev, c, 0x02)); 1605 for(j=0;j<16;j++) { 1606 if (dev->id[c][j].curr_req != NULL) { 1607 workrequ = dev->id[c][j].curr_req; 1608 printk("\n que cdb= "); 1609 for (k=0; k < workrequ->cmd_len; k++) { 1610 printk(" %2x ",workrequ->cmnd[k]); 1611 } 1612 printk(" last_lenu= %x ",(unsigned int)dev->id[c][j].last_len); 1613 } 1614 } 1615 return SUCCESS; 1616 } 1617 1618 static const char *atp870u_info(struct Scsi_Host *notused) 1619 { 1620 static char buffer[128]; 1621 1622 strcpy(buffer, "ACARD AEC-6710/6712/67160 PCI Ultra/W/LVD SCSI-3 Adapter Driver V2.6+ac "); 1623 1624 return buffer; 1625 } 1626 1627 static int atp870u_show_info(struct seq_file *m, struct Scsi_Host *HBAptr) 1628 { 1629 seq_puts(m, "ACARD AEC-671X Driver Version: 2.6+ac\n\n" 1630 "Adapter Configuration:\n"); 1631 seq_printf(m, " Base IO: %#.4lx\n", HBAptr->io_port); 1632 seq_printf(m, " IRQ: %d\n", HBAptr->irq); 1633 return 0; 1634 } 1635 1636 1637 static int atp870u_biosparam(struct scsi_device *disk, struct block_device *dev, 1638 sector_t capacity, int *ip) 1639 { 1640 int heads, sectors, cylinders; 1641 1642 heads = 64; 1643 sectors = 32; 1644 cylinders = (unsigned long)capacity / (heads * sectors); 1645 if (cylinders > 1024) { 1646 heads = 255; 1647 sectors = 63; 1648 cylinders = (unsigned long)capacity / (heads * sectors); 1649 } 1650 ip[0] = heads; 1651 ip[1] = sectors; 1652 ip[2] = cylinders; 1653 1654 return 0; 1655 } 1656 1657 static void atp870u_remove (struct pci_dev *pdev) 1658 { 1659 struct atp_unit *devext = pci_get_drvdata(pdev); 1660 struct Scsi_Host *pshost = devext->host; 1661 1662 1663 scsi_remove_host(pshost); 1664 free_irq(pshost->irq, pshost); 1665 pci_release_regions(pdev); 1666 pci_disable_device(pdev); 1667 atp870u_free_tables(pshost); 1668 scsi_host_put(pshost); 1669 } 1670 MODULE_LICENSE("GPL"); 1671 1672 static struct scsi_host_template atp870u_template = { 1673 .module = THIS_MODULE, 1674 .name = "atp870u" /* name */, 1675 .proc_name = "atp870u", 1676 .show_info = atp870u_show_info, 1677 .info = atp870u_info /* info */, 1678 .queuecommand = atp870u_queuecommand /* queuecommand */, 1679 .eh_abort_handler = atp870u_abort /* abort */, 1680 .bios_param = atp870u_biosparam /* biosparm */, 1681 .can_queue = qcnt /* can_queue */, 1682 .this_id = 7 /* SCSI ID */, 1683 .sg_tablesize = ATP870U_SCATTER /*SG_ALL*/ /*SG_NONE*/, 1684 .use_clustering = ENABLE_CLUSTERING, 1685 .max_sectors = ATP870U_MAX_SECTORS, 1686 }; 1687 1688 static struct pci_device_id atp870u_id_table[] = { 1689 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, ATP885_DEVID) }, 1690 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, ATP880_DEVID1) }, 1691 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, ATP880_DEVID2) }, 1692 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7610) }, 1693 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612UW) }, 1694 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612U) }, 1695 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612S) }, 1696 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612D) }, 1697 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_AEC7612SUW) }, 1698 { PCI_DEVICE(PCI_VENDOR_ID_ARTOP, PCI_DEVICE_ID_ARTOP_8060) }, 1699 { 0, }, 1700 }; 1701 1702 MODULE_DEVICE_TABLE(pci, atp870u_id_table); 1703 1704 static struct pci_driver atp870u_driver = { 1705 .id_table = atp870u_id_table, 1706 .name = "atp870u", 1707 .probe = atp870u_probe, 1708 .remove = atp870u_remove, 1709 }; 1710 1711 module_pci_driver(atp870u_driver); 1712 1713 static void atp_is(struct atp_unit *dev, unsigned char c, bool wide_chip, unsigned char lvdmode) 1714 { 1715 unsigned char i, j, k, rmb, n; 1716 unsigned short int m; 1717 static unsigned char mbuf[512]; 1718 static unsigned char satn[9] = { 0, 0, 0, 0, 0, 0, 0, 6, 6 }; 1719 static unsigned char inqd[9] = { 0x12, 0, 0, 0, 0x24, 0, 0, 0x24, 6 }; 1720 static unsigned char synn[6] = { 0x80, 1, 3, 1, 0x19, 0x0e }; 1721 unsigned char synu[6] = { 0x80, 1, 3, 1, 0x0a, 0x0e }; 1722 static unsigned char synw[6] = { 0x80, 1, 3, 1, 0x19, 0x0e }; 1723 static unsigned char synw_870[6] = { 0x80, 1, 3, 1, 0x0c, 0x07 }; 1724 unsigned char synuw[6] = { 0x80, 1, 3, 1, 0x0a, 0x0e }; 1725 static unsigned char wide[6] = { 0x80, 1, 2, 3, 1, 0 }; 1726 static unsigned char u3[9] = { 0x80, 1, 6, 4, 0x09, 00, 0x0e, 0x01, 0x02 }; 1727 1728 for (i = 0; i < 16; i++) { 1729 if (!wide_chip && (i > 7)) 1730 break; 1731 m = 1; 1732 m = m << i; 1733 if ((m & dev->active_id[c]) != 0) { 1734 continue; 1735 } 1736 if (i == dev->host_id[c]) { 1737 printk(KERN_INFO " ID: %2d Host Adapter\n", dev->host_id[c]); 1738 continue; 1739 } 1740 atp_writeb_io(dev, c, 0x1b, wide_chip ? 0x01 : 0x00); 1741 atp_writeb_io(dev, c, 1, 0x08); 1742 atp_writeb_io(dev, c, 2, 0x7f); 1743 atp_writeb_io(dev, c, 3, satn[0]); 1744 atp_writeb_io(dev, c, 4, satn[1]); 1745 atp_writeb_io(dev, c, 5, satn[2]); 1746 atp_writeb_io(dev, c, 6, satn[3]); 1747 atp_writeb_io(dev, c, 7, satn[4]); 1748 atp_writeb_io(dev, c, 8, satn[5]); 1749 atp_writeb_io(dev, c, 0x0f, 0); 1750 atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp); 1751 atp_writeb_io(dev, c, 0x12, 0); 1752 atp_writeb_io(dev, c, 0x13, satn[6]); 1753 atp_writeb_io(dev, c, 0x14, satn[7]); 1754 j = i; 1755 if ((j & 0x08) != 0) { 1756 j = (j & 0x07) | 0x40; 1757 } 1758 atp_writeb_io(dev, c, 0x15, j); 1759 atp_writeb_io(dev, c, 0x18, satn[8]); 1760 1761 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00) 1762 cpu_relax(); 1763 1764 if (atp_readb_io(dev, c, 0x17) != 0x11 && atp_readb_io(dev, c, 0x17) != 0x8e) 1765 continue; 1766 1767 while (atp_readb_io(dev, c, 0x17) != 0x8e) 1768 cpu_relax(); 1769 1770 dev->active_id[c] |= m; 1771 1772 atp_writeb_io(dev, c, 0x10, 0x30); 1773 if (is885(dev) || is880(dev)) 1774 atp_writeb_io(dev, c, 0x14, 0x00); 1775 else /* result of is870() merge - is this a bug? */ 1776 atp_writeb_io(dev, c, 0x04, 0x00); 1777 1778 phase_cmd: 1779 atp_writeb_io(dev, c, 0x18, 0x08); 1780 1781 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00) 1782 cpu_relax(); 1783 1784 j = atp_readb_io(dev, c, 0x17); 1785 if (j != 0x16) { 1786 atp_writeb_io(dev, c, 0x10, 0x41); 1787 goto phase_cmd; 1788 } 1789 sel_ok: 1790 atp_writeb_io(dev, c, 3, inqd[0]); 1791 atp_writeb_io(dev, c, 4, inqd[1]); 1792 atp_writeb_io(dev, c, 5, inqd[2]); 1793 atp_writeb_io(dev, c, 6, inqd[3]); 1794 atp_writeb_io(dev, c, 7, inqd[4]); 1795 atp_writeb_io(dev, c, 8, inqd[5]); 1796 atp_writeb_io(dev, c, 0x0f, 0); 1797 atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp); 1798 atp_writeb_io(dev, c, 0x12, 0); 1799 atp_writeb_io(dev, c, 0x13, inqd[6]); 1800 atp_writeb_io(dev, c, 0x14, inqd[7]); 1801 atp_writeb_io(dev, c, 0x18, inqd[8]); 1802 1803 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00) 1804 cpu_relax(); 1805 1806 if (atp_readb_io(dev, c, 0x17) != 0x11 && atp_readb_io(dev, c, 0x17) != 0x8e) 1807 continue; 1808 1809 while (atp_readb_io(dev, c, 0x17) != 0x8e) 1810 cpu_relax(); 1811 1812 if (wide_chip) 1813 atp_writeb_io(dev, c, 0x1b, 0x00); 1814 1815 atp_writeb_io(dev, c, 0x18, 0x08); 1816 j = 0; 1817 rd_inq_data: 1818 k = atp_readb_io(dev, c, 0x1f); 1819 if ((k & 0x01) != 0) { 1820 mbuf[j++] = atp_readb_io(dev, c, 0x19); 1821 goto rd_inq_data; 1822 } 1823 if ((k & 0x80) == 0) { 1824 goto rd_inq_data; 1825 } 1826 j = atp_readb_io(dev, c, 0x17); 1827 if (j == 0x16) { 1828 goto inq_ok; 1829 } 1830 atp_writeb_io(dev, c, 0x10, 0x46); 1831 atp_writeb_io(dev, c, 0x12, 0); 1832 atp_writeb_io(dev, c, 0x13, 0); 1833 atp_writeb_io(dev, c, 0x14, 0); 1834 atp_writeb_io(dev, c, 0x18, 0x08); 1835 1836 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00) 1837 cpu_relax(); 1838 1839 if (atp_readb_io(dev, c, 0x17) != 0x16) 1840 goto sel_ok; 1841 1842 inq_ok: 1843 mbuf[36] = 0; 1844 printk(KERN_INFO " ID: %2d %s\n", i, &mbuf[8]); 1845 dev->id[c][i].devtype = mbuf[0]; 1846 rmb = mbuf[1]; 1847 n = mbuf[7]; 1848 if (!wide_chip) 1849 goto not_wide; 1850 if ((mbuf[7] & 0x60) == 0) { 1851 goto not_wide; 1852 } 1853 if (is885(dev) || is880(dev)) { 1854 if ((i < 8) && ((dev->global_map[c] & 0x20) == 0)) 1855 goto not_wide; 1856 } else { /* result of is870() merge - is this a bug? */ 1857 if ((dev->global_map[c] & 0x20) == 0) 1858 goto not_wide; 1859 } 1860 if (lvdmode == 0) { 1861 goto chg_wide; 1862 } 1863 if (dev->sp[c][i] != 0x04) // force u2 1864 { 1865 goto chg_wide; 1866 } 1867 1868 atp_writeb_io(dev, c, 0x1b, 0x01); 1869 atp_writeb_io(dev, c, 3, satn[0]); 1870 atp_writeb_io(dev, c, 4, satn[1]); 1871 atp_writeb_io(dev, c, 5, satn[2]); 1872 atp_writeb_io(dev, c, 6, satn[3]); 1873 atp_writeb_io(dev, c, 7, satn[4]); 1874 atp_writeb_io(dev, c, 8, satn[5]); 1875 atp_writeb_io(dev, c, 0x0f, 0); 1876 atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp); 1877 atp_writeb_io(dev, c, 0x12, 0); 1878 atp_writeb_io(dev, c, 0x13, satn[6]); 1879 atp_writeb_io(dev, c, 0x14, satn[7]); 1880 atp_writeb_io(dev, c, 0x18, satn[8]); 1881 1882 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00) 1883 cpu_relax(); 1884 1885 if (atp_readb_io(dev, c, 0x17) != 0x11 && atp_readb_io(dev, c, 0x17) != 0x8e) 1886 continue; 1887 1888 while (atp_readb_io(dev, c, 0x17) != 0x8e) 1889 cpu_relax(); 1890 1891 try_u3: 1892 j = 0; 1893 atp_writeb_io(dev, c, 0x14, 0x09); 1894 atp_writeb_io(dev, c, 0x18, 0x20); 1895 1896 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) { 1897 if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0) 1898 atp_writeb_io(dev, c, 0x19, u3[j++]); 1899 cpu_relax(); 1900 } 1901 1902 while ((atp_readb_io(dev, c, 0x17) & 0x80) == 0x00) 1903 cpu_relax(); 1904 1905 j = atp_readb_io(dev, c, 0x17) & 0x0f; 1906 if (j == 0x0f) { 1907 goto u3p_in; 1908 } 1909 if (j == 0x0a) { 1910 goto u3p_cmd; 1911 } 1912 if (j == 0x0e) { 1913 goto try_u3; 1914 } 1915 continue; 1916 u3p_out: 1917 atp_writeb_io(dev, c, 0x18, 0x20); 1918 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) { 1919 if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0) 1920 atp_writeb_io(dev, c, 0x19, 0); 1921 cpu_relax(); 1922 } 1923 j = atp_readb_io(dev, c, 0x17) & 0x0f; 1924 if (j == 0x0f) { 1925 goto u3p_in; 1926 } 1927 if (j == 0x0a) { 1928 goto u3p_cmd; 1929 } 1930 if (j == 0x0e) { 1931 goto u3p_out; 1932 } 1933 continue; 1934 u3p_in: 1935 atp_writeb_io(dev, c, 0x14, 0x09); 1936 atp_writeb_io(dev, c, 0x18, 0x20); 1937 k = 0; 1938 u3p_in1: 1939 j = atp_readb_io(dev, c, 0x1f); 1940 if ((j & 0x01) != 0) { 1941 mbuf[k++] = atp_readb_io(dev, c, 0x19); 1942 goto u3p_in1; 1943 } 1944 if ((j & 0x80) == 0x00) { 1945 goto u3p_in1; 1946 } 1947 j = atp_readb_io(dev, c, 0x17) & 0x0f; 1948 if (j == 0x0f) { 1949 goto u3p_in; 1950 } 1951 if (j == 0x0a) { 1952 goto u3p_cmd; 1953 } 1954 if (j == 0x0e) { 1955 goto u3p_out; 1956 } 1957 continue; 1958 u3p_cmd: 1959 atp_writeb_io(dev, c, 0x10, 0x30); 1960 atp_writeb_io(dev, c, 0x14, 0x00); 1961 atp_writeb_io(dev, c, 0x18, 0x08); 1962 1963 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00); 1964 1965 j = atp_readb_io(dev, c, 0x17); 1966 if (j != 0x16) { 1967 if (j == 0x4e) { 1968 goto u3p_out; 1969 } 1970 continue; 1971 } 1972 if (mbuf[0] != 0x01) { 1973 goto chg_wide; 1974 } 1975 if (mbuf[1] != 0x06) { 1976 goto chg_wide; 1977 } 1978 if (mbuf[2] != 0x04) { 1979 goto chg_wide; 1980 } 1981 if (mbuf[3] == 0x09) { 1982 m = 1; 1983 m = m << i; 1984 dev->wide_id[c] |= m; 1985 dev->id[c][i].devsp = 0xce; 1986 #ifdef ED_DBGP 1987 printk("dev->id[%2d][%2d].devsp = %2x\n",c,i,dev->id[c][i].devsp); 1988 #endif 1989 continue; 1990 } 1991 chg_wide: 1992 atp_writeb_io(dev, c, 0x1b, 0x01); 1993 atp_writeb_io(dev, c, 3, satn[0]); 1994 atp_writeb_io(dev, c, 4, satn[1]); 1995 atp_writeb_io(dev, c, 5, satn[2]); 1996 atp_writeb_io(dev, c, 6, satn[3]); 1997 atp_writeb_io(dev, c, 7, satn[4]); 1998 atp_writeb_io(dev, c, 8, satn[5]); 1999 atp_writeb_io(dev, c, 0x0f, 0); 2000 atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp); 2001 atp_writeb_io(dev, c, 0x12, 0); 2002 atp_writeb_io(dev, c, 0x13, satn[6]); 2003 atp_writeb_io(dev, c, 0x14, satn[7]); 2004 atp_writeb_io(dev, c, 0x18, satn[8]); 2005 2006 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00) 2007 cpu_relax(); 2008 2009 if (atp_readb_io(dev, c, 0x17) != 0x11 && atp_readb_io(dev, c, 0x17) != 0x8e) 2010 continue; 2011 2012 while (atp_readb_io(dev, c, 0x17) != 0x8e) 2013 cpu_relax(); 2014 2015 try_wide: 2016 j = 0; 2017 atp_writeb_io(dev, c, 0x14, 0x05); 2018 atp_writeb_io(dev, c, 0x18, 0x20); 2019 2020 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) { 2021 if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0) 2022 atp_writeb_io(dev, c, 0x19, wide[j++]); 2023 cpu_relax(); 2024 } 2025 2026 while ((atp_readb_io(dev, c, 0x17) & 0x80) == 0x00) 2027 cpu_relax(); 2028 2029 j = atp_readb_io(dev, c, 0x17) & 0x0f; 2030 if (j == 0x0f) { 2031 goto widep_in; 2032 } 2033 if (j == 0x0a) { 2034 goto widep_cmd; 2035 } 2036 if (j == 0x0e) { 2037 goto try_wide; 2038 } 2039 continue; 2040 widep_out: 2041 atp_writeb_io(dev, c, 0x18, 0x20); 2042 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) { 2043 if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0) 2044 atp_writeb_io(dev, c, 0x19, 0); 2045 cpu_relax(); 2046 } 2047 j = atp_readb_io(dev, c, 0x17) & 0x0f; 2048 if (j == 0x0f) { 2049 goto widep_in; 2050 } 2051 if (j == 0x0a) { 2052 goto widep_cmd; 2053 } 2054 if (j == 0x0e) { 2055 goto widep_out; 2056 } 2057 continue; 2058 widep_in: 2059 atp_writeb_io(dev, c, 0x14, 0xff); 2060 atp_writeb_io(dev, c, 0x18, 0x20); 2061 k = 0; 2062 widep_in1: 2063 j = atp_readb_io(dev, c, 0x1f); 2064 if ((j & 0x01) != 0) { 2065 mbuf[k++] = atp_readb_io(dev, c, 0x19); 2066 goto widep_in1; 2067 } 2068 if ((j & 0x80) == 0x00) { 2069 goto widep_in1; 2070 } 2071 j = atp_readb_io(dev, c, 0x17) & 0x0f; 2072 if (j == 0x0f) { 2073 goto widep_in; 2074 } 2075 if (j == 0x0a) { 2076 goto widep_cmd; 2077 } 2078 if (j == 0x0e) { 2079 goto widep_out; 2080 } 2081 continue; 2082 widep_cmd: 2083 atp_writeb_io(dev, c, 0x10, 0x30); 2084 atp_writeb_io(dev, c, 0x14, 0x00); 2085 atp_writeb_io(dev, c, 0x18, 0x08); 2086 2087 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00) 2088 cpu_relax(); 2089 2090 j = atp_readb_io(dev, c, 0x17); 2091 if (j != 0x16) { 2092 if (j == 0x4e) { 2093 goto widep_out; 2094 } 2095 continue; 2096 } 2097 if (mbuf[0] != 0x01) { 2098 goto not_wide; 2099 } 2100 if (mbuf[1] != 0x02) { 2101 goto not_wide; 2102 } 2103 if (mbuf[2] != 0x03) { 2104 goto not_wide; 2105 } 2106 if (mbuf[3] != 0x01) { 2107 goto not_wide; 2108 } 2109 m = 1; 2110 m = m << i; 2111 dev->wide_id[c] |= m; 2112 not_wide: 2113 if ((dev->id[c][i].devtype == 0x00) || (dev->id[c][i].devtype == 0x07) || ((dev->id[c][i].devtype == 0x05) && ((n & 0x10) != 0))) { 2114 m = 1; 2115 m = m << i; 2116 if ((dev->async[c] & m) != 0) { 2117 goto set_sync; 2118 } 2119 } 2120 continue; 2121 set_sync: 2122 if ((!is885(dev) && !is880(dev)) || (dev->sp[c][i] == 0x02)) { 2123 synu[4] = 0x0c; 2124 synuw[4] = 0x0c; 2125 } else { 2126 if (dev->sp[c][i] >= 0x03) { 2127 synu[4] = 0x0a; 2128 synuw[4] = 0x0a; 2129 } 2130 } 2131 j = 0; 2132 if ((m & dev->wide_id[c]) != 0) { 2133 j |= 0x01; 2134 } 2135 atp_writeb_io(dev, c, 0x1b, j); 2136 atp_writeb_io(dev, c, 3, satn[0]); 2137 atp_writeb_io(dev, c, 4, satn[1]); 2138 atp_writeb_io(dev, c, 5, satn[2]); 2139 atp_writeb_io(dev, c, 6, satn[3]); 2140 atp_writeb_io(dev, c, 7, satn[4]); 2141 atp_writeb_io(dev, c, 8, satn[5]); 2142 atp_writeb_io(dev, c, 0x0f, 0); 2143 atp_writeb_io(dev, c, 0x11, dev->id[c][i].devsp); 2144 atp_writeb_io(dev, c, 0x12, 0); 2145 atp_writeb_io(dev, c, 0x13, satn[6]); 2146 atp_writeb_io(dev, c, 0x14, satn[7]); 2147 atp_writeb_io(dev, c, 0x18, satn[8]); 2148 2149 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00) 2150 cpu_relax(); 2151 2152 if (atp_readb_io(dev, c, 0x17) != 0x11 && atp_readb_io(dev, c, 0x17) != 0x8e) 2153 continue; 2154 2155 while (atp_readb_io(dev, c, 0x17) != 0x8e) 2156 cpu_relax(); 2157 2158 try_sync: 2159 j = 0; 2160 atp_writeb_io(dev, c, 0x14, 0x06); 2161 atp_writeb_io(dev, c, 0x18, 0x20); 2162 2163 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0) { 2164 if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0) { 2165 if ((m & dev->wide_id[c]) != 0) { 2166 if (is885(dev) || is880(dev)) { 2167 if ((m & dev->ultra_map[c]) != 0) { 2168 atp_writeb_io(dev, c, 0x19, synuw[j++]); 2169 } else { 2170 atp_writeb_io(dev, c, 0x19, synw[j++]); 2171 } 2172 } else 2173 atp_writeb_io(dev, c, 0x19, synw_870[j++]); 2174 } else { 2175 if ((m & dev->ultra_map[c]) != 0) { 2176 atp_writeb_io(dev, c, 0x19, synu[j++]); 2177 } else { 2178 atp_writeb_io(dev, c, 0x19, synn[j++]); 2179 } 2180 } 2181 } 2182 } 2183 2184 while ((atp_readb_io(dev, c, 0x17) & 0x80) == 0x00) 2185 cpu_relax(); 2186 2187 j = atp_readb_io(dev, c, 0x17) & 0x0f; 2188 if (j == 0x0f) { 2189 goto phase_ins; 2190 } 2191 if (j == 0x0a) { 2192 goto phase_cmds; 2193 } 2194 if (j == 0x0e) { 2195 goto try_sync; 2196 } 2197 continue; 2198 phase_outs: 2199 atp_writeb_io(dev, c, 0x18, 0x20); 2200 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00) { 2201 if ((atp_readb_io(dev, c, 0x1f) & 0x01) != 0x00) 2202 atp_writeb_io(dev, c, 0x19, 0x00); 2203 cpu_relax(); 2204 } 2205 j = atp_readb_io(dev, c, 0x17); 2206 if (j == 0x85) { 2207 goto tar_dcons; 2208 } 2209 j &= 0x0f; 2210 if (j == 0x0f) { 2211 goto phase_ins; 2212 } 2213 if (j == 0x0a) { 2214 goto phase_cmds; 2215 } 2216 if (j == 0x0e) { 2217 goto phase_outs; 2218 } 2219 continue; 2220 phase_ins: 2221 if (is885(dev) || is880(dev)) 2222 atp_writeb_io(dev, c, 0x14, 0x06); 2223 else 2224 atp_writeb_io(dev, c, 0x14, 0xff); 2225 atp_writeb_io(dev, c, 0x18, 0x20); 2226 k = 0; 2227 phase_ins1: 2228 j = atp_readb_io(dev, c, 0x1f); 2229 if ((j & 0x01) != 0x00) { 2230 mbuf[k++] = atp_readb_io(dev, c, 0x19); 2231 goto phase_ins1; 2232 } 2233 if ((j & 0x80) == 0x00) { 2234 goto phase_ins1; 2235 } 2236 2237 while ((atp_readb_io(dev, c, 0x17) & 0x80) == 0x00); 2238 2239 j = atp_readb_io(dev, c, 0x17); 2240 if (j == 0x85) { 2241 goto tar_dcons; 2242 } 2243 j &= 0x0f; 2244 if (j == 0x0f) { 2245 goto phase_ins; 2246 } 2247 if (j == 0x0a) { 2248 goto phase_cmds; 2249 } 2250 if (j == 0x0e) { 2251 goto phase_outs; 2252 } 2253 continue; 2254 phase_cmds: 2255 atp_writeb_io(dev, c, 0x10, 0x30); 2256 tar_dcons: 2257 atp_writeb_io(dev, c, 0x14, 0x00); 2258 atp_writeb_io(dev, c, 0x18, 0x08); 2259 2260 while ((atp_readb_io(dev, c, 0x1f) & 0x80) == 0x00) 2261 cpu_relax(); 2262 2263 j = atp_readb_io(dev, c, 0x17); 2264 if (j != 0x16) { 2265 continue; 2266 } 2267 if (mbuf[0] != 0x01) { 2268 continue; 2269 } 2270 if (mbuf[1] != 0x03) { 2271 continue; 2272 } 2273 if (mbuf[4] == 0x00) { 2274 continue; 2275 } 2276 if (mbuf[3] > 0x64) { 2277 continue; 2278 } 2279 if (is885(dev) || is880(dev)) { 2280 if (mbuf[4] > 0x0e) { 2281 mbuf[4] = 0x0e; 2282 } 2283 } else { 2284 if (mbuf[4] > 0x0c) { 2285 mbuf[4] = 0x0c; 2286 } 2287 } 2288 dev->id[c][i].devsp = mbuf[4]; 2289 if (is885(dev) || is880(dev)) 2290 if (mbuf[3] < 0x0c) { 2291 j = 0xb0; 2292 goto set_syn_ok; 2293 } 2294 if ((mbuf[3] < 0x0d) && (rmb == 0)) { 2295 j = 0xa0; 2296 goto set_syn_ok; 2297 } 2298 if (mbuf[3] < 0x1a) { 2299 j = 0x20; 2300 goto set_syn_ok; 2301 } 2302 if (mbuf[3] < 0x33) { 2303 j = 0x40; 2304 goto set_syn_ok; 2305 } 2306 if (mbuf[3] < 0x4c) { 2307 j = 0x50; 2308 goto set_syn_ok; 2309 } 2310 j = 0x60; 2311 set_syn_ok: 2312 dev->id[c][i].devsp = (dev->id[c][i].devsp & 0x0f) | j; 2313 #ifdef ED_DBGP 2314 printk("dev->id[%2d][%2d].devsp = %2x\n",c,i,dev->id[c][i].devsp); 2315 #endif 2316 } 2317 } 2318