1 /* 2 ******************************************************************************* 3 ** O.S : Linux 4 ** FILE NAME : arcmsr_hba.c 5 ** BY : Nick Cheng, C.L. Huang 6 ** Description: SCSI RAID Device Driver for Areca RAID Controller 7 ******************************************************************************* 8 ** Copyright (C) 2002 - 2014, Areca Technology Corporation All rights reserved 9 ** 10 ** Web site: www.areca.com.tw 11 ** E-mail: support@areca.com.tw 12 ** 13 ** This program is free software; you can redistribute it and/or modify 14 ** it under the terms of the GNU General Public License version 2 as 15 ** published by the Free Software Foundation. 16 ** This program is distributed in the hope that it will be useful, 17 ** but WITHOUT ANY WARRANTY; without even the implied warranty of 18 ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 ** GNU General Public License for more details. 20 ******************************************************************************* 21 ** Redistribution and use in source and binary forms, with or without 22 ** modification, are permitted provided that the following conditions 23 ** are met: 24 ** 1. Redistributions of source code must retain the above copyright 25 ** notice, this list of conditions and the following disclaimer. 26 ** 2. Redistributions in binary form must reproduce the above copyright 27 ** notice, this list of conditions and the following disclaimer in the 28 ** documentation and/or other materials provided with the distribution. 29 ** 3. The name of the author may not be used to endorse or promote products 30 ** derived from this software without specific prior written permission. 31 ** 32 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 33 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 34 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 35 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 36 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT 37 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 38 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 39 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 41 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 ******************************************************************************* 43 ** For history of changes, see Documentation/scsi/ChangeLog.arcmsr 44 ** Firmware Specification, see Documentation/scsi/arcmsr_spec.txt 45 ******************************************************************************* 46 */ 47 #include <linux/module.h> 48 #include <linux/reboot.h> 49 #include <linux/spinlock.h> 50 #include <linux/pci_ids.h> 51 #include <linux/interrupt.h> 52 #include <linux/moduleparam.h> 53 #include <linux/errno.h> 54 #include <linux/types.h> 55 #include <linux/delay.h> 56 #include <linux/dma-mapping.h> 57 #include <linux/timer.h> 58 #include <linux/slab.h> 59 #include <linux/pci.h> 60 #include <linux/aer.h> 61 #include <linux/circ_buf.h> 62 #include <asm/dma.h> 63 #include <asm/io.h> 64 #include <linux/uaccess.h> 65 #include <scsi/scsi_host.h> 66 #include <scsi/scsi.h> 67 #include <scsi/scsi_cmnd.h> 68 #include <scsi/scsi_tcq.h> 69 #include <scsi/scsi_device.h> 70 #include <scsi/scsi_transport.h> 71 #include <scsi/scsicam.h> 72 #include "arcmsr.h" 73 MODULE_AUTHOR("Nick Cheng, C.L. Huang <support@areca.com.tw>"); 74 MODULE_DESCRIPTION("Areca ARC11xx/12xx/16xx/188x SAS/SATA RAID Controller Driver"); 75 MODULE_LICENSE("Dual BSD/GPL"); 76 MODULE_VERSION(ARCMSR_DRIVER_VERSION); 77 78 static int msix_enable = 1; 79 module_param(msix_enable, int, S_IRUGO); 80 MODULE_PARM_DESC(msix_enable, "Enable MSI-X interrupt(0 ~ 1), msix_enable=1(enable), =0(disable)"); 81 82 static int msi_enable = 1; 83 module_param(msi_enable, int, S_IRUGO); 84 MODULE_PARM_DESC(msi_enable, "Enable MSI interrupt(0 ~ 1), msi_enable=1(enable), =0(disable)"); 85 86 static int host_can_queue = ARCMSR_DEFAULT_OUTSTANDING_CMD; 87 module_param(host_can_queue, int, S_IRUGO); 88 MODULE_PARM_DESC(host_can_queue, " adapter queue depth(32 ~ 1024), default is 128"); 89 90 static int cmd_per_lun = ARCMSR_DEFAULT_CMD_PERLUN; 91 module_param(cmd_per_lun, int, S_IRUGO); 92 MODULE_PARM_DESC(cmd_per_lun, " device queue depth(1 ~ 128), default is 32"); 93 94 static int dma_mask_64 = 0; 95 module_param(dma_mask_64, int, S_IRUGO); 96 MODULE_PARM_DESC(dma_mask_64, " set DMA mask to 64 bits(0 ~ 1), dma_mask_64=1(64 bits), =0(32 bits)"); 97 98 static int set_date_time = 0; 99 module_param(set_date_time, int, S_IRUGO); 100 MODULE_PARM_DESC(set_date_time, " send date, time to iop(0 ~ 1), set_date_time=1(enable), default(=0) is disable"); 101 102 #define ARCMSR_SLEEPTIME 10 103 #define ARCMSR_RETRYCOUNT 12 104 105 static wait_queue_head_t wait_q; 106 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, 107 struct scsi_cmnd *cmd); 108 static int arcmsr_iop_confirm(struct AdapterControlBlock *acb); 109 static int arcmsr_abort(struct scsi_cmnd *); 110 static int arcmsr_bus_reset(struct scsi_cmnd *); 111 static int arcmsr_bios_param(struct scsi_device *sdev, 112 struct block_device *bdev, sector_t capacity, int *info); 113 static int arcmsr_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd); 114 static int arcmsr_probe(struct pci_dev *pdev, 115 const struct pci_device_id *id); 116 static int arcmsr_suspend(struct pci_dev *pdev, pm_message_t state); 117 static int arcmsr_resume(struct pci_dev *pdev); 118 static void arcmsr_remove(struct pci_dev *pdev); 119 static void arcmsr_shutdown(struct pci_dev *pdev); 120 static void arcmsr_iop_init(struct AdapterControlBlock *acb); 121 static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb); 122 static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb); 123 static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb, 124 u32 intmask_org); 125 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb); 126 static void arcmsr_hbaA_flush_cache(struct AdapterControlBlock *acb); 127 static void arcmsr_hbaB_flush_cache(struct AdapterControlBlock *acb); 128 static void arcmsr_request_device_map(struct timer_list *t); 129 static void arcmsr_message_isr_bh_fn(struct work_struct *work); 130 static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb); 131 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb); 132 static void arcmsr_hbaC_message_isr(struct AdapterControlBlock *pACB); 133 static void arcmsr_hbaD_message_isr(struct AdapterControlBlock *acb); 134 static void arcmsr_hbaE_message_isr(struct AdapterControlBlock *acb); 135 static void arcmsr_hbaE_postqueue_isr(struct AdapterControlBlock *acb); 136 static void arcmsr_hardware_reset(struct AdapterControlBlock *acb); 137 static const char *arcmsr_info(struct Scsi_Host *); 138 static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb); 139 static void arcmsr_free_irq(struct pci_dev *, struct AdapterControlBlock *); 140 static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb); 141 static void arcmsr_set_iop_datetime(struct timer_list *); 142 static int arcmsr_adjust_disk_queue_depth(struct scsi_device *sdev, int queue_depth) 143 { 144 if (queue_depth > ARCMSR_MAX_CMD_PERLUN) 145 queue_depth = ARCMSR_MAX_CMD_PERLUN; 146 return scsi_change_queue_depth(sdev, queue_depth); 147 } 148 149 static struct scsi_host_template arcmsr_scsi_host_template = { 150 .module = THIS_MODULE, 151 .name = "Areca SAS/SATA RAID driver", 152 .info = arcmsr_info, 153 .queuecommand = arcmsr_queue_command, 154 .eh_abort_handler = arcmsr_abort, 155 .eh_bus_reset_handler = arcmsr_bus_reset, 156 .bios_param = arcmsr_bios_param, 157 .change_queue_depth = arcmsr_adjust_disk_queue_depth, 158 .can_queue = ARCMSR_DEFAULT_OUTSTANDING_CMD, 159 .this_id = ARCMSR_SCSI_INITIATOR_ID, 160 .sg_tablesize = ARCMSR_DEFAULT_SG_ENTRIES, 161 .max_sectors = ARCMSR_MAX_XFER_SECTORS_C, 162 .cmd_per_lun = ARCMSR_DEFAULT_CMD_PERLUN, 163 .shost_attrs = arcmsr_host_attrs, 164 .no_write_same = 1, 165 }; 166 167 static struct pci_device_id arcmsr_device_id_table[] = { 168 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1110), 169 .driver_data = ACB_ADAPTER_TYPE_A}, 170 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1120), 171 .driver_data = ACB_ADAPTER_TYPE_A}, 172 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1130), 173 .driver_data = ACB_ADAPTER_TYPE_A}, 174 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1160), 175 .driver_data = ACB_ADAPTER_TYPE_A}, 176 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1170), 177 .driver_data = ACB_ADAPTER_TYPE_A}, 178 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1200), 179 .driver_data = ACB_ADAPTER_TYPE_B}, 180 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1201), 181 .driver_data = ACB_ADAPTER_TYPE_B}, 182 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1202), 183 .driver_data = ACB_ADAPTER_TYPE_B}, 184 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1203), 185 .driver_data = ACB_ADAPTER_TYPE_B}, 186 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1210), 187 .driver_data = ACB_ADAPTER_TYPE_A}, 188 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1214), 189 .driver_data = ACB_ADAPTER_TYPE_D}, 190 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1220), 191 .driver_data = ACB_ADAPTER_TYPE_A}, 192 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1230), 193 .driver_data = ACB_ADAPTER_TYPE_A}, 194 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1260), 195 .driver_data = ACB_ADAPTER_TYPE_A}, 196 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1270), 197 .driver_data = ACB_ADAPTER_TYPE_A}, 198 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1280), 199 .driver_data = ACB_ADAPTER_TYPE_A}, 200 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1380), 201 .driver_data = ACB_ADAPTER_TYPE_A}, 202 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1381), 203 .driver_data = ACB_ADAPTER_TYPE_A}, 204 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1680), 205 .driver_data = ACB_ADAPTER_TYPE_A}, 206 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1681), 207 .driver_data = ACB_ADAPTER_TYPE_A}, 208 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1880), 209 .driver_data = ACB_ADAPTER_TYPE_C}, 210 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1884), 211 .driver_data = ACB_ADAPTER_TYPE_E}, 212 {0, 0}, /* Terminating entry */ 213 }; 214 MODULE_DEVICE_TABLE(pci, arcmsr_device_id_table); 215 216 static struct pci_driver arcmsr_pci_driver = { 217 .name = "arcmsr", 218 .id_table = arcmsr_device_id_table, 219 .probe = arcmsr_probe, 220 .remove = arcmsr_remove, 221 .suspend = arcmsr_suspend, 222 .resume = arcmsr_resume, 223 .shutdown = arcmsr_shutdown, 224 }; 225 /* 226 **************************************************************************** 227 **************************************************************************** 228 */ 229 230 static void arcmsr_free_io_queue(struct AdapterControlBlock *acb) 231 { 232 switch (acb->adapter_type) { 233 case ACB_ADAPTER_TYPE_B: 234 case ACB_ADAPTER_TYPE_D: 235 case ACB_ADAPTER_TYPE_E: { 236 dma_free_coherent(&acb->pdev->dev, acb->ioqueue_size, 237 acb->dma_coherent2, acb->dma_coherent_handle2); 238 break; 239 } 240 } 241 } 242 243 static bool arcmsr_remap_pciregion(struct AdapterControlBlock *acb) 244 { 245 struct pci_dev *pdev = acb->pdev; 246 switch (acb->adapter_type){ 247 case ACB_ADAPTER_TYPE_A:{ 248 acb->pmuA = ioremap(pci_resource_start(pdev,0), pci_resource_len(pdev,0)); 249 if (!acb->pmuA) { 250 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no); 251 return false; 252 } 253 break; 254 } 255 case ACB_ADAPTER_TYPE_B:{ 256 void __iomem *mem_base0, *mem_base1; 257 mem_base0 = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0)); 258 if (!mem_base0) { 259 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no); 260 return false; 261 } 262 mem_base1 = ioremap(pci_resource_start(pdev, 2), pci_resource_len(pdev, 2)); 263 if (!mem_base1) { 264 iounmap(mem_base0); 265 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no); 266 return false; 267 } 268 acb->mem_base0 = mem_base0; 269 acb->mem_base1 = mem_base1; 270 break; 271 } 272 case ACB_ADAPTER_TYPE_C:{ 273 acb->pmuC = ioremap_nocache(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1)); 274 if (!acb->pmuC) { 275 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no); 276 return false; 277 } 278 if (readl(&acb->pmuC->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 279 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &acb->pmuC->outbound_doorbell_clear);/*clear interrupt*/ 280 return true; 281 } 282 break; 283 } 284 case ACB_ADAPTER_TYPE_D: { 285 void __iomem *mem_base0; 286 unsigned long addr, range, flags; 287 288 addr = (unsigned long)pci_resource_start(pdev, 0); 289 range = pci_resource_len(pdev, 0); 290 flags = pci_resource_flags(pdev, 0); 291 mem_base0 = ioremap(addr, range); 292 if (!mem_base0) { 293 pr_notice("arcmsr%d: memory mapping region fail\n", 294 acb->host->host_no); 295 return false; 296 } 297 acb->mem_base0 = mem_base0; 298 break; 299 } 300 case ACB_ADAPTER_TYPE_E: { 301 acb->pmuE = ioremap(pci_resource_start(pdev, 1), 302 pci_resource_len(pdev, 1)); 303 if (!acb->pmuE) { 304 pr_notice("arcmsr%d: memory mapping region fail \n", 305 acb->host->host_no); 306 return false; 307 } 308 writel(0, &acb->pmuE->host_int_status); /*clear interrupt*/ 309 writel(ARCMSR_HBEMU_DOORBELL_SYNC, &acb->pmuE->iobound_doorbell); /* synchronize doorbell to 0 */ 310 acb->in_doorbell = 0; 311 acb->out_doorbell = 0; 312 break; 313 } 314 } 315 return true; 316 } 317 318 static void arcmsr_unmap_pciregion(struct AdapterControlBlock *acb) 319 { 320 switch (acb->adapter_type) { 321 case ACB_ADAPTER_TYPE_A:{ 322 iounmap(acb->pmuA); 323 } 324 break; 325 case ACB_ADAPTER_TYPE_B:{ 326 iounmap(acb->mem_base0); 327 iounmap(acb->mem_base1); 328 } 329 330 break; 331 case ACB_ADAPTER_TYPE_C:{ 332 iounmap(acb->pmuC); 333 } 334 break; 335 case ACB_ADAPTER_TYPE_D: 336 iounmap(acb->mem_base0); 337 break; 338 case ACB_ADAPTER_TYPE_E: 339 iounmap(acb->pmuE); 340 break; 341 } 342 } 343 344 static irqreturn_t arcmsr_do_interrupt(int irq, void *dev_id) 345 { 346 irqreturn_t handle_state; 347 struct AdapterControlBlock *acb = dev_id; 348 349 handle_state = arcmsr_interrupt(acb); 350 return handle_state; 351 } 352 353 static int arcmsr_bios_param(struct scsi_device *sdev, 354 struct block_device *bdev, sector_t capacity, int *geom) 355 { 356 int ret, heads, sectors, cylinders, total_capacity; 357 unsigned char *buffer;/* return copy of block device's partition table */ 358 359 buffer = scsi_bios_ptable(bdev); 360 if (buffer) { 361 ret = scsi_partsize(buffer, capacity, &geom[2], &geom[0], &geom[1]); 362 kfree(buffer); 363 if (ret != -1) 364 return ret; 365 } 366 total_capacity = capacity; 367 heads = 64; 368 sectors = 32; 369 cylinders = total_capacity / (heads * sectors); 370 if (cylinders > 1024) { 371 heads = 255; 372 sectors = 63; 373 cylinders = total_capacity / (heads * sectors); 374 } 375 geom[0] = heads; 376 geom[1] = sectors; 377 geom[2] = cylinders; 378 return 0; 379 } 380 381 static uint8_t arcmsr_hbaA_wait_msgint_ready(struct AdapterControlBlock *acb) 382 { 383 struct MessageUnit_A __iomem *reg = acb->pmuA; 384 int i; 385 386 for (i = 0; i < 2000; i++) { 387 if (readl(®->outbound_intstatus) & 388 ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 389 writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT, 390 ®->outbound_intstatus); 391 return true; 392 } 393 msleep(10); 394 } /* max 20 seconds */ 395 396 return false; 397 } 398 399 static uint8_t arcmsr_hbaB_wait_msgint_ready(struct AdapterControlBlock *acb) 400 { 401 struct MessageUnit_B *reg = acb->pmuB; 402 int i; 403 404 for (i = 0; i < 2000; i++) { 405 if (readl(reg->iop2drv_doorbell) 406 & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 407 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, 408 reg->iop2drv_doorbell); 409 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, 410 reg->drv2iop_doorbell); 411 return true; 412 } 413 msleep(10); 414 } /* max 20 seconds */ 415 416 return false; 417 } 418 419 static uint8_t arcmsr_hbaC_wait_msgint_ready(struct AdapterControlBlock *pACB) 420 { 421 struct MessageUnit_C __iomem *phbcmu = pACB->pmuC; 422 int i; 423 424 for (i = 0; i < 2000; i++) { 425 if (readl(&phbcmu->outbound_doorbell) 426 & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 427 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, 428 &phbcmu->outbound_doorbell_clear); /*clear interrupt*/ 429 return true; 430 } 431 msleep(10); 432 } /* max 20 seconds */ 433 434 return false; 435 } 436 437 static bool arcmsr_hbaD_wait_msgint_ready(struct AdapterControlBlock *pACB) 438 { 439 struct MessageUnit_D *reg = pACB->pmuD; 440 int i; 441 442 for (i = 0; i < 2000; i++) { 443 if (readl(reg->outbound_doorbell) 444 & ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE) { 445 writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE, 446 reg->outbound_doorbell); 447 return true; 448 } 449 msleep(10); 450 } /* max 20 seconds */ 451 return false; 452 } 453 454 static bool arcmsr_hbaE_wait_msgint_ready(struct AdapterControlBlock *pACB) 455 { 456 int i; 457 uint32_t read_doorbell; 458 struct MessageUnit_E __iomem *phbcmu = pACB->pmuE; 459 460 for (i = 0; i < 2000; i++) { 461 read_doorbell = readl(&phbcmu->iobound_doorbell); 462 if ((read_doorbell ^ pACB->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) { 463 writel(0, &phbcmu->host_int_status); /*clear interrupt*/ 464 pACB->in_doorbell = read_doorbell; 465 return true; 466 } 467 msleep(10); 468 } /* max 20 seconds */ 469 return false; 470 } 471 472 static void arcmsr_hbaA_flush_cache(struct AdapterControlBlock *acb) 473 { 474 struct MessageUnit_A __iomem *reg = acb->pmuA; 475 int retry_count = 30; 476 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, ®->inbound_msgaddr0); 477 do { 478 if (arcmsr_hbaA_wait_msgint_ready(acb)) 479 break; 480 else { 481 retry_count--; 482 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \ 483 timeout, retry count down = %d \n", acb->host->host_no, retry_count); 484 } 485 } while (retry_count != 0); 486 } 487 488 static void arcmsr_hbaB_flush_cache(struct AdapterControlBlock *acb) 489 { 490 struct MessageUnit_B *reg = acb->pmuB; 491 int retry_count = 30; 492 writel(ARCMSR_MESSAGE_FLUSH_CACHE, reg->drv2iop_doorbell); 493 do { 494 if (arcmsr_hbaB_wait_msgint_ready(acb)) 495 break; 496 else { 497 retry_count--; 498 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \ 499 timeout,retry count down = %d \n", acb->host->host_no, retry_count); 500 } 501 } while (retry_count != 0); 502 } 503 504 static void arcmsr_hbaC_flush_cache(struct AdapterControlBlock *pACB) 505 { 506 struct MessageUnit_C __iomem *reg = pACB->pmuC; 507 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 508 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, ®->inbound_msgaddr0); 509 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell); 510 do { 511 if (arcmsr_hbaC_wait_msgint_ready(pACB)) { 512 break; 513 } else { 514 retry_count--; 515 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \ 516 timeout,retry count down = %d \n", pACB->host->host_no, retry_count); 517 } 518 } while (retry_count != 0); 519 return; 520 } 521 522 static void arcmsr_hbaD_flush_cache(struct AdapterControlBlock *pACB) 523 { 524 int retry_count = 15; 525 struct MessageUnit_D *reg = pACB->pmuD; 526 527 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, reg->inbound_msgaddr0); 528 do { 529 if (arcmsr_hbaD_wait_msgint_ready(pACB)) 530 break; 531 532 retry_count--; 533 pr_notice("arcmsr%d: wait 'flush adapter " 534 "cache' timeout, retry count down = %d\n", 535 pACB->host->host_no, retry_count); 536 } while (retry_count != 0); 537 } 538 539 static void arcmsr_hbaE_flush_cache(struct AdapterControlBlock *pACB) 540 { 541 int retry_count = 30; 542 struct MessageUnit_E __iomem *reg = pACB->pmuE; 543 544 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, ®->inbound_msgaddr0); 545 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 546 writel(pACB->out_doorbell, ®->iobound_doorbell); 547 do { 548 if (arcmsr_hbaE_wait_msgint_ready(pACB)) 549 break; 550 retry_count--; 551 pr_notice("arcmsr%d: wait 'flush adapter " 552 "cache' timeout, retry count down = %d\n", 553 pACB->host->host_no, retry_count); 554 } while (retry_count != 0); 555 } 556 557 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb) 558 { 559 switch (acb->adapter_type) { 560 561 case ACB_ADAPTER_TYPE_A: { 562 arcmsr_hbaA_flush_cache(acb); 563 } 564 break; 565 566 case ACB_ADAPTER_TYPE_B: { 567 arcmsr_hbaB_flush_cache(acb); 568 } 569 break; 570 case ACB_ADAPTER_TYPE_C: { 571 arcmsr_hbaC_flush_cache(acb); 572 } 573 break; 574 case ACB_ADAPTER_TYPE_D: 575 arcmsr_hbaD_flush_cache(acb); 576 break; 577 case ACB_ADAPTER_TYPE_E: 578 arcmsr_hbaE_flush_cache(acb); 579 break; 580 } 581 } 582 583 static void arcmsr_hbaB_assign_regAddr(struct AdapterControlBlock *acb) 584 { 585 struct MessageUnit_B *reg = acb->pmuB; 586 587 if (acb->pdev->device == PCI_DEVICE_ID_ARECA_1203) { 588 reg->drv2iop_doorbell = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_1203); 589 reg->drv2iop_doorbell_mask = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_MASK_1203); 590 reg->iop2drv_doorbell = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_1203); 591 reg->iop2drv_doorbell_mask = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_MASK_1203); 592 } else { 593 reg->drv2iop_doorbell= MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL); 594 reg->drv2iop_doorbell_mask = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_MASK); 595 reg->iop2drv_doorbell = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL); 596 reg->iop2drv_doorbell_mask = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_MASK); 597 } 598 reg->message_wbuffer = MEM_BASE1(ARCMSR_MESSAGE_WBUFFER); 599 reg->message_rbuffer = MEM_BASE1(ARCMSR_MESSAGE_RBUFFER); 600 reg->message_rwbuffer = MEM_BASE1(ARCMSR_MESSAGE_RWBUFFER); 601 } 602 603 static void arcmsr_hbaD_assign_regAddr(struct AdapterControlBlock *acb) 604 { 605 struct MessageUnit_D *reg = acb->pmuD; 606 607 reg->chip_id = MEM_BASE0(ARCMSR_ARC1214_CHIP_ID); 608 reg->cpu_mem_config = MEM_BASE0(ARCMSR_ARC1214_CPU_MEMORY_CONFIGURATION); 609 reg->i2o_host_interrupt_mask = MEM_BASE0(ARCMSR_ARC1214_I2_HOST_INTERRUPT_MASK); 610 reg->sample_at_reset = MEM_BASE0(ARCMSR_ARC1214_SAMPLE_RESET); 611 reg->reset_request = MEM_BASE0(ARCMSR_ARC1214_RESET_REQUEST); 612 reg->host_int_status = MEM_BASE0(ARCMSR_ARC1214_MAIN_INTERRUPT_STATUS); 613 reg->pcief0_int_enable = MEM_BASE0(ARCMSR_ARC1214_PCIE_F0_INTERRUPT_ENABLE); 614 reg->inbound_msgaddr0 = MEM_BASE0(ARCMSR_ARC1214_INBOUND_MESSAGE0); 615 reg->inbound_msgaddr1 = MEM_BASE0(ARCMSR_ARC1214_INBOUND_MESSAGE1); 616 reg->outbound_msgaddr0 = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_MESSAGE0); 617 reg->outbound_msgaddr1 = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_MESSAGE1); 618 reg->inbound_doorbell = MEM_BASE0(ARCMSR_ARC1214_INBOUND_DOORBELL); 619 reg->outbound_doorbell = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_DOORBELL); 620 reg->outbound_doorbell_enable = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_DOORBELL_ENABLE); 621 reg->inboundlist_base_low = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_BASE_LOW); 622 reg->inboundlist_base_high = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_BASE_HIGH); 623 reg->inboundlist_write_pointer = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_WRITE_POINTER); 624 reg->outboundlist_base_low = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_BASE_LOW); 625 reg->outboundlist_base_high = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_BASE_HIGH); 626 reg->outboundlist_copy_pointer = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_COPY_POINTER); 627 reg->outboundlist_read_pointer = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_READ_POINTER); 628 reg->outboundlist_interrupt_cause = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_INTERRUPT_CAUSE); 629 reg->outboundlist_interrupt_enable = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_INTERRUPT_ENABLE); 630 reg->message_wbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_WBUFFER); 631 reg->message_rbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_RBUFFER); 632 reg->msgcode_rwbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_RWBUFFER); 633 } 634 635 static bool arcmsr_alloc_io_queue(struct AdapterControlBlock *acb) 636 { 637 bool rtn = true; 638 void *dma_coherent; 639 dma_addr_t dma_coherent_handle; 640 struct pci_dev *pdev = acb->pdev; 641 642 switch (acb->adapter_type) { 643 case ACB_ADAPTER_TYPE_B: { 644 acb->ioqueue_size = roundup(sizeof(struct MessageUnit_B), 32); 645 dma_coherent = dma_alloc_coherent(&pdev->dev, acb->ioqueue_size, 646 &dma_coherent_handle, GFP_KERNEL); 647 if (!dma_coherent) { 648 pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no); 649 return false; 650 } 651 acb->dma_coherent_handle2 = dma_coherent_handle; 652 acb->dma_coherent2 = dma_coherent; 653 acb->pmuB = (struct MessageUnit_B *)dma_coherent; 654 arcmsr_hbaB_assign_regAddr(acb); 655 } 656 break; 657 case ACB_ADAPTER_TYPE_D: { 658 acb->ioqueue_size = roundup(sizeof(struct MessageUnit_D), 32); 659 dma_coherent = dma_alloc_coherent(&pdev->dev, acb->ioqueue_size, 660 &dma_coherent_handle, GFP_KERNEL); 661 if (!dma_coherent) { 662 pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no); 663 return false; 664 } 665 acb->dma_coherent_handle2 = dma_coherent_handle; 666 acb->dma_coherent2 = dma_coherent; 667 acb->pmuD = (struct MessageUnit_D *)dma_coherent; 668 arcmsr_hbaD_assign_regAddr(acb); 669 } 670 break; 671 case ACB_ADAPTER_TYPE_E: { 672 uint32_t completeQ_size; 673 completeQ_size = sizeof(struct deliver_completeQ) * ARCMSR_MAX_HBE_DONEQUEUE + 128; 674 acb->ioqueue_size = roundup(completeQ_size, 32); 675 dma_coherent = dma_alloc_coherent(&pdev->dev, acb->ioqueue_size, 676 &dma_coherent_handle, GFP_KERNEL); 677 if (!dma_coherent){ 678 pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no); 679 return false; 680 } 681 acb->dma_coherent_handle2 = dma_coherent_handle; 682 acb->dma_coherent2 = dma_coherent; 683 acb->pCompletionQ = dma_coherent; 684 acb->completionQ_entry = acb->ioqueue_size / sizeof(struct deliver_completeQ); 685 acb->doneq_index = 0; 686 } 687 break; 688 default: 689 break; 690 } 691 return rtn; 692 } 693 694 static int arcmsr_alloc_ccb_pool(struct AdapterControlBlock *acb) 695 { 696 struct pci_dev *pdev = acb->pdev; 697 void *dma_coherent; 698 dma_addr_t dma_coherent_handle; 699 struct CommandControlBlock *ccb_tmp; 700 int i = 0, j = 0; 701 unsigned long cdb_phyaddr, next_ccb_phy; 702 unsigned long roundup_ccbsize; 703 unsigned long max_xfer_len; 704 unsigned long max_sg_entrys; 705 uint32_t firm_config_version, curr_phy_upper32; 706 707 for (i = 0; i < ARCMSR_MAX_TARGETID; i++) 708 for (j = 0; j < ARCMSR_MAX_TARGETLUN; j++) 709 acb->devstate[i][j] = ARECA_RAID_GONE; 710 711 max_xfer_len = ARCMSR_MAX_XFER_LEN; 712 max_sg_entrys = ARCMSR_DEFAULT_SG_ENTRIES; 713 firm_config_version = acb->firm_cfg_version; 714 if((firm_config_version & 0xFF) >= 3){ 715 max_xfer_len = (ARCMSR_CDB_SG_PAGE_LENGTH << ((firm_config_version >> 8) & 0xFF)) * 1024;/* max 4M byte */ 716 max_sg_entrys = (max_xfer_len/4096); 717 } 718 acb->host->max_sectors = max_xfer_len/512; 719 acb->host->sg_tablesize = max_sg_entrys; 720 roundup_ccbsize = roundup(sizeof(struct CommandControlBlock) + (max_sg_entrys - 1) * sizeof(struct SG64ENTRY), 32); 721 acb->uncache_size = roundup_ccbsize * acb->maxFreeCCB; 722 acb->uncache_size += acb->ioqueue_size; 723 dma_coherent = dma_alloc_coherent(&pdev->dev, acb->uncache_size, &dma_coherent_handle, GFP_KERNEL); 724 if(!dma_coherent){ 725 printk(KERN_NOTICE "arcmsr%d: dma_alloc_coherent got error\n", acb->host->host_no); 726 return -ENOMEM; 727 } 728 acb->dma_coherent = dma_coherent; 729 acb->dma_coherent_handle = dma_coherent_handle; 730 memset(dma_coherent, 0, acb->uncache_size); 731 acb->ccbsize = roundup_ccbsize; 732 ccb_tmp = dma_coherent; 733 curr_phy_upper32 = upper_32_bits(dma_coherent_handle); 734 acb->vir2phy_offset = (unsigned long)dma_coherent - (unsigned long)dma_coherent_handle; 735 for(i = 0; i < acb->maxFreeCCB; i++){ 736 cdb_phyaddr = (unsigned long)dma_coherent_handle + offsetof(struct CommandControlBlock, arcmsr_cdb); 737 switch (acb->adapter_type) { 738 case ACB_ADAPTER_TYPE_A: 739 case ACB_ADAPTER_TYPE_B: 740 ccb_tmp->cdb_phyaddr = cdb_phyaddr >> 5; 741 break; 742 case ACB_ADAPTER_TYPE_C: 743 case ACB_ADAPTER_TYPE_D: 744 case ACB_ADAPTER_TYPE_E: 745 ccb_tmp->cdb_phyaddr = cdb_phyaddr; 746 break; 747 } 748 acb->pccb_pool[i] = ccb_tmp; 749 ccb_tmp->acb = acb; 750 ccb_tmp->smid = (u32)i << 16; 751 INIT_LIST_HEAD(&ccb_tmp->list); 752 next_ccb_phy = dma_coherent_handle + roundup_ccbsize; 753 if (upper_32_bits(next_ccb_phy) != curr_phy_upper32) { 754 acb->maxFreeCCB = i; 755 acb->host->can_queue = i; 756 break; 757 } 758 else 759 list_add_tail(&ccb_tmp->list, &acb->ccb_free_list); 760 ccb_tmp = (struct CommandControlBlock *)((unsigned long)ccb_tmp + roundup_ccbsize); 761 dma_coherent_handle = next_ccb_phy; 762 } 763 acb->dma_coherent_handle2 = dma_coherent_handle; 764 acb->dma_coherent2 = ccb_tmp; 765 switch (acb->adapter_type) { 766 case ACB_ADAPTER_TYPE_B: 767 acb->pmuB = (struct MessageUnit_B *)acb->dma_coherent2; 768 arcmsr_hbaB_assign_regAddr(acb); 769 break; 770 case ACB_ADAPTER_TYPE_D: 771 acb->pmuD = (struct MessageUnit_D *)acb->dma_coherent2; 772 arcmsr_hbaD_assign_regAddr(acb); 773 break; 774 case ACB_ADAPTER_TYPE_E: 775 acb->pCompletionQ = acb->dma_coherent2; 776 acb->completionQ_entry = acb->ioqueue_size / sizeof(struct deliver_completeQ); 777 acb->doneq_index = 0; 778 break; 779 } 780 return 0; 781 } 782 783 static void arcmsr_message_isr_bh_fn(struct work_struct *work) 784 { 785 struct AdapterControlBlock *acb = container_of(work, 786 struct AdapterControlBlock, arcmsr_do_message_isr_bh); 787 char *acb_dev_map = (char *)acb->device_map; 788 uint32_t __iomem *signature = NULL; 789 char __iomem *devicemap = NULL; 790 int target, lun; 791 struct scsi_device *psdev; 792 char diff, temp; 793 794 acb->acb_flags &= ~ACB_F_MSG_GET_CONFIG; 795 switch (acb->adapter_type) { 796 case ACB_ADAPTER_TYPE_A: { 797 struct MessageUnit_A __iomem *reg = acb->pmuA; 798 799 signature = (uint32_t __iomem *)(®->message_rwbuffer[0]); 800 devicemap = (char __iomem *)(®->message_rwbuffer[21]); 801 break; 802 } 803 case ACB_ADAPTER_TYPE_B: { 804 struct MessageUnit_B *reg = acb->pmuB; 805 806 signature = (uint32_t __iomem *)(®->message_rwbuffer[0]); 807 devicemap = (char __iomem *)(®->message_rwbuffer[21]); 808 break; 809 } 810 case ACB_ADAPTER_TYPE_C: { 811 struct MessageUnit_C __iomem *reg = acb->pmuC; 812 813 signature = (uint32_t __iomem *)(®->msgcode_rwbuffer[0]); 814 devicemap = (char __iomem *)(®->msgcode_rwbuffer[21]); 815 break; 816 } 817 case ACB_ADAPTER_TYPE_D: { 818 struct MessageUnit_D *reg = acb->pmuD; 819 820 signature = (uint32_t __iomem *)(®->msgcode_rwbuffer[0]); 821 devicemap = (char __iomem *)(®->msgcode_rwbuffer[21]); 822 break; 823 } 824 case ACB_ADAPTER_TYPE_E: { 825 struct MessageUnit_E __iomem *reg = acb->pmuE; 826 827 signature = (uint32_t __iomem *)(®->msgcode_rwbuffer[0]); 828 devicemap = (char __iomem *)(®->msgcode_rwbuffer[21]); 829 break; 830 } 831 } 832 atomic_inc(&acb->rq_map_token); 833 if (readl(signature) != ARCMSR_SIGNATURE_GET_CONFIG) 834 return; 835 for (target = 0; target < ARCMSR_MAX_TARGETID - 1; 836 target++) { 837 temp = readb(devicemap); 838 diff = (*acb_dev_map) ^ temp; 839 if (diff != 0) { 840 *acb_dev_map = temp; 841 for (lun = 0; lun < ARCMSR_MAX_TARGETLUN; 842 lun++) { 843 if ((diff & 0x01) == 1 && 844 (temp & 0x01) == 1) { 845 scsi_add_device(acb->host, 846 0, target, lun); 847 } else if ((diff & 0x01) == 1 848 && (temp & 0x01) == 0) { 849 psdev = scsi_device_lookup(acb->host, 850 0, target, lun); 851 if (psdev != NULL) { 852 scsi_remove_device(psdev); 853 scsi_device_put(psdev); 854 } 855 } 856 temp >>= 1; 857 diff >>= 1; 858 } 859 } 860 devicemap++; 861 acb_dev_map++; 862 } 863 } 864 865 static int 866 arcmsr_request_irq(struct pci_dev *pdev, struct AdapterControlBlock *acb) 867 { 868 unsigned long flags; 869 int nvec, i; 870 871 if (msix_enable == 0) 872 goto msi_int0; 873 nvec = pci_alloc_irq_vectors(pdev, 1, ARCMST_NUM_MSIX_VECTORS, 874 PCI_IRQ_MSIX); 875 if (nvec > 0) { 876 pr_info("arcmsr%d: msi-x enabled\n", acb->host->host_no); 877 flags = 0; 878 } else { 879 msi_int0: 880 if (msi_enable == 1) { 881 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); 882 if (nvec == 1) { 883 dev_info(&pdev->dev, "msi enabled\n"); 884 goto msi_int1; 885 } 886 } 887 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_LEGACY); 888 if (nvec < 1) 889 return FAILED; 890 msi_int1: 891 flags = IRQF_SHARED; 892 } 893 894 acb->vector_count = nvec; 895 for (i = 0; i < nvec; i++) { 896 if (request_irq(pci_irq_vector(pdev, i), arcmsr_do_interrupt, 897 flags, "arcmsr", acb)) { 898 pr_warn("arcmsr%d: request_irq =%d failed!\n", 899 acb->host->host_no, pci_irq_vector(pdev, i)); 900 goto out_free_irq; 901 } 902 } 903 904 return SUCCESS; 905 out_free_irq: 906 while (--i >= 0) 907 free_irq(pci_irq_vector(pdev, i), acb); 908 pci_free_irq_vectors(pdev); 909 return FAILED; 910 } 911 912 static void arcmsr_init_get_devmap_timer(struct AdapterControlBlock *pacb) 913 { 914 INIT_WORK(&pacb->arcmsr_do_message_isr_bh, arcmsr_message_isr_bh_fn); 915 atomic_set(&pacb->rq_map_token, 16); 916 atomic_set(&pacb->ante_token_value, 16); 917 pacb->fw_flag = FW_NORMAL; 918 timer_setup(&pacb->eternal_timer, arcmsr_request_device_map, 0); 919 pacb->eternal_timer.expires = jiffies + msecs_to_jiffies(6 * HZ); 920 add_timer(&pacb->eternal_timer); 921 } 922 923 static void arcmsr_init_set_datetime_timer(struct AdapterControlBlock *pacb) 924 { 925 timer_setup(&pacb->refresh_timer, arcmsr_set_iop_datetime, 0); 926 pacb->refresh_timer.expires = jiffies + msecs_to_jiffies(60 * 1000); 927 add_timer(&pacb->refresh_timer); 928 } 929 930 static int arcmsr_set_dma_mask(struct AdapterControlBlock *acb) 931 { 932 struct pci_dev *pcidev = acb->pdev; 933 934 if (IS_DMA64) { 935 if (((acb->adapter_type == ACB_ADAPTER_TYPE_A) && !dma_mask_64) || 936 dma_set_mask(&pcidev->dev, DMA_BIT_MASK(64))) 937 goto dma32; 938 if (dma_set_coherent_mask(&pcidev->dev, DMA_BIT_MASK(64)) || 939 dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(64))) { 940 printk("arcmsr: set DMA 64 mask failed\n"); 941 return -ENXIO; 942 } 943 } else { 944 dma32: 945 if (dma_set_mask(&pcidev->dev, DMA_BIT_MASK(32)) || 946 dma_set_coherent_mask(&pcidev->dev, DMA_BIT_MASK(32)) || 947 dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32))) { 948 printk("arcmsr: set DMA 32-bit mask failed\n"); 949 return -ENXIO; 950 } 951 } 952 return 0; 953 } 954 955 static int arcmsr_probe(struct pci_dev *pdev, const struct pci_device_id *id) 956 { 957 struct Scsi_Host *host; 958 struct AdapterControlBlock *acb; 959 uint8_t bus,dev_fun; 960 int error; 961 error = pci_enable_device(pdev); 962 if(error){ 963 return -ENODEV; 964 } 965 host = scsi_host_alloc(&arcmsr_scsi_host_template, sizeof(struct AdapterControlBlock)); 966 if(!host){ 967 goto pci_disable_dev; 968 } 969 init_waitqueue_head(&wait_q); 970 bus = pdev->bus->number; 971 dev_fun = pdev->devfn; 972 acb = (struct AdapterControlBlock *) host->hostdata; 973 memset(acb,0,sizeof(struct AdapterControlBlock)); 974 acb->pdev = pdev; 975 acb->adapter_type = id->driver_data; 976 if (arcmsr_set_dma_mask(acb)) 977 goto scsi_host_release; 978 acb->host = host; 979 host->max_lun = ARCMSR_MAX_TARGETLUN; 980 host->max_id = ARCMSR_MAX_TARGETID; /*16:8*/ 981 host->max_cmd_len = 16; /*this is issue of 64bit LBA ,over 2T byte*/ 982 if ((host_can_queue < ARCMSR_MIN_OUTSTANDING_CMD) || (host_can_queue > ARCMSR_MAX_OUTSTANDING_CMD)) 983 host_can_queue = ARCMSR_DEFAULT_OUTSTANDING_CMD; 984 host->can_queue = host_can_queue; /* max simultaneous cmds */ 985 if ((cmd_per_lun < ARCMSR_MIN_CMD_PERLUN) || (cmd_per_lun > ARCMSR_MAX_CMD_PERLUN)) 986 cmd_per_lun = ARCMSR_DEFAULT_CMD_PERLUN; 987 host->cmd_per_lun = cmd_per_lun; 988 host->this_id = ARCMSR_SCSI_INITIATOR_ID; 989 host->unique_id = (bus << 8) | dev_fun; 990 pci_set_drvdata(pdev, host); 991 pci_set_master(pdev); 992 error = pci_request_regions(pdev, "arcmsr"); 993 if(error){ 994 goto scsi_host_release; 995 } 996 spin_lock_init(&acb->eh_lock); 997 spin_lock_init(&acb->ccblist_lock); 998 spin_lock_init(&acb->postq_lock); 999 spin_lock_init(&acb->doneq_lock); 1000 spin_lock_init(&acb->rqbuffer_lock); 1001 spin_lock_init(&acb->wqbuffer_lock); 1002 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED | 1003 ACB_F_MESSAGE_RQBUFFER_CLEARED | 1004 ACB_F_MESSAGE_WQBUFFER_READED); 1005 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER; 1006 INIT_LIST_HEAD(&acb->ccb_free_list); 1007 error = arcmsr_remap_pciregion(acb); 1008 if(!error){ 1009 goto pci_release_regs; 1010 } 1011 error = arcmsr_alloc_io_queue(acb); 1012 if (!error) 1013 goto unmap_pci_region; 1014 error = arcmsr_get_firmware_spec(acb); 1015 if(!error){ 1016 goto free_hbb_mu; 1017 } 1018 arcmsr_free_io_queue(acb); 1019 error = arcmsr_alloc_ccb_pool(acb); 1020 if(error){ 1021 goto unmap_pci_region; 1022 } 1023 error = scsi_add_host(host, &pdev->dev); 1024 if(error){ 1025 goto free_ccb_pool; 1026 } 1027 if (arcmsr_request_irq(pdev, acb) == FAILED) 1028 goto scsi_host_remove; 1029 arcmsr_iop_init(acb); 1030 arcmsr_init_get_devmap_timer(acb); 1031 if (set_date_time) 1032 arcmsr_init_set_datetime_timer(acb); 1033 if(arcmsr_alloc_sysfs_attr(acb)) 1034 goto out_free_sysfs; 1035 scsi_scan_host(host); 1036 return 0; 1037 out_free_sysfs: 1038 if (set_date_time) 1039 del_timer_sync(&acb->refresh_timer); 1040 del_timer_sync(&acb->eternal_timer); 1041 flush_work(&acb->arcmsr_do_message_isr_bh); 1042 arcmsr_stop_adapter_bgrb(acb); 1043 arcmsr_flush_adapter_cache(acb); 1044 arcmsr_free_irq(pdev, acb); 1045 scsi_host_remove: 1046 scsi_remove_host(host); 1047 free_ccb_pool: 1048 arcmsr_free_ccb_pool(acb); 1049 goto unmap_pci_region; 1050 free_hbb_mu: 1051 arcmsr_free_io_queue(acb); 1052 unmap_pci_region: 1053 arcmsr_unmap_pciregion(acb); 1054 pci_release_regs: 1055 pci_release_regions(pdev); 1056 scsi_host_release: 1057 scsi_host_put(host); 1058 pci_disable_dev: 1059 pci_disable_device(pdev); 1060 return -ENODEV; 1061 } 1062 1063 static void arcmsr_free_irq(struct pci_dev *pdev, 1064 struct AdapterControlBlock *acb) 1065 { 1066 int i; 1067 1068 for (i = 0; i < acb->vector_count; i++) 1069 free_irq(pci_irq_vector(pdev, i), acb); 1070 pci_free_irq_vectors(pdev); 1071 } 1072 1073 static int arcmsr_suspend(struct pci_dev *pdev, pm_message_t state) 1074 { 1075 uint32_t intmask_org; 1076 struct Scsi_Host *host = pci_get_drvdata(pdev); 1077 struct AdapterControlBlock *acb = 1078 (struct AdapterControlBlock *)host->hostdata; 1079 1080 intmask_org = arcmsr_disable_outbound_ints(acb); 1081 arcmsr_free_irq(pdev, acb); 1082 del_timer_sync(&acb->eternal_timer); 1083 if (set_date_time) 1084 del_timer_sync(&acb->refresh_timer); 1085 flush_work(&acb->arcmsr_do_message_isr_bh); 1086 arcmsr_stop_adapter_bgrb(acb); 1087 arcmsr_flush_adapter_cache(acb); 1088 pci_set_drvdata(pdev, host); 1089 pci_save_state(pdev); 1090 pci_disable_device(pdev); 1091 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1092 return 0; 1093 } 1094 1095 static int arcmsr_resume(struct pci_dev *pdev) 1096 { 1097 struct Scsi_Host *host = pci_get_drvdata(pdev); 1098 struct AdapterControlBlock *acb = 1099 (struct AdapterControlBlock *)host->hostdata; 1100 1101 pci_set_power_state(pdev, PCI_D0); 1102 pci_enable_wake(pdev, PCI_D0, 0); 1103 pci_restore_state(pdev); 1104 if (pci_enable_device(pdev)) { 1105 pr_warn("%s: pci_enable_device error\n", __func__); 1106 return -ENODEV; 1107 } 1108 if (arcmsr_set_dma_mask(acb)) 1109 goto controller_unregister; 1110 pci_set_master(pdev); 1111 if (arcmsr_request_irq(pdev, acb) == FAILED) 1112 goto controller_stop; 1113 switch (acb->adapter_type) { 1114 case ACB_ADAPTER_TYPE_B: { 1115 struct MessageUnit_B *reg = acb->pmuB; 1116 uint32_t i; 1117 for (i = 0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) { 1118 reg->post_qbuffer[i] = 0; 1119 reg->done_qbuffer[i] = 0; 1120 } 1121 reg->postq_index = 0; 1122 reg->doneq_index = 0; 1123 break; 1124 } 1125 case ACB_ADAPTER_TYPE_E: 1126 writel(0, &acb->pmuE->host_int_status); 1127 writel(ARCMSR_HBEMU_DOORBELL_SYNC, &acb->pmuE->iobound_doorbell); 1128 acb->in_doorbell = 0; 1129 acb->out_doorbell = 0; 1130 acb->doneq_index = 0; 1131 break; 1132 } 1133 arcmsr_iop_init(acb); 1134 arcmsr_init_get_devmap_timer(acb); 1135 if (set_date_time) 1136 arcmsr_init_set_datetime_timer(acb); 1137 return 0; 1138 controller_stop: 1139 arcmsr_stop_adapter_bgrb(acb); 1140 arcmsr_flush_adapter_cache(acb); 1141 controller_unregister: 1142 scsi_remove_host(host); 1143 arcmsr_free_ccb_pool(acb); 1144 arcmsr_unmap_pciregion(acb); 1145 pci_release_regions(pdev); 1146 scsi_host_put(host); 1147 pci_disable_device(pdev); 1148 return -ENODEV; 1149 } 1150 1151 static uint8_t arcmsr_hbaA_abort_allcmd(struct AdapterControlBlock *acb) 1152 { 1153 struct MessageUnit_A __iomem *reg = acb->pmuA; 1154 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, ®->inbound_msgaddr0); 1155 if (!arcmsr_hbaA_wait_msgint_ready(acb)) { 1156 printk(KERN_NOTICE 1157 "arcmsr%d: wait 'abort all outstanding command' timeout\n" 1158 , acb->host->host_no); 1159 return false; 1160 } 1161 return true; 1162 } 1163 1164 static uint8_t arcmsr_hbaB_abort_allcmd(struct AdapterControlBlock *acb) 1165 { 1166 struct MessageUnit_B *reg = acb->pmuB; 1167 1168 writel(ARCMSR_MESSAGE_ABORT_CMD, reg->drv2iop_doorbell); 1169 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 1170 printk(KERN_NOTICE 1171 "arcmsr%d: wait 'abort all outstanding command' timeout\n" 1172 , acb->host->host_no); 1173 return false; 1174 } 1175 return true; 1176 } 1177 static uint8_t arcmsr_hbaC_abort_allcmd(struct AdapterControlBlock *pACB) 1178 { 1179 struct MessageUnit_C __iomem *reg = pACB->pmuC; 1180 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, ®->inbound_msgaddr0); 1181 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell); 1182 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) { 1183 printk(KERN_NOTICE 1184 "arcmsr%d: wait 'abort all outstanding command' timeout\n" 1185 , pACB->host->host_no); 1186 return false; 1187 } 1188 return true; 1189 } 1190 1191 static uint8_t arcmsr_hbaD_abort_allcmd(struct AdapterControlBlock *pACB) 1192 { 1193 struct MessageUnit_D *reg = pACB->pmuD; 1194 1195 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, reg->inbound_msgaddr0); 1196 if (!arcmsr_hbaD_wait_msgint_ready(pACB)) { 1197 pr_notice("arcmsr%d: wait 'abort all outstanding " 1198 "command' timeout\n", pACB->host->host_no); 1199 return false; 1200 } 1201 return true; 1202 } 1203 1204 static uint8_t arcmsr_hbaE_abort_allcmd(struct AdapterControlBlock *pACB) 1205 { 1206 struct MessageUnit_E __iomem *reg = pACB->pmuE; 1207 1208 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, ®->inbound_msgaddr0); 1209 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 1210 writel(pACB->out_doorbell, ®->iobound_doorbell); 1211 if (!arcmsr_hbaE_wait_msgint_ready(pACB)) { 1212 pr_notice("arcmsr%d: wait 'abort all outstanding " 1213 "command' timeout\n", pACB->host->host_no); 1214 return false; 1215 } 1216 return true; 1217 } 1218 1219 static uint8_t arcmsr_abort_allcmd(struct AdapterControlBlock *acb) 1220 { 1221 uint8_t rtnval = 0; 1222 switch (acb->adapter_type) { 1223 case ACB_ADAPTER_TYPE_A: { 1224 rtnval = arcmsr_hbaA_abort_allcmd(acb); 1225 } 1226 break; 1227 1228 case ACB_ADAPTER_TYPE_B: { 1229 rtnval = arcmsr_hbaB_abort_allcmd(acb); 1230 } 1231 break; 1232 1233 case ACB_ADAPTER_TYPE_C: { 1234 rtnval = arcmsr_hbaC_abort_allcmd(acb); 1235 } 1236 break; 1237 1238 case ACB_ADAPTER_TYPE_D: 1239 rtnval = arcmsr_hbaD_abort_allcmd(acb); 1240 break; 1241 case ACB_ADAPTER_TYPE_E: 1242 rtnval = arcmsr_hbaE_abort_allcmd(acb); 1243 break; 1244 } 1245 return rtnval; 1246 } 1247 1248 static void arcmsr_pci_unmap_dma(struct CommandControlBlock *ccb) 1249 { 1250 struct scsi_cmnd *pcmd = ccb->pcmd; 1251 1252 scsi_dma_unmap(pcmd); 1253 } 1254 1255 static void arcmsr_ccb_complete(struct CommandControlBlock *ccb) 1256 { 1257 struct AdapterControlBlock *acb = ccb->acb; 1258 struct scsi_cmnd *pcmd = ccb->pcmd; 1259 unsigned long flags; 1260 atomic_dec(&acb->ccboutstandingcount); 1261 arcmsr_pci_unmap_dma(ccb); 1262 ccb->startdone = ARCMSR_CCB_DONE; 1263 spin_lock_irqsave(&acb->ccblist_lock, flags); 1264 list_add_tail(&ccb->list, &acb->ccb_free_list); 1265 spin_unlock_irqrestore(&acb->ccblist_lock, flags); 1266 pcmd->scsi_done(pcmd); 1267 } 1268 1269 static void arcmsr_report_sense_info(struct CommandControlBlock *ccb) 1270 { 1271 1272 struct scsi_cmnd *pcmd = ccb->pcmd; 1273 struct SENSE_DATA *sensebuffer = (struct SENSE_DATA *)pcmd->sense_buffer; 1274 pcmd->result = (DID_OK << 16) | (CHECK_CONDITION << 1); 1275 if (sensebuffer) { 1276 int sense_data_length = 1277 sizeof(struct SENSE_DATA) < SCSI_SENSE_BUFFERSIZE 1278 ? sizeof(struct SENSE_DATA) : SCSI_SENSE_BUFFERSIZE; 1279 memset(sensebuffer, 0, SCSI_SENSE_BUFFERSIZE); 1280 memcpy(sensebuffer, ccb->arcmsr_cdb.SenseData, sense_data_length); 1281 sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS; 1282 sensebuffer->Valid = 1; 1283 pcmd->result |= (DRIVER_SENSE << 24); 1284 } 1285 } 1286 1287 static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb) 1288 { 1289 u32 orig_mask = 0; 1290 switch (acb->adapter_type) { 1291 case ACB_ADAPTER_TYPE_A : { 1292 struct MessageUnit_A __iomem *reg = acb->pmuA; 1293 orig_mask = readl(®->outbound_intmask); 1294 writel(orig_mask|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE, \ 1295 ®->outbound_intmask); 1296 } 1297 break; 1298 case ACB_ADAPTER_TYPE_B : { 1299 struct MessageUnit_B *reg = acb->pmuB; 1300 orig_mask = readl(reg->iop2drv_doorbell_mask); 1301 writel(0, reg->iop2drv_doorbell_mask); 1302 } 1303 break; 1304 case ACB_ADAPTER_TYPE_C:{ 1305 struct MessageUnit_C __iomem *reg = acb->pmuC; 1306 /* disable all outbound interrupt */ 1307 orig_mask = readl(®->host_int_mask); /* disable outbound message0 int */ 1308 writel(orig_mask|ARCMSR_HBCMU_ALL_INTMASKENABLE, ®->host_int_mask); 1309 } 1310 break; 1311 case ACB_ADAPTER_TYPE_D: { 1312 struct MessageUnit_D *reg = acb->pmuD; 1313 /* disable all outbound interrupt */ 1314 writel(ARCMSR_ARC1214_ALL_INT_DISABLE, reg->pcief0_int_enable); 1315 } 1316 break; 1317 case ACB_ADAPTER_TYPE_E: { 1318 struct MessageUnit_E __iomem *reg = acb->pmuE; 1319 orig_mask = readl(®->host_int_mask); 1320 writel(orig_mask | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR, ®->host_int_mask); 1321 readl(®->host_int_mask); /* Dummy readl to force pci flush */ 1322 } 1323 break; 1324 } 1325 return orig_mask; 1326 } 1327 1328 static void arcmsr_report_ccb_state(struct AdapterControlBlock *acb, 1329 struct CommandControlBlock *ccb, bool error) 1330 { 1331 uint8_t id, lun; 1332 id = ccb->pcmd->device->id; 1333 lun = ccb->pcmd->device->lun; 1334 if (!error) { 1335 if (acb->devstate[id][lun] == ARECA_RAID_GONE) 1336 acb->devstate[id][lun] = ARECA_RAID_GOOD; 1337 ccb->pcmd->result = DID_OK << 16; 1338 arcmsr_ccb_complete(ccb); 1339 }else{ 1340 switch (ccb->arcmsr_cdb.DeviceStatus) { 1341 case ARCMSR_DEV_SELECT_TIMEOUT: { 1342 acb->devstate[id][lun] = ARECA_RAID_GONE; 1343 ccb->pcmd->result = DID_NO_CONNECT << 16; 1344 arcmsr_ccb_complete(ccb); 1345 } 1346 break; 1347 1348 case ARCMSR_DEV_ABORTED: 1349 1350 case ARCMSR_DEV_INIT_FAIL: { 1351 acb->devstate[id][lun] = ARECA_RAID_GONE; 1352 ccb->pcmd->result = DID_BAD_TARGET << 16; 1353 arcmsr_ccb_complete(ccb); 1354 } 1355 break; 1356 1357 case ARCMSR_DEV_CHECK_CONDITION: { 1358 acb->devstate[id][lun] = ARECA_RAID_GOOD; 1359 arcmsr_report_sense_info(ccb); 1360 arcmsr_ccb_complete(ccb); 1361 } 1362 break; 1363 1364 default: 1365 printk(KERN_NOTICE 1366 "arcmsr%d: scsi id = %d lun = %d isr get command error done, \ 1367 but got unknown DeviceStatus = 0x%x \n" 1368 , acb->host->host_no 1369 , id 1370 , lun 1371 , ccb->arcmsr_cdb.DeviceStatus); 1372 acb->devstate[id][lun] = ARECA_RAID_GONE; 1373 ccb->pcmd->result = DID_NO_CONNECT << 16; 1374 arcmsr_ccb_complete(ccb); 1375 break; 1376 } 1377 } 1378 } 1379 1380 static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, struct CommandControlBlock *pCCB, bool error) 1381 { 1382 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) { 1383 if (pCCB->startdone == ARCMSR_CCB_ABORTED) { 1384 struct scsi_cmnd *abortcmd = pCCB->pcmd; 1385 if (abortcmd) { 1386 abortcmd->result |= DID_ABORT << 16; 1387 arcmsr_ccb_complete(pCCB); 1388 printk(KERN_NOTICE "arcmsr%d: pCCB ='0x%p' isr got aborted command \n", 1389 acb->host->host_no, pCCB); 1390 } 1391 return; 1392 } 1393 printk(KERN_NOTICE "arcmsr%d: isr get an illegal ccb command \ 1394 done acb = '0x%p'" 1395 "ccb = '0x%p' ccbacb = '0x%p' startdone = 0x%x" 1396 " ccboutstandingcount = %d \n" 1397 , acb->host->host_no 1398 , acb 1399 , pCCB 1400 , pCCB->acb 1401 , pCCB->startdone 1402 , atomic_read(&acb->ccboutstandingcount)); 1403 return; 1404 } 1405 arcmsr_report_ccb_state(acb, pCCB, error); 1406 } 1407 1408 static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb) 1409 { 1410 int i = 0; 1411 uint32_t flag_ccb; 1412 struct ARCMSR_CDB *pARCMSR_CDB; 1413 bool error; 1414 struct CommandControlBlock *pCCB; 1415 unsigned long ccb_cdb_phy, cdb_phy_hipart; 1416 1417 switch (acb->adapter_type) { 1418 1419 case ACB_ADAPTER_TYPE_A: { 1420 struct MessageUnit_A __iomem *reg = acb->pmuA; 1421 uint32_t outbound_intstatus; 1422 outbound_intstatus = readl(®->outbound_intstatus) & 1423 acb->outbound_int_enable; 1424 /*clear and abort all outbound posted Q*/ 1425 writel(outbound_intstatus, ®->outbound_intstatus);/*clear interrupt*/ 1426 while(((flag_ccb = readl(®->outbound_queueport)) != 0xFFFFFFFF) 1427 && (i++ < acb->maxOutstanding)) { 1428 ccb_cdb_phy = (flag_ccb << 5) & 0xffffffff; 1429 if (acb->cdb_phyadd_hipart) 1430 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart; 1431 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy); 1432 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb); 1433 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false; 1434 arcmsr_drain_donequeue(acb, pCCB, error); 1435 } 1436 } 1437 break; 1438 1439 case ACB_ADAPTER_TYPE_B: { 1440 struct MessageUnit_B *reg = acb->pmuB; 1441 /*clear all outbound posted Q*/ 1442 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); /* clear doorbell interrupt */ 1443 for (i = 0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) { 1444 flag_ccb = reg->done_qbuffer[i]; 1445 if (flag_ccb != 0) { 1446 reg->done_qbuffer[i] = 0; 1447 ccb_cdb_phy = (flag_ccb << 5) & 0xffffffff; 1448 if (acb->cdb_phyadd_hipart) 1449 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart; 1450 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy); 1451 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb); 1452 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false; 1453 arcmsr_drain_donequeue(acb, pCCB, error); 1454 } 1455 reg->post_qbuffer[i] = 0; 1456 } 1457 reg->doneq_index = 0; 1458 reg->postq_index = 0; 1459 } 1460 break; 1461 case ACB_ADAPTER_TYPE_C: { 1462 struct MessageUnit_C __iomem *reg = acb->pmuC; 1463 while ((readl(®->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < acb->maxOutstanding)) { 1464 /*need to do*/ 1465 flag_ccb = readl(®->outbound_queueport_low); 1466 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0); 1467 if (acb->cdb_phyadd_hipart) 1468 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart; 1469 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy); 1470 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb); 1471 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false; 1472 arcmsr_drain_donequeue(acb, pCCB, error); 1473 } 1474 } 1475 break; 1476 case ACB_ADAPTER_TYPE_D: { 1477 struct MessageUnit_D *pmu = acb->pmuD; 1478 uint32_t outbound_write_pointer; 1479 uint32_t doneq_index, index_stripped, addressLow, residual, toggle; 1480 unsigned long flags; 1481 1482 residual = atomic_read(&acb->ccboutstandingcount); 1483 for (i = 0; i < residual; i++) { 1484 spin_lock_irqsave(&acb->doneq_lock, flags); 1485 outbound_write_pointer = 1486 pmu->done_qbuffer[0].addressLow + 1; 1487 doneq_index = pmu->doneq_index; 1488 if ((doneq_index & 0xFFF) != 1489 (outbound_write_pointer & 0xFFF)) { 1490 toggle = doneq_index & 0x4000; 1491 index_stripped = (doneq_index & 0xFFF) + 1; 1492 index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE; 1493 pmu->doneq_index = index_stripped ? (index_stripped | toggle) : 1494 ((toggle ^ 0x4000) + 1); 1495 doneq_index = pmu->doneq_index; 1496 spin_unlock_irqrestore(&acb->doneq_lock, flags); 1497 cdb_phy_hipart = pmu->done_qbuffer[doneq_index & 1498 0xFFF].addressHigh; 1499 addressLow = pmu->done_qbuffer[doneq_index & 1500 0xFFF].addressLow; 1501 ccb_cdb_phy = (addressLow & 0xFFFFFFF0); 1502 if (acb->cdb_phyadd_hipart) 1503 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart; 1504 pARCMSR_CDB = (struct ARCMSR_CDB *) 1505 (acb->vir2phy_offset + ccb_cdb_phy); 1506 pCCB = container_of(pARCMSR_CDB, 1507 struct CommandControlBlock, arcmsr_cdb); 1508 error = (addressLow & 1509 ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? 1510 true : false; 1511 arcmsr_drain_donequeue(acb, pCCB, error); 1512 writel(doneq_index, 1513 pmu->outboundlist_read_pointer); 1514 } else { 1515 spin_unlock_irqrestore(&acb->doneq_lock, flags); 1516 mdelay(10); 1517 } 1518 } 1519 pmu->postq_index = 0; 1520 pmu->doneq_index = 0x40FF; 1521 } 1522 break; 1523 case ACB_ADAPTER_TYPE_E: 1524 arcmsr_hbaE_postqueue_isr(acb); 1525 break; 1526 } 1527 } 1528 1529 static void arcmsr_remove_scsi_devices(struct AdapterControlBlock *acb) 1530 { 1531 char *acb_dev_map = (char *)acb->device_map; 1532 int target, lun, i; 1533 struct scsi_device *psdev; 1534 struct CommandControlBlock *ccb; 1535 char temp; 1536 1537 for (i = 0; i < acb->maxFreeCCB; i++) { 1538 ccb = acb->pccb_pool[i]; 1539 if (ccb->startdone == ARCMSR_CCB_START) { 1540 ccb->pcmd->result = DID_NO_CONNECT << 16; 1541 arcmsr_pci_unmap_dma(ccb); 1542 ccb->pcmd->scsi_done(ccb->pcmd); 1543 } 1544 } 1545 for (target = 0; target < ARCMSR_MAX_TARGETID; target++) { 1546 temp = *acb_dev_map; 1547 if (temp) { 1548 for (lun = 0; lun < ARCMSR_MAX_TARGETLUN; lun++) { 1549 if (temp & 1) { 1550 psdev = scsi_device_lookup(acb->host, 1551 0, target, lun); 1552 if (psdev != NULL) { 1553 scsi_remove_device(psdev); 1554 scsi_device_put(psdev); 1555 } 1556 } 1557 temp >>= 1; 1558 } 1559 *acb_dev_map = 0; 1560 } 1561 acb_dev_map++; 1562 } 1563 } 1564 1565 static void arcmsr_free_pcidev(struct AdapterControlBlock *acb) 1566 { 1567 struct pci_dev *pdev; 1568 struct Scsi_Host *host; 1569 1570 host = acb->host; 1571 arcmsr_free_sysfs_attr(acb); 1572 scsi_remove_host(host); 1573 flush_work(&acb->arcmsr_do_message_isr_bh); 1574 del_timer_sync(&acb->eternal_timer); 1575 if (set_date_time) 1576 del_timer_sync(&acb->refresh_timer); 1577 pdev = acb->pdev; 1578 arcmsr_free_irq(pdev, acb); 1579 arcmsr_free_ccb_pool(acb); 1580 arcmsr_unmap_pciregion(acb); 1581 pci_release_regions(pdev); 1582 scsi_host_put(host); 1583 pci_disable_device(pdev); 1584 } 1585 1586 static void arcmsr_remove(struct pci_dev *pdev) 1587 { 1588 struct Scsi_Host *host = pci_get_drvdata(pdev); 1589 struct AdapterControlBlock *acb = 1590 (struct AdapterControlBlock *) host->hostdata; 1591 int poll_count = 0; 1592 uint16_t dev_id; 1593 1594 pci_read_config_word(pdev, PCI_DEVICE_ID, &dev_id); 1595 if (dev_id == 0xffff) { 1596 acb->acb_flags &= ~ACB_F_IOP_INITED; 1597 acb->acb_flags |= ACB_F_ADAPTER_REMOVED; 1598 arcmsr_remove_scsi_devices(acb); 1599 arcmsr_free_pcidev(acb); 1600 return; 1601 } 1602 arcmsr_free_sysfs_attr(acb); 1603 scsi_remove_host(host); 1604 flush_work(&acb->arcmsr_do_message_isr_bh); 1605 del_timer_sync(&acb->eternal_timer); 1606 if (set_date_time) 1607 del_timer_sync(&acb->refresh_timer); 1608 arcmsr_disable_outbound_ints(acb); 1609 arcmsr_stop_adapter_bgrb(acb); 1610 arcmsr_flush_adapter_cache(acb); 1611 acb->acb_flags |= ACB_F_SCSISTOPADAPTER; 1612 acb->acb_flags &= ~ACB_F_IOP_INITED; 1613 1614 for (poll_count = 0; poll_count < acb->maxOutstanding; poll_count++){ 1615 if (!atomic_read(&acb->ccboutstandingcount)) 1616 break; 1617 arcmsr_interrupt(acb);/* FIXME: need spinlock */ 1618 msleep(25); 1619 } 1620 1621 if (atomic_read(&acb->ccboutstandingcount)) { 1622 int i; 1623 1624 arcmsr_abort_allcmd(acb); 1625 arcmsr_done4abort_postqueue(acb); 1626 for (i = 0; i < acb->maxFreeCCB; i++) { 1627 struct CommandControlBlock *ccb = acb->pccb_pool[i]; 1628 if (ccb->startdone == ARCMSR_CCB_START) { 1629 ccb->startdone = ARCMSR_CCB_ABORTED; 1630 ccb->pcmd->result = DID_ABORT << 16; 1631 arcmsr_ccb_complete(ccb); 1632 } 1633 } 1634 } 1635 arcmsr_free_irq(pdev, acb); 1636 arcmsr_free_ccb_pool(acb); 1637 arcmsr_unmap_pciregion(acb); 1638 pci_release_regions(pdev); 1639 scsi_host_put(host); 1640 pci_disable_device(pdev); 1641 } 1642 1643 static void arcmsr_shutdown(struct pci_dev *pdev) 1644 { 1645 struct Scsi_Host *host = pci_get_drvdata(pdev); 1646 struct AdapterControlBlock *acb = 1647 (struct AdapterControlBlock *)host->hostdata; 1648 if (acb->acb_flags & ACB_F_ADAPTER_REMOVED) 1649 return; 1650 del_timer_sync(&acb->eternal_timer); 1651 if (set_date_time) 1652 del_timer_sync(&acb->refresh_timer); 1653 arcmsr_disable_outbound_ints(acb); 1654 arcmsr_free_irq(pdev, acb); 1655 flush_work(&acb->arcmsr_do_message_isr_bh); 1656 arcmsr_stop_adapter_bgrb(acb); 1657 arcmsr_flush_adapter_cache(acb); 1658 } 1659 1660 static int arcmsr_module_init(void) 1661 { 1662 int error = 0; 1663 error = pci_register_driver(&arcmsr_pci_driver); 1664 return error; 1665 } 1666 1667 static void arcmsr_module_exit(void) 1668 { 1669 pci_unregister_driver(&arcmsr_pci_driver); 1670 } 1671 module_init(arcmsr_module_init); 1672 module_exit(arcmsr_module_exit); 1673 1674 static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb, 1675 u32 intmask_org) 1676 { 1677 u32 mask; 1678 switch (acb->adapter_type) { 1679 1680 case ACB_ADAPTER_TYPE_A: { 1681 struct MessageUnit_A __iomem *reg = acb->pmuA; 1682 mask = intmask_org & ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE | 1683 ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE| 1684 ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE); 1685 writel(mask, ®->outbound_intmask); 1686 acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff; 1687 } 1688 break; 1689 1690 case ACB_ADAPTER_TYPE_B: { 1691 struct MessageUnit_B *reg = acb->pmuB; 1692 mask = intmask_org | (ARCMSR_IOP2DRV_DATA_WRITE_OK | 1693 ARCMSR_IOP2DRV_DATA_READ_OK | 1694 ARCMSR_IOP2DRV_CDB_DONE | 1695 ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); 1696 writel(mask, reg->iop2drv_doorbell_mask); 1697 acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f; 1698 } 1699 break; 1700 case ACB_ADAPTER_TYPE_C: { 1701 struct MessageUnit_C __iomem *reg = acb->pmuC; 1702 mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK|ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK); 1703 writel(intmask_org & mask, ®->host_int_mask); 1704 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f; 1705 } 1706 break; 1707 case ACB_ADAPTER_TYPE_D: { 1708 struct MessageUnit_D *reg = acb->pmuD; 1709 1710 mask = ARCMSR_ARC1214_ALL_INT_ENABLE; 1711 writel(intmask_org | mask, reg->pcief0_int_enable); 1712 break; 1713 } 1714 case ACB_ADAPTER_TYPE_E: { 1715 struct MessageUnit_E __iomem *reg = acb->pmuE; 1716 1717 mask = ~(ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR); 1718 writel(intmask_org & mask, ®->host_int_mask); 1719 break; 1720 } 1721 } 1722 } 1723 1724 static int arcmsr_build_ccb(struct AdapterControlBlock *acb, 1725 struct CommandControlBlock *ccb, struct scsi_cmnd *pcmd) 1726 { 1727 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb; 1728 int8_t *psge = (int8_t *)&arcmsr_cdb->u; 1729 __le32 address_lo, address_hi; 1730 int arccdbsize = 0x30; 1731 __le32 length = 0; 1732 int i; 1733 struct scatterlist *sg; 1734 int nseg; 1735 ccb->pcmd = pcmd; 1736 memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB)); 1737 arcmsr_cdb->TargetID = pcmd->device->id; 1738 arcmsr_cdb->LUN = pcmd->device->lun; 1739 arcmsr_cdb->Function = 1; 1740 arcmsr_cdb->msgContext = 0; 1741 memcpy(arcmsr_cdb->Cdb, pcmd->cmnd, pcmd->cmd_len); 1742 1743 nseg = scsi_dma_map(pcmd); 1744 if (unlikely(nseg > acb->host->sg_tablesize || nseg < 0)) 1745 return FAILED; 1746 scsi_for_each_sg(pcmd, sg, nseg, i) { 1747 /* Get the physical address of the current data pointer */ 1748 length = cpu_to_le32(sg_dma_len(sg)); 1749 address_lo = cpu_to_le32(dma_addr_lo32(sg_dma_address(sg))); 1750 address_hi = cpu_to_le32(dma_addr_hi32(sg_dma_address(sg))); 1751 if (address_hi == 0) { 1752 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge; 1753 1754 pdma_sg->address = address_lo; 1755 pdma_sg->length = length; 1756 psge += sizeof (struct SG32ENTRY); 1757 arccdbsize += sizeof (struct SG32ENTRY); 1758 } else { 1759 struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge; 1760 1761 pdma_sg->addresshigh = address_hi; 1762 pdma_sg->address = address_lo; 1763 pdma_sg->length = length|cpu_to_le32(IS_SG64_ADDR); 1764 psge += sizeof (struct SG64ENTRY); 1765 arccdbsize += sizeof (struct SG64ENTRY); 1766 } 1767 } 1768 arcmsr_cdb->sgcount = (uint8_t)nseg; 1769 arcmsr_cdb->DataLength = scsi_bufflen(pcmd); 1770 arcmsr_cdb->msgPages = arccdbsize/0x100 + (arccdbsize % 0x100 ? 1 : 0); 1771 if ( arccdbsize > 256) 1772 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE; 1773 if (pcmd->sc_data_direction == DMA_TO_DEVICE) 1774 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE; 1775 ccb->arc_cdb_size = arccdbsize; 1776 return SUCCESS; 1777 } 1778 1779 static void arcmsr_post_ccb(struct AdapterControlBlock *acb, struct CommandControlBlock *ccb) 1780 { 1781 uint32_t cdb_phyaddr = ccb->cdb_phyaddr; 1782 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb; 1783 atomic_inc(&acb->ccboutstandingcount); 1784 ccb->startdone = ARCMSR_CCB_START; 1785 switch (acb->adapter_type) { 1786 case ACB_ADAPTER_TYPE_A: { 1787 struct MessageUnit_A __iomem *reg = acb->pmuA; 1788 1789 if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) 1790 writel(cdb_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE, 1791 ®->inbound_queueport); 1792 else 1793 writel(cdb_phyaddr, ®->inbound_queueport); 1794 break; 1795 } 1796 1797 case ACB_ADAPTER_TYPE_B: { 1798 struct MessageUnit_B *reg = acb->pmuB; 1799 uint32_t ending_index, index = reg->postq_index; 1800 1801 ending_index = ((index + 1) % ARCMSR_MAX_HBB_POSTQUEUE); 1802 reg->post_qbuffer[ending_index] = 0; 1803 if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1804 reg->post_qbuffer[index] = 1805 cdb_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE; 1806 } else { 1807 reg->post_qbuffer[index] = cdb_phyaddr; 1808 } 1809 index++; 1810 index %= ARCMSR_MAX_HBB_POSTQUEUE;/*if last index number set it to 0 */ 1811 reg->postq_index = index; 1812 writel(ARCMSR_DRV2IOP_CDB_POSTED, reg->drv2iop_doorbell); 1813 } 1814 break; 1815 case ACB_ADAPTER_TYPE_C: { 1816 struct MessageUnit_C __iomem *phbcmu = acb->pmuC; 1817 uint32_t ccb_post_stamp, arc_cdb_size; 1818 1819 arc_cdb_size = (ccb->arc_cdb_size > 0x300) ? 0x300 : ccb->arc_cdb_size; 1820 ccb_post_stamp = (cdb_phyaddr | ((arc_cdb_size - 1) >> 6) | 1); 1821 writel(upper_32_bits(ccb->cdb_phyaddr), &phbcmu->inbound_queueport_high); 1822 writel(ccb_post_stamp, &phbcmu->inbound_queueport_low); 1823 } 1824 break; 1825 case ACB_ADAPTER_TYPE_D: { 1826 struct MessageUnit_D *pmu = acb->pmuD; 1827 u16 index_stripped; 1828 u16 postq_index, toggle; 1829 unsigned long flags; 1830 struct InBound_SRB *pinbound_srb; 1831 1832 spin_lock_irqsave(&acb->postq_lock, flags); 1833 postq_index = pmu->postq_index; 1834 pinbound_srb = (struct InBound_SRB *)&(pmu->post_qbuffer[postq_index & 0xFF]); 1835 pinbound_srb->addressHigh = upper_32_bits(ccb->cdb_phyaddr); 1836 pinbound_srb->addressLow = cdb_phyaddr; 1837 pinbound_srb->length = ccb->arc_cdb_size >> 2; 1838 arcmsr_cdb->msgContext = dma_addr_lo32(cdb_phyaddr); 1839 toggle = postq_index & 0x4000; 1840 index_stripped = postq_index + 1; 1841 index_stripped &= (ARCMSR_MAX_ARC1214_POSTQUEUE - 1); 1842 pmu->postq_index = index_stripped ? (index_stripped | toggle) : 1843 (toggle ^ 0x4000); 1844 writel(postq_index, pmu->inboundlist_write_pointer); 1845 spin_unlock_irqrestore(&acb->postq_lock, flags); 1846 break; 1847 } 1848 case ACB_ADAPTER_TYPE_E: { 1849 struct MessageUnit_E __iomem *pmu = acb->pmuE; 1850 u32 ccb_post_stamp, arc_cdb_size; 1851 1852 arc_cdb_size = (ccb->arc_cdb_size > 0x300) ? 0x300 : ccb->arc_cdb_size; 1853 ccb_post_stamp = (ccb->smid | ((arc_cdb_size - 1) >> 6)); 1854 writel(0, &pmu->inbound_queueport_high); 1855 writel(ccb_post_stamp, &pmu->inbound_queueport_low); 1856 break; 1857 } 1858 } 1859 } 1860 1861 static void arcmsr_hbaA_stop_bgrb(struct AdapterControlBlock *acb) 1862 { 1863 struct MessageUnit_A __iomem *reg = acb->pmuA; 1864 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1865 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, ®->inbound_msgaddr0); 1866 if (!arcmsr_hbaA_wait_msgint_ready(acb)) { 1867 printk(KERN_NOTICE 1868 "arcmsr%d: wait 'stop adapter background rebuild' timeout\n" 1869 , acb->host->host_no); 1870 } 1871 } 1872 1873 static void arcmsr_hbaB_stop_bgrb(struct AdapterControlBlock *acb) 1874 { 1875 struct MessageUnit_B *reg = acb->pmuB; 1876 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1877 writel(ARCMSR_MESSAGE_STOP_BGRB, reg->drv2iop_doorbell); 1878 1879 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 1880 printk(KERN_NOTICE 1881 "arcmsr%d: wait 'stop adapter background rebuild' timeout\n" 1882 , acb->host->host_no); 1883 } 1884 } 1885 1886 static void arcmsr_hbaC_stop_bgrb(struct AdapterControlBlock *pACB) 1887 { 1888 struct MessageUnit_C __iomem *reg = pACB->pmuC; 1889 pACB->acb_flags &= ~ACB_F_MSG_START_BGRB; 1890 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, ®->inbound_msgaddr0); 1891 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell); 1892 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) { 1893 printk(KERN_NOTICE 1894 "arcmsr%d: wait 'stop adapter background rebuild' timeout\n" 1895 , pACB->host->host_no); 1896 } 1897 return; 1898 } 1899 1900 static void arcmsr_hbaD_stop_bgrb(struct AdapterControlBlock *pACB) 1901 { 1902 struct MessageUnit_D *reg = pACB->pmuD; 1903 1904 pACB->acb_flags &= ~ACB_F_MSG_START_BGRB; 1905 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, reg->inbound_msgaddr0); 1906 if (!arcmsr_hbaD_wait_msgint_ready(pACB)) 1907 pr_notice("arcmsr%d: wait 'stop adapter background rebuild' " 1908 "timeout\n", pACB->host->host_no); 1909 } 1910 1911 static void arcmsr_hbaE_stop_bgrb(struct AdapterControlBlock *pACB) 1912 { 1913 struct MessageUnit_E __iomem *reg = pACB->pmuE; 1914 1915 pACB->acb_flags &= ~ACB_F_MSG_START_BGRB; 1916 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, ®->inbound_msgaddr0); 1917 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 1918 writel(pACB->out_doorbell, ®->iobound_doorbell); 1919 if (!arcmsr_hbaE_wait_msgint_ready(pACB)) { 1920 pr_notice("arcmsr%d: wait 'stop adapter background rebuild' " 1921 "timeout\n", pACB->host->host_no); 1922 } 1923 } 1924 1925 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb) 1926 { 1927 switch (acb->adapter_type) { 1928 case ACB_ADAPTER_TYPE_A: { 1929 arcmsr_hbaA_stop_bgrb(acb); 1930 } 1931 break; 1932 1933 case ACB_ADAPTER_TYPE_B: { 1934 arcmsr_hbaB_stop_bgrb(acb); 1935 } 1936 break; 1937 case ACB_ADAPTER_TYPE_C: { 1938 arcmsr_hbaC_stop_bgrb(acb); 1939 } 1940 break; 1941 case ACB_ADAPTER_TYPE_D: 1942 arcmsr_hbaD_stop_bgrb(acb); 1943 break; 1944 case ACB_ADAPTER_TYPE_E: 1945 arcmsr_hbaE_stop_bgrb(acb); 1946 break; 1947 } 1948 } 1949 1950 static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb) 1951 { 1952 dma_free_coherent(&acb->pdev->dev, acb->uncache_size, acb->dma_coherent, acb->dma_coherent_handle); 1953 } 1954 1955 static void arcmsr_iop_message_read(struct AdapterControlBlock *acb) 1956 { 1957 switch (acb->adapter_type) { 1958 case ACB_ADAPTER_TYPE_A: { 1959 struct MessageUnit_A __iomem *reg = acb->pmuA; 1960 writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, ®->inbound_doorbell); 1961 } 1962 break; 1963 1964 case ACB_ADAPTER_TYPE_B: { 1965 struct MessageUnit_B *reg = acb->pmuB; 1966 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell); 1967 } 1968 break; 1969 case ACB_ADAPTER_TYPE_C: { 1970 struct MessageUnit_C __iomem *reg = acb->pmuC; 1971 1972 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, ®->inbound_doorbell); 1973 } 1974 break; 1975 case ACB_ADAPTER_TYPE_D: { 1976 struct MessageUnit_D *reg = acb->pmuD; 1977 writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ, 1978 reg->inbound_doorbell); 1979 } 1980 break; 1981 case ACB_ADAPTER_TYPE_E: { 1982 struct MessageUnit_E __iomem *reg = acb->pmuE; 1983 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK; 1984 writel(acb->out_doorbell, ®->iobound_doorbell); 1985 } 1986 break; 1987 } 1988 } 1989 1990 static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb) 1991 { 1992 switch (acb->adapter_type) { 1993 case ACB_ADAPTER_TYPE_A: { 1994 struct MessageUnit_A __iomem *reg = acb->pmuA; 1995 /* 1996 ** push inbound doorbell tell iop, driver data write ok 1997 ** and wait reply on next hwinterrupt for next Qbuffer post 1998 */ 1999 writel(ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK, ®->inbound_doorbell); 2000 } 2001 break; 2002 2003 case ACB_ADAPTER_TYPE_B: { 2004 struct MessageUnit_B *reg = acb->pmuB; 2005 /* 2006 ** push inbound doorbell tell iop, driver data write ok 2007 ** and wait reply on next hwinterrupt for next Qbuffer post 2008 */ 2009 writel(ARCMSR_DRV2IOP_DATA_WRITE_OK, reg->drv2iop_doorbell); 2010 } 2011 break; 2012 case ACB_ADAPTER_TYPE_C: { 2013 struct MessageUnit_C __iomem *reg = acb->pmuC; 2014 /* 2015 ** push inbound doorbell tell iop, driver data write ok 2016 ** and wait reply on next hwinterrupt for next Qbuffer post 2017 */ 2018 writel(ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK, ®->inbound_doorbell); 2019 } 2020 break; 2021 case ACB_ADAPTER_TYPE_D: { 2022 struct MessageUnit_D *reg = acb->pmuD; 2023 writel(ARCMSR_ARC1214_DRV2IOP_DATA_IN_READY, 2024 reg->inbound_doorbell); 2025 } 2026 break; 2027 case ACB_ADAPTER_TYPE_E: { 2028 struct MessageUnit_E __iomem *reg = acb->pmuE; 2029 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK; 2030 writel(acb->out_doorbell, ®->iobound_doorbell); 2031 } 2032 break; 2033 } 2034 } 2035 2036 struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *acb) 2037 { 2038 struct QBUFFER __iomem *qbuffer = NULL; 2039 switch (acb->adapter_type) { 2040 2041 case ACB_ADAPTER_TYPE_A: { 2042 struct MessageUnit_A __iomem *reg = acb->pmuA; 2043 qbuffer = (struct QBUFFER __iomem *)®->message_rbuffer; 2044 } 2045 break; 2046 2047 case ACB_ADAPTER_TYPE_B: { 2048 struct MessageUnit_B *reg = acb->pmuB; 2049 qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer; 2050 } 2051 break; 2052 case ACB_ADAPTER_TYPE_C: { 2053 struct MessageUnit_C __iomem *phbcmu = acb->pmuC; 2054 qbuffer = (struct QBUFFER __iomem *)&phbcmu->message_rbuffer; 2055 } 2056 break; 2057 case ACB_ADAPTER_TYPE_D: { 2058 struct MessageUnit_D *reg = acb->pmuD; 2059 qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer; 2060 } 2061 break; 2062 case ACB_ADAPTER_TYPE_E: { 2063 struct MessageUnit_E __iomem *reg = acb->pmuE; 2064 qbuffer = (struct QBUFFER __iomem *)®->message_rbuffer; 2065 } 2066 break; 2067 } 2068 return qbuffer; 2069 } 2070 2071 static struct QBUFFER __iomem *arcmsr_get_iop_wqbuffer(struct AdapterControlBlock *acb) 2072 { 2073 struct QBUFFER __iomem *pqbuffer = NULL; 2074 switch (acb->adapter_type) { 2075 2076 case ACB_ADAPTER_TYPE_A: { 2077 struct MessageUnit_A __iomem *reg = acb->pmuA; 2078 pqbuffer = (struct QBUFFER __iomem *) ®->message_wbuffer; 2079 } 2080 break; 2081 2082 case ACB_ADAPTER_TYPE_B: { 2083 struct MessageUnit_B *reg = acb->pmuB; 2084 pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer; 2085 } 2086 break; 2087 case ACB_ADAPTER_TYPE_C: { 2088 struct MessageUnit_C __iomem *reg = acb->pmuC; 2089 pqbuffer = (struct QBUFFER __iomem *)®->message_wbuffer; 2090 } 2091 break; 2092 case ACB_ADAPTER_TYPE_D: { 2093 struct MessageUnit_D *reg = acb->pmuD; 2094 pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer; 2095 } 2096 break; 2097 case ACB_ADAPTER_TYPE_E: { 2098 struct MessageUnit_E __iomem *reg = acb->pmuE; 2099 pqbuffer = (struct QBUFFER __iomem *)®->message_wbuffer; 2100 } 2101 break; 2102 } 2103 return pqbuffer; 2104 } 2105 2106 static uint32_t 2107 arcmsr_Read_iop_rqbuffer_in_DWORD(struct AdapterControlBlock *acb, 2108 struct QBUFFER __iomem *prbuffer) 2109 { 2110 uint8_t *pQbuffer; 2111 uint8_t *buf1 = NULL; 2112 uint32_t __iomem *iop_data; 2113 uint32_t iop_len, data_len, *buf2 = NULL; 2114 2115 iop_data = (uint32_t __iomem *)prbuffer->data; 2116 iop_len = readl(&prbuffer->data_len); 2117 if (iop_len > 0) { 2118 buf1 = kmalloc(128, GFP_ATOMIC); 2119 buf2 = (uint32_t *)buf1; 2120 if (buf1 == NULL) 2121 return 0; 2122 data_len = iop_len; 2123 while (data_len >= 4) { 2124 *buf2++ = readl(iop_data); 2125 iop_data++; 2126 data_len -= 4; 2127 } 2128 if (data_len) 2129 *buf2 = readl(iop_data); 2130 buf2 = (uint32_t *)buf1; 2131 } 2132 while (iop_len > 0) { 2133 pQbuffer = &acb->rqbuffer[acb->rqbuf_putIndex]; 2134 *pQbuffer = *buf1; 2135 acb->rqbuf_putIndex++; 2136 /* if last, index number set it to 0 */ 2137 acb->rqbuf_putIndex %= ARCMSR_MAX_QBUFFER; 2138 buf1++; 2139 iop_len--; 2140 } 2141 kfree(buf2); 2142 /* let IOP know data has been read */ 2143 arcmsr_iop_message_read(acb); 2144 return 1; 2145 } 2146 2147 uint32_t 2148 arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, 2149 struct QBUFFER __iomem *prbuffer) { 2150 2151 uint8_t *pQbuffer; 2152 uint8_t __iomem *iop_data; 2153 uint32_t iop_len; 2154 2155 if (acb->adapter_type > ACB_ADAPTER_TYPE_B) 2156 return arcmsr_Read_iop_rqbuffer_in_DWORD(acb, prbuffer); 2157 iop_data = (uint8_t __iomem *)prbuffer->data; 2158 iop_len = readl(&prbuffer->data_len); 2159 while (iop_len > 0) { 2160 pQbuffer = &acb->rqbuffer[acb->rqbuf_putIndex]; 2161 *pQbuffer = readb(iop_data); 2162 acb->rqbuf_putIndex++; 2163 acb->rqbuf_putIndex %= ARCMSR_MAX_QBUFFER; 2164 iop_data++; 2165 iop_len--; 2166 } 2167 arcmsr_iop_message_read(acb); 2168 return 1; 2169 } 2170 2171 static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb) 2172 { 2173 unsigned long flags; 2174 struct QBUFFER __iomem *prbuffer; 2175 int32_t buf_empty_len; 2176 2177 spin_lock_irqsave(&acb->rqbuffer_lock, flags); 2178 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2179 buf_empty_len = (acb->rqbuf_putIndex - acb->rqbuf_getIndex - 1) & 2180 (ARCMSR_MAX_QBUFFER - 1); 2181 if (buf_empty_len >= readl(&prbuffer->data_len)) { 2182 if (arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 2183 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2184 } else 2185 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2186 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags); 2187 } 2188 2189 static void arcmsr_write_ioctldata2iop_in_DWORD(struct AdapterControlBlock *acb) 2190 { 2191 uint8_t *pQbuffer; 2192 struct QBUFFER __iomem *pwbuffer; 2193 uint8_t *buf1 = NULL; 2194 uint32_t __iomem *iop_data; 2195 uint32_t allxfer_len = 0, data_len, *buf2 = NULL, data; 2196 2197 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) { 2198 buf1 = kmalloc(128, GFP_ATOMIC); 2199 buf2 = (uint32_t *)buf1; 2200 if (buf1 == NULL) 2201 return; 2202 2203 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED); 2204 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 2205 iop_data = (uint32_t __iomem *)pwbuffer->data; 2206 while ((acb->wqbuf_getIndex != acb->wqbuf_putIndex) 2207 && (allxfer_len < 124)) { 2208 pQbuffer = &acb->wqbuffer[acb->wqbuf_getIndex]; 2209 *buf1 = *pQbuffer; 2210 acb->wqbuf_getIndex++; 2211 acb->wqbuf_getIndex %= ARCMSR_MAX_QBUFFER; 2212 buf1++; 2213 allxfer_len++; 2214 } 2215 data_len = allxfer_len; 2216 buf1 = (uint8_t *)buf2; 2217 while (data_len >= 4) { 2218 data = *buf2++; 2219 writel(data, iop_data); 2220 iop_data++; 2221 data_len -= 4; 2222 } 2223 if (data_len) { 2224 data = *buf2; 2225 writel(data, iop_data); 2226 } 2227 writel(allxfer_len, &pwbuffer->data_len); 2228 kfree(buf1); 2229 arcmsr_iop_message_wrote(acb); 2230 } 2231 } 2232 2233 void 2234 arcmsr_write_ioctldata2iop(struct AdapterControlBlock *acb) 2235 { 2236 uint8_t *pQbuffer; 2237 struct QBUFFER __iomem *pwbuffer; 2238 uint8_t __iomem *iop_data; 2239 int32_t allxfer_len = 0; 2240 2241 if (acb->adapter_type > ACB_ADAPTER_TYPE_B) { 2242 arcmsr_write_ioctldata2iop_in_DWORD(acb); 2243 return; 2244 } 2245 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) { 2246 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED); 2247 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 2248 iop_data = (uint8_t __iomem *)pwbuffer->data; 2249 while ((acb->wqbuf_getIndex != acb->wqbuf_putIndex) 2250 && (allxfer_len < 124)) { 2251 pQbuffer = &acb->wqbuffer[acb->wqbuf_getIndex]; 2252 writeb(*pQbuffer, iop_data); 2253 acb->wqbuf_getIndex++; 2254 acb->wqbuf_getIndex %= ARCMSR_MAX_QBUFFER; 2255 iop_data++; 2256 allxfer_len++; 2257 } 2258 writel(allxfer_len, &pwbuffer->data_len); 2259 arcmsr_iop_message_wrote(acb); 2260 } 2261 } 2262 2263 static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb) 2264 { 2265 unsigned long flags; 2266 2267 spin_lock_irqsave(&acb->wqbuffer_lock, flags); 2268 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READED; 2269 if (acb->wqbuf_getIndex != acb->wqbuf_putIndex) 2270 arcmsr_write_ioctldata2iop(acb); 2271 if (acb->wqbuf_getIndex == acb->wqbuf_putIndex) 2272 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED; 2273 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags); 2274 } 2275 2276 static void arcmsr_hbaA_doorbell_isr(struct AdapterControlBlock *acb) 2277 { 2278 uint32_t outbound_doorbell; 2279 struct MessageUnit_A __iomem *reg = acb->pmuA; 2280 outbound_doorbell = readl(®->outbound_doorbell); 2281 do { 2282 writel(outbound_doorbell, ®->outbound_doorbell); 2283 if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) 2284 arcmsr_iop2drv_data_wrote_handle(acb); 2285 if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) 2286 arcmsr_iop2drv_data_read_handle(acb); 2287 outbound_doorbell = readl(®->outbound_doorbell); 2288 } while (outbound_doorbell & (ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 2289 | ARCMSR_OUTBOUND_IOP331_DATA_READ_OK)); 2290 } 2291 static void arcmsr_hbaC_doorbell_isr(struct AdapterControlBlock *pACB) 2292 { 2293 uint32_t outbound_doorbell; 2294 struct MessageUnit_C __iomem *reg = pACB->pmuC; 2295 /* 2296 ******************************************************************* 2297 ** Maybe here we need to check wrqbuffer_lock is lock or not 2298 ** DOORBELL: din! don! 2299 ** check if there are any mail need to pack from firmware 2300 ******************************************************************* 2301 */ 2302 outbound_doorbell = readl(®->outbound_doorbell); 2303 do { 2304 writel(outbound_doorbell, ®->outbound_doorbell_clear); 2305 readl(®->outbound_doorbell_clear); 2306 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) 2307 arcmsr_iop2drv_data_wrote_handle(pACB); 2308 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) 2309 arcmsr_iop2drv_data_read_handle(pACB); 2310 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) 2311 arcmsr_hbaC_message_isr(pACB); 2312 outbound_doorbell = readl(®->outbound_doorbell); 2313 } while (outbound_doorbell & (ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 2314 | ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 2315 | ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE)); 2316 } 2317 2318 static void arcmsr_hbaD_doorbell_isr(struct AdapterControlBlock *pACB) 2319 { 2320 uint32_t outbound_doorbell; 2321 struct MessageUnit_D *pmu = pACB->pmuD; 2322 2323 outbound_doorbell = readl(pmu->outbound_doorbell); 2324 do { 2325 writel(outbound_doorbell, pmu->outbound_doorbell); 2326 if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE) 2327 arcmsr_hbaD_message_isr(pACB); 2328 if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK) 2329 arcmsr_iop2drv_data_wrote_handle(pACB); 2330 if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK) 2331 arcmsr_iop2drv_data_read_handle(pACB); 2332 outbound_doorbell = readl(pmu->outbound_doorbell); 2333 } while (outbound_doorbell & (ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK 2334 | ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK 2335 | ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE)); 2336 } 2337 2338 static void arcmsr_hbaE_doorbell_isr(struct AdapterControlBlock *pACB) 2339 { 2340 uint32_t outbound_doorbell, in_doorbell, tmp; 2341 struct MessageUnit_E __iomem *reg = pACB->pmuE; 2342 2343 in_doorbell = readl(®->iobound_doorbell); 2344 outbound_doorbell = in_doorbell ^ pACB->in_doorbell; 2345 do { 2346 writel(0, ®->host_int_status); /* clear interrupt */ 2347 if (outbound_doorbell & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) { 2348 arcmsr_iop2drv_data_wrote_handle(pACB); 2349 } 2350 if (outbound_doorbell & ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK) { 2351 arcmsr_iop2drv_data_read_handle(pACB); 2352 } 2353 if (outbound_doorbell & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) { 2354 arcmsr_hbaE_message_isr(pACB); 2355 } 2356 tmp = in_doorbell; 2357 in_doorbell = readl(®->iobound_doorbell); 2358 outbound_doorbell = tmp ^ in_doorbell; 2359 } while (outbound_doorbell & (ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK 2360 | ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK 2361 | ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE)); 2362 pACB->in_doorbell = in_doorbell; 2363 } 2364 2365 static void arcmsr_hbaA_postqueue_isr(struct AdapterControlBlock *acb) 2366 { 2367 uint32_t flag_ccb; 2368 struct MessageUnit_A __iomem *reg = acb->pmuA; 2369 struct ARCMSR_CDB *pARCMSR_CDB; 2370 struct CommandControlBlock *pCCB; 2371 bool error; 2372 unsigned long cdb_phy_addr; 2373 2374 while ((flag_ccb = readl(®->outbound_queueport)) != 0xFFFFFFFF) { 2375 cdb_phy_addr = (flag_ccb << 5) & 0xffffffff; 2376 if (acb->cdb_phyadd_hipart) 2377 cdb_phy_addr = cdb_phy_addr | acb->cdb_phyadd_hipart; 2378 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + cdb_phy_addr); 2379 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb); 2380 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false; 2381 arcmsr_drain_donequeue(acb, pCCB, error); 2382 } 2383 } 2384 static void arcmsr_hbaB_postqueue_isr(struct AdapterControlBlock *acb) 2385 { 2386 uint32_t index; 2387 uint32_t flag_ccb; 2388 struct MessageUnit_B *reg = acb->pmuB; 2389 struct ARCMSR_CDB *pARCMSR_CDB; 2390 struct CommandControlBlock *pCCB; 2391 bool error; 2392 unsigned long cdb_phy_addr; 2393 2394 index = reg->doneq_index; 2395 while ((flag_ccb = reg->done_qbuffer[index]) != 0) { 2396 cdb_phy_addr = (flag_ccb << 5) & 0xffffffff; 2397 if (acb->cdb_phyadd_hipart) 2398 cdb_phy_addr = cdb_phy_addr | acb->cdb_phyadd_hipart; 2399 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + cdb_phy_addr); 2400 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb); 2401 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false; 2402 arcmsr_drain_donequeue(acb, pCCB, error); 2403 reg->done_qbuffer[index] = 0; 2404 index++; 2405 index %= ARCMSR_MAX_HBB_POSTQUEUE; 2406 reg->doneq_index = index; 2407 } 2408 } 2409 2410 static void arcmsr_hbaC_postqueue_isr(struct AdapterControlBlock *acb) 2411 { 2412 struct MessageUnit_C __iomem *phbcmu; 2413 struct ARCMSR_CDB *arcmsr_cdb; 2414 struct CommandControlBlock *ccb; 2415 uint32_t flag_ccb, throttling = 0; 2416 unsigned long ccb_cdb_phy; 2417 int error; 2418 2419 phbcmu = acb->pmuC; 2420 /* areca cdb command done */ 2421 /* Use correct offset and size for syncing */ 2422 2423 while ((flag_ccb = readl(&phbcmu->outbound_queueport_low)) != 2424 0xFFFFFFFF) { 2425 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0); 2426 if (acb->cdb_phyadd_hipart) 2427 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart; 2428 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset 2429 + ccb_cdb_phy); 2430 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, 2431 arcmsr_cdb); 2432 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) 2433 ? true : false; 2434 /* check if command done with no error */ 2435 arcmsr_drain_donequeue(acb, ccb, error); 2436 throttling++; 2437 if (throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) { 2438 writel(ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING, 2439 &phbcmu->inbound_doorbell); 2440 throttling = 0; 2441 } 2442 } 2443 } 2444 2445 static void arcmsr_hbaD_postqueue_isr(struct AdapterControlBlock *acb) 2446 { 2447 u32 outbound_write_pointer, doneq_index, index_stripped, toggle; 2448 uint32_t addressLow; 2449 int error; 2450 struct MessageUnit_D *pmu; 2451 struct ARCMSR_CDB *arcmsr_cdb; 2452 struct CommandControlBlock *ccb; 2453 unsigned long flags, ccb_cdb_phy, cdb_phy_hipart; 2454 2455 spin_lock_irqsave(&acb->doneq_lock, flags); 2456 pmu = acb->pmuD; 2457 outbound_write_pointer = pmu->done_qbuffer[0].addressLow + 1; 2458 doneq_index = pmu->doneq_index; 2459 if ((doneq_index & 0xFFF) != (outbound_write_pointer & 0xFFF)) { 2460 do { 2461 toggle = doneq_index & 0x4000; 2462 index_stripped = (doneq_index & 0xFFF) + 1; 2463 index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE; 2464 pmu->doneq_index = index_stripped ? (index_stripped | toggle) : 2465 ((toggle ^ 0x4000) + 1); 2466 doneq_index = pmu->doneq_index; 2467 cdb_phy_hipart = pmu->done_qbuffer[doneq_index & 2468 0xFFF].addressHigh; 2469 addressLow = pmu->done_qbuffer[doneq_index & 2470 0xFFF].addressLow; 2471 ccb_cdb_phy = (addressLow & 0xFFFFFFF0); 2472 if (acb->cdb_phyadd_hipart) 2473 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart; 2474 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset 2475 + ccb_cdb_phy); 2476 ccb = container_of(arcmsr_cdb, 2477 struct CommandControlBlock, arcmsr_cdb); 2478 error = (addressLow & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) 2479 ? true : false; 2480 arcmsr_drain_donequeue(acb, ccb, error); 2481 writel(doneq_index, pmu->outboundlist_read_pointer); 2482 } while ((doneq_index & 0xFFF) != 2483 (outbound_write_pointer & 0xFFF)); 2484 } 2485 writel(ARCMSR_ARC1214_OUTBOUND_LIST_INTERRUPT_CLEAR, 2486 pmu->outboundlist_interrupt_cause); 2487 readl(pmu->outboundlist_interrupt_cause); 2488 spin_unlock_irqrestore(&acb->doneq_lock, flags); 2489 } 2490 2491 static void arcmsr_hbaE_postqueue_isr(struct AdapterControlBlock *acb) 2492 { 2493 uint32_t doneq_index; 2494 uint16_t cmdSMID; 2495 int error; 2496 struct MessageUnit_E __iomem *pmu; 2497 struct CommandControlBlock *ccb; 2498 unsigned long flags; 2499 2500 spin_lock_irqsave(&acb->doneq_lock, flags); 2501 doneq_index = acb->doneq_index; 2502 pmu = acb->pmuE; 2503 while ((readl(&pmu->reply_post_producer_index) & 0xFFFF) != doneq_index) { 2504 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID; 2505 ccb = acb->pccb_pool[cmdSMID]; 2506 error = (acb->pCompletionQ[doneq_index].cmdFlag 2507 & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false; 2508 arcmsr_drain_donequeue(acb, ccb, error); 2509 doneq_index++; 2510 if (doneq_index >= acb->completionQ_entry) 2511 doneq_index = 0; 2512 } 2513 acb->doneq_index = doneq_index; 2514 writel(doneq_index, &pmu->reply_post_consumer_index); 2515 spin_unlock_irqrestore(&acb->doneq_lock, flags); 2516 } 2517 2518 /* 2519 ********************************************************************************** 2520 ** Handle a message interrupt 2521 ** 2522 ** The only message interrupt we expect is in response to a query for the current adapter config. 2523 ** We want this in order to compare the drivemap so that we can detect newly-attached drives. 2524 ********************************************************************************** 2525 */ 2526 static void arcmsr_hbaA_message_isr(struct AdapterControlBlock *acb) 2527 { 2528 struct MessageUnit_A __iomem *reg = acb->pmuA; 2529 /*clear interrupt and message state*/ 2530 writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT, ®->outbound_intstatus); 2531 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG) 2532 schedule_work(&acb->arcmsr_do_message_isr_bh); 2533 } 2534 static void arcmsr_hbaB_message_isr(struct AdapterControlBlock *acb) 2535 { 2536 struct MessageUnit_B *reg = acb->pmuB; 2537 2538 /*clear interrupt and message state*/ 2539 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); 2540 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG) 2541 schedule_work(&acb->arcmsr_do_message_isr_bh); 2542 } 2543 /* 2544 ********************************************************************************** 2545 ** Handle a message interrupt 2546 ** 2547 ** The only message interrupt we expect is in response to a query for the 2548 ** current adapter config. 2549 ** We want this in order to compare the drivemap so that we can detect newly-attached drives. 2550 ********************************************************************************** 2551 */ 2552 static void arcmsr_hbaC_message_isr(struct AdapterControlBlock *acb) 2553 { 2554 struct MessageUnit_C __iomem *reg = acb->pmuC; 2555 /*clear interrupt and message state*/ 2556 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, ®->outbound_doorbell_clear); 2557 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG) 2558 schedule_work(&acb->arcmsr_do_message_isr_bh); 2559 } 2560 2561 static void arcmsr_hbaD_message_isr(struct AdapterControlBlock *acb) 2562 { 2563 struct MessageUnit_D *reg = acb->pmuD; 2564 2565 writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE, reg->outbound_doorbell); 2566 readl(reg->outbound_doorbell); 2567 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG) 2568 schedule_work(&acb->arcmsr_do_message_isr_bh); 2569 } 2570 2571 static void arcmsr_hbaE_message_isr(struct AdapterControlBlock *acb) 2572 { 2573 struct MessageUnit_E __iomem *reg = acb->pmuE; 2574 2575 writel(0, ®->host_int_status); 2576 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG) 2577 schedule_work(&acb->arcmsr_do_message_isr_bh); 2578 } 2579 2580 static int arcmsr_hbaA_handle_isr(struct AdapterControlBlock *acb) 2581 { 2582 uint32_t outbound_intstatus; 2583 struct MessageUnit_A __iomem *reg = acb->pmuA; 2584 outbound_intstatus = readl(®->outbound_intstatus) & 2585 acb->outbound_int_enable; 2586 if (!(outbound_intstatus & ARCMSR_MU_OUTBOUND_HANDLE_INT)) 2587 return IRQ_NONE; 2588 do { 2589 writel(outbound_intstatus, ®->outbound_intstatus); 2590 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) 2591 arcmsr_hbaA_doorbell_isr(acb); 2592 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) 2593 arcmsr_hbaA_postqueue_isr(acb); 2594 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) 2595 arcmsr_hbaA_message_isr(acb); 2596 outbound_intstatus = readl(®->outbound_intstatus) & 2597 acb->outbound_int_enable; 2598 } while (outbound_intstatus & (ARCMSR_MU_OUTBOUND_DOORBELL_INT 2599 | ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 2600 | ARCMSR_MU_OUTBOUND_MESSAGE0_INT)); 2601 return IRQ_HANDLED; 2602 } 2603 2604 static int arcmsr_hbaB_handle_isr(struct AdapterControlBlock *acb) 2605 { 2606 uint32_t outbound_doorbell; 2607 struct MessageUnit_B *reg = acb->pmuB; 2608 outbound_doorbell = readl(reg->iop2drv_doorbell) & 2609 acb->outbound_int_enable; 2610 if (!outbound_doorbell) 2611 return IRQ_NONE; 2612 do { 2613 writel(~outbound_doorbell, reg->iop2drv_doorbell); 2614 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell); 2615 if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) 2616 arcmsr_iop2drv_data_wrote_handle(acb); 2617 if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) 2618 arcmsr_iop2drv_data_read_handle(acb); 2619 if (outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) 2620 arcmsr_hbaB_postqueue_isr(acb); 2621 if (outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) 2622 arcmsr_hbaB_message_isr(acb); 2623 outbound_doorbell = readl(reg->iop2drv_doorbell) & 2624 acb->outbound_int_enable; 2625 } while (outbound_doorbell & (ARCMSR_IOP2DRV_DATA_WRITE_OK 2626 | ARCMSR_IOP2DRV_DATA_READ_OK 2627 | ARCMSR_IOP2DRV_CDB_DONE 2628 | ARCMSR_IOP2DRV_MESSAGE_CMD_DONE)); 2629 return IRQ_HANDLED; 2630 } 2631 2632 static int arcmsr_hbaC_handle_isr(struct AdapterControlBlock *pACB) 2633 { 2634 uint32_t host_interrupt_status; 2635 struct MessageUnit_C __iomem *phbcmu = pACB->pmuC; 2636 /* 2637 ********************************************* 2638 ** check outbound intstatus 2639 ********************************************* 2640 */ 2641 host_interrupt_status = readl(&phbcmu->host_int_status) & 2642 (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | 2643 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR); 2644 if (!host_interrupt_status) 2645 return IRQ_NONE; 2646 do { 2647 if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) 2648 arcmsr_hbaC_doorbell_isr(pACB); 2649 /* MU post queue interrupts*/ 2650 if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) 2651 arcmsr_hbaC_postqueue_isr(pACB); 2652 host_interrupt_status = readl(&phbcmu->host_int_status); 2653 } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | 2654 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR)); 2655 return IRQ_HANDLED; 2656 } 2657 2658 static irqreturn_t arcmsr_hbaD_handle_isr(struct AdapterControlBlock *pACB) 2659 { 2660 u32 host_interrupt_status; 2661 struct MessageUnit_D *pmu = pACB->pmuD; 2662 2663 host_interrupt_status = readl(pmu->host_int_status) & 2664 (ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR | 2665 ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR); 2666 if (!host_interrupt_status) 2667 return IRQ_NONE; 2668 do { 2669 /* MU post queue interrupts*/ 2670 if (host_interrupt_status & 2671 ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR) 2672 arcmsr_hbaD_postqueue_isr(pACB); 2673 if (host_interrupt_status & 2674 ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR) 2675 arcmsr_hbaD_doorbell_isr(pACB); 2676 host_interrupt_status = readl(pmu->host_int_status); 2677 } while (host_interrupt_status & 2678 (ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR | 2679 ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR)); 2680 return IRQ_HANDLED; 2681 } 2682 2683 static irqreturn_t arcmsr_hbaE_handle_isr(struct AdapterControlBlock *pACB) 2684 { 2685 uint32_t host_interrupt_status; 2686 struct MessageUnit_E __iomem *pmu = pACB->pmuE; 2687 2688 host_interrupt_status = readl(&pmu->host_int_status) & 2689 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | 2690 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR); 2691 if (!host_interrupt_status) 2692 return IRQ_NONE; 2693 do { 2694 /* MU ioctl transfer doorbell interrupts*/ 2695 if (host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) { 2696 arcmsr_hbaE_doorbell_isr(pACB); 2697 } 2698 /* MU post queue interrupts*/ 2699 if (host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) { 2700 arcmsr_hbaE_postqueue_isr(pACB); 2701 } 2702 host_interrupt_status = readl(&pmu->host_int_status); 2703 } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | 2704 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR)); 2705 return IRQ_HANDLED; 2706 } 2707 2708 static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb) 2709 { 2710 switch (acb->adapter_type) { 2711 case ACB_ADAPTER_TYPE_A: 2712 return arcmsr_hbaA_handle_isr(acb); 2713 break; 2714 case ACB_ADAPTER_TYPE_B: 2715 return arcmsr_hbaB_handle_isr(acb); 2716 break; 2717 case ACB_ADAPTER_TYPE_C: 2718 return arcmsr_hbaC_handle_isr(acb); 2719 case ACB_ADAPTER_TYPE_D: 2720 return arcmsr_hbaD_handle_isr(acb); 2721 case ACB_ADAPTER_TYPE_E: 2722 return arcmsr_hbaE_handle_isr(acb); 2723 default: 2724 return IRQ_NONE; 2725 } 2726 } 2727 2728 static void arcmsr_iop_parking(struct AdapterControlBlock *acb) 2729 { 2730 if (acb) { 2731 /* stop adapter background rebuild */ 2732 if (acb->acb_flags & ACB_F_MSG_START_BGRB) { 2733 uint32_t intmask_org; 2734 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 2735 intmask_org = arcmsr_disable_outbound_ints(acb); 2736 arcmsr_stop_adapter_bgrb(acb); 2737 arcmsr_flush_adapter_cache(acb); 2738 arcmsr_enable_outbound_ints(acb, intmask_org); 2739 } 2740 } 2741 } 2742 2743 2744 void arcmsr_clear_iop2drv_rqueue_buffer(struct AdapterControlBlock *acb) 2745 { 2746 uint32_t i; 2747 2748 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2749 for (i = 0; i < 15; i++) { 2750 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2751 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2752 acb->rqbuf_getIndex = 0; 2753 acb->rqbuf_putIndex = 0; 2754 arcmsr_iop_message_read(acb); 2755 mdelay(30); 2756 } else if (acb->rqbuf_getIndex != 2757 acb->rqbuf_putIndex) { 2758 acb->rqbuf_getIndex = 0; 2759 acb->rqbuf_putIndex = 0; 2760 mdelay(30); 2761 } else 2762 break; 2763 } 2764 } 2765 } 2766 2767 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, 2768 struct scsi_cmnd *cmd) 2769 { 2770 char *buffer; 2771 unsigned short use_sg; 2772 int retvalue = 0, transfer_len = 0; 2773 unsigned long flags; 2774 struct CMD_MESSAGE_FIELD *pcmdmessagefld; 2775 uint32_t controlcode = (uint32_t)cmd->cmnd[5] << 24 | 2776 (uint32_t)cmd->cmnd[6] << 16 | 2777 (uint32_t)cmd->cmnd[7] << 8 | 2778 (uint32_t)cmd->cmnd[8]; 2779 struct scatterlist *sg; 2780 2781 use_sg = scsi_sg_count(cmd); 2782 sg = scsi_sglist(cmd); 2783 buffer = kmap_atomic(sg_page(sg)) + sg->offset; 2784 if (use_sg > 1) { 2785 retvalue = ARCMSR_MESSAGE_FAIL; 2786 goto message_out; 2787 } 2788 transfer_len += sg->length; 2789 if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) { 2790 retvalue = ARCMSR_MESSAGE_FAIL; 2791 pr_info("%s: ARCMSR_MESSAGE_FAIL!\n", __func__); 2792 goto message_out; 2793 } 2794 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *)buffer; 2795 switch (controlcode) { 2796 case ARCMSR_MESSAGE_READ_RQBUFFER: { 2797 unsigned char *ver_addr; 2798 uint8_t *ptmpQbuffer; 2799 uint32_t allxfer_len = 0; 2800 ver_addr = kmalloc(ARCMSR_API_DATA_BUFLEN, GFP_ATOMIC); 2801 if (!ver_addr) { 2802 retvalue = ARCMSR_MESSAGE_FAIL; 2803 pr_info("%s: memory not enough!\n", __func__); 2804 goto message_out; 2805 } 2806 ptmpQbuffer = ver_addr; 2807 spin_lock_irqsave(&acb->rqbuffer_lock, flags); 2808 if (acb->rqbuf_getIndex != acb->rqbuf_putIndex) { 2809 unsigned int tail = acb->rqbuf_getIndex; 2810 unsigned int head = acb->rqbuf_putIndex; 2811 unsigned int cnt_to_end = CIRC_CNT_TO_END(head, tail, ARCMSR_MAX_QBUFFER); 2812 2813 allxfer_len = CIRC_CNT(head, tail, ARCMSR_MAX_QBUFFER); 2814 if (allxfer_len > ARCMSR_API_DATA_BUFLEN) 2815 allxfer_len = ARCMSR_API_DATA_BUFLEN; 2816 2817 if (allxfer_len <= cnt_to_end) 2818 memcpy(ptmpQbuffer, acb->rqbuffer + tail, allxfer_len); 2819 else { 2820 memcpy(ptmpQbuffer, acb->rqbuffer + tail, cnt_to_end); 2821 memcpy(ptmpQbuffer + cnt_to_end, acb->rqbuffer, allxfer_len - cnt_to_end); 2822 } 2823 acb->rqbuf_getIndex = (acb->rqbuf_getIndex + allxfer_len) % ARCMSR_MAX_QBUFFER; 2824 } 2825 memcpy(pcmdmessagefld->messagedatabuffer, ver_addr, 2826 allxfer_len); 2827 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2828 struct QBUFFER __iomem *prbuffer; 2829 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2830 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2831 if (arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 2832 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2833 } 2834 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags); 2835 kfree(ver_addr); 2836 pcmdmessagefld->cmdmessage.Length = allxfer_len; 2837 if (acb->fw_flag == FW_DEADLOCK) 2838 pcmdmessagefld->cmdmessage.ReturnCode = 2839 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON; 2840 else 2841 pcmdmessagefld->cmdmessage.ReturnCode = 2842 ARCMSR_MESSAGE_RETURNCODE_OK; 2843 break; 2844 } 2845 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 2846 unsigned char *ver_addr; 2847 uint32_t user_len; 2848 int32_t cnt2end; 2849 uint8_t *pQbuffer, *ptmpuserbuffer; 2850 2851 user_len = pcmdmessagefld->cmdmessage.Length; 2852 if (user_len > ARCMSR_API_DATA_BUFLEN) { 2853 retvalue = ARCMSR_MESSAGE_FAIL; 2854 goto message_out; 2855 } 2856 2857 ver_addr = kmalloc(ARCMSR_API_DATA_BUFLEN, GFP_ATOMIC); 2858 if (!ver_addr) { 2859 retvalue = ARCMSR_MESSAGE_FAIL; 2860 goto message_out; 2861 } 2862 ptmpuserbuffer = ver_addr; 2863 2864 memcpy(ptmpuserbuffer, 2865 pcmdmessagefld->messagedatabuffer, user_len); 2866 spin_lock_irqsave(&acb->wqbuffer_lock, flags); 2867 if (acb->wqbuf_putIndex != acb->wqbuf_getIndex) { 2868 struct SENSE_DATA *sensebuffer = 2869 (struct SENSE_DATA *)cmd->sense_buffer; 2870 arcmsr_write_ioctldata2iop(acb); 2871 /* has error report sensedata */ 2872 sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS; 2873 sensebuffer->SenseKey = ILLEGAL_REQUEST; 2874 sensebuffer->AdditionalSenseLength = 0x0A; 2875 sensebuffer->AdditionalSenseCode = 0x20; 2876 sensebuffer->Valid = 1; 2877 retvalue = ARCMSR_MESSAGE_FAIL; 2878 } else { 2879 pQbuffer = &acb->wqbuffer[acb->wqbuf_putIndex]; 2880 cnt2end = ARCMSR_MAX_QBUFFER - acb->wqbuf_putIndex; 2881 if (user_len > cnt2end) { 2882 memcpy(pQbuffer, ptmpuserbuffer, cnt2end); 2883 ptmpuserbuffer += cnt2end; 2884 user_len -= cnt2end; 2885 acb->wqbuf_putIndex = 0; 2886 pQbuffer = acb->wqbuffer; 2887 } 2888 memcpy(pQbuffer, ptmpuserbuffer, user_len); 2889 acb->wqbuf_putIndex += user_len; 2890 acb->wqbuf_putIndex %= ARCMSR_MAX_QBUFFER; 2891 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 2892 acb->acb_flags &= 2893 ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 2894 arcmsr_write_ioctldata2iop(acb); 2895 } 2896 } 2897 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags); 2898 kfree(ver_addr); 2899 if (acb->fw_flag == FW_DEADLOCK) 2900 pcmdmessagefld->cmdmessage.ReturnCode = 2901 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON; 2902 else 2903 pcmdmessagefld->cmdmessage.ReturnCode = 2904 ARCMSR_MESSAGE_RETURNCODE_OK; 2905 break; 2906 } 2907 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 2908 uint8_t *pQbuffer = acb->rqbuffer; 2909 2910 arcmsr_clear_iop2drv_rqueue_buffer(acb); 2911 spin_lock_irqsave(&acb->rqbuffer_lock, flags); 2912 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2913 acb->rqbuf_getIndex = 0; 2914 acb->rqbuf_putIndex = 0; 2915 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2916 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags); 2917 if (acb->fw_flag == FW_DEADLOCK) 2918 pcmdmessagefld->cmdmessage.ReturnCode = 2919 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON; 2920 else 2921 pcmdmessagefld->cmdmessage.ReturnCode = 2922 ARCMSR_MESSAGE_RETURNCODE_OK; 2923 break; 2924 } 2925 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: { 2926 uint8_t *pQbuffer = acb->wqbuffer; 2927 spin_lock_irqsave(&acb->wqbuffer_lock, flags); 2928 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED | 2929 ACB_F_MESSAGE_WQBUFFER_READED); 2930 acb->wqbuf_getIndex = 0; 2931 acb->wqbuf_putIndex = 0; 2932 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2933 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags); 2934 if (acb->fw_flag == FW_DEADLOCK) 2935 pcmdmessagefld->cmdmessage.ReturnCode = 2936 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON; 2937 else 2938 pcmdmessagefld->cmdmessage.ReturnCode = 2939 ARCMSR_MESSAGE_RETURNCODE_OK; 2940 break; 2941 } 2942 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 2943 uint8_t *pQbuffer; 2944 arcmsr_clear_iop2drv_rqueue_buffer(acb); 2945 spin_lock_irqsave(&acb->rqbuffer_lock, flags); 2946 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2947 acb->rqbuf_getIndex = 0; 2948 acb->rqbuf_putIndex = 0; 2949 pQbuffer = acb->rqbuffer; 2950 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2951 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags); 2952 spin_lock_irqsave(&acb->wqbuffer_lock, flags); 2953 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED | 2954 ACB_F_MESSAGE_WQBUFFER_READED); 2955 acb->wqbuf_getIndex = 0; 2956 acb->wqbuf_putIndex = 0; 2957 pQbuffer = acb->wqbuffer; 2958 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2959 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags); 2960 if (acb->fw_flag == FW_DEADLOCK) 2961 pcmdmessagefld->cmdmessage.ReturnCode = 2962 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON; 2963 else 2964 pcmdmessagefld->cmdmessage.ReturnCode = 2965 ARCMSR_MESSAGE_RETURNCODE_OK; 2966 break; 2967 } 2968 case ARCMSR_MESSAGE_RETURN_CODE_3F: { 2969 if (acb->fw_flag == FW_DEADLOCK) 2970 pcmdmessagefld->cmdmessage.ReturnCode = 2971 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON; 2972 else 2973 pcmdmessagefld->cmdmessage.ReturnCode = 2974 ARCMSR_MESSAGE_RETURNCODE_3F; 2975 break; 2976 } 2977 case ARCMSR_MESSAGE_SAY_HELLO: { 2978 int8_t *hello_string = "Hello! I am ARCMSR"; 2979 if (acb->fw_flag == FW_DEADLOCK) 2980 pcmdmessagefld->cmdmessage.ReturnCode = 2981 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON; 2982 else 2983 pcmdmessagefld->cmdmessage.ReturnCode = 2984 ARCMSR_MESSAGE_RETURNCODE_OK; 2985 memcpy(pcmdmessagefld->messagedatabuffer, 2986 hello_string, (int16_t)strlen(hello_string)); 2987 break; 2988 } 2989 case ARCMSR_MESSAGE_SAY_GOODBYE: { 2990 if (acb->fw_flag == FW_DEADLOCK) 2991 pcmdmessagefld->cmdmessage.ReturnCode = 2992 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON; 2993 else 2994 pcmdmessagefld->cmdmessage.ReturnCode = 2995 ARCMSR_MESSAGE_RETURNCODE_OK; 2996 arcmsr_iop_parking(acb); 2997 break; 2998 } 2999 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: { 3000 if (acb->fw_flag == FW_DEADLOCK) 3001 pcmdmessagefld->cmdmessage.ReturnCode = 3002 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON; 3003 else 3004 pcmdmessagefld->cmdmessage.ReturnCode = 3005 ARCMSR_MESSAGE_RETURNCODE_OK; 3006 arcmsr_flush_adapter_cache(acb); 3007 break; 3008 } 3009 default: 3010 retvalue = ARCMSR_MESSAGE_FAIL; 3011 pr_info("%s: unknown controlcode!\n", __func__); 3012 } 3013 message_out: 3014 if (use_sg) { 3015 struct scatterlist *sg = scsi_sglist(cmd); 3016 kunmap_atomic(buffer - sg->offset); 3017 } 3018 return retvalue; 3019 } 3020 3021 static struct CommandControlBlock *arcmsr_get_freeccb(struct AdapterControlBlock *acb) 3022 { 3023 struct list_head *head = &acb->ccb_free_list; 3024 struct CommandControlBlock *ccb = NULL; 3025 unsigned long flags; 3026 spin_lock_irqsave(&acb->ccblist_lock, flags); 3027 if (!list_empty(head)) { 3028 ccb = list_entry(head->next, struct CommandControlBlock, list); 3029 list_del_init(&ccb->list); 3030 }else{ 3031 spin_unlock_irqrestore(&acb->ccblist_lock, flags); 3032 return NULL; 3033 } 3034 spin_unlock_irqrestore(&acb->ccblist_lock, flags); 3035 return ccb; 3036 } 3037 3038 static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb, 3039 struct scsi_cmnd *cmd) 3040 { 3041 switch (cmd->cmnd[0]) { 3042 case INQUIRY: { 3043 unsigned char inqdata[36]; 3044 char *buffer; 3045 struct scatterlist *sg; 3046 3047 if (cmd->device->lun) { 3048 cmd->result = (DID_TIME_OUT << 16); 3049 cmd->scsi_done(cmd); 3050 return; 3051 } 3052 inqdata[0] = TYPE_PROCESSOR; 3053 /* Periph Qualifier & Periph Dev Type */ 3054 inqdata[1] = 0; 3055 /* rem media bit & Dev Type Modifier */ 3056 inqdata[2] = 0; 3057 /* ISO, ECMA, & ANSI versions */ 3058 inqdata[4] = 31; 3059 /* length of additional data */ 3060 strncpy(&inqdata[8], "Areca ", 8); 3061 /* Vendor Identification */ 3062 strncpy(&inqdata[16], "RAID controller ", 16); 3063 /* Product Identification */ 3064 strncpy(&inqdata[32], "R001", 4); /* Product Revision */ 3065 3066 sg = scsi_sglist(cmd); 3067 buffer = kmap_atomic(sg_page(sg)) + sg->offset; 3068 3069 memcpy(buffer, inqdata, sizeof(inqdata)); 3070 sg = scsi_sglist(cmd); 3071 kunmap_atomic(buffer - sg->offset); 3072 3073 cmd->scsi_done(cmd); 3074 } 3075 break; 3076 case WRITE_BUFFER: 3077 case READ_BUFFER: { 3078 if (arcmsr_iop_message_xfer(acb, cmd)) 3079 cmd->result = (DID_ERROR << 16); 3080 cmd->scsi_done(cmd); 3081 } 3082 break; 3083 default: 3084 cmd->scsi_done(cmd); 3085 } 3086 } 3087 3088 static int arcmsr_queue_command_lck(struct scsi_cmnd *cmd, 3089 void (* done)(struct scsi_cmnd *)) 3090 { 3091 struct Scsi_Host *host = cmd->device->host; 3092 struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata; 3093 struct CommandControlBlock *ccb; 3094 int target = cmd->device->id; 3095 3096 if (acb->acb_flags & ACB_F_ADAPTER_REMOVED) { 3097 cmd->result = (DID_NO_CONNECT << 16); 3098 cmd->scsi_done(cmd); 3099 return 0; 3100 } 3101 cmd->scsi_done = done; 3102 cmd->host_scribble = NULL; 3103 cmd->result = 0; 3104 if (target == 16) { 3105 /* virtual device for iop message transfer */ 3106 arcmsr_handle_virtual_command(acb, cmd); 3107 return 0; 3108 } 3109 ccb = arcmsr_get_freeccb(acb); 3110 if (!ccb) 3111 return SCSI_MLQUEUE_HOST_BUSY; 3112 if (arcmsr_build_ccb( acb, ccb, cmd ) == FAILED) { 3113 cmd->result = (DID_ERROR << 16) | (RESERVATION_CONFLICT << 1); 3114 cmd->scsi_done(cmd); 3115 return 0; 3116 } 3117 arcmsr_post_ccb(acb, ccb); 3118 return 0; 3119 } 3120 3121 static DEF_SCSI_QCMD(arcmsr_queue_command) 3122 3123 static void arcmsr_get_adapter_config(struct AdapterControlBlock *pACB, uint32_t *rwbuffer) 3124 { 3125 int count; 3126 uint32_t *acb_firm_model = (uint32_t *)pACB->firm_model; 3127 uint32_t *acb_firm_version = (uint32_t *)pACB->firm_version; 3128 uint32_t *acb_device_map = (uint32_t *)pACB->device_map; 3129 uint32_t *firm_model = &rwbuffer[15]; 3130 uint32_t *firm_version = &rwbuffer[17]; 3131 uint32_t *device_map = &rwbuffer[21]; 3132 3133 count = 2; 3134 while (count) { 3135 *acb_firm_model = readl(firm_model); 3136 acb_firm_model++; 3137 firm_model++; 3138 count--; 3139 } 3140 count = 4; 3141 while (count) { 3142 *acb_firm_version = readl(firm_version); 3143 acb_firm_version++; 3144 firm_version++; 3145 count--; 3146 } 3147 count = 4; 3148 while (count) { 3149 *acb_device_map = readl(device_map); 3150 acb_device_map++; 3151 device_map++; 3152 count--; 3153 } 3154 pACB->signature = readl(&rwbuffer[0]); 3155 pACB->firm_request_len = readl(&rwbuffer[1]); 3156 pACB->firm_numbers_queue = readl(&rwbuffer[2]); 3157 pACB->firm_sdram_size = readl(&rwbuffer[3]); 3158 pACB->firm_hd_channels = readl(&rwbuffer[4]); 3159 pACB->firm_cfg_version = readl(&rwbuffer[25]); 3160 pr_notice("Areca RAID Controller%d: Model %s, F/W %s\n", 3161 pACB->host->host_no, 3162 pACB->firm_model, 3163 pACB->firm_version); 3164 } 3165 3166 static bool arcmsr_hbaA_get_config(struct AdapterControlBlock *acb) 3167 { 3168 struct MessageUnit_A __iomem *reg = acb->pmuA; 3169 3170 arcmsr_wait_firmware_ready(acb); 3171 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0); 3172 if (!arcmsr_hbaA_wait_msgint_ready(acb)) { 3173 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \ 3174 miscellaneous data' timeout \n", acb->host->host_no); 3175 return false; 3176 } 3177 arcmsr_get_adapter_config(acb, reg->message_rwbuffer); 3178 return true; 3179 } 3180 static bool arcmsr_hbaB_get_config(struct AdapterControlBlock *acb) 3181 { 3182 struct MessageUnit_B *reg = acb->pmuB; 3183 3184 arcmsr_wait_firmware_ready(acb); 3185 writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell); 3186 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 3187 printk(KERN_ERR "arcmsr%d: can't set driver mode.\n", acb->host->host_no); 3188 return false; 3189 } 3190 writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell); 3191 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 3192 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \ 3193 miscellaneous data' timeout \n", acb->host->host_no); 3194 return false; 3195 } 3196 arcmsr_get_adapter_config(acb, reg->message_rwbuffer); 3197 return true; 3198 } 3199 3200 static bool arcmsr_hbaC_get_config(struct AdapterControlBlock *pACB) 3201 { 3202 uint32_t intmask_org; 3203 struct MessageUnit_C __iomem *reg = pACB->pmuC; 3204 3205 /* disable all outbound interrupt */ 3206 intmask_org = readl(®->host_int_mask); /* disable outbound message0 int */ 3207 writel(intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE, ®->host_int_mask); 3208 /* wait firmware ready */ 3209 arcmsr_wait_firmware_ready(pACB); 3210 /* post "get config" instruction */ 3211 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0); 3212 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell); 3213 /* wait message ready */ 3214 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) { 3215 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \ 3216 miscellaneous data' timeout \n", pACB->host->host_no); 3217 return false; 3218 } 3219 arcmsr_get_adapter_config(pACB, reg->msgcode_rwbuffer); 3220 return true; 3221 } 3222 3223 static bool arcmsr_hbaD_get_config(struct AdapterControlBlock *acb) 3224 { 3225 struct MessageUnit_D *reg = acb->pmuD; 3226 3227 if (readl(acb->pmuD->outbound_doorbell) & 3228 ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE) { 3229 writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE, 3230 acb->pmuD->outbound_doorbell);/*clear interrupt*/ 3231 } 3232 arcmsr_wait_firmware_ready(acb); 3233 /* post "get config" instruction */ 3234 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, reg->inbound_msgaddr0); 3235 /* wait message ready */ 3236 if (!arcmsr_hbaD_wait_msgint_ready(acb)) { 3237 pr_notice("arcmsr%d: wait get adapter firmware " 3238 "miscellaneous data timeout\n", acb->host->host_no); 3239 return false; 3240 } 3241 arcmsr_get_adapter_config(acb, reg->msgcode_rwbuffer); 3242 return true; 3243 } 3244 3245 static bool arcmsr_hbaE_get_config(struct AdapterControlBlock *pACB) 3246 { 3247 struct MessageUnit_E __iomem *reg = pACB->pmuE; 3248 uint32_t intmask_org; 3249 3250 /* disable all outbound interrupt */ 3251 intmask_org = readl(®->host_int_mask); /* disable outbound message0 int */ 3252 writel(intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE, ®->host_int_mask); 3253 /* wait firmware ready */ 3254 arcmsr_wait_firmware_ready(pACB); 3255 mdelay(20); 3256 /* post "get config" instruction */ 3257 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0); 3258 3259 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 3260 writel(pACB->out_doorbell, ®->iobound_doorbell); 3261 /* wait message ready */ 3262 if (!arcmsr_hbaE_wait_msgint_ready(pACB)) { 3263 pr_notice("arcmsr%d: wait get adapter firmware " 3264 "miscellaneous data timeout\n", pACB->host->host_no); 3265 return false; 3266 } 3267 arcmsr_get_adapter_config(pACB, reg->msgcode_rwbuffer); 3268 return true; 3269 } 3270 3271 static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb) 3272 { 3273 bool rtn = false; 3274 3275 switch (acb->adapter_type) { 3276 case ACB_ADAPTER_TYPE_A: 3277 rtn = arcmsr_hbaA_get_config(acb); 3278 break; 3279 case ACB_ADAPTER_TYPE_B: 3280 rtn = arcmsr_hbaB_get_config(acb); 3281 break; 3282 case ACB_ADAPTER_TYPE_C: 3283 rtn = arcmsr_hbaC_get_config(acb); 3284 break; 3285 case ACB_ADAPTER_TYPE_D: 3286 rtn = arcmsr_hbaD_get_config(acb); 3287 break; 3288 case ACB_ADAPTER_TYPE_E: 3289 rtn = arcmsr_hbaE_get_config(acb); 3290 break; 3291 default: 3292 break; 3293 } 3294 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3295 if (acb->host->can_queue >= acb->firm_numbers_queue) 3296 acb->host->can_queue = acb->maxOutstanding; 3297 else 3298 acb->maxOutstanding = acb->host->can_queue; 3299 acb->maxFreeCCB = acb->host->can_queue; 3300 if (acb->maxFreeCCB < ARCMSR_MAX_FREECCB_NUM) 3301 acb->maxFreeCCB += 64; 3302 return rtn; 3303 } 3304 3305 static int arcmsr_hbaA_polling_ccbdone(struct AdapterControlBlock *acb, 3306 struct CommandControlBlock *poll_ccb) 3307 { 3308 struct MessageUnit_A __iomem *reg = acb->pmuA; 3309 struct CommandControlBlock *ccb; 3310 struct ARCMSR_CDB *arcmsr_cdb; 3311 uint32_t flag_ccb, outbound_intstatus, poll_ccb_done = 0, poll_count = 0; 3312 int rtn; 3313 bool error; 3314 unsigned long ccb_cdb_phy; 3315 3316 polling_hba_ccb_retry: 3317 poll_count++; 3318 outbound_intstatus = readl(®->outbound_intstatus) & acb->outbound_int_enable; 3319 writel(outbound_intstatus, ®->outbound_intstatus);/*clear interrupt*/ 3320 while (1) { 3321 if ((flag_ccb = readl(®->outbound_queueport)) == 0xFFFFFFFF) { 3322 if (poll_ccb_done){ 3323 rtn = SUCCESS; 3324 break; 3325 }else { 3326 msleep(25); 3327 if (poll_count > 100){ 3328 rtn = FAILED; 3329 break; 3330 } 3331 goto polling_hba_ccb_retry; 3332 } 3333 } 3334 ccb_cdb_phy = (flag_ccb << 5) & 0xffffffff; 3335 if (acb->cdb_phyadd_hipart) 3336 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart; 3337 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy); 3338 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb); 3339 poll_ccb_done |= (ccb == poll_ccb) ? 1 : 0; 3340 if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) { 3341 if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) { 3342 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'" 3343 " poll command abort successfully \n" 3344 , acb->host->host_no 3345 , ccb->pcmd->device->id 3346 , (u32)ccb->pcmd->device->lun 3347 , ccb); 3348 ccb->pcmd->result = DID_ABORT << 16; 3349 arcmsr_ccb_complete(ccb); 3350 continue; 3351 } 3352 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb" 3353 " command done ccb = '0x%p'" 3354 "ccboutstandingcount = %d \n" 3355 , acb->host->host_no 3356 , ccb 3357 , atomic_read(&acb->ccboutstandingcount)); 3358 continue; 3359 } 3360 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false; 3361 arcmsr_report_ccb_state(acb, ccb, error); 3362 } 3363 return rtn; 3364 } 3365 3366 static int arcmsr_hbaB_polling_ccbdone(struct AdapterControlBlock *acb, 3367 struct CommandControlBlock *poll_ccb) 3368 { 3369 struct MessageUnit_B *reg = acb->pmuB; 3370 struct ARCMSR_CDB *arcmsr_cdb; 3371 struct CommandControlBlock *ccb; 3372 uint32_t flag_ccb, poll_ccb_done = 0, poll_count = 0; 3373 int index, rtn; 3374 bool error; 3375 unsigned long ccb_cdb_phy; 3376 3377 polling_hbb_ccb_retry: 3378 poll_count++; 3379 /* clear doorbell interrupt */ 3380 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); 3381 while(1){ 3382 index = reg->doneq_index; 3383 flag_ccb = reg->done_qbuffer[index]; 3384 if (flag_ccb == 0) { 3385 if (poll_ccb_done){ 3386 rtn = SUCCESS; 3387 break; 3388 }else { 3389 msleep(25); 3390 if (poll_count > 100){ 3391 rtn = FAILED; 3392 break; 3393 } 3394 goto polling_hbb_ccb_retry; 3395 } 3396 } 3397 reg->done_qbuffer[index] = 0; 3398 index++; 3399 /*if last index number set it to 0 */ 3400 index %= ARCMSR_MAX_HBB_POSTQUEUE; 3401 reg->doneq_index = index; 3402 /* check if command done with no error*/ 3403 ccb_cdb_phy = (flag_ccb << 5) & 0xffffffff; 3404 if (acb->cdb_phyadd_hipart) 3405 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart; 3406 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy); 3407 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb); 3408 poll_ccb_done |= (ccb == poll_ccb) ? 1 : 0; 3409 if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) { 3410 if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) { 3411 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'" 3412 " poll command abort successfully \n" 3413 ,acb->host->host_no 3414 ,ccb->pcmd->device->id 3415 ,(u32)ccb->pcmd->device->lun 3416 ,ccb); 3417 ccb->pcmd->result = DID_ABORT << 16; 3418 arcmsr_ccb_complete(ccb); 3419 continue; 3420 } 3421 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb" 3422 " command done ccb = '0x%p'" 3423 "ccboutstandingcount = %d \n" 3424 , acb->host->host_no 3425 , ccb 3426 , atomic_read(&acb->ccboutstandingcount)); 3427 continue; 3428 } 3429 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false; 3430 arcmsr_report_ccb_state(acb, ccb, error); 3431 } 3432 return rtn; 3433 } 3434 3435 static int arcmsr_hbaC_polling_ccbdone(struct AdapterControlBlock *acb, 3436 struct CommandControlBlock *poll_ccb) 3437 { 3438 struct MessageUnit_C __iomem *reg = acb->pmuC; 3439 uint32_t flag_ccb; 3440 struct ARCMSR_CDB *arcmsr_cdb; 3441 bool error; 3442 struct CommandControlBlock *pCCB; 3443 uint32_t poll_ccb_done = 0, poll_count = 0; 3444 int rtn; 3445 unsigned long ccb_cdb_phy; 3446 3447 polling_hbc_ccb_retry: 3448 poll_count++; 3449 while (1) { 3450 if ((readl(®->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) == 0) { 3451 if (poll_ccb_done) { 3452 rtn = SUCCESS; 3453 break; 3454 } else { 3455 msleep(25); 3456 if (poll_count > 100) { 3457 rtn = FAILED; 3458 break; 3459 } 3460 goto polling_hbc_ccb_retry; 3461 } 3462 } 3463 flag_ccb = readl(®->outbound_queueport_low); 3464 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0); 3465 if (acb->cdb_phyadd_hipart) 3466 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart; 3467 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy); 3468 pCCB = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb); 3469 poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0; 3470 /* check ifcommand done with no error*/ 3471 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) { 3472 if (pCCB->startdone == ARCMSR_CCB_ABORTED) { 3473 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'" 3474 " poll command abort successfully \n" 3475 , acb->host->host_no 3476 , pCCB->pcmd->device->id 3477 , (u32)pCCB->pcmd->device->lun 3478 , pCCB); 3479 pCCB->pcmd->result = DID_ABORT << 16; 3480 arcmsr_ccb_complete(pCCB); 3481 continue; 3482 } 3483 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb" 3484 " command done ccb = '0x%p'" 3485 "ccboutstandingcount = %d \n" 3486 , acb->host->host_no 3487 , pCCB 3488 , atomic_read(&acb->ccboutstandingcount)); 3489 continue; 3490 } 3491 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false; 3492 arcmsr_report_ccb_state(acb, pCCB, error); 3493 } 3494 return rtn; 3495 } 3496 3497 static int arcmsr_hbaD_polling_ccbdone(struct AdapterControlBlock *acb, 3498 struct CommandControlBlock *poll_ccb) 3499 { 3500 bool error; 3501 uint32_t poll_ccb_done = 0, poll_count = 0, flag_ccb; 3502 int rtn, doneq_index, index_stripped, outbound_write_pointer, toggle; 3503 unsigned long flags, ccb_cdb_phy, cdb_phy_hipart; 3504 struct ARCMSR_CDB *arcmsr_cdb; 3505 struct CommandControlBlock *pCCB; 3506 struct MessageUnit_D *pmu = acb->pmuD; 3507 3508 polling_hbaD_ccb_retry: 3509 poll_count++; 3510 while (1) { 3511 spin_lock_irqsave(&acb->doneq_lock, flags); 3512 outbound_write_pointer = pmu->done_qbuffer[0].addressLow + 1; 3513 doneq_index = pmu->doneq_index; 3514 if ((outbound_write_pointer & 0xFFF) == (doneq_index & 0xFFF)) { 3515 spin_unlock_irqrestore(&acb->doneq_lock, flags); 3516 if (poll_ccb_done) { 3517 rtn = SUCCESS; 3518 break; 3519 } else { 3520 msleep(25); 3521 if (poll_count > 40) { 3522 rtn = FAILED; 3523 break; 3524 } 3525 goto polling_hbaD_ccb_retry; 3526 } 3527 } 3528 toggle = doneq_index & 0x4000; 3529 index_stripped = (doneq_index & 0xFFF) + 1; 3530 index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE; 3531 pmu->doneq_index = index_stripped ? (index_stripped | toggle) : 3532 ((toggle ^ 0x4000) + 1); 3533 doneq_index = pmu->doneq_index; 3534 spin_unlock_irqrestore(&acb->doneq_lock, flags); 3535 cdb_phy_hipart = pmu->done_qbuffer[doneq_index & 3536 0xFFF].addressHigh; 3537 flag_ccb = pmu->done_qbuffer[doneq_index & 0xFFF].addressLow; 3538 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0); 3539 if (acb->cdb_phyadd_hipart) 3540 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart; 3541 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + 3542 ccb_cdb_phy); 3543 pCCB = container_of(arcmsr_cdb, struct CommandControlBlock, 3544 arcmsr_cdb); 3545 poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0; 3546 if ((pCCB->acb != acb) || 3547 (pCCB->startdone != ARCMSR_CCB_START)) { 3548 if (pCCB->startdone == ARCMSR_CCB_ABORTED) { 3549 pr_notice("arcmsr%d: scsi id = %d " 3550 "lun = %d ccb = '0x%p' poll command " 3551 "abort successfully\n" 3552 , acb->host->host_no 3553 , pCCB->pcmd->device->id 3554 , (u32)pCCB->pcmd->device->lun 3555 , pCCB); 3556 pCCB->pcmd->result = DID_ABORT << 16; 3557 arcmsr_ccb_complete(pCCB); 3558 continue; 3559 } 3560 pr_notice("arcmsr%d: polling an illegal " 3561 "ccb command done ccb = '0x%p' " 3562 "ccboutstandingcount = %d\n" 3563 , acb->host->host_no 3564 , pCCB 3565 , atomic_read(&acb->ccboutstandingcount)); 3566 continue; 3567 } 3568 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) 3569 ? true : false; 3570 arcmsr_report_ccb_state(acb, pCCB, error); 3571 } 3572 return rtn; 3573 } 3574 3575 static int arcmsr_hbaE_polling_ccbdone(struct AdapterControlBlock *acb, 3576 struct CommandControlBlock *poll_ccb) 3577 { 3578 bool error; 3579 uint32_t poll_ccb_done = 0, poll_count = 0, doneq_index; 3580 uint16_t cmdSMID; 3581 unsigned long flags; 3582 int rtn; 3583 struct CommandControlBlock *pCCB; 3584 struct MessageUnit_E __iomem *reg = acb->pmuE; 3585 3586 polling_hbaC_ccb_retry: 3587 poll_count++; 3588 while (1) { 3589 spin_lock_irqsave(&acb->doneq_lock, flags); 3590 doneq_index = acb->doneq_index; 3591 if ((readl(®->reply_post_producer_index) & 0xFFFF) == 3592 doneq_index) { 3593 spin_unlock_irqrestore(&acb->doneq_lock, flags); 3594 if (poll_ccb_done) { 3595 rtn = SUCCESS; 3596 break; 3597 } else { 3598 msleep(25); 3599 if (poll_count > 40) { 3600 rtn = FAILED; 3601 break; 3602 } 3603 goto polling_hbaC_ccb_retry; 3604 } 3605 } 3606 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID; 3607 doneq_index++; 3608 if (doneq_index >= acb->completionQ_entry) 3609 doneq_index = 0; 3610 acb->doneq_index = doneq_index; 3611 spin_unlock_irqrestore(&acb->doneq_lock, flags); 3612 pCCB = acb->pccb_pool[cmdSMID]; 3613 poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0; 3614 /* check if command done with no error*/ 3615 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) { 3616 if (pCCB->startdone == ARCMSR_CCB_ABORTED) { 3617 pr_notice("arcmsr%d: scsi id = %d " 3618 "lun = %d ccb = '0x%p' poll command " 3619 "abort successfully\n" 3620 , acb->host->host_no 3621 , pCCB->pcmd->device->id 3622 , (u32)pCCB->pcmd->device->lun 3623 , pCCB); 3624 pCCB->pcmd->result = DID_ABORT << 16; 3625 arcmsr_ccb_complete(pCCB); 3626 continue; 3627 } 3628 pr_notice("arcmsr%d: polling an illegal " 3629 "ccb command done ccb = '0x%p' " 3630 "ccboutstandingcount = %d\n" 3631 , acb->host->host_no 3632 , pCCB 3633 , atomic_read(&acb->ccboutstandingcount)); 3634 continue; 3635 } 3636 error = (acb->pCompletionQ[doneq_index].cmdFlag & 3637 ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false; 3638 arcmsr_report_ccb_state(acb, pCCB, error); 3639 } 3640 writel(doneq_index, ®->reply_post_consumer_index); 3641 return rtn; 3642 } 3643 3644 static int arcmsr_polling_ccbdone(struct AdapterControlBlock *acb, 3645 struct CommandControlBlock *poll_ccb) 3646 { 3647 int rtn = 0; 3648 switch (acb->adapter_type) { 3649 3650 case ACB_ADAPTER_TYPE_A: { 3651 rtn = arcmsr_hbaA_polling_ccbdone(acb, poll_ccb); 3652 } 3653 break; 3654 3655 case ACB_ADAPTER_TYPE_B: { 3656 rtn = arcmsr_hbaB_polling_ccbdone(acb, poll_ccb); 3657 } 3658 break; 3659 case ACB_ADAPTER_TYPE_C: { 3660 rtn = arcmsr_hbaC_polling_ccbdone(acb, poll_ccb); 3661 } 3662 break; 3663 case ACB_ADAPTER_TYPE_D: 3664 rtn = arcmsr_hbaD_polling_ccbdone(acb, poll_ccb); 3665 break; 3666 case ACB_ADAPTER_TYPE_E: 3667 rtn = arcmsr_hbaE_polling_ccbdone(acb, poll_ccb); 3668 break; 3669 } 3670 return rtn; 3671 } 3672 3673 static void arcmsr_set_iop_datetime(struct timer_list *t) 3674 { 3675 struct AdapterControlBlock *pacb = from_timer(pacb, t, refresh_timer); 3676 unsigned int next_time; 3677 struct tm tm; 3678 3679 union { 3680 struct { 3681 uint16_t signature; 3682 uint8_t year; 3683 uint8_t month; 3684 uint8_t date; 3685 uint8_t hour; 3686 uint8_t minute; 3687 uint8_t second; 3688 } a; 3689 struct { 3690 uint32_t msg_time[2]; 3691 } b; 3692 } datetime; 3693 3694 time64_to_tm(ktime_get_real_seconds(), -sys_tz.tz_minuteswest * 60, &tm); 3695 3696 datetime.a.signature = 0x55AA; 3697 datetime.a.year = tm.tm_year - 100; /* base 2000 instead of 1900 */ 3698 datetime.a.month = tm.tm_mon; 3699 datetime.a.date = tm.tm_mday; 3700 datetime.a.hour = tm.tm_hour; 3701 datetime.a.minute = tm.tm_min; 3702 datetime.a.second = tm.tm_sec; 3703 3704 switch (pacb->adapter_type) { 3705 case ACB_ADAPTER_TYPE_A: { 3706 struct MessageUnit_A __iomem *reg = pacb->pmuA; 3707 writel(datetime.b.msg_time[0], ®->message_rwbuffer[0]); 3708 writel(datetime.b.msg_time[1], ®->message_rwbuffer[1]); 3709 writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, ®->inbound_msgaddr0); 3710 break; 3711 } 3712 case ACB_ADAPTER_TYPE_B: { 3713 uint32_t __iomem *rwbuffer; 3714 struct MessageUnit_B *reg = pacb->pmuB; 3715 rwbuffer = reg->message_rwbuffer; 3716 writel(datetime.b.msg_time[0], rwbuffer++); 3717 writel(datetime.b.msg_time[1], rwbuffer++); 3718 writel(ARCMSR_MESSAGE_SYNC_TIMER, reg->drv2iop_doorbell); 3719 break; 3720 } 3721 case ACB_ADAPTER_TYPE_C: { 3722 struct MessageUnit_C __iomem *reg = pacb->pmuC; 3723 writel(datetime.b.msg_time[0], ®->msgcode_rwbuffer[0]); 3724 writel(datetime.b.msg_time[1], ®->msgcode_rwbuffer[1]); 3725 writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, ®->inbound_msgaddr0); 3726 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell); 3727 break; 3728 } 3729 case ACB_ADAPTER_TYPE_D: { 3730 uint32_t __iomem *rwbuffer; 3731 struct MessageUnit_D *reg = pacb->pmuD; 3732 rwbuffer = reg->msgcode_rwbuffer; 3733 writel(datetime.b.msg_time[0], rwbuffer++); 3734 writel(datetime.b.msg_time[1], rwbuffer++); 3735 writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, reg->inbound_msgaddr0); 3736 break; 3737 } 3738 case ACB_ADAPTER_TYPE_E: { 3739 struct MessageUnit_E __iomem *reg = pacb->pmuE; 3740 writel(datetime.b.msg_time[0], ®->msgcode_rwbuffer[0]); 3741 writel(datetime.b.msg_time[1], ®->msgcode_rwbuffer[1]); 3742 writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, ®->inbound_msgaddr0); 3743 pacb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 3744 writel(pacb->out_doorbell, ®->iobound_doorbell); 3745 break; 3746 } 3747 } 3748 if (sys_tz.tz_minuteswest) 3749 next_time = ARCMSR_HOURS; 3750 else 3751 next_time = ARCMSR_MINUTES; 3752 mod_timer(&pacb->refresh_timer, jiffies + msecs_to_jiffies(next_time)); 3753 } 3754 3755 static int arcmsr_iop_confirm(struct AdapterControlBlock *acb) 3756 { 3757 uint32_t cdb_phyaddr, cdb_phyaddr_hi32; 3758 dma_addr_t dma_coherent_handle; 3759 3760 /* 3761 ******************************************************************** 3762 ** here we need to tell iop 331 our freeccb.HighPart 3763 ** if freeccb.HighPart is not zero 3764 ******************************************************************** 3765 */ 3766 switch (acb->adapter_type) { 3767 case ACB_ADAPTER_TYPE_B: 3768 case ACB_ADAPTER_TYPE_D: 3769 dma_coherent_handle = acb->dma_coherent_handle2; 3770 break; 3771 case ACB_ADAPTER_TYPE_E: 3772 dma_coherent_handle = acb->dma_coherent_handle + 3773 offsetof(struct CommandControlBlock, arcmsr_cdb); 3774 break; 3775 default: 3776 dma_coherent_handle = acb->dma_coherent_handle; 3777 break; 3778 } 3779 cdb_phyaddr = lower_32_bits(dma_coherent_handle); 3780 cdb_phyaddr_hi32 = upper_32_bits(dma_coherent_handle); 3781 acb->cdb_phyaddr_hi32 = cdb_phyaddr_hi32; 3782 acb->cdb_phyadd_hipart = ((uint64_t)cdb_phyaddr_hi32) << 32; 3783 /* 3784 *********************************************************************** 3785 ** if adapter type B, set window of "post command Q" 3786 *********************************************************************** 3787 */ 3788 switch (acb->adapter_type) { 3789 3790 case ACB_ADAPTER_TYPE_A: { 3791 if (cdb_phyaddr_hi32 != 0) { 3792 struct MessageUnit_A __iomem *reg = acb->pmuA; 3793 writel(ARCMSR_SIGNATURE_SET_CONFIG, \ 3794 ®->message_rwbuffer[0]); 3795 writel(cdb_phyaddr_hi32, ®->message_rwbuffer[1]); 3796 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, \ 3797 ®->inbound_msgaddr0); 3798 if (!arcmsr_hbaA_wait_msgint_ready(acb)) { 3799 printk(KERN_NOTICE "arcmsr%d: ""set ccb high \ 3800 part physical address timeout\n", 3801 acb->host->host_no); 3802 return 1; 3803 } 3804 } 3805 } 3806 break; 3807 3808 case ACB_ADAPTER_TYPE_B: { 3809 uint32_t __iomem *rwbuffer; 3810 3811 struct MessageUnit_B *reg = acb->pmuB; 3812 reg->postq_index = 0; 3813 reg->doneq_index = 0; 3814 writel(ARCMSR_MESSAGE_SET_POST_WINDOW, reg->drv2iop_doorbell); 3815 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 3816 printk(KERN_NOTICE "arcmsr%d: cannot set driver mode\n", \ 3817 acb->host->host_no); 3818 return 1; 3819 } 3820 rwbuffer = reg->message_rwbuffer; 3821 /* driver "set config" signature */ 3822 writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++); 3823 /* normal should be zero */ 3824 writel(cdb_phyaddr_hi32, rwbuffer++); 3825 /* postQ size (256 + 8)*4 */ 3826 writel(cdb_phyaddr, rwbuffer++); 3827 /* doneQ size (256 + 8)*4 */ 3828 writel(cdb_phyaddr + 1056, rwbuffer++); 3829 /* ccb maxQ size must be --> [(256 + 8)*4]*/ 3830 writel(1056, rwbuffer); 3831 3832 writel(ARCMSR_MESSAGE_SET_CONFIG, reg->drv2iop_doorbell); 3833 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 3834 printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \ 3835 timeout \n",acb->host->host_no); 3836 return 1; 3837 } 3838 writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell); 3839 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 3840 pr_err("arcmsr%d: can't set driver mode.\n", 3841 acb->host->host_no); 3842 return 1; 3843 } 3844 } 3845 break; 3846 case ACB_ADAPTER_TYPE_C: { 3847 struct MessageUnit_C __iomem *reg = acb->pmuC; 3848 3849 printk(KERN_NOTICE "arcmsr%d: cdb_phyaddr_hi32=0x%x\n", 3850 acb->adapter_index, cdb_phyaddr_hi32); 3851 writel(ARCMSR_SIGNATURE_SET_CONFIG, ®->msgcode_rwbuffer[0]); 3852 writel(cdb_phyaddr_hi32, ®->msgcode_rwbuffer[1]); 3853 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, ®->inbound_msgaddr0); 3854 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell); 3855 if (!arcmsr_hbaC_wait_msgint_ready(acb)) { 3856 printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \ 3857 timeout \n", acb->host->host_no); 3858 return 1; 3859 } 3860 } 3861 break; 3862 case ACB_ADAPTER_TYPE_D: { 3863 uint32_t __iomem *rwbuffer; 3864 struct MessageUnit_D *reg = acb->pmuD; 3865 reg->postq_index = 0; 3866 reg->doneq_index = 0; 3867 rwbuffer = reg->msgcode_rwbuffer; 3868 writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++); 3869 writel(cdb_phyaddr_hi32, rwbuffer++); 3870 writel(cdb_phyaddr, rwbuffer++); 3871 writel(cdb_phyaddr + (ARCMSR_MAX_ARC1214_POSTQUEUE * 3872 sizeof(struct InBound_SRB)), rwbuffer++); 3873 writel(0x100, rwbuffer); 3874 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, reg->inbound_msgaddr0); 3875 if (!arcmsr_hbaD_wait_msgint_ready(acb)) { 3876 pr_notice("arcmsr%d: 'set command Q window' timeout\n", 3877 acb->host->host_no); 3878 return 1; 3879 } 3880 } 3881 break; 3882 case ACB_ADAPTER_TYPE_E: { 3883 struct MessageUnit_E __iomem *reg = acb->pmuE; 3884 writel(ARCMSR_SIGNATURE_SET_CONFIG, ®->msgcode_rwbuffer[0]); 3885 writel(ARCMSR_SIGNATURE_1884, ®->msgcode_rwbuffer[1]); 3886 writel(cdb_phyaddr, ®->msgcode_rwbuffer[2]); 3887 writel(cdb_phyaddr_hi32, ®->msgcode_rwbuffer[3]); 3888 writel(acb->ccbsize, ®->msgcode_rwbuffer[4]); 3889 dma_coherent_handle = acb->dma_coherent_handle2; 3890 cdb_phyaddr = (uint32_t)(dma_coherent_handle & 0xffffffff); 3891 cdb_phyaddr_hi32 = (uint32_t)((dma_coherent_handle >> 16) >> 16); 3892 writel(cdb_phyaddr, ®->msgcode_rwbuffer[5]); 3893 writel(cdb_phyaddr_hi32, ®->msgcode_rwbuffer[6]); 3894 writel(acb->ioqueue_size, ®->msgcode_rwbuffer[7]); 3895 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, ®->inbound_msgaddr0); 3896 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 3897 writel(acb->out_doorbell, ®->iobound_doorbell); 3898 if (!arcmsr_hbaE_wait_msgint_ready(acb)) { 3899 pr_notice("arcmsr%d: 'set command Q window' timeout \n", 3900 acb->host->host_no); 3901 return 1; 3902 } 3903 } 3904 break; 3905 } 3906 return 0; 3907 } 3908 3909 static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb) 3910 { 3911 uint32_t firmware_state = 0; 3912 switch (acb->adapter_type) { 3913 3914 case ACB_ADAPTER_TYPE_A: { 3915 struct MessageUnit_A __iomem *reg = acb->pmuA; 3916 do { 3917 if (!(acb->acb_flags & ACB_F_IOP_INITED)) 3918 msleep(20); 3919 firmware_state = readl(®->outbound_msgaddr1); 3920 } while ((firmware_state & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0); 3921 } 3922 break; 3923 3924 case ACB_ADAPTER_TYPE_B: { 3925 struct MessageUnit_B *reg = acb->pmuB; 3926 do { 3927 if (!(acb->acb_flags & ACB_F_IOP_INITED)) 3928 msleep(20); 3929 firmware_state = readl(reg->iop2drv_doorbell); 3930 } while ((firmware_state & ARCMSR_MESSAGE_FIRMWARE_OK) == 0); 3931 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell); 3932 } 3933 break; 3934 case ACB_ADAPTER_TYPE_C: { 3935 struct MessageUnit_C __iomem *reg = acb->pmuC; 3936 do { 3937 if (!(acb->acb_flags & ACB_F_IOP_INITED)) 3938 msleep(20); 3939 firmware_state = readl(®->outbound_msgaddr1); 3940 } while ((firmware_state & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0); 3941 } 3942 break; 3943 case ACB_ADAPTER_TYPE_D: { 3944 struct MessageUnit_D *reg = acb->pmuD; 3945 do { 3946 if (!(acb->acb_flags & ACB_F_IOP_INITED)) 3947 msleep(20); 3948 firmware_state = readl(reg->outbound_msgaddr1); 3949 } while ((firmware_state & 3950 ARCMSR_ARC1214_MESSAGE_FIRMWARE_OK) == 0); 3951 } 3952 break; 3953 case ACB_ADAPTER_TYPE_E: { 3954 struct MessageUnit_E __iomem *reg = acb->pmuE; 3955 do { 3956 if (!(acb->acb_flags & ACB_F_IOP_INITED)) 3957 msleep(20); 3958 firmware_state = readl(®->outbound_msgaddr1); 3959 } while ((firmware_state & ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK) == 0); 3960 } 3961 break; 3962 } 3963 } 3964 3965 static void arcmsr_request_device_map(struct timer_list *t) 3966 { 3967 struct AdapterControlBlock *acb = from_timer(acb, t, eternal_timer); 3968 if (unlikely(atomic_read(&acb->rq_map_token) == 0) || 3969 (acb->acb_flags & ACB_F_BUS_RESET) || 3970 (acb->acb_flags & ACB_F_ABORT)) { 3971 mod_timer(&acb->eternal_timer, 3972 jiffies + msecs_to_jiffies(6 * HZ)); 3973 } else { 3974 acb->fw_flag = FW_NORMAL; 3975 if (atomic_read(&acb->ante_token_value) == 3976 atomic_read(&acb->rq_map_token)) { 3977 atomic_set(&acb->rq_map_token, 16); 3978 } 3979 atomic_set(&acb->ante_token_value, 3980 atomic_read(&acb->rq_map_token)); 3981 if (atomic_dec_and_test(&acb->rq_map_token)) { 3982 mod_timer(&acb->eternal_timer, jiffies + 3983 msecs_to_jiffies(6 * HZ)); 3984 return; 3985 } 3986 switch (acb->adapter_type) { 3987 case ACB_ADAPTER_TYPE_A: { 3988 struct MessageUnit_A __iomem *reg = acb->pmuA; 3989 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0); 3990 break; 3991 } 3992 case ACB_ADAPTER_TYPE_B: { 3993 struct MessageUnit_B *reg = acb->pmuB; 3994 writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell); 3995 break; 3996 } 3997 case ACB_ADAPTER_TYPE_C: { 3998 struct MessageUnit_C __iomem *reg = acb->pmuC; 3999 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0); 4000 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell); 4001 break; 4002 } 4003 case ACB_ADAPTER_TYPE_D: { 4004 struct MessageUnit_D *reg = acb->pmuD; 4005 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, reg->inbound_msgaddr0); 4006 break; 4007 } 4008 case ACB_ADAPTER_TYPE_E: { 4009 struct MessageUnit_E __iomem *reg = acb->pmuE; 4010 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0); 4011 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 4012 writel(acb->out_doorbell, ®->iobound_doorbell); 4013 break; 4014 } 4015 default: 4016 return; 4017 } 4018 acb->acb_flags |= ACB_F_MSG_GET_CONFIG; 4019 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ)); 4020 } 4021 } 4022 4023 static void arcmsr_hbaA_start_bgrb(struct AdapterControlBlock *acb) 4024 { 4025 struct MessageUnit_A __iomem *reg = acb->pmuA; 4026 acb->acb_flags |= ACB_F_MSG_START_BGRB; 4027 writel(ARCMSR_INBOUND_MESG0_START_BGRB, ®->inbound_msgaddr0); 4028 if (!arcmsr_hbaA_wait_msgint_ready(acb)) { 4029 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \ 4030 rebuild' timeout \n", acb->host->host_no); 4031 } 4032 } 4033 4034 static void arcmsr_hbaB_start_bgrb(struct AdapterControlBlock *acb) 4035 { 4036 struct MessageUnit_B *reg = acb->pmuB; 4037 acb->acb_flags |= ACB_F_MSG_START_BGRB; 4038 writel(ARCMSR_MESSAGE_START_BGRB, reg->drv2iop_doorbell); 4039 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 4040 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \ 4041 rebuild' timeout \n",acb->host->host_no); 4042 } 4043 } 4044 4045 static void arcmsr_hbaC_start_bgrb(struct AdapterControlBlock *pACB) 4046 { 4047 struct MessageUnit_C __iomem *phbcmu = pACB->pmuC; 4048 pACB->acb_flags |= ACB_F_MSG_START_BGRB; 4049 writel(ARCMSR_INBOUND_MESG0_START_BGRB, &phbcmu->inbound_msgaddr0); 4050 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &phbcmu->inbound_doorbell); 4051 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) { 4052 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \ 4053 rebuild' timeout \n", pACB->host->host_no); 4054 } 4055 return; 4056 } 4057 4058 static void arcmsr_hbaD_start_bgrb(struct AdapterControlBlock *pACB) 4059 { 4060 struct MessageUnit_D *pmu = pACB->pmuD; 4061 4062 pACB->acb_flags |= ACB_F_MSG_START_BGRB; 4063 writel(ARCMSR_INBOUND_MESG0_START_BGRB, pmu->inbound_msgaddr0); 4064 if (!arcmsr_hbaD_wait_msgint_ready(pACB)) { 4065 pr_notice("arcmsr%d: wait 'start adapter " 4066 "background rebuild' timeout\n", pACB->host->host_no); 4067 } 4068 } 4069 4070 static void arcmsr_hbaE_start_bgrb(struct AdapterControlBlock *pACB) 4071 { 4072 struct MessageUnit_E __iomem *pmu = pACB->pmuE; 4073 4074 pACB->acb_flags |= ACB_F_MSG_START_BGRB; 4075 writel(ARCMSR_INBOUND_MESG0_START_BGRB, &pmu->inbound_msgaddr0); 4076 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 4077 writel(pACB->out_doorbell, &pmu->iobound_doorbell); 4078 if (!arcmsr_hbaE_wait_msgint_ready(pACB)) { 4079 pr_notice("arcmsr%d: wait 'start adapter " 4080 "background rebuild' timeout \n", pACB->host->host_no); 4081 } 4082 } 4083 4084 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb) 4085 { 4086 switch (acb->adapter_type) { 4087 case ACB_ADAPTER_TYPE_A: 4088 arcmsr_hbaA_start_bgrb(acb); 4089 break; 4090 case ACB_ADAPTER_TYPE_B: 4091 arcmsr_hbaB_start_bgrb(acb); 4092 break; 4093 case ACB_ADAPTER_TYPE_C: 4094 arcmsr_hbaC_start_bgrb(acb); 4095 break; 4096 case ACB_ADAPTER_TYPE_D: 4097 arcmsr_hbaD_start_bgrb(acb); 4098 break; 4099 case ACB_ADAPTER_TYPE_E: 4100 arcmsr_hbaE_start_bgrb(acb); 4101 break; 4102 } 4103 } 4104 4105 static void arcmsr_clear_doorbell_queue_buffer(struct AdapterControlBlock *acb) 4106 { 4107 switch (acb->adapter_type) { 4108 case ACB_ADAPTER_TYPE_A: { 4109 struct MessageUnit_A __iomem *reg = acb->pmuA; 4110 uint32_t outbound_doorbell; 4111 /* empty doorbell Qbuffer if door bell ringed */ 4112 outbound_doorbell = readl(®->outbound_doorbell); 4113 /*clear doorbell interrupt */ 4114 writel(outbound_doorbell, ®->outbound_doorbell); 4115 writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, ®->inbound_doorbell); 4116 } 4117 break; 4118 4119 case ACB_ADAPTER_TYPE_B: { 4120 struct MessageUnit_B *reg = acb->pmuB; 4121 uint32_t outbound_doorbell, i; 4122 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); 4123 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell); 4124 /* let IOP know data has been read */ 4125 for(i=0; i < 200; i++) { 4126 msleep(20); 4127 outbound_doorbell = readl(reg->iop2drv_doorbell); 4128 if( outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) { 4129 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); 4130 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell); 4131 } else 4132 break; 4133 } 4134 } 4135 break; 4136 case ACB_ADAPTER_TYPE_C: { 4137 struct MessageUnit_C __iomem *reg = acb->pmuC; 4138 uint32_t outbound_doorbell, i; 4139 /* empty doorbell Qbuffer if door bell ringed */ 4140 outbound_doorbell = readl(®->outbound_doorbell); 4141 writel(outbound_doorbell, ®->outbound_doorbell_clear); 4142 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, ®->inbound_doorbell); 4143 for (i = 0; i < 200; i++) { 4144 msleep(20); 4145 outbound_doorbell = readl(®->outbound_doorbell); 4146 if (outbound_doorbell & 4147 ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) { 4148 writel(outbound_doorbell, 4149 ®->outbound_doorbell_clear); 4150 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, 4151 ®->inbound_doorbell); 4152 } else 4153 break; 4154 } 4155 } 4156 break; 4157 case ACB_ADAPTER_TYPE_D: { 4158 struct MessageUnit_D *reg = acb->pmuD; 4159 uint32_t outbound_doorbell, i; 4160 /* empty doorbell Qbuffer if door bell ringed */ 4161 outbound_doorbell = readl(reg->outbound_doorbell); 4162 writel(outbound_doorbell, reg->outbound_doorbell); 4163 writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ, 4164 reg->inbound_doorbell); 4165 for (i = 0; i < 200; i++) { 4166 msleep(20); 4167 outbound_doorbell = readl(reg->outbound_doorbell); 4168 if (outbound_doorbell & 4169 ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK) { 4170 writel(outbound_doorbell, 4171 reg->outbound_doorbell); 4172 writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ, 4173 reg->inbound_doorbell); 4174 } else 4175 break; 4176 } 4177 } 4178 break; 4179 case ACB_ADAPTER_TYPE_E: { 4180 struct MessageUnit_E __iomem *reg = acb->pmuE; 4181 uint32_t i, tmp; 4182 4183 acb->in_doorbell = readl(®->iobound_doorbell); 4184 writel(0, ®->host_int_status); /*clear interrupt*/ 4185 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK; 4186 writel(acb->out_doorbell, ®->iobound_doorbell); 4187 for(i=0; i < 200; i++) { 4188 msleep(20); 4189 tmp = acb->in_doorbell; 4190 acb->in_doorbell = readl(®->iobound_doorbell); 4191 if((tmp ^ acb->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) { 4192 writel(0, ®->host_int_status); /*clear interrupt*/ 4193 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK; 4194 writel(acb->out_doorbell, ®->iobound_doorbell); 4195 } else 4196 break; 4197 } 4198 } 4199 break; 4200 } 4201 } 4202 4203 static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb) 4204 { 4205 switch (acb->adapter_type) { 4206 case ACB_ADAPTER_TYPE_A: 4207 return; 4208 case ACB_ADAPTER_TYPE_B: 4209 { 4210 struct MessageUnit_B *reg = acb->pmuB; 4211 writel(ARCMSR_MESSAGE_ACTIVE_EOI_MODE, reg->drv2iop_doorbell); 4212 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 4213 printk(KERN_NOTICE "ARCMSR IOP enables EOI_MODE TIMEOUT"); 4214 return; 4215 } 4216 } 4217 break; 4218 case ACB_ADAPTER_TYPE_C: 4219 return; 4220 } 4221 return; 4222 } 4223 4224 static void arcmsr_hardware_reset(struct AdapterControlBlock *acb) 4225 { 4226 uint8_t value[64]; 4227 int i, count = 0; 4228 struct MessageUnit_A __iomem *pmuA = acb->pmuA; 4229 struct MessageUnit_C __iomem *pmuC = acb->pmuC; 4230 struct MessageUnit_D *pmuD = acb->pmuD; 4231 4232 /* backup pci config data */ 4233 printk(KERN_NOTICE "arcmsr%d: executing hw bus reset .....\n", acb->host->host_no); 4234 for (i = 0; i < 64; i++) { 4235 pci_read_config_byte(acb->pdev, i, &value[i]); 4236 } 4237 /* hardware reset signal */ 4238 if (acb->dev_id == 0x1680) { 4239 writel(ARCMSR_ARC1680_BUS_RESET, &pmuA->reserved1[0]); 4240 } else if (acb->dev_id == 0x1880) { 4241 do { 4242 count++; 4243 writel(0xF, &pmuC->write_sequence); 4244 writel(0x4, &pmuC->write_sequence); 4245 writel(0xB, &pmuC->write_sequence); 4246 writel(0x2, &pmuC->write_sequence); 4247 writel(0x7, &pmuC->write_sequence); 4248 writel(0xD, &pmuC->write_sequence); 4249 } while (((readl(&pmuC->host_diagnostic) & ARCMSR_ARC1880_DiagWrite_ENABLE) == 0) && (count < 5)); 4250 writel(ARCMSR_ARC1880_RESET_ADAPTER, &pmuC->host_diagnostic); 4251 } else if (acb->dev_id == 0x1884) { 4252 struct MessageUnit_E __iomem *pmuE = acb->pmuE; 4253 do { 4254 count++; 4255 writel(0x4, &pmuE->write_sequence_3xxx); 4256 writel(0xB, &pmuE->write_sequence_3xxx); 4257 writel(0x2, &pmuE->write_sequence_3xxx); 4258 writel(0x7, &pmuE->write_sequence_3xxx); 4259 writel(0xD, &pmuE->write_sequence_3xxx); 4260 mdelay(10); 4261 } while (((readl(&pmuE->host_diagnostic_3xxx) & 4262 ARCMSR_ARC1884_DiagWrite_ENABLE) == 0) && (count < 5)); 4263 writel(ARCMSR_ARC188X_RESET_ADAPTER, &pmuE->host_diagnostic_3xxx); 4264 } else if (acb->dev_id == 0x1214) { 4265 writel(0x20, pmuD->reset_request); 4266 } else { 4267 pci_write_config_byte(acb->pdev, 0x84, 0x20); 4268 } 4269 msleep(2000); 4270 /* write back pci config data */ 4271 for (i = 0; i < 64; i++) { 4272 pci_write_config_byte(acb->pdev, i, value[i]); 4273 } 4274 msleep(1000); 4275 return; 4276 } 4277 4278 static bool arcmsr_reset_in_progress(struct AdapterControlBlock *acb) 4279 { 4280 bool rtn = true; 4281 4282 switch(acb->adapter_type) { 4283 case ACB_ADAPTER_TYPE_A:{ 4284 struct MessageUnit_A __iomem *reg = acb->pmuA; 4285 rtn = ((readl(®->outbound_msgaddr1) & 4286 ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) ? true : false; 4287 } 4288 break; 4289 case ACB_ADAPTER_TYPE_B:{ 4290 struct MessageUnit_B *reg = acb->pmuB; 4291 rtn = ((readl(reg->iop2drv_doorbell) & 4292 ARCMSR_MESSAGE_FIRMWARE_OK) == 0) ? true : false; 4293 } 4294 break; 4295 case ACB_ADAPTER_TYPE_C:{ 4296 struct MessageUnit_C __iomem *reg = acb->pmuC; 4297 rtn = (readl(®->host_diagnostic) & 0x04) ? true : false; 4298 } 4299 break; 4300 case ACB_ADAPTER_TYPE_D:{ 4301 struct MessageUnit_D *reg = acb->pmuD; 4302 rtn = ((readl(reg->sample_at_reset) & 0x80) == 0) ? 4303 true : false; 4304 } 4305 break; 4306 case ACB_ADAPTER_TYPE_E:{ 4307 struct MessageUnit_E __iomem *reg = acb->pmuE; 4308 rtn = (readl(®->host_diagnostic_3xxx) & 4309 ARCMSR_ARC188X_RESET_ADAPTER) ? true : false; 4310 } 4311 break; 4312 } 4313 return rtn; 4314 } 4315 4316 static void arcmsr_iop_init(struct AdapterControlBlock *acb) 4317 { 4318 uint32_t intmask_org; 4319 /* disable all outbound interrupt */ 4320 intmask_org = arcmsr_disable_outbound_ints(acb); 4321 arcmsr_wait_firmware_ready(acb); 4322 arcmsr_iop_confirm(acb); 4323 /*start background rebuild*/ 4324 arcmsr_start_adapter_bgrb(acb); 4325 /* empty doorbell Qbuffer if door bell ringed */ 4326 arcmsr_clear_doorbell_queue_buffer(acb); 4327 arcmsr_enable_eoi_mode(acb); 4328 /* enable outbound Post Queue,outbound doorbell Interrupt */ 4329 arcmsr_enable_outbound_ints(acb, intmask_org); 4330 acb->acb_flags |= ACB_F_IOP_INITED; 4331 } 4332 4333 static uint8_t arcmsr_iop_reset(struct AdapterControlBlock *acb) 4334 { 4335 struct CommandControlBlock *ccb; 4336 uint32_t intmask_org; 4337 uint8_t rtnval = 0x00; 4338 int i = 0; 4339 unsigned long flags; 4340 4341 if (atomic_read(&acb->ccboutstandingcount) != 0) { 4342 /* disable all outbound interrupt */ 4343 intmask_org = arcmsr_disable_outbound_ints(acb); 4344 /* talk to iop 331 outstanding command aborted */ 4345 rtnval = arcmsr_abort_allcmd(acb); 4346 /* clear all outbound posted Q */ 4347 arcmsr_done4abort_postqueue(acb); 4348 for (i = 0; i < acb->maxFreeCCB; i++) { 4349 ccb = acb->pccb_pool[i]; 4350 if (ccb->startdone == ARCMSR_CCB_START) { 4351 scsi_dma_unmap(ccb->pcmd); 4352 ccb->startdone = ARCMSR_CCB_DONE; 4353 ccb->ccb_flags = 0; 4354 spin_lock_irqsave(&acb->ccblist_lock, flags); 4355 list_add_tail(&ccb->list, &acb->ccb_free_list); 4356 spin_unlock_irqrestore(&acb->ccblist_lock, flags); 4357 } 4358 } 4359 atomic_set(&acb->ccboutstandingcount, 0); 4360 /* enable all outbound interrupt */ 4361 arcmsr_enable_outbound_ints(acb, intmask_org); 4362 return rtnval; 4363 } 4364 return rtnval; 4365 } 4366 4367 static int arcmsr_bus_reset(struct scsi_cmnd *cmd) 4368 { 4369 struct AdapterControlBlock *acb; 4370 int retry_count = 0; 4371 int rtn = FAILED; 4372 acb = (struct AdapterControlBlock *) cmd->device->host->hostdata; 4373 if (acb->acb_flags & ACB_F_ADAPTER_REMOVED) 4374 return SUCCESS; 4375 pr_notice("arcmsr: executing bus reset eh.....num_resets = %d," 4376 " num_aborts = %d \n", acb->num_resets, acb->num_aborts); 4377 acb->num_resets++; 4378 4379 if (acb->acb_flags & ACB_F_BUS_RESET) { 4380 long timeout; 4381 pr_notice("arcmsr: there is a bus reset eh proceeding...\n"); 4382 timeout = wait_event_timeout(wait_q, (acb->acb_flags 4383 & ACB_F_BUS_RESET) == 0, 220 * HZ); 4384 if (timeout) 4385 return SUCCESS; 4386 } 4387 acb->acb_flags |= ACB_F_BUS_RESET; 4388 if (!arcmsr_iop_reset(acb)) { 4389 arcmsr_hardware_reset(acb); 4390 acb->acb_flags &= ~ACB_F_IOP_INITED; 4391 wait_reset_done: 4392 ssleep(ARCMSR_SLEEPTIME); 4393 if (arcmsr_reset_in_progress(acb)) { 4394 if (retry_count > ARCMSR_RETRYCOUNT) { 4395 acb->fw_flag = FW_DEADLOCK; 4396 pr_notice("arcmsr%d: waiting for hw bus reset" 4397 " return, RETRY TERMINATED!!\n", 4398 acb->host->host_no); 4399 return FAILED; 4400 } 4401 retry_count++; 4402 goto wait_reset_done; 4403 } 4404 arcmsr_iop_init(acb); 4405 atomic_set(&acb->rq_map_token, 16); 4406 atomic_set(&acb->ante_token_value, 16); 4407 acb->fw_flag = FW_NORMAL; 4408 mod_timer(&acb->eternal_timer, jiffies + 4409 msecs_to_jiffies(6 * HZ)); 4410 acb->acb_flags &= ~ACB_F_BUS_RESET; 4411 rtn = SUCCESS; 4412 pr_notice("arcmsr: scsi bus reset eh returns with success\n"); 4413 } else { 4414 acb->acb_flags &= ~ACB_F_BUS_RESET; 4415 atomic_set(&acb->rq_map_token, 16); 4416 atomic_set(&acb->ante_token_value, 16); 4417 acb->fw_flag = FW_NORMAL; 4418 mod_timer(&acb->eternal_timer, jiffies + 4419 msecs_to_jiffies(6 * HZ)); 4420 rtn = SUCCESS; 4421 } 4422 return rtn; 4423 } 4424 4425 static int arcmsr_abort_one_cmd(struct AdapterControlBlock *acb, 4426 struct CommandControlBlock *ccb) 4427 { 4428 int rtn; 4429 rtn = arcmsr_polling_ccbdone(acb, ccb); 4430 return rtn; 4431 } 4432 4433 static int arcmsr_abort(struct scsi_cmnd *cmd) 4434 { 4435 struct AdapterControlBlock *acb = 4436 (struct AdapterControlBlock *)cmd->device->host->hostdata; 4437 int i = 0; 4438 int rtn = FAILED; 4439 uint32_t intmask_org; 4440 4441 if (acb->acb_flags & ACB_F_ADAPTER_REMOVED) 4442 return SUCCESS; 4443 printk(KERN_NOTICE 4444 "arcmsr%d: abort device command of scsi id = %d lun = %d\n", 4445 acb->host->host_no, cmd->device->id, (u32)cmd->device->lun); 4446 acb->acb_flags |= ACB_F_ABORT; 4447 acb->num_aborts++; 4448 /* 4449 ************************************************ 4450 ** the all interrupt service routine is locked 4451 ** we need to handle it as soon as possible and exit 4452 ************************************************ 4453 */ 4454 if (!atomic_read(&acb->ccboutstandingcount)) { 4455 acb->acb_flags &= ~ACB_F_ABORT; 4456 return rtn; 4457 } 4458 4459 intmask_org = arcmsr_disable_outbound_ints(acb); 4460 for (i = 0; i < acb->maxFreeCCB; i++) { 4461 struct CommandControlBlock *ccb = acb->pccb_pool[i]; 4462 if (ccb->startdone == ARCMSR_CCB_START && ccb->pcmd == cmd) { 4463 ccb->startdone = ARCMSR_CCB_ABORTED; 4464 rtn = arcmsr_abort_one_cmd(acb, ccb); 4465 break; 4466 } 4467 } 4468 acb->acb_flags &= ~ACB_F_ABORT; 4469 arcmsr_enable_outbound_ints(acb, intmask_org); 4470 return rtn; 4471 } 4472 4473 static const char *arcmsr_info(struct Scsi_Host *host) 4474 { 4475 struct AdapterControlBlock *acb = 4476 (struct AdapterControlBlock *) host->hostdata; 4477 static char buf[256]; 4478 char *type; 4479 int raid6 = 1; 4480 switch (acb->pdev->device) { 4481 case PCI_DEVICE_ID_ARECA_1110: 4482 case PCI_DEVICE_ID_ARECA_1200: 4483 case PCI_DEVICE_ID_ARECA_1202: 4484 case PCI_DEVICE_ID_ARECA_1210: 4485 raid6 = 0; 4486 /*FALLTHRU*/ 4487 case PCI_DEVICE_ID_ARECA_1120: 4488 case PCI_DEVICE_ID_ARECA_1130: 4489 case PCI_DEVICE_ID_ARECA_1160: 4490 case PCI_DEVICE_ID_ARECA_1170: 4491 case PCI_DEVICE_ID_ARECA_1201: 4492 case PCI_DEVICE_ID_ARECA_1203: 4493 case PCI_DEVICE_ID_ARECA_1220: 4494 case PCI_DEVICE_ID_ARECA_1230: 4495 case PCI_DEVICE_ID_ARECA_1260: 4496 case PCI_DEVICE_ID_ARECA_1270: 4497 case PCI_DEVICE_ID_ARECA_1280: 4498 type = "SATA"; 4499 break; 4500 case PCI_DEVICE_ID_ARECA_1214: 4501 case PCI_DEVICE_ID_ARECA_1380: 4502 case PCI_DEVICE_ID_ARECA_1381: 4503 case PCI_DEVICE_ID_ARECA_1680: 4504 case PCI_DEVICE_ID_ARECA_1681: 4505 case PCI_DEVICE_ID_ARECA_1880: 4506 case PCI_DEVICE_ID_ARECA_1884: 4507 type = "SAS/SATA"; 4508 break; 4509 default: 4510 type = "unknown"; 4511 raid6 = 0; 4512 break; 4513 } 4514 sprintf(buf, "Areca %s RAID Controller %s\narcmsr version %s\n", 4515 type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION); 4516 return buf; 4517 } 4518