1 /* 2 ******************************************************************************* 3 ** O.S : Linux 4 ** FILE NAME : arcmsr_hba.c 5 ** BY : Nick Cheng, C.L. Huang 6 ** Description: SCSI RAID Device Driver for Areca RAID Controller 7 ******************************************************************************* 8 ** Copyright (C) 2002 - 2014, Areca Technology Corporation All rights reserved 9 ** 10 ** Web site: www.areca.com.tw 11 ** E-mail: support@areca.com.tw 12 ** 13 ** This program is free software; you can redistribute it and/or modify 14 ** it under the terms of the GNU General Public License version 2 as 15 ** published by the Free Software Foundation. 16 ** This program is distributed in the hope that it will be useful, 17 ** but WITHOUT ANY WARRANTY; without even the implied warranty of 18 ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 ** GNU General Public License for more details. 20 ******************************************************************************* 21 ** Redistribution and use in source and binary forms, with or without 22 ** modification, are permitted provided that the following conditions 23 ** are met: 24 ** 1. Redistributions of source code must retain the above copyright 25 ** notice, this list of conditions and the following disclaimer. 26 ** 2. Redistributions in binary form must reproduce the above copyright 27 ** notice, this list of conditions and the following disclaimer in the 28 ** documentation and/or other materials provided with the distribution. 29 ** 3. The name of the author may not be used to endorse or promote products 30 ** derived from this software without specific prior written permission. 31 ** 32 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 33 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 34 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 35 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 36 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT 37 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 38 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 39 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 41 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 ******************************************************************************* 43 ** For history of changes, see Documentation/scsi/ChangeLog.arcmsr 44 ** Firmware Specification, see Documentation/scsi/arcmsr_spec.txt 45 ******************************************************************************* 46 */ 47 #include <linux/module.h> 48 #include <linux/reboot.h> 49 #include <linux/spinlock.h> 50 #include <linux/pci_ids.h> 51 #include <linux/interrupt.h> 52 #include <linux/moduleparam.h> 53 #include <linux/errno.h> 54 #include <linux/types.h> 55 #include <linux/delay.h> 56 #include <linux/dma-mapping.h> 57 #include <linux/timer.h> 58 #include <linux/slab.h> 59 #include <linux/pci.h> 60 #include <linux/aer.h> 61 #include <linux/circ_buf.h> 62 #include <asm/dma.h> 63 #include <asm/io.h> 64 #include <linux/uaccess.h> 65 #include <scsi/scsi_host.h> 66 #include <scsi/scsi.h> 67 #include <scsi/scsi_cmnd.h> 68 #include <scsi/scsi_tcq.h> 69 #include <scsi/scsi_device.h> 70 #include <scsi/scsi_transport.h> 71 #include <scsi/scsicam.h> 72 #include "arcmsr.h" 73 MODULE_AUTHOR("Nick Cheng, C.L. Huang <support@areca.com.tw>"); 74 MODULE_DESCRIPTION("Areca ARC11xx/12xx/16xx/188x SAS/SATA RAID Controller Driver"); 75 MODULE_LICENSE("Dual BSD/GPL"); 76 MODULE_VERSION(ARCMSR_DRIVER_VERSION); 77 78 static int msix_enable = 1; 79 module_param(msix_enable, int, S_IRUGO); 80 MODULE_PARM_DESC(msix_enable, "Enable MSI-X interrupt(0 ~ 1), msix_enable=1(enable), =0(disable)"); 81 82 static int msi_enable = 1; 83 module_param(msi_enable, int, S_IRUGO); 84 MODULE_PARM_DESC(msi_enable, "Enable MSI interrupt(0 ~ 1), msi_enable=1(enable), =0(disable)"); 85 86 static int host_can_queue = ARCMSR_DEFAULT_OUTSTANDING_CMD; 87 module_param(host_can_queue, int, S_IRUGO); 88 MODULE_PARM_DESC(host_can_queue, " adapter queue depth(32 ~ 1024), default is 128"); 89 90 static int cmd_per_lun = ARCMSR_DEFAULT_CMD_PERLUN; 91 module_param(cmd_per_lun, int, S_IRUGO); 92 MODULE_PARM_DESC(cmd_per_lun, " device queue depth(1 ~ 128), default is 32"); 93 94 static int set_date_time = 0; 95 module_param(set_date_time, int, S_IRUGO); 96 MODULE_PARM_DESC(set_date_time, " send date, time to iop(0 ~ 1), set_date_time=1(enable), default(=0) is disable"); 97 98 #define ARCMSR_SLEEPTIME 10 99 #define ARCMSR_RETRYCOUNT 12 100 101 static wait_queue_head_t wait_q; 102 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, 103 struct scsi_cmnd *cmd); 104 static int arcmsr_iop_confirm(struct AdapterControlBlock *acb); 105 static int arcmsr_abort(struct scsi_cmnd *); 106 static int arcmsr_bus_reset(struct scsi_cmnd *); 107 static int arcmsr_bios_param(struct scsi_device *sdev, 108 struct block_device *bdev, sector_t capacity, int *info); 109 static int arcmsr_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd); 110 static int arcmsr_probe(struct pci_dev *pdev, 111 const struct pci_device_id *id); 112 static int arcmsr_suspend(struct pci_dev *pdev, pm_message_t state); 113 static int arcmsr_resume(struct pci_dev *pdev); 114 static void arcmsr_remove(struct pci_dev *pdev); 115 static void arcmsr_shutdown(struct pci_dev *pdev); 116 static void arcmsr_iop_init(struct AdapterControlBlock *acb); 117 static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb); 118 static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb); 119 static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb, 120 u32 intmask_org); 121 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb); 122 static void arcmsr_hbaA_flush_cache(struct AdapterControlBlock *acb); 123 static void arcmsr_hbaB_flush_cache(struct AdapterControlBlock *acb); 124 static void arcmsr_request_device_map(struct timer_list *t); 125 static void arcmsr_message_isr_bh_fn(struct work_struct *work); 126 static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb); 127 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb); 128 static void arcmsr_hbaC_message_isr(struct AdapterControlBlock *pACB); 129 static void arcmsr_hbaD_message_isr(struct AdapterControlBlock *acb); 130 static void arcmsr_hbaE_message_isr(struct AdapterControlBlock *acb); 131 static void arcmsr_hbaE_postqueue_isr(struct AdapterControlBlock *acb); 132 static void arcmsr_hardware_reset(struct AdapterControlBlock *acb); 133 static const char *arcmsr_info(struct Scsi_Host *); 134 static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb); 135 static void arcmsr_free_irq(struct pci_dev *, struct AdapterControlBlock *); 136 static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb); 137 static void arcmsr_set_iop_datetime(struct timer_list *); 138 static int arcmsr_adjust_disk_queue_depth(struct scsi_device *sdev, int queue_depth) 139 { 140 if (queue_depth > ARCMSR_MAX_CMD_PERLUN) 141 queue_depth = ARCMSR_MAX_CMD_PERLUN; 142 return scsi_change_queue_depth(sdev, queue_depth); 143 } 144 145 static struct scsi_host_template arcmsr_scsi_host_template = { 146 .module = THIS_MODULE, 147 .name = "Areca SAS/SATA RAID driver", 148 .info = arcmsr_info, 149 .queuecommand = arcmsr_queue_command, 150 .eh_abort_handler = arcmsr_abort, 151 .eh_bus_reset_handler = arcmsr_bus_reset, 152 .bios_param = arcmsr_bios_param, 153 .change_queue_depth = arcmsr_adjust_disk_queue_depth, 154 .can_queue = ARCMSR_DEFAULT_OUTSTANDING_CMD, 155 .this_id = ARCMSR_SCSI_INITIATOR_ID, 156 .sg_tablesize = ARCMSR_DEFAULT_SG_ENTRIES, 157 .max_sectors = ARCMSR_MAX_XFER_SECTORS_C, 158 .cmd_per_lun = ARCMSR_DEFAULT_CMD_PERLUN, 159 .use_clustering = ENABLE_CLUSTERING, 160 .shost_attrs = arcmsr_host_attrs, 161 .no_write_same = 1, 162 }; 163 164 static struct pci_device_id arcmsr_device_id_table[] = { 165 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1110), 166 .driver_data = ACB_ADAPTER_TYPE_A}, 167 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1120), 168 .driver_data = ACB_ADAPTER_TYPE_A}, 169 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1130), 170 .driver_data = ACB_ADAPTER_TYPE_A}, 171 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1160), 172 .driver_data = ACB_ADAPTER_TYPE_A}, 173 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1170), 174 .driver_data = ACB_ADAPTER_TYPE_A}, 175 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1200), 176 .driver_data = ACB_ADAPTER_TYPE_B}, 177 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1201), 178 .driver_data = ACB_ADAPTER_TYPE_B}, 179 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1202), 180 .driver_data = ACB_ADAPTER_TYPE_B}, 181 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1203), 182 .driver_data = ACB_ADAPTER_TYPE_B}, 183 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1210), 184 .driver_data = ACB_ADAPTER_TYPE_A}, 185 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1214), 186 .driver_data = ACB_ADAPTER_TYPE_D}, 187 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1220), 188 .driver_data = ACB_ADAPTER_TYPE_A}, 189 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1230), 190 .driver_data = ACB_ADAPTER_TYPE_A}, 191 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1260), 192 .driver_data = ACB_ADAPTER_TYPE_A}, 193 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1270), 194 .driver_data = ACB_ADAPTER_TYPE_A}, 195 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1280), 196 .driver_data = ACB_ADAPTER_TYPE_A}, 197 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1380), 198 .driver_data = ACB_ADAPTER_TYPE_A}, 199 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1381), 200 .driver_data = ACB_ADAPTER_TYPE_A}, 201 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1680), 202 .driver_data = ACB_ADAPTER_TYPE_A}, 203 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1681), 204 .driver_data = ACB_ADAPTER_TYPE_A}, 205 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1880), 206 .driver_data = ACB_ADAPTER_TYPE_C}, 207 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1884), 208 .driver_data = ACB_ADAPTER_TYPE_E}, 209 {0, 0}, /* Terminating entry */ 210 }; 211 MODULE_DEVICE_TABLE(pci, arcmsr_device_id_table); 212 213 static struct pci_driver arcmsr_pci_driver = { 214 .name = "arcmsr", 215 .id_table = arcmsr_device_id_table, 216 .probe = arcmsr_probe, 217 .remove = arcmsr_remove, 218 .suspend = arcmsr_suspend, 219 .resume = arcmsr_resume, 220 .shutdown = arcmsr_shutdown, 221 }; 222 /* 223 **************************************************************************** 224 **************************************************************************** 225 */ 226 227 static void arcmsr_free_mu(struct AdapterControlBlock *acb) 228 { 229 switch (acb->adapter_type) { 230 case ACB_ADAPTER_TYPE_B: 231 case ACB_ADAPTER_TYPE_D: 232 case ACB_ADAPTER_TYPE_E: { 233 dma_free_coherent(&acb->pdev->dev, acb->roundup_ccbsize, 234 acb->dma_coherent2, acb->dma_coherent_handle2); 235 break; 236 } 237 } 238 } 239 240 static bool arcmsr_remap_pciregion(struct AdapterControlBlock *acb) 241 { 242 struct pci_dev *pdev = acb->pdev; 243 switch (acb->adapter_type){ 244 case ACB_ADAPTER_TYPE_A:{ 245 acb->pmuA = ioremap(pci_resource_start(pdev,0), pci_resource_len(pdev,0)); 246 if (!acb->pmuA) { 247 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no); 248 return false; 249 } 250 break; 251 } 252 case ACB_ADAPTER_TYPE_B:{ 253 void __iomem *mem_base0, *mem_base1; 254 mem_base0 = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0)); 255 if (!mem_base0) { 256 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no); 257 return false; 258 } 259 mem_base1 = ioremap(pci_resource_start(pdev, 2), pci_resource_len(pdev, 2)); 260 if (!mem_base1) { 261 iounmap(mem_base0); 262 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no); 263 return false; 264 } 265 acb->mem_base0 = mem_base0; 266 acb->mem_base1 = mem_base1; 267 break; 268 } 269 case ACB_ADAPTER_TYPE_C:{ 270 acb->pmuC = ioremap_nocache(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1)); 271 if (!acb->pmuC) { 272 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no); 273 return false; 274 } 275 if (readl(&acb->pmuC->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 276 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &acb->pmuC->outbound_doorbell_clear);/*clear interrupt*/ 277 return true; 278 } 279 break; 280 } 281 case ACB_ADAPTER_TYPE_D: { 282 void __iomem *mem_base0; 283 unsigned long addr, range, flags; 284 285 addr = (unsigned long)pci_resource_start(pdev, 0); 286 range = pci_resource_len(pdev, 0); 287 flags = pci_resource_flags(pdev, 0); 288 mem_base0 = ioremap(addr, range); 289 if (!mem_base0) { 290 pr_notice("arcmsr%d: memory mapping region fail\n", 291 acb->host->host_no); 292 return false; 293 } 294 acb->mem_base0 = mem_base0; 295 break; 296 } 297 case ACB_ADAPTER_TYPE_E: { 298 acb->pmuE = ioremap(pci_resource_start(pdev, 1), 299 pci_resource_len(pdev, 1)); 300 if (!acb->pmuE) { 301 pr_notice("arcmsr%d: memory mapping region fail \n", 302 acb->host->host_no); 303 return false; 304 } 305 writel(0, &acb->pmuE->host_int_status); /*clear interrupt*/ 306 writel(ARCMSR_HBEMU_DOORBELL_SYNC, &acb->pmuE->iobound_doorbell); /* synchronize doorbell to 0 */ 307 acb->in_doorbell = 0; 308 acb->out_doorbell = 0; 309 break; 310 } 311 } 312 return true; 313 } 314 315 static void arcmsr_unmap_pciregion(struct AdapterControlBlock *acb) 316 { 317 switch (acb->adapter_type) { 318 case ACB_ADAPTER_TYPE_A:{ 319 iounmap(acb->pmuA); 320 } 321 break; 322 case ACB_ADAPTER_TYPE_B:{ 323 iounmap(acb->mem_base0); 324 iounmap(acb->mem_base1); 325 } 326 327 break; 328 case ACB_ADAPTER_TYPE_C:{ 329 iounmap(acb->pmuC); 330 } 331 break; 332 case ACB_ADAPTER_TYPE_D: 333 iounmap(acb->mem_base0); 334 break; 335 case ACB_ADAPTER_TYPE_E: 336 iounmap(acb->pmuE); 337 break; 338 } 339 } 340 341 static irqreturn_t arcmsr_do_interrupt(int irq, void *dev_id) 342 { 343 irqreturn_t handle_state; 344 struct AdapterControlBlock *acb = dev_id; 345 346 handle_state = arcmsr_interrupt(acb); 347 return handle_state; 348 } 349 350 static int arcmsr_bios_param(struct scsi_device *sdev, 351 struct block_device *bdev, sector_t capacity, int *geom) 352 { 353 int ret, heads, sectors, cylinders, total_capacity; 354 unsigned char *buffer;/* return copy of block device's partition table */ 355 356 buffer = scsi_bios_ptable(bdev); 357 if (buffer) { 358 ret = scsi_partsize(buffer, capacity, &geom[2], &geom[0], &geom[1]); 359 kfree(buffer); 360 if (ret != -1) 361 return ret; 362 } 363 total_capacity = capacity; 364 heads = 64; 365 sectors = 32; 366 cylinders = total_capacity / (heads * sectors); 367 if (cylinders > 1024) { 368 heads = 255; 369 sectors = 63; 370 cylinders = total_capacity / (heads * sectors); 371 } 372 geom[0] = heads; 373 geom[1] = sectors; 374 geom[2] = cylinders; 375 return 0; 376 } 377 378 static uint8_t arcmsr_hbaA_wait_msgint_ready(struct AdapterControlBlock *acb) 379 { 380 struct MessageUnit_A __iomem *reg = acb->pmuA; 381 int i; 382 383 for (i = 0; i < 2000; i++) { 384 if (readl(®->outbound_intstatus) & 385 ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 386 writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT, 387 ®->outbound_intstatus); 388 return true; 389 } 390 msleep(10); 391 } /* max 20 seconds */ 392 393 return false; 394 } 395 396 static uint8_t arcmsr_hbaB_wait_msgint_ready(struct AdapterControlBlock *acb) 397 { 398 struct MessageUnit_B *reg = acb->pmuB; 399 int i; 400 401 for (i = 0; i < 2000; i++) { 402 if (readl(reg->iop2drv_doorbell) 403 & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 404 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, 405 reg->iop2drv_doorbell); 406 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, 407 reg->drv2iop_doorbell); 408 return true; 409 } 410 msleep(10); 411 } /* max 20 seconds */ 412 413 return false; 414 } 415 416 static uint8_t arcmsr_hbaC_wait_msgint_ready(struct AdapterControlBlock *pACB) 417 { 418 struct MessageUnit_C __iomem *phbcmu = pACB->pmuC; 419 int i; 420 421 for (i = 0; i < 2000; i++) { 422 if (readl(&phbcmu->outbound_doorbell) 423 & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 424 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, 425 &phbcmu->outbound_doorbell_clear); /*clear interrupt*/ 426 return true; 427 } 428 msleep(10); 429 } /* max 20 seconds */ 430 431 return false; 432 } 433 434 static bool arcmsr_hbaD_wait_msgint_ready(struct AdapterControlBlock *pACB) 435 { 436 struct MessageUnit_D *reg = pACB->pmuD; 437 int i; 438 439 for (i = 0; i < 2000; i++) { 440 if (readl(reg->outbound_doorbell) 441 & ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE) { 442 writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE, 443 reg->outbound_doorbell); 444 return true; 445 } 446 msleep(10); 447 } /* max 20 seconds */ 448 return false; 449 } 450 451 static bool arcmsr_hbaE_wait_msgint_ready(struct AdapterControlBlock *pACB) 452 { 453 int i; 454 uint32_t read_doorbell; 455 struct MessageUnit_E __iomem *phbcmu = pACB->pmuE; 456 457 for (i = 0; i < 2000; i++) { 458 read_doorbell = readl(&phbcmu->iobound_doorbell); 459 if ((read_doorbell ^ pACB->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) { 460 writel(0, &phbcmu->host_int_status); /*clear interrupt*/ 461 pACB->in_doorbell = read_doorbell; 462 return true; 463 } 464 msleep(10); 465 } /* max 20 seconds */ 466 return false; 467 } 468 469 static void arcmsr_hbaA_flush_cache(struct AdapterControlBlock *acb) 470 { 471 struct MessageUnit_A __iomem *reg = acb->pmuA; 472 int retry_count = 30; 473 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, ®->inbound_msgaddr0); 474 do { 475 if (arcmsr_hbaA_wait_msgint_ready(acb)) 476 break; 477 else { 478 retry_count--; 479 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \ 480 timeout, retry count down = %d \n", acb->host->host_no, retry_count); 481 } 482 } while (retry_count != 0); 483 } 484 485 static void arcmsr_hbaB_flush_cache(struct AdapterControlBlock *acb) 486 { 487 struct MessageUnit_B *reg = acb->pmuB; 488 int retry_count = 30; 489 writel(ARCMSR_MESSAGE_FLUSH_CACHE, reg->drv2iop_doorbell); 490 do { 491 if (arcmsr_hbaB_wait_msgint_ready(acb)) 492 break; 493 else { 494 retry_count--; 495 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \ 496 timeout,retry count down = %d \n", acb->host->host_no, retry_count); 497 } 498 } while (retry_count != 0); 499 } 500 501 static void arcmsr_hbaC_flush_cache(struct AdapterControlBlock *pACB) 502 { 503 struct MessageUnit_C __iomem *reg = pACB->pmuC; 504 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 505 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, ®->inbound_msgaddr0); 506 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell); 507 do { 508 if (arcmsr_hbaC_wait_msgint_ready(pACB)) { 509 break; 510 } else { 511 retry_count--; 512 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \ 513 timeout,retry count down = %d \n", pACB->host->host_no, retry_count); 514 } 515 } while (retry_count != 0); 516 return; 517 } 518 519 static void arcmsr_hbaD_flush_cache(struct AdapterControlBlock *pACB) 520 { 521 int retry_count = 15; 522 struct MessageUnit_D *reg = pACB->pmuD; 523 524 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, reg->inbound_msgaddr0); 525 do { 526 if (arcmsr_hbaD_wait_msgint_ready(pACB)) 527 break; 528 529 retry_count--; 530 pr_notice("arcmsr%d: wait 'flush adapter " 531 "cache' timeout, retry count down = %d\n", 532 pACB->host->host_no, retry_count); 533 } while (retry_count != 0); 534 } 535 536 static void arcmsr_hbaE_flush_cache(struct AdapterControlBlock *pACB) 537 { 538 int retry_count = 30; 539 struct MessageUnit_E __iomem *reg = pACB->pmuE; 540 541 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, ®->inbound_msgaddr0); 542 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 543 writel(pACB->out_doorbell, ®->iobound_doorbell); 544 do { 545 if (arcmsr_hbaE_wait_msgint_ready(pACB)) 546 break; 547 retry_count--; 548 pr_notice("arcmsr%d: wait 'flush adapter " 549 "cache' timeout, retry count down = %d\n", 550 pACB->host->host_no, retry_count); 551 } while (retry_count != 0); 552 } 553 554 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb) 555 { 556 switch (acb->adapter_type) { 557 558 case ACB_ADAPTER_TYPE_A: { 559 arcmsr_hbaA_flush_cache(acb); 560 } 561 break; 562 563 case ACB_ADAPTER_TYPE_B: { 564 arcmsr_hbaB_flush_cache(acb); 565 } 566 break; 567 case ACB_ADAPTER_TYPE_C: { 568 arcmsr_hbaC_flush_cache(acb); 569 } 570 break; 571 case ACB_ADAPTER_TYPE_D: 572 arcmsr_hbaD_flush_cache(acb); 573 break; 574 case ACB_ADAPTER_TYPE_E: 575 arcmsr_hbaE_flush_cache(acb); 576 break; 577 } 578 } 579 580 static bool arcmsr_alloc_io_queue(struct AdapterControlBlock *acb) 581 { 582 bool rtn = true; 583 void *dma_coherent; 584 dma_addr_t dma_coherent_handle; 585 struct pci_dev *pdev = acb->pdev; 586 587 switch (acb->adapter_type) { 588 case ACB_ADAPTER_TYPE_B: { 589 struct MessageUnit_B *reg; 590 acb->roundup_ccbsize = roundup(sizeof(struct MessageUnit_B), 32); 591 dma_coherent = dma_zalloc_coherent(&pdev->dev, acb->roundup_ccbsize, 592 &dma_coherent_handle, GFP_KERNEL); 593 if (!dma_coherent) { 594 pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no); 595 return false; 596 } 597 acb->dma_coherent_handle2 = dma_coherent_handle; 598 acb->dma_coherent2 = dma_coherent; 599 reg = (struct MessageUnit_B *)dma_coherent; 600 acb->pmuB = reg; 601 if (acb->pdev->device == PCI_DEVICE_ID_ARECA_1203) { 602 reg->drv2iop_doorbell = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_1203); 603 reg->drv2iop_doorbell_mask = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_MASK_1203); 604 reg->iop2drv_doorbell = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_1203); 605 reg->iop2drv_doorbell_mask = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_MASK_1203); 606 } else { 607 reg->drv2iop_doorbell = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL); 608 reg->drv2iop_doorbell_mask = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_MASK); 609 reg->iop2drv_doorbell = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL); 610 reg->iop2drv_doorbell_mask = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_MASK); 611 } 612 reg->message_wbuffer = MEM_BASE1(ARCMSR_MESSAGE_WBUFFER); 613 reg->message_rbuffer = MEM_BASE1(ARCMSR_MESSAGE_RBUFFER); 614 reg->message_rwbuffer = MEM_BASE1(ARCMSR_MESSAGE_RWBUFFER); 615 } 616 break; 617 case ACB_ADAPTER_TYPE_D: { 618 struct MessageUnit_D *reg; 619 620 acb->roundup_ccbsize = roundup(sizeof(struct MessageUnit_D), 32); 621 dma_coherent = dma_zalloc_coherent(&pdev->dev, acb->roundup_ccbsize, 622 &dma_coherent_handle, GFP_KERNEL); 623 if (!dma_coherent) { 624 pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no); 625 return false; 626 } 627 acb->dma_coherent_handle2 = dma_coherent_handle; 628 acb->dma_coherent2 = dma_coherent; 629 reg = (struct MessageUnit_D *)dma_coherent; 630 acb->pmuD = reg; 631 reg->chip_id = MEM_BASE0(ARCMSR_ARC1214_CHIP_ID); 632 reg->cpu_mem_config = MEM_BASE0(ARCMSR_ARC1214_CPU_MEMORY_CONFIGURATION); 633 reg->i2o_host_interrupt_mask = MEM_BASE0(ARCMSR_ARC1214_I2_HOST_INTERRUPT_MASK); 634 reg->sample_at_reset = MEM_BASE0(ARCMSR_ARC1214_SAMPLE_RESET); 635 reg->reset_request = MEM_BASE0(ARCMSR_ARC1214_RESET_REQUEST); 636 reg->host_int_status = MEM_BASE0(ARCMSR_ARC1214_MAIN_INTERRUPT_STATUS); 637 reg->pcief0_int_enable = MEM_BASE0(ARCMSR_ARC1214_PCIE_F0_INTERRUPT_ENABLE); 638 reg->inbound_msgaddr0 = MEM_BASE0(ARCMSR_ARC1214_INBOUND_MESSAGE0); 639 reg->inbound_msgaddr1 = MEM_BASE0(ARCMSR_ARC1214_INBOUND_MESSAGE1); 640 reg->outbound_msgaddr0 = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_MESSAGE0); 641 reg->outbound_msgaddr1 = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_MESSAGE1); 642 reg->inbound_doorbell = MEM_BASE0(ARCMSR_ARC1214_INBOUND_DOORBELL); 643 reg->outbound_doorbell = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_DOORBELL); 644 reg->outbound_doorbell_enable = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_DOORBELL_ENABLE); 645 reg->inboundlist_base_low = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_BASE_LOW); 646 reg->inboundlist_base_high = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_BASE_HIGH); 647 reg->inboundlist_write_pointer = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_WRITE_POINTER); 648 reg->outboundlist_base_low = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_BASE_LOW); 649 reg->outboundlist_base_high = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_BASE_HIGH); 650 reg->outboundlist_copy_pointer = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_COPY_POINTER); 651 reg->outboundlist_read_pointer = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_READ_POINTER); 652 reg->outboundlist_interrupt_cause = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_INTERRUPT_CAUSE); 653 reg->outboundlist_interrupt_enable = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_INTERRUPT_ENABLE); 654 reg->message_wbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_WBUFFER); 655 reg->message_rbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_RBUFFER); 656 reg->msgcode_rwbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_RWBUFFER); 657 } 658 break; 659 case ACB_ADAPTER_TYPE_E: { 660 uint32_t completeQ_size; 661 completeQ_size = sizeof(struct deliver_completeQ) * ARCMSR_MAX_HBE_DONEQUEUE + 128; 662 acb->roundup_ccbsize = roundup(completeQ_size, 32); 663 dma_coherent = dma_zalloc_coherent(&pdev->dev, acb->roundup_ccbsize, 664 &dma_coherent_handle, GFP_KERNEL); 665 if (!dma_coherent){ 666 pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no); 667 return false; 668 } 669 acb->dma_coherent_handle2 = dma_coherent_handle; 670 acb->dma_coherent2 = dma_coherent; 671 acb->pCompletionQ = dma_coherent; 672 acb->completionQ_entry = acb->roundup_ccbsize / sizeof(struct deliver_completeQ); 673 acb->doneq_index = 0; 674 } 675 break; 676 default: 677 break; 678 } 679 return rtn; 680 } 681 682 static int arcmsr_alloc_ccb_pool(struct AdapterControlBlock *acb) 683 { 684 struct pci_dev *pdev = acb->pdev; 685 void *dma_coherent; 686 dma_addr_t dma_coherent_handle; 687 struct CommandControlBlock *ccb_tmp; 688 int i = 0, j = 0; 689 dma_addr_t cdb_phyaddr; 690 unsigned long roundup_ccbsize; 691 unsigned long max_xfer_len; 692 unsigned long max_sg_entrys; 693 uint32_t firm_config_version; 694 695 for (i = 0; i < ARCMSR_MAX_TARGETID; i++) 696 for (j = 0; j < ARCMSR_MAX_TARGETLUN; j++) 697 acb->devstate[i][j] = ARECA_RAID_GONE; 698 699 max_xfer_len = ARCMSR_MAX_XFER_LEN; 700 max_sg_entrys = ARCMSR_DEFAULT_SG_ENTRIES; 701 firm_config_version = acb->firm_cfg_version; 702 if((firm_config_version & 0xFF) >= 3){ 703 max_xfer_len = (ARCMSR_CDB_SG_PAGE_LENGTH << ((firm_config_version >> 8) & 0xFF)) * 1024;/* max 4M byte */ 704 max_sg_entrys = (max_xfer_len/4096); 705 } 706 acb->host->max_sectors = max_xfer_len/512; 707 acb->host->sg_tablesize = max_sg_entrys; 708 roundup_ccbsize = roundup(sizeof(struct CommandControlBlock) + (max_sg_entrys - 1) * sizeof(struct SG64ENTRY), 32); 709 acb->uncache_size = roundup_ccbsize * acb->maxFreeCCB; 710 dma_coherent = dma_alloc_coherent(&pdev->dev, acb->uncache_size, &dma_coherent_handle, GFP_KERNEL); 711 if(!dma_coherent){ 712 printk(KERN_NOTICE "arcmsr%d: dma_alloc_coherent got error\n", acb->host->host_no); 713 return -ENOMEM; 714 } 715 acb->dma_coherent = dma_coherent; 716 acb->dma_coherent_handle = dma_coherent_handle; 717 memset(dma_coherent, 0, acb->uncache_size); 718 acb->ccbsize = roundup_ccbsize; 719 ccb_tmp = dma_coherent; 720 acb->vir2phy_offset = (unsigned long)dma_coherent - (unsigned long)dma_coherent_handle; 721 for(i = 0; i < acb->maxFreeCCB; i++){ 722 cdb_phyaddr = dma_coherent_handle + offsetof(struct CommandControlBlock, arcmsr_cdb); 723 switch (acb->adapter_type) { 724 case ACB_ADAPTER_TYPE_A: 725 case ACB_ADAPTER_TYPE_B: 726 ccb_tmp->cdb_phyaddr = cdb_phyaddr >> 5; 727 break; 728 case ACB_ADAPTER_TYPE_C: 729 case ACB_ADAPTER_TYPE_D: 730 case ACB_ADAPTER_TYPE_E: 731 ccb_tmp->cdb_phyaddr = cdb_phyaddr; 732 break; 733 } 734 acb->pccb_pool[i] = ccb_tmp; 735 ccb_tmp->acb = acb; 736 ccb_tmp->smid = (u32)i << 16; 737 INIT_LIST_HEAD(&ccb_tmp->list); 738 list_add_tail(&ccb_tmp->list, &acb->ccb_free_list); 739 ccb_tmp = (struct CommandControlBlock *)((unsigned long)ccb_tmp + roundup_ccbsize); 740 dma_coherent_handle = dma_coherent_handle + roundup_ccbsize; 741 } 742 return 0; 743 } 744 745 static void arcmsr_message_isr_bh_fn(struct work_struct *work) 746 { 747 struct AdapterControlBlock *acb = container_of(work, 748 struct AdapterControlBlock, arcmsr_do_message_isr_bh); 749 char *acb_dev_map = (char *)acb->device_map; 750 uint32_t __iomem *signature = NULL; 751 char __iomem *devicemap = NULL; 752 int target, lun; 753 struct scsi_device *psdev; 754 char diff, temp; 755 756 acb->acb_flags &= ~ACB_F_MSG_GET_CONFIG; 757 switch (acb->adapter_type) { 758 case ACB_ADAPTER_TYPE_A: { 759 struct MessageUnit_A __iomem *reg = acb->pmuA; 760 761 signature = (uint32_t __iomem *)(®->message_rwbuffer[0]); 762 devicemap = (char __iomem *)(®->message_rwbuffer[21]); 763 break; 764 } 765 case ACB_ADAPTER_TYPE_B: { 766 struct MessageUnit_B *reg = acb->pmuB; 767 768 signature = (uint32_t __iomem *)(®->message_rwbuffer[0]); 769 devicemap = (char __iomem *)(®->message_rwbuffer[21]); 770 break; 771 } 772 case ACB_ADAPTER_TYPE_C: { 773 struct MessageUnit_C __iomem *reg = acb->pmuC; 774 775 signature = (uint32_t __iomem *)(®->msgcode_rwbuffer[0]); 776 devicemap = (char __iomem *)(®->msgcode_rwbuffer[21]); 777 break; 778 } 779 case ACB_ADAPTER_TYPE_D: { 780 struct MessageUnit_D *reg = acb->pmuD; 781 782 signature = (uint32_t __iomem *)(®->msgcode_rwbuffer[0]); 783 devicemap = (char __iomem *)(®->msgcode_rwbuffer[21]); 784 break; 785 } 786 case ACB_ADAPTER_TYPE_E: { 787 struct MessageUnit_E __iomem *reg = acb->pmuE; 788 789 signature = (uint32_t __iomem *)(®->msgcode_rwbuffer[0]); 790 devicemap = (char __iomem *)(®->msgcode_rwbuffer[21]); 791 break; 792 } 793 } 794 atomic_inc(&acb->rq_map_token); 795 if (readl(signature) != ARCMSR_SIGNATURE_GET_CONFIG) 796 return; 797 for (target = 0; target < ARCMSR_MAX_TARGETID - 1; 798 target++) { 799 temp = readb(devicemap); 800 diff = (*acb_dev_map) ^ temp; 801 if (diff != 0) { 802 *acb_dev_map = temp; 803 for (lun = 0; lun < ARCMSR_MAX_TARGETLUN; 804 lun++) { 805 if ((diff & 0x01) == 1 && 806 (temp & 0x01) == 1) { 807 scsi_add_device(acb->host, 808 0, target, lun); 809 } else if ((diff & 0x01) == 1 810 && (temp & 0x01) == 0) { 811 psdev = scsi_device_lookup(acb->host, 812 0, target, lun); 813 if (psdev != NULL) { 814 scsi_remove_device(psdev); 815 scsi_device_put(psdev); 816 } 817 } 818 temp >>= 1; 819 diff >>= 1; 820 } 821 } 822 devicemap++; 823 acb_dev_map++; 824 } 825 } 826 827 static int 828 arcmsr_request_irq(struct pci_dev *pdev, struct AdapterControlBlock *acb) 829 { 830 unsigned long flags; 831 int nvec, i; 832 833 if (msix_enable == 0) 834 goto msi_int0; 835 nvec = pci_alloc_irq_vectors(pdev, 1, ARCMST_NUM_MSIX_VECTORS, 836 PCI_IRQ_MSIX); 837 if (nvec > 0) { 838 pr_info("arcmsr%d: msi-x enabled\n", acb->host->host_no); 839 flags = 0; 840 } else { 841 msi_int0: 842 if (msi_enable == 1) { 843 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); 844 if (nvec == 1) { 845 dev_info(&pdev->dev, "msi enabled\n"); 846 goto msi_int1; 847 } 848 } 849 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_LEGACY); 850 if (nvec < 1) 851 return FAILED; 852 msi_int1: 853 flags = IRQF_SHARED; 854 } 855 856 acb->vector_count = nvec; 857 for (i = 0; i < nvec; i++) { 858 if (request_irq(pci_irq_vector(pdev, i), arcmsr_do_interrupt, 859 flags, "arcmsr", acb)) { 860 pr_warn("arcmsr%d: request_irq =%d failed!\n", 861 acb->host->host_no, pci_irq_vector(pdev, i)); 862 goto out_free_irq; 863 } 864 } 865 866 return SUCCESS; 867 out_free_irq: 868 while (--i >= 0) 869 free_irq(pci_irq_vector(pdev, i), acb); 870 pci_free_irq_vectors(pdev); 871 return FAILED; 872 } 873 874 static void arcmsr_init_get_devmap_timer(struct AdapterControlBlock *pacb) 875 { 876 INIT_WORK(&pacb->arcmsr_do_message_isr_bh, arcmsr_message_isr_bh_fn); 877 atomic_set(&pacb->rq_map_token, 16); 878 atomic_set(&pacb->ante_token_value, 16); 879 pacb->fw_flag = FW_NORMAL; 880 timer_setup(&pacb->eternal_timer, arcmsr_request_device_map, 0); 881 pacb->eternal_timer.expires = jiffies + msecs_to_jiffies(6 * HZ); 882 add_timer(&pacb->eternal_timer); 883 } 884 885 static void arcmsr_init_set_datetime_timer(struct AdapterControlBlock *pacb) 886 { 887 timer_setup(&pacb->refresh_timer, arcmsr_set_iop_datetime, 0); 888 pacb->refresh_timer.expires = jiffies + msecs_to_jiffies(60 * 1000); 889 add_timer(&pacb->refresh_timer); 890 } 891 892 static int arcmsr_probe(struct pci_dev *pdev, const struct pci_device_id *id) 893 { 894 struct Scsi_Host *host; 895 struct AdapterControlBlock *acb; 896 uint8_t bus,dev_fun; 897 int error; 898 error = pci_enable_device(pdev); 899 if(error){ 900 return -ENODEV; 901 } 902 host = scsi_host_alloc(&arcmsr_scsi_host_template, sizeof(struct AdapterControlBlock)); 903 if(!host){ 904 goto pci_disable_dev; 905 } 906 error = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 907 if(error){ 908 error = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 909 if(error){ 910 printk(KERN_WARNING 911 "scsi%d: No suitable DMA mask available\n", 912 host->host_no); 913 goto scsi_host_release; 914 } 915 } 916 init_waitqueue_head(&wait_q); 917 bus = pdev->bus->number; 918 dev_fun = pdev->devfn; 919 acb = (struct AdapterControlBlock *) host->hostdata; 920 memset(acb,0,sizeof(struct AdapterControlBlock)); 921 acb->pdev = pdev; 922 acb->host = host; 923 host->max_lun = ARCMSR_MAX_TARGETLUN; 924 host->max_id = ARCMSR_MAX_TARGETID; /*16:8*/ 925 host->max_cmd_len = 16; /*this is issue of 64bit LBA ,over 2T byte*/ 926 if ((host_can_queue < ARCMSR_MIN_OUTSTANDING_CMD) || (host_can_queue > ARCMSR_MAX_OUTSTANDING_CMD)) 927 host_can_queue = ARCMSR_DEFAULT_OUTSTANDING_CMD; 928 host->can_queue = host_can_queue; /* max simultaneous cmds */ 929 if ((cmd_per_lun < ARCMSR_MIN_CMD_PERLUN) || (cmd_per_lun > ARCMSR_MAX_CMD_PERLUN)) 930 cmd_per_lun = ARCMSR_DEFAULT_CMD_PERLUN; 931 host->cmd_per_lun = cmd_per_lun; 932 host->this_id = ARCMSR_SCSI_INITIATOR_ID; 933 host->unique_id = (bus << 8) | dev_fun; 934 pci_set_drvdata(pdev, host); 935 pci_set_master(pdev); 936 error = pci_request_regions(pdev, "arcmsr"); 937 if(error){ 938 goto scsi_host_release; 939 } 940 spin_lock_init(&acb->eh_lock); 941 spin_lock_init(&acb->ccblist_lock); 942 spin_lock_init(&acb->postq_lock); 943 spin_lock_init(&acb->doneq_lock); 944 spin_lock_init(&acb->rqbuffer_lock); 945 spin_lock_init(&acb->wqbuffer_lock); 946 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED | 947 ACB_F_MESSAGE_RQBUFFER_CLEARED | 948 ACB_F_MESSAGE_WQBUFFER_READED); 949 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER; 950 INIT_LIST_HEAD(&acb->ccb_free_list); 951 acb->adapter_type = id->driver_data; 952 error = arcmsr_remap_pciregion(acb); 953 if(!error){ 954 goto pci_release_regs; 955 } 956 error = arcmsr_alloc_io_queue(acb); 957 if (!error) 958 goto unmap_pci_region; 959 error = arcmsr_get_firmware_spec(acb); 960 if(!error){ 961 goto free_hbb_mu; 962 } 963 error = arcmsr_alloc_ccb_pool(acb); 964 if(error){ 965 goto free_hbb_mu; 966 } 967 error = scsi_add_host(host, &pdev->dev); 968 if(error){ 969 goto free_ccb_pool; 970 } 971 if (arcmsr_request_irq(pdev, acb) == FAILED) 972 goto scsi_host_remove; 973 arcmsr_iop_init(acb); 974 arcmsr_init_get_devmap_timer(acb); 975 if (set_date_time) 976 arcmsr_init_set_datetime_timer(acb); 977 if(arcmsr_alloc_sysfs_attr(acb)) 978 goto out_free_sysfs; 979 scsi_scan_host(host); 980 return 0; 981 out_free_sysfs: 982 if (set_date_time) 983 del_timer_sync(&acb->refresh_timer); 984 del_timer_sync(&acb->eternal_timer); 985 flush_work(&acb->arcmsr_do_message_isr_bh); 986 arcmsr_stop_adapter_bgrb(acb); 987 arcmsr_flush_adapter_cache(acb); 988 arcmsr_free_irq(pdev, acb); 989 scsi_host_remove: 990 scsi_remove_host(host); 991 free_ccb_pool: 992 arcmsr_free_ccb_pool(acb); 993 free_hbb_mu: 994 arcmsr_free_mu(acb); 995 unmap_pci_region: 996 arcmsr_unmap_pciregion(acb); 997 pci_release_regs: 998 pci_release_regions(pdev); 999 scsi_host_release: 1000 scsi_host_put(host); 1001 pci_disable_dev: 1002 pci_disable_device(pdev); 1003 return -ENODEV; 1004 } 1005 1006 static void arcmsr_free_irq(struct pci_dev *pdev, 1007 struct AdapterControlBlock *acb) 1008 { 1009 int i; 1010 1011 for (i = 0; i < acb->vector_count; i++) 1012 free_irq(pci_irq_vector(pdev, i), acb); 1013 pci_free_irq_vectors(pdev); 1014 } 1015 1016 static int arcmsr_suspend(struct pci_dev *pdev, pm_message_t state) 1017 { 1018 uint32_t intmask_org; 1019 struct Scsi_Host *host = pci_get_drvdata(pdev); 1020 struct AdapterControlBlock *acb = 1021 (struct AdapterControlBlock *)host->hostdata; 1022 1023 intmask_org = arcmsr_disable_outbound_ints(acb); 1024 arcmsr_free_irq(pdev, acb); 1025 del_timer_sync(&acb->eternal_timer); 1026 if (set_date_time) 1027 del_timer_sync(&acb->refresh_timer); 1028 flush_work(&acb->arcmsr_do_message_isr_bh); 1029 arcmsr_stop_adapter_bgrb(acb); 1030 arcmsr_flush_adapter_cache(acb); 1031 pci_set_drvdata(pdev, host); 1032 pci_save_state(pdev); 1033 pci_disable_device(pdev); 1034 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1035 return 0; 1036 } 1037 1038 static int arcmsr_resume(struct pci_dev *pdev) 1039 { 1040 int error; 1041 struct Scsi_Host *host = pci_get_drvdata(pdev); 1042 struct AdapterControlBlock *acb = 1043 (struct AdapterControlBlock *)host->hostdata; 1044 1045 pci_set_power_state(pdev, PCI_D0); 1046 pci_enable_wake(pdev, PCI_D0, 0); 1047 pci_restore_state(pdev); 1048 if (pci_enable_device(pdev)) { 1049 pr_warn("%s: pci_enable_device error\n", __func__); 1050 return -ENODEV; 1051 } 1052 error = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); 1053 if (error) { 1054 error = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 1055 if (error) { 1056 pr_warn("scsi%d: No suitable DMA mask available\n", 1057 host->host_no); 1058 goto controller_unregister; 1059 } 1060 } 1061 pci_set_master(pdev); 1062 if (arcmsr_request_irq(pdev, acb) == FAILED) 1063 goto controller_stop; 1064 if (acb->adapter_type == ACB_ADAPTER_TYPE_E) { 1065 writel(0, &acb->pmuE->host_int_status); 1066 writel(ARCMSR_HBEMU_DOORBELL_SYNC, &acb->pmuE->iobound_doorbell); 1067 acb->in_doorbell = 0; 1068 acb->out_doorbell = 0; 1069 acb->doneq_index = 0; 1070 } 1071 arcmsr_iop_init(acb); 1072 arcmsr_init_get_devmap_timer(acb); 1073 if (set_date_time) 1074 arcmsr_init_set_datetime_timer(acb); 1075 return 0; 1076 controller_stop: 1077 arcmsr_stop_adapter_bgrb(acb); 1078 arcmsr_flush_adapter_cache(acb); 1079 controller_unregister: 1080 scsi_remove_host(host); 1081 arcmsr_free_ccb_pool(acb); 1082 arcmsr_unmap_pciregion(acb); 1083 pci_release_regions(pdev); 1084 scsi_host_put(host); 1085 pci_disable_device(pdev); 1086 return -ENODEV; 1087 } 1088 1089 static uint8_t arcmsr_hbaA_abort_allcmd(struct AdapterControlBlock *acb) 1090 { 1091 struct MessageUnit_A __iomem *reg = acb->pmuA; 1092 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, ®->inbound_msgaddr0); 1093 if (!arcmsr_hbaA_wait_msgint_ready(acb)) { 1094 printk(KERN_NOTICE 1095 "arcmsr%d: wait 'abort all outstanding command' timeout\n" 1096 , acb->host->host_no); 1097 return false; 1098 } 1099 return true; 1100 } 1101 1102 static uint8_t arcmsr_hbaB_abort_allcmd(struct AdapterControlBlock *acb) 1103 { 1104 struct MessageUnit_B *reg = acb->pmuB; 1105 1106 writel(ARCMSR_MESSAGE_ABORT_CMD, reg->drv2iop_doorbell); 1107 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 1108 printk(KERN_NOTICE 1109 "arcmsr%d: wait 'abort all outstanding command' timeout\n" 1110 , acb->host->host_no); 1111 return false; 1112 } 1113 return true; 1114 } 1115 static uint8_t arcmsr_hbaC_abort_allcmd(struct AdapterControlBlock *pACB) 1116 { 1117 struct MessageUnit_C __iomem *reg = pACB->pmuC; 1118 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, ®->inbound_msgaddr0); 1119 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell); 1120 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) { 1121 printk(KERN_NOTICE 1122 "arcmsr%d: wait 'abort all outstanding command' timeout\n" 1123 , pACB->host->host_no); 1124 return false; 1125 } 1126 return true; 1127 } 1128 1129 static uint8_t arcmsr_hbaD_abort_allcmd(struct AdapterControlBlock *pACB) 1130 { 1131 struct MessageUnit_D *reg = pACB->pmuD; 1132 1133 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, reg->inbound_msgaddr0); 1134 if (!arcmsr_hbaD_wait_msgint_ready(pACB)) { 1135 pr_notice("arcmsr%d: wait 'abort all outstanding " 1136 "command' timeout\n", pACB->host->host_no); 1137 return false; 1138 } 1139 return true; 1140 } 1141 1142 static uint8_t arcmsr_hbaE_abort_allcmd(struct AdapterControlBlock *pACB) 1143 { 1144 struct MessageUnit_E __iomem *reg = pACB->pmuE; 1145 1146 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, ®->inbound_msgaddr0); 1147 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 1148 writel(pACB->out_doorbell, ®->iobound_doorbell); 1149 if (!arcmsr_hbaE_wait_msgint_ready(pACB)) { 1150 pr_notice("arcmsr%d: wait 'abort all outstanding " 1151 "command' timeout\n", pACB->host->host_no); 1152 return false; 1153 } 1154 return true; 1155 } 1156 1157 static uint8_t arcmsr_abort_allcmd(struct AdapterControlBlock *acb) 1158 { 1159 uint8_t rtnval = 0; 1160 switch (acb->adapter_type) { 1161 case ACB_ADAPTER_TYPE_A: { 1162 rtnval = arcmsr_hbaA_abort_allcmd(acb); 1163 } 1164 break; 1165 1166 case ACB_ADAPTER_TYPE_B: { 1167 rtnval = arcmsr_hbaB_abort_allcmd(acb); 1168 } 1169 break; 1170 1171 case ACB_ADAPTER_TYPE_C: { 1172 rtnval = arcmsr_hbaC_abort_allcmd(acb); 1173 } 1174 break; 1175 1176 case ACB_ADAPTER_TYPE_D: 1177 rtnval = arcmsr_hbaD_abort_allcmd(acb); 1178 break; 1179 case ACB_ADAPTER_TYPE_E: 1180 rtnval = arcmsr_hbaE_abort_allcmd(acb); 1181 break; 1182 } 1183 return rtnval; 1184 } 1185 1186 static void arcmsr_pci_unmap_dma(struct CommandControlBlock *ccb) 1187 { 1188 struct scsi_cmnd *pcmd = ccb->pcmd; 1189 1190 scsi_dma_unmap(pcmd); 1191 } 1192 1193 static void arcmsr_ccb_complete(struct CommandControlBlock *ccb) 1194 { 1195 struct AdapterControlBlock *acb = ccb->acb; 1196 struct scsi_cmnd *pcmd = ccb->pcmd; 1197 unsigned long flags; 1198 atomic_dec(&acb->ccboutstandingcount); 1199 arcmsr_pci_unmap_dma(ccb); 1200 ccb->startdone = ARCMSR_CCB_DONE; 1201 spin_lock_irqsave(&acb->ccblist_lock, flags); 1202 list_add_tail(&ccb->list, &acb->ccb_free_list); 1203 spin_unlock_irqrestore(&acb->ccblist_lock, flags); 1204 pcmd->scsi_done(pcmd); 1205 } 1206 1207 static void arcmsr_report_sense_info(struct CommandControlBlock *ccb) 1208 { 1209 1210 struct scsi_cmnd *pcmd = ccb->pcmd; 1211 struct SENSE_DATA *sensebuffer = (struct SENSE_DATA *)pcmd->sense_buffer; 1212 pcmd->result = (DID_OK << 16) | (CHECK_CONDITION << 1); 1213 if (sensebuffer) { 1214 int sense_data_length = 1215 sizeof(struct SENSE_DATA) < SCSI_SENSE_BUFFERSIZE 1216 ? sizeof(struct SENSE_DATA) : SCSI_SENSE_BUFFERSIZE; 1217 memset(sensebuffer, 0, SCSI_SENSE_BUFFERSIZE); 1218 memcpy(sensebuffer, ccb->arcmsr_cdb.SenseData, sense_data_length); 1219 sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS; 1220 sensebuffer->Valid = 1; 1221 pcmd->result |= (DRIVER_SENSE << 24); 1222 } 1223 } 1224 1225 static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb) 1226 { 1227 u32 orig_mask = 0; 1228 switch (acb->adapter_type) { 1229 case ACB_ADAPTER_TYPE_A : { 1230 struct MessageUnit_A __iomem *reg = acb->pmuA; 1231 orig_mask = readl(®->outbound_intmask); 1232 writel(orig_mask|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE, \ 1233 ®->outbound_intmask); 1234 } 1235 break; 1236 case ACB_ADAPTER_TYPE_B : { 1237 struct MessageUnit_B *reg = acb->pmuB; 1238 orig_mask = readl(reg->iop2drv_doorbell_mask); 1239 writel(0, reg->iop2drv_doorbell_mask); 1240 } 1241 break; 1242 case ACB_ADAPTER_TYPE_C:{ 1243 struct MessageUnit_C __iomem *reg = acb->pmuC; 1244 /* disable all outbound interrupt */ 1245 orig_mask = readl(®->host_int_mask); /* disable outbound message0 int */ 1246 writel(orig_mask|ARCMSR_HBCMU_ALL_INTMASKENABLE, ®->host_int_mask); 1247 } 1248 break; 1249 case ACB_ADAPTER_TYPE_D: { 1250 struct MessageUnit_D *reg = acb->pmuD; 1251 /* disable all outbound interrupt */ 1252 writel(ARCMSR_ARC1214_ALL_INT_DISABLE, reg->pcief0_int_enable); 1253 } 1254 break; 1255 case ACB_ADAPTER_TYPE_E: { 1256 struct MessageUnit_E __iomem *reg = acb->pmuE; 1257 orig_mask = readl(®->host_int_mask); 1258 writel(orig_mask | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR, ®->host_int_mask); 1259 readl(®->host_int_mask); /* Dummy readl to force pci flush */ 1260 } 1261 break; 1262 } 1263 return orig_mask; 1264 } 1265 1266 static void arcmsr_report_ccb_state(struct AdapterControlBlock *acb, 1267 struct CommandControlBlock *ccb, bool error) 1268 { 1269 uint8_t id, lun; 1270 id = ccb->pcmd->device->id; 1271 lun = ccb->pcmd->device->lun; 1272 if (!error) { 1273 if (acb->devstate[id][lun] == ARECA_RAID_GONE) 1274 acb->devstate[id][lun] = ARECA_RAID_GOOD; 1275 ccb->pcmd->result = DID_OK << 16; 1276 arcmsr_ccb_complete(ccb); 1277 }else{ 1278 switch (ccb->arcmsr_cdb.DeviceStatus) { 1279 case ARCMSR_DEV_SELECT_TIMEOUT: { 1280 acb->devstate[id][lun] = ARECA_RAID_GONE; 1281 ccb->pcmd->result = DID_NO_CONNECT << 16; 1282 arcmsr_ccb_complete(ccb); 1283 } 1284 break; 1285 1286 case ARCMSR_DEV_ABORTED: 1287 1288 case ARCMSR_DEV_INIT_FAIL: { 1289 acb->devstate[id][lun] = ARECA_RAID_GONE; 1290 ccb->pcmd->result = DID_BAD_TARGET << 16; 1291 arcmsr_ccb_complete(ccb); 1292 } 1293 break; 1294 1295 case ARCMSR_DEV_CHECK_CONDITION: { 1296 acb->devstate[id][lun] = ARECA_RAID_GOOD; 1297 arcmsr_report_sense_info(ccb); 1298 arcmsr_ccb_complete(ccb); 1299 } 1300 break; 1301 1302 default: 1303 printk(KERN_NOTICE 1304 "arcmsr%d: scsi id = %d lun = %d isr get command error done, \ 1305 but got unknown DeviceStatus = 0x%x \n" 1306 , acb->host->host_no 1307 , id 1308 , lun 1309 , ccb->arcmsr_cdb.DeviceStatus); 1310 acb->devstate[id][lun] = ARECA_RAID_GONE; 1311 ccb->pcmd->result = DID_NO_CONNECT << 16; 1312 arcmsr_ccb_complete(ccb); 1313 break; 1314 } 1315 } 1316 } 1317 1318 static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, struct CommandControlBlock *pCCB, bool error) 1319 { 1320 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) { 1321 if (pCCB->startdone == ARCMSR_CCB_ABORTED) { 1322 struct scsi_cmnd *abortcmd = pCCB->pcmd; 1323 if (abortcmd) { 1324 abortcmd->result |= DID_ABORT << 16; 1325 arcmsr_ccb_complete(pCCB); 1326 printk(KERN_NOTICE "arcmsr%d: pCCB ='0x%p' isr got aborted command \n", 1327 acb->host->host_no, pCCB); 1328 } 1329 return; 1330 } 1331 printk(KERN_NOTICE "arcmsr%d: isr get an illegal ccb command \ 1332 done acb = '0x%p'" 1333 "ccb = '0x%p' ccbacb = '0x%p' startdone = 0x%x" 1334 " ccboutstandingcount = %d \n" 1335 , acb->host->host_no 1336 , acb 1337 , pCCB 1338 , pCCB->acb 1339 , pCCB->startdone 1340 , atomic_read(&acb->ccboutstandingcount)); 1341 return; 1342 } 1343 arcmsr_report_ccb_state(acb, pCCB, error); 1344 } 1345 1346 static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb) 1347 { 1348 int i = 0; 1349 uint32_t flag_ccb, ccb_cdb_phy; 1350 struct ARCMSR_CDB *pARCMSR_CDB; 1351 bool error; 1352 struct CommandControlBlock *pCCB; 1353 switch (acb->adapter_type) { 1354 1355 case ACB_ADAPTER_TYPE_A: { 1356 struct MessageUnit_A __iomem *reg = acb->pmuA; 1357 uint32_t outbound_intstatus; 1358 outbound_intstatus = readl(®->outbound_intstatus) & 1359 acb->outbound_int_enable; 1360 /*clear and abort all outbound posted Q*/ 1361 writel(outbound_intstatus, ®->outbound_intstatus);/*clear interrupt*/ 1362 while(((flag_ccb = readl(®->outbound_queueport)) != 0xFFFFFFFF) 1363 && (i++ < acb->maxOutstanding)) { 1364 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));/*frame must be 32 bytes aligned*/ 1365 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb); 1366 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false; 1367 arcmsr_drain_donequeue(acb, pCCB, error); 1368 } 1369 } 1370 break; 1371 1372 case ACB_ADAPTER_TYPE_B: { 1373 struct MessageUnit_B *reg = acb->pmuB; 1374 /*clear all outbound posted Q*/ 1375 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); /* clear doorbell interrupt */ 1376 for (i = 0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) { 1377 flag_ccb = reg->done_qbuffer[i]; 1378 if (flag_ccb != 0) { 1379 reg->done_qbuffer[i] = 0; 1380 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+(flag_ccb << 5));/*frame must be 32 bytes aligned*/ 1381 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb); 1382 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false; 1383 arcmsr_drain_donequeue(acb, pCCB, error); 1384 } 1385 reg->post_qbuffer[i] = 0; 1386 } 1387 reg->doneq_index = 0; 1388 reg->postq_index = 0; 1389 } 1390 break; 1391 case ACB_ADAPTER_TYPE_C: { 1392 struct MessageUnit_C __iomem *reg = acb->pmuC; 1393 while ((readl(®->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < acb->maxOutstanding)) { 1394 /*need to do*/ 1395 flag_ccb = readl(®->outbound_queueport_low); 1396 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0); 1397 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+ccb_cdb_phy);/*frame must be 32 bytes aligned*/ 1398 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb); 1399 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false; 1400 arcmsr_drain_donequeue(acb, pCCB, error); 1401 } 1402 } 1403 break; 1404 case ACB_ADAPTER_TYPE_D: { 1405 struct MessageUnit_D *pmu = acb->pmuD; 1406 uint32_t outbound_write_pointer; 1407 uint32_t doneq_index, index_stripped, addressLow, residual, toggle; 1408 unsigned long flags; 1409 1410 residual = atomic_read(&acb->ccboutstandingcount); 1411 for (i = 0; i < residual; i++) { 1412 spin_lock_irqsave(&acb->doneq_lock, flags); 1413 outbound_write_pointer = 1414 pmu->done_qbuffer[0].addressLow + 1; 1415 doneq_index = pmu->doneq_index; 1416 if ((doneq_index & 0xFFF) != 1417 (outbound_write_pointer & 0xFFF)) { 1418 toggle = doneq_index & 0x4000; 1419 index_stripped = (doneq_index & 0xFFF) + 1; 1420 index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE; 1421 pmu->doneq_index = index_stripped ? (index_stripped | toggle) : 1422 ((toggle ^ 0x4000) + 1); 1423 doneq_index = pmu->doneq_index; 1424 spin_unlock_irqrestore(&acb->doneq_lock, flags); 1425 addressLow = pmu->done_qbuffer[doneq_index & 1426 0xFFF].addressLow; 1427 ccb_cdb_phy = (addressLow & 0xFFFFFFF0); 1428 pARCMSR_CDB = (struct ARCMSR_CDB *) 1429 (acb->vir2phy_offset + ccb_cdb_phy); 1430 pCCB = container_of(pARCMSR_CDB, 1431 struct CommandControlBlock, arcmsr_cdb); 1432 error = (addressLow & 1433 ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? 1434 true : false; 1435 arcmsr_drain_donequeue(acb, pCCB, error); 1436 writel(doneq_index, 1437 pmu->outboundlist_read_pointer); 1438 } else { 1439 spin_unlock_irqrestore(&acb->doneq_lock, flags); 1440 mdelay(10); 1441 } 1442 } 1443 pmu->postq_index = 0; 1444 pmu->doneq_index = 0x40FF; 1445 } 1446 break; 1447 case ACB_ADAPTER_TYPE_E: 1448 arcmsr_hbaE_postqueue_isr(acb); 1449 break; 1450 } 1451 } 1452 1453 static void arcmsr_remove_scsi_devices(struct AdapterControlBlock *acb) 1454 { 1455 char *acb_dev_map = (char *)acb->device_map; 1456 int target, lun, i; 1457 struct scsi_device *psdev; 1458 struct CommandControlBlock *ccb; 1459 char temp; 1460 1461 for (i = 0; i < acb->maxFreeCCB; i++) { 1462 ccb = acb->pccb_pool[i]; 1463 if (ccb->startdone == ARCMSR_CCB_START) { 1464 ccb->pcmd->result = DID_NO_CONNECT << 16; 1465 arcmsr_pci_unmap_dma(ccb); 1466 ccb->pcmd->scsi_done(ccb->pcmd); 1467 } 1468 } 1469 for (target = 0; target < ARCMSR_MAX_TARGETID; target++) { 1470 temp = *acb_dev_map; 1471 if (temp) { 1472 for (lun = 0; lun < ARCMSR_MAX_TARGETLUN; lun++) { 1473 if (temp & 1) { 1474 psdev = scsi_device_lookup(acb->host, 1475 0, target, lun); 1476 if (psdev != NULL) { 1477 scsi_remove_device(psdev); 1478 scsi_device_put(psdev); 1479 } 1480 } 1481 temp >>= 1; 1482 } 1483 *acb_dev_map = 0; 1484 } 1485 acb_dev_map++; 1486 } 1487 } 1488 1489 static void arcmsr_free_pcidev(struct AdapterControlBlock *acb) 1490 { 1491 struct pci_dev *pdev; 1492 struct Scsi_Host *host; 1493 1494 host = acb->host; 1495 arcmsr_free_sysfs_attr(acb); 1496 scsi_remove_host(host); 1497 flush_work(&acb->arcmsr_do_message_isr_bh); 1498 del_timer_sync(&acb->eternal_timer); 1499 if (set_date_time) 1500 del_timer_sync(&acb->refresh_timer); 1501 pdev = acb->pdev; 1502 arcmsr_free_irq(pdev, acb); 1503 arcmsr_free_ccb_pool(acb); 1504 arcmsr_free_mu(acb); 1505 arcmsr_unmap_pciregion(acb); 1506 pci_release_regions(pdev); 1507 scsi_host_put(host); 1508 pci_disable_device(pdev); 1509 } 1510 1511 static void arcmsr_remove(struct pci_dev *pdev) 1512 { 1513 struct Scsi_Host *host = pci_get_drvdata(pdev); 1514 struct AdapterControlBlock *acb = 1515 (struct AdapterControlBlock *) host->hostdata; 1516 int poll_count = 0; 1517 uint16_t dev_id; 1518 1519 pci_read_config_word(pdev, PCI_DEVICE_ID, &dev_id); 1520 if (dev_id == 0xffff) { 1521 acb->acb_flags &= ~ACB_F_IOP_INITED; 1522 acb->acb_flags |= ACB_F_ADAPTER_REMOVED; 1523 arcmsr_remove_scsi_devices(acb); 1524 arcmsr_free_pcidev(acb); 1525 return; 1526 } 1527 arcmsr_free_sysfs_attr(acb); 1528 scsi_remove_host(host); 1529 flush_work(&acb->arcmsr_do_message_isr_bh); 1530 del_timer_sync(&acb->eternal_timer); 1531 if (set_date_time) 1532 del_timer_sync(&acb->refresh_timer); 1533 arcmsr_disable_outbound_ints(acb); 1534 arcmsr_stop_adapter_bgrb(acb); 1535 arcmsr_flush_adapter_cache(acb); 1536 acb->acb_flags |= ACB_F_SCSISTOPADAPTER; 1537 acb->acb_flags &= ~ACB_F_IOP_INITED; 1538 1539 for (poll_count = 0; poll_count < acb->maxOutstanding; poll_count++){ 1540 if (!atomic_read(&acb->ccboutstandingcount)) 1541 break; 1542 arcmsr_interrupt(acb);/* FIXME: need spinlock */ 1543 msleep(25); 1544 } 1545 1546 if (atomic_read(&acb->ccboutstandingcount)) { 1547 int i; 1548 1549 arcmsr_abort_allcmd(acb); 1550 arcmsr_done4abort_postqueue(acb); 1551 for (i = 0; i < acb->maxFreeCCB; i++) { 1552 struct CommandControlBlock *ccb = acb->pccb_pool[i]; 1553 if (ccb->startdone == ARCMSR_CCB_START) { 1554 ccb->startdone = ARCMSR_CCB_ABORTED; 1555 ccb->pcmd->result = DID_ABORT << 16; 1556 arcmsr_ccb_complete(ccb); 1557 } 1558 } 1559 } 1560 arcmsr_free_irq(pdev, acb); 1561 arcmsr_free_ccb_pool(acb); 1562 arcmsr_free_mu(acb); 1563 arcmsr_unmap_pciregion(acb); 1564 pci_release_regions(pdev); 1565 scsi_host_put(host); 1566 pci_disable_device(pdev); 1567 } 1568 1569 static void arcmsr_shutdown(struct pci_dev *pdev) 1570 { 1571 struct Scsi_Host *host = pci_get_drvdata(pdev); 1572 struct AdapterControlBlock *acb = 1573 (struct AdapterControlBlock *)host->hostdata; 1574 if (acb->acb_flags & ACB_F_ADAPTER_REMOVED) 1575 return; 1576 del_timer_sync(&acb->eternal_timer); 1577 if (set_date_time) 1578 del_timer_sync(&acb->refresh_timer); 1579 arcmsr_disable_outbound_ints(acb); 1580 arcmsr_free_irq(pdev, acb); 1581 flush_work(&acb->arcmsr_do_message_isr_bh); 1582 arcmsr_stop_adapter_bgrb(acb); 1583 arcmsr_flush_adapter_cache(acb); 1584 } 1585 1586 static int arcmsr_module_init(void) 1587 { 1588 int error = 0; 1589 error = pci_register_driver(&arcmsr_pci_driver); 1590 return error; 1591 } 1592 1593 static void arcmsr_module_exit(void) 1594 { 1595 pci_unregister_driver(&arcmsr_pci_driver); 1596 } 1597 module_init(arcmsr_module_init); 1598 module_exit(arcmsr_module_exit); 1599 1600 static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb, 1601 u32 intmask_org) 1602 { 1603 u32 mask; 1604 switch (acb->adapter_type) { 1605 1606 case ACB_ADAPTER_TYPE_A: { 1607 struct MessageUnit_A __iomem *reg = acb->pmuA; 1608 mask = intmask_org & ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE | 1609 ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE| 1610 ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE); 1611 writel(mask, ®->outbound_intmask); 1612 acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff; 1613 } 1614 break; 1615 1616 case ACB_ADAPTER_TYPE_B: { 1617 struct MessageUnit_B *reg = acb->pmuB; 1618 mask = intmask_org | (ARCMSR_IOP2DRV_DATA_WRITE_OK | 1619 ARCMSR_IOP2DRV_DATA_READ_OK | 1620 ARCMSR_IOP2DRV_CDB_DONE | 1621 ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); 1622 writel(mask, reg->iop2drv_doorbell_mask); 1623 acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f; 1624 } 1625 break; 1626 case ACB_ADAPTER_TYPE_C: { 1627 struct MessageUnit_C __iomem *reg = acb->pmuC; 1628 mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK|ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK); 1629 writel(intmask_org & mask, ®->host_int_mask); 1630 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f; 1631 } 1632 break; 1633 case ACB_ADAPTER_TYPE_D: { 1634 struct MessageUnit_D *reg = acb->pmuD; 1635 1636 mask = ARCMSR_ARC1214_ALL_INT_ENABLE; 1637 writel(intmask_org | mask, reg->pcief0_int_enable); 1638 break; 1639 } 1640 case ACB_ADAPTER_TYPE_E: { 1641 struct MessageUnit_E __iomem *reg = acb->pmuE; 1642 1643 mask = ~(ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR); 1644 writel(intmask_org & mask, ®->host_int_mask); 1645 break; 1646 } 1647 } 1648 } 1649 1650 static int arcmsr_build_ccb(struct AdapterControlBlock *acb, 1651 struct CommandControlBlock *ccb, struct scsi_cmnd *pcmd) 1652 { 1653 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb; 1654 int8_t *psge = (int8_t *)&arcmsr_cdb->u; 1655 __le32 address_lo, address_hi; 1656 int arccdbsize = 0x30; 1657 __le32 length = 0; 1658 int i; 1659 struct scatterlist *sg; 1660 int nseg; 1661 ccb->pcmd = pcmd; 1662 memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB)); 1663 arcmsr_cdb->TargetID = pcmd->device->id; 1664 arcmsr_cdb->LUN = pcmd->device->lun; 1665 arcmsr_cdb->Function = 1; 1666 arcmsr_cdb->msgContext = 0; 1667 memcpy(arcmsr_cdb->Cdb, pcmd->cmnd, pcmd->cmd_len); 1668 1669 nseg = scsi_dma_map(pcmd); 1670 if (unlikely(nseg > acb->host->sg_tablesize || nseg < 0)) 1671 return FAILED; 1672 scsi_for_each_sg(pcmd, sg, nseg, i) { 1673 /* Get the physical address of the current data pointer */ 1674 length = cpu_to_le32(sg_dma_len(sg)); 1675 address_lo = cpu_to_le32(dma_addr_lo32(sg_dma_address(sg))); 1676 address_hi = cpu_to_le32(dma_addr_hi32(sg_dma_address(sg))); 1677 if (address_hi == 0) { 1678 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge; 1679 1680 pdma_sg->address = address_lo; 1681 pdma_sg->length = length; 1682 psge += sizeof (struct SG32ENTRY); 1683 arccdbsize += sizeof (struct SG32ENTRY); 1684 } else { 1685 struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge; 1686 1687 pdma_sg->addresshigh = address_hi; 1688 pdma_sg->address = address_lo; 1689 pdma_sg->length = length|cpu_to_le32(IS_SG64_ADDR); 1690 psge += sizeof (struct SG64ENTRY); 1691 arccdbsize += sizeof (struct SG64ENTRY); 1692 } 1693 } 1694 arcmsr_cdb->sgcount = (uint8_t)nseg; 1695 arcmsr_cdb->DataLength = scsi_bufflen(pcmd); 1696 arcmsr_cdb->msgPages = arccdbsize/0x100 + (arccdbsize % 0x100 ? 1 : 0); 1697 if ( arccdbsize > 256) 1698 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE; 1699 if (pcmd->sc_data_direction == DMA_TO_DEVICE) 1700 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE; 1701 ccb->arc_cdb_size = arccdbsize; 1702 return SUCCESS; 1703 } 1704 1705 static void arcmsr_post_ccb(struct AdapterControlBlock *acb, struct CommandControlBlock *ccb) 1706 { 1707 uint32_t cdb_phyaddr = ccb->cdb_phyaddr; 1708 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb; 1709 atomic_inc(&acb->ccboutstandingcount); 1710 ccb->startdone = ARCMSR_CCB_START; 1711 switch (acb->adapter_type) { 1712 case ACB_ADAPTER_TYPE_A: { 1713 struct MessageUnit_A __iomem *reg = acb->pmuA; 1714 1715 if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) 1716 writel(cdb_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE, 1717 ®->inbound_queueport); 1718 else 1719 writel(cdb_phyaddr, ®->inbound_queueport); 1720 break; 1721 } 1722 1723 case ACB_ADAPTER_TYPE_B: { 1724 struct MessageUnit_B *reg = acb->pmuB; 1725 uint32_t ending_index, index = reg->postq_index; 1726 1727 ending_index = ((index + 1) % ARCMSR_MAX_HBB_POSTQUEUE); 1728 reg->post_qbuffer[ending_index] = 0; 1729 if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1730 reg->post_qbuffer[index] = 1731 cdb_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE; 1732 } else { 1733 reg->post_qbuffer[index] = cdb_phyaddr; 1734 } 1735 index++; 1736 index %= ARCMSR_MAX_HBB_POSTQUEUE;/*if last index number set it to 0 */ 1737 reg->postq_index = index; 1738 writel(ARCMSR_DRV2IOP_CDB_POSTED, reg->drv2iop_doorbell); 1739 } 1740 break; 1741 case ACB_ADAPTER_TYPE_C: { 1742 struct MessageUnit_C __iomem *phbcmu = acb->pmuC; 1743 uint32_t ccb_post_stamp, arc_cdb_size; 1744 1745 arc_cdb_size = (ccb->arc_cdb_size > 0x300) ? 0x300 : ccb->arc_cdb_size; 1746 ccb_post_stamp = (cdb_phyaddr | ((arc_cdb_size - 1) >> 6) | 1); 1747 if (acb->cdb_phyaddr_hi32) { 1748 writel(acb->cdb_phyaddr_hi32, &phbcmu->inbound_queueport_high); 1749 writel(ccb_post_stamp, &phbcmu->inbound_queueport_low); 1750 } else { 1751 writel(ccb_post_stamp, &phbcmu->inbound_queueport_low); 1752 } 1753 } 1754 break; 1755 case ACB_ADAPTER_TYPE_D: { 1756 struct MessageUnit_D *pmu = acb->pmuD; 1757 u16 index_stripped; 1758 u16 postq_index, toggle; 1759 unsigned long flags; 1760 struct InBound_SRB *pinbound_srb; 1761 1762 spin_lock_irqsave(&acb->postq_lock, flags); 1763 postq_index = pmu->postq_index; 1764 pinbound_srb = (struct InBound_SRB *)&(pmu->post_qbuffer[postq_index & 0xFF]); 1765 pinbound_srb->addressHigh = dma_addr_hi32(cdb_phyaddr); 1766 pinbound_srb->addressLow = dma_addr_lo32(cdb_phyaddr); 1767 pinbound_srb->length = ccb->arc_cdb_size >> 2; 1768 arcmsr_cdb->msgContext = dma_addr_lo32(cdb_phyaddr); 1769 toggle = postq_index & 0x4000; 1770 index_stripped = postq_index + 1; 1771 index_stripped &= (ARCMSR_MAX_ARC1214_POSTQUEUE - 1); 1772 pmu->postq_index = index_stripped ? (index_stripped | toggle) : 1773 (toggle ^ 0x4000); 1774 writel(postq_index, pmu->inboundlist_write_pointer); 1775 spin_unlock_irqrestore(&acb->postq_lock, flags); 1776 break; 1777 } 1778 case ACB_ADAPTER_TYPE_E: { 1779 struct MessageUnit_E __iomem *pmu = acb->pmuE; 1780 u32 ccb_post_stamp, arc_cdb_size; 1781 1782 arc_cdb_size = (ccb->arc_cdb_size > 0x300) ? 0x300 : ccb->arc_cdb_size; 1783 ccb_post_stamp = (ccb->smid | ((arc_cdb_size - 1) >> 6)); 1784 writel(0, &pmu->inbound_queueport_high); 1785 writel(ccb_post_stamp, &pmu->inbound_queueport_low); 1786 break; 1787 } 1788 } 1789 } 1790 1791 static void arcmsr_hbaA_stop_bgrb(struct AdapterControlBlock *acb) 1792 { 1793 struct MessageUnit_A __iomem *reg = acb->pmuA; 1794 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1795 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, ®->inbound_msgaddr0); 1796 if (!arcmsr_hbaA_wait_msgint_ready(acb)) { 1797 printk(KERN_NOTICE 1798 "arcmsr%d: wait 'stop adapter background rebuild' timeout\n" 1799 , acb->host->host_no); 1800 } 1801 } 1802 1803 static void arcmsr_hbaB_stop_bgrb(struct AdapterControlBlock *acb) 1804 { 1805 struct MessageUnit_B *reg = acb->pmuB; 1806 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1807 writel(ARCMSR_MESSAGE_STOP_BGRB, reg->drv2iop_doorbell); 1808 1809 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 1810 printk(KERN_NOTICE 1811 "arcmsr%d: wait 'stop adapter background rebuild' timeout\n" 1812 , acb->host->host_no); 1813 } 1814 } 1815 1816 static void arcmsr_hbaC_stop_bgrb(struct AdapterControlBlock *pACB) 1817 { 1818 struct MessageUnit_C __iomem *reg = pACB->pmuC; 1819 pACB->acb_flags &= ~ACB_F_MSG_START_BGRB; 1820 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, ®->inbound_msgaddr0); 1821 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell); 1822 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) { 1823 printk(KERN_NOTICE 1824 "arcmsr%d: wait 'stop adapter background rebuild' timeout\n" 1825 , pACB->host->host_no); 1826 } 1827 return; 1828 } 1829 1830 static void arcmsr_hbaD_stop_bgrb(struct AdapterControlBlock *pACB) 1831 { 1832 struct MessageUnit_D *reg = pACB->pmuD; 1833 1834 pACB->acb_flags &= ~ACB_F_MSG_START_BGRB; 1835 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, reg->inbound_msgaddr0); 1836 if (!arcmsr_hbaD_wait_msgint_ready(pACB)) 1837 pr_notice("arcmsr%d: wait 'stop adapter background rebuild' " 1838 "timeout\n", pACB->host->host_no); 1839 } 1840 1841 static void arcmsr_hbaE_stop_bgrb(struct AdapterControlBlock *pACB) 1842 { 1843 struct MessageUnit_E __iomem *reg = pACB->pmuE; 1844 1845 pACB->acb_flags &= ~ACB_F_MSG_START_BGRB; 1846 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, ®->inbound_msgaddr0); 1847 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 1848 writel(pACB->out_doorbell, ®->iobound_doorbell); 1849 if (!arcmsr_hbaE_wait_msgint_ready(pACB)) { 1850 pr_notice("arcmsr%d: wait 'stop adapter background rebuild' " 1851 "timeout\n", pACB->host->host_no); 1852 } 1853 } 1854 1855 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb) 1856 { 1857 switch (acb->adapter_type) { 1858 case ACB_ADAPTER_TYPE_A: { 1859 arcmsr_hbaA_stop_bgrb(acb); 1860 } 1861 break; 1862 1863 case ACB_ADAPTER_TYPE_B: { 1864 arcmsr_hbaB_stop_bgrb(acb); 1865 } 1866 break; 1867 case ACB_ADAPTER_TYPE_C: { 1868 arcmsr_hbaC_stop_bgrb(acb); 1869 } 1870 break; 1871 case ACB_ADAPTER_TYPE_D: 1872 arcmsr_hbaD_stop_bgrb(acb); 1873 break; 1874 case ACB_ADAPTER_TYPE_E: 1875 arcmsr_hbaE_stop_bgrb(acb); 1876 break; 1877 } 1878 } 1879 1880 static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb) 1881 { 1882 dma_free_coherent(&acb->pdev->dev, acb->uncache_size, acb->dma_coherent, acb->dma_coherent_handle); 1883 } 1884 1885 static void arcmsr_iop_message_read(struct AdapterControlBlock *acb) 1886 { 1887 switch (acb->adapter_type) { 1888 case ACB_ADAPTER_TYPE_A: { 1889 struct MessageUnit_A __iomem *reg = acb->pmuA; 1890 writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, ®->inbound_doorbell); 1891 } 1892 break; 1893 1894 case ACB_ADAPTER_TYPE_B: { 1895 struct MessageUnit_B *reg = acb->pmuB; 1896 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell); 1897 } 1898 break; 1899 case ACB_ADAPTER_TYPE_C: { 1900 struct MessageUnit_C __iomem *reg = acb->pmuC; 1901 1902 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, ®->inbound_doorbell); 1903 } 1904 break; 1905 case ACB_ADAPTER_TYPE_D: { 1906 struct MessageUnit_D *reg = acb->pmuD; 1907 writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ, 1908 reg->inbound_doorbell); 1909 } 1910 break; 1911 case ACB_ADAPTER_TYPE_E: { 1912 struct MessageUnit_E __iomem *reg = acb->pmuE; 1913 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK; 1914 writel(acb->out_doorbell, ®->iobound_doorbell); 1915 } 1916 break; 1917 } 1918 } 1919 1920 static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb) 1921 { 1922 switch (acb->adapter_type) { 1923 case ACB_ADAPTER_TYPE_A: { 1924 struct MessageUnit_A __iomem *reg = acb->pmuA; 1925 /* 1926 ** push inbound doorbell tell iop, driver data write ok 1927 ** and wait reply on next hwinterrupt for next Qbuffer post 1928 */ 1929 writel(ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK, ®->inbound_doorbell); 1930 } 1931 break; 1932 1933 case ACB_ADAPTER_TYPE_B: { 1934 struct MessageUnit_B *reg = acb->pmuB; 1935 /* 1936 ** push inbound doorbell tell iop, driver data write ok 1937 ** and wait reply on next hwinterrupt for next Qbuffer post 1938 */ 1939 writel(ARCMSR_DRV2IOP_DATA_WRITE_OK, reg->drv2iop_doorbell); 1940 } 1941 break; 1942 case ACB_ADAPTER_TYPE_C: { 1943 struct MessageUnit_C __iomem *reg = acb->pmuC; 1944 /* 1945 ** push inbound doorbell tell iop, driver data write ok 1946 ** and wait reply on next hwinterrupt for next Qbuffer post 1947 */ 1948 writel(ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK, ®->inbound_doorbell); 1949 } 1950 break; 1951 case ACB_ADAPTER_TYPE_D: { 1952 struct MessageUnit_D *reg = acb->pmuD; 1953 writel(ARCMSR_ARC1214_DRV2IOP_DATA_IN_READY, 1954 reg->inbound_doorbell); 1955 } 1956 break; 1957 case ACB_ADAPTER_TYPE_E: { 1958 struct MessageUnit_E __iomem *reg = acb->pmuE; 1959 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK; 1960 writel(acb->out_doorbell, ®->iobound_doorbell); 1961 } 1962 break; 1963 } 1964 } 1965 1966 struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *acb) 1967 { 1968 struct QBUFFER __iomem *qbuffer = NULL; 1969 switch (acb->adapter_type) { 1970 1971 case ACB_ADAPTER_TYPE_A: { 1972 struct MessageUnit_A __iomem *reg = acb->pmuA; 1973 qbuffer = (struct QBUFFER __iomem *)®->message_rbuffer; 1974 } 1975 break; 1976 1977 case ACB_ADAPTER_TYPE_B: { 1978 struct MessageUnit_B *reg = acb->pmuB; 1979 qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer; 1980 } 1981 break; 1982 case ACB_ADAPTER_TYPE_C: { 1983 struct MessageUnit_C __iomem *phbcmu = acb->pmuC; 1984 qbuffer = (struct QBUFFER __iomem *)&phbcmu->message_rbuffer; 1985 } 1986 break; 1987 case ACB_ADAPTER_TYPE_D: { 1988 struct MessageUnit_D *reg = acb->pmuD; 1989 qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer; 1990 } 1991 break; 1992 case ACB_ADAPTER_TYPE_E: { 1993 struct MessageUnit_E __iomem *reg = acb->pmuE; 1994 qbuffer = (struct QBUFFER __iomem *)®->message_rbuffer; 1995 } 1996 break; 1997 } 1998 return qbuffer; 1999 } 2000 2001 static struct QBUFFER __iomem *arcmsr_get_iop_wqbuffer(struct AdapterControlBlock *acb) 2002 { 2003 struct QBUFFER __iomem *pqbuffer = NULL; 2004 switch (acb->adapter_type) { 2005 2006 case ACB_ADAPTER_TYPE_A: { 2007 struct MessageUnit_A __iomem *reg = acb->pmuA; 2008 pqbuffer = (struct QBUFFER __iomem *) ®->message_wbuffer; 2009 } 2010 break; 2011 2012 case ACB_ADAPTER_TYPE_B: { 2013 struct MessageUnit_B *reg = acb->pmuB; 2014 pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer; 2015 } 2016 break; 2017 case ACB_ADAPTER_TYPE_C: { 2018 struct MessageUnit_C __iomem *reg = acb->pmuC; 2019 pqbuffer = (struct QBUFFER __iomem *)®->message_wbuffer; 2020 } 2021 break; 2022 case ACB_ADAPTER_TYPE_D: { 2023 struct MessageUnit_D *reg = acb->pmuD; 2024 pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer; 2025 } 2026 break; 2027 case ACB_ADAPTER_TYPE_E: { 2028 struct MessageUnit_E __iomem *reg = acb->pmuE; 2029 pqbuffer = (struct QBUFFER __iomem *)®->message_wbuffer; 2030 } 2031 break; 2032 } 2033 return pqbuffer; 2034 } 2035 2036 static uint32_t 2037 arcmsr_Read_iop_rqbuffer_in_DWORD(struct AdapterControlBlock *acb, 2038 struct QBUFFER __iomem *prbuffer) 2039 { 2040 uint8_t *pQbuffer; 2041 uint8_t *buf1 = NULL; 2042 uint32_t __iomem *iop_data; 2043 uint32_t iop_len, data_len, *buf2 = NULL; 2044 2045 iop_data = (uint32_t __iomem *)prbuffer->data; 2046 iop_len = readl(&prbuffer->data_len); 2047 if (iop_len > 0) { 2048 buf1 = kmalloc(128, GFP_ATOMIC); 2049 buf2 = (uint32_t *)buf1; 2050 if (buf1 == NULL) 2051 return 0; 2052 data_len = iop_len; 2053 while (data_len >= 4) { 2054 *buf2++ = readl(iop_data); 2055 iop_data++; 2056 data_len -= 4; 2057 } 2058 if (data_len) 2059 *buf2 = readl(iop_data); 2060 buf2 = (uint32_t *)buf1; 2061 } 2062 while (iop_len > 0) { 2063 pQbuffer = &acb->rqbuffer[acb->rqbuf_putIndex]; 2064 *pQbuffer = *buf1; 2065 acb->rqbuf_putIndex++; 2066 /* if last, index number set it to 0 */ 2067 acb->rqbuf_putIndex %= ARCMSR_MAX_QBUFFER; 2068 buf1++; 2069 iop_len--; 2070 } 2071 kfree(buf2); 2072 /* let IOP know data has been read */ 2073 arcmsr_iop_message_read(acb); 2074 return 1; 2075 } 2076 2077 uint32_t 2078 arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, 2079 struct QBUFFER __iomem *prbuffer) { 2080 2081 uint8_t *pQbuffer; 2082 uint8_t __iomem *iop_data; 2083 uint32_t iop_len; 2084 2085 if (acb->adapter_type > ACB_ADAPTER_TYPE_B) 2086 return arcmsr_Read_iop_rqbuffer_in_DWORD(acb, prbuffer); 2087 iop_data = (uint8_t __iomem *)prbuffer->data; 2088 iop_len = readl(&prbuffer->data_len); 2089 while (iop_len > 0) { 2090 pQbuffer = &acb->rqbuffer[acb->rqbuf_putIndex]; 2091 *pQbuffer = readb(iop_data); 2092 acb->rqbuf_putIndex++; 2093 acb->rqbuf_putIndex %= ARCMSR_MAX_QBUFFER; 2094 iop_data++; 2095 iop_len--; 2096 } 2097 arcmsr_iop_message_read(acb); 2098 return 1; 2099 } 2100 2101 static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb) 2102 { 2103 unsigned long flags; 2104 struct QBUFFER __iomem *prbuffer; 2105 int32_t buf_empty_len; 2106 2107 spin_lock_irqsave(&acb->rqbuffer_lock, flags); 2108 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2109 buf_empty_len = (acb->rqbuf_putIndex - acb->rqbuf_getIndex - 1) & 2110 (ARCMSR_MAX_QBUFFER - 1); 2111 if (buf_empty_len >= readl(&prbuffer->data_len)) { 2112 if (arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 2113 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2114 } else 2115 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2116 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags); 2117 } 2118 2119 static void arcmsr_write_ioctldata2iop_in_DWORD(struct AdapterControlBlock *acb) 2120 { 2121 uint8_t *pQbuffer; 2122 struct QBUFFER __iomem *pwbuffer; 2123 uint8_t *buf1 = NULL; 2124 uint32_t __iomem *iop_data; 2125 uint32_t allxfer_len = 0, data_len, *buf2 = NULL, data; 2126 2127 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) { 2128 buf1 = kmalloc(128, GFP_ATOMIC); 2129 buf2 = (uint32_t *)buf1; 2130 if (buf1 == NULL) 2131 return; 2132 2133 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED); 2134 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 2135 iop_data = (uint32_t __iomem *)pwbuffer->data; 2136 while ((acb->wqbuf_getIndex != acb->wqbuf_putIndex) 2137 && (allxfer_len < 124)) { 2138 pQbuffer = &acb->wqbuffer[acb->wqbuf_getIndex]; 2139 *buf1 = *pQbuffer; 2140 acb->wqbuf_getIndex++; 2141 acb->wqbuf_getIndex %= ARCMSR_MAX_QBUFFER; 2142 buf1++; 2143 allxfer_len++; 2144 } 2145 data_len = allxfer_len; 2146 buf1 = (uint8_t *)buf2; 2147 while (data_len >= 4) { 2148 data = *buf2++; 2149 writel(data, iop_data); 2150 iop_data++; 2151 data_len -= 4; 2152 } 2153 if (data_len) { 2154 data = *buf2; 2155 writel(data, iop_data); 2156 } 2157 writel(allxfer_len, &pwbuffer->data_len); 2158 kfree(buf1); 2159 arcmsr_iop_message_wrote(acb); 2160 } 2161 } 2162 2163 void 2164 arcmsr_write_ioctldata2iop(struct AdapterControlBlock *acb) 2165 { 2166 uint8_t *pQbuffer; 2167 struct QBUFFER __iomem *pwbuffer; 2168 uint8_t __iomem *iop_data; 2169 int32_t allxfer_len = 0; 2170 2171 if (acb->adapter_type > ACB_ADAPTER_TYPE_B) { 2172 arcmsr_write_ioctldata2iop_in_DWORD(acb); 2173 return; 2174 } 2175 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) { 2176 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED); 2177 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 2178 iop_data = (uint8_t __iomem *)pwbuffer->data; 2179 while ((acb->wqbuf_getIndex != acb->wqbuf_putIndex) 2180 && (allxfer_len < 124)) { 2181 pQbuffer = &acb->wqbuffer[acb->wqbuf_getIndex]; 2182 writeb(*pQbuffer, iop_data); 2183 acb->wqbuf_getIndex++; 2184 acb->wqbuf_getIndex %= ARCMSR_MAX_QBUFFER; 2185 iop_data++; 2186 allxfer_len++; 2187 } 2188 writel(allxfer_len, &pwbuffer->data_len); 2189 arcmsr_iop_message_wrote(acb); 2190 } 2191 } 2192 2193 static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb) 2194 { 2195 unsigned long flags; 2196 2197 spin_lock_irqsave(&acb->wqbuffer_lock, flags); 2198 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READED; 2199 if (acb->wqbuf_getIndex != acb->wqbuf_putIndex) 2200 arcmsr_write_ioctldata2iop(acb); 2201 if (acb->wqbuf_getIndex == acb->wqbuf_putIndex) 2202 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED; 2203 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags); 2204 } 2205 2206 static void arcmsr_hbaA_doorbell_isr(struct AdapterControlBlock *acb) 2207 { 2208 uint32_t outbound_doorbell; 2209 struct MessageUnit_A __iomem *reg = acb->pmuA; 2210 outbound_doorbell = readl(®->outbound_doorbell); 2211 do { 2212 writel(outbound_doorbell, ®->outbound_doorbell); 2213 if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) 2214 arcmsr_iop2drv_data_wrote_handle(acb); 2215 if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) 2216 arcmsr_iop2drv_data_read_handle(acb); 2217 outbound_doorbell = readl(®->outbound_doorbell); 2218 } while (outbound_doorbell & (ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 2219 | ARCMSR_OUTBOUND_IOP331_DATA_READ_OK)); 2220 } 2221 static void arcmsr_hbaC_doorbell_isr(struct AdapterControlBlock *pACB) 2222 { 2223 uint32_t outbound_doorbell; 2224 struct MessageUnit_C __iomem *reg = pACB->pmuC; 2225 /* 2226 ******************************************************************* 2227 ** Maybe here we need to check wrqbuffer_lock is lock or not 2228 ** DOORBELL: din! don! 2229 ** check if there are any mail need to pack from firmware 2230 ******************************************************************* 2231 */ 2232 outbound_doorbell = readl(®->outbound_doorbell); 2233 do { 2234 writel(outbound_doorbell, ®->outbound_doorbell_clear); 2235 readl(®->outbound_doorbell_clear); 2236 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) 2237 arcmsr_iop2drv_data_wrote_handle(pACB); 2238 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) 2239 arcmsr_iop2drv_data_read_handle(pACB); 2240 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) 2241 arcmsr_hbaC_message_isr(pACB); 2242 outbound_doorbell = readl(®->outbound_doorbell); 2243 } while (outbound_doorbell & (ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 2244 | ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 2245 | ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE)); 2246 } 2247 2248 static void arcmsr_hbaD_doorbell_isr(struct AdapterControlBlock *pACB) 2249 { 2250 uint32_t outbound_doorbell; 2251 struct MessageUnit_D *pmu = pACB->pmuD; 2252 2253 outbound_doorbell = readl(pmu->outbound_doorbell); 2254 do { 2255 writel(outbound_doorbell, pmu->outbound_doorbell); 2256 if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE) 2257 arcmsr_hbaD_message_isr(pACB); 2258 if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK) 2259 arcmsr_iop2drv_data_wrote_handle(pACB); 2260 if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK) 2261 arcmsr_iop2drv_data_read_handle(pACB); 2262 outbound_doorbell = readl(pmu->outbound_doorbell); 2263 } while (outbound_doorbell & (ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK 2264 | ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK 2265 | ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE)); 2266 } 2267 2268 static void arcmsr_hbaE_doorbell_isr(struct AdapterControlBlock *pACB) 2269 { 2270 uint32_t outbound_doorbell, in_doorbell, tmp; 2271 struct MessageUnit_E __iomem *reg = pACB->pmuE; 2272 2273 in_doorbell = readl(®->iobound_doorbell); 2274 outbound_doorbell = in_doorbell ^ pACB->in_doorbell; 2275 do { 2276 writel(0, ®->host_int_status); /* clear interrupt */ 2277 if (outbound_doorbell & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) { 2278 arcmsr_iop2drv_data_wrote_handle(pACB); 2279 } 2280 if (outbound_doorbell & ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK) { 2281 arcmsr_iop2drv_data_read_handle(pACB); 2282 } 2283 if (outbound_doorbell & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) { 2284 arcmsr_hbaE_message_isr(pACB); 2285 } 2286 tmp = in_doorbell; 2287 in_doorbell = readl(®->iobound_doorbell); 2288 outbound_doorbell = tmp ^ in_doorbell; 2289 } while (outbound_doorbell & (ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK 2290 | ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK 2291 | ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE)); 2292 pACB->in_doorbell = in_doorbell; 2293 } 2294 2295 static void arcmsr_hbaA_postqueue_isr(struct AdapterControlBlock *acb) 2296 { 2297 uint32_t flag_ccb; 2298 struct MessageUnit_A __iomem *reg = acb->pmuA; 2299 struct ARCMSR_CDB *pARCMSR_CDB; 2300 struct CommandControlBlock *pCCB; 2301 bool error; 2302 while ((flag_ccb = readl(®->outbound_queueport)) != 0xFFFFFFFF) { 2303 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));/*frame must be 32 bytes aligned*/ 2304 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb); 2305 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false; 2306 arcmsr_drain_donequeue(acb, pCCB, error); 2307 } 2308 } 2309 static void arcmsr_hbaB_postqueue_isr(struct AdapterControlBlock *acb) 2310 { 2311 uint32_t index; 2312 uint32_t flag_ccb; 2313 struct MessageUnit_B *reg = acb->pmuB; 2314 struct ARCMSR_CDB *pARCMSR_CDB; 2315 struct CommandControlBlock *pCCB; 2316 bool error; 2317 index = reg->doneq_index; 2318 while ((flag_ccb = reg->done_qbuffer[index]) != 0) { 2319 reg->done_qbuffer[index] = 0; 2320 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+(flag_ccb << 5));/*frame must be 32 bytes aligned*/ 2321 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb); 2322 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false; 2323 arcmsr_drain_donequeue(acb, pCCB, error); 2324 index++; 2325 index %= ARCMSR_MAX_HBB_POSTQUEUE; 2326 reg->doneq_index = index; 2327 } 2328 } 2329 2330 static void arcmsr_hbaC_postqueue_isr(struct AdapterControlBlock *acb) 2331 { 2332 struct MessageUnit_C __iomem *phbcmu; 2333 struct ARCMSR_CDB *arcmsr_cdb; 2334 struct CommandControlBlock *ccb; 2335 uint32_t flag_ccb, ccb_cdb_phy, throttling = 0; 2336 int error; 2337 2338 phbcmu = acb->pmuC; 2339 /* areca cdb command done */ 2340 /* Use correct offset and size for syncing */ 2341 2342 while ((flag_ccb = readl(&phbcmu->outbound_queueport_low)) != 2343 0xFFFFFFFF) { 2344 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0); 2345 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset 2346 + ccb_cdb_phy); 2347 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, 2348 arcmsr_cdb); 2349 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) 2350 ? true : false; 2351 /* check if command done with no error */ 2352 arcmsr_drain_donequeue(acb, ccb, error); 2353 throttling++; 2354 if (throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) { 2355 writel(ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING, 2356 &phbcmu->inbound_doorbell); 2357 throttling = 0; 2358 } 2359 } 2360 } 2361 2362 static void arcmsr_hbaD_postqueue_isr(struct AdapterControlBlock *acb) 2363 { 2364 u32 outbound_write_pointer, doneq_index, index_stripped, toggle; 2365 uint32_t addressLow, ccb_cdb_phy; 2366 int error; 2367 struct MessageUnit_D *pmu; 2368 struct ARCMSR_CDB *arcmsr_cdb; 2369 struct CommandControlBlock *ccb; 2370 unsigned long flags; 2371 2372 spin_lock_irqsave(&acb->doneq_lock, flags); 2373 pmu = acb->pmuD; 2374 outbound_write_pointer = pmu->done_qbuffer[0].addressLow + 1; 2375 doneq_index = pmu->doneq_index; 2376 if ((doneq_index & 0xFFF) != (outbound_write_pointer & 0xFFF)) { 2377 do { 2378 toggle = doneq_index & 0x4000; 2379 index_stripped = (doneq_index & 0xFFF) + 1; 2380 index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE; 2381 pmu->doneq_index = index_stripped ? (index_stripped | toggle) : 2382 ((toggle ^ 0x4000) + 1); 2383 doneq_index = pmu->doneq_index; 2384 addressLow = pmu->done_qbuffer[doneq_index & 2385 0xFFF].addressLow; 2386 ccb_cdb_phy = (addressLow & 0xFFFFFFF0); 2387 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset 2388 + ccb_cdb_phy); 2389 ccb = container_of(arcmsr_cdb, 2390 struct CommandControlBlock, arcmsr_cdb); 2391 error = (addressLow & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) 2392 ? true : false; 2393 arcmsr_drain_donequeue(acb, ccb, error); 2394 writel(doneq_index, pmu->outboundlist_read_pointer); 2395 } while ((doneq_index & 0xFFF) != 2396 (outbound_write_pointer & 0xFFF)); 2397 } 2398 writel(ARCMSR_ARC1214_OUTBOUND_LIST_INTERRUPT_CLEAR, 2399 pmu->outboundlist_interrupt_cause); 2400 readl(pmu->outboundlist_interrupt_cause); 2401 spin_unlock_irqrestore(&acb->doneq_lock, flags); 2402 } 2403 2404 static void arcmsr_hbaE_postqueue_isr(struct AdapterControlBlock *acb) 2405 { 2406 uint32_t doneq_index; 2407 uint16_t cmdSMID; 2408 int error; 2409 struct MessageUnit_E __iomem *pmu; 2410 struct CommandControlBlock *ccb; 2411 unsigned long flags; 2412 2413 spin_lock_irqsave(&acb->doneq_lock, flags); 2414 doneq_index = acb->doneq_index; 2415 pmu = acb->pmuE; 2416 while ((readl(&pmu->reply_post_producer_index) & 0xFFFF) != doneq_index) { 2417 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID; 2418 ccb = acb->pccb_pool[cmdSMID]; 2419 error = (acb->pCompletionQ[doneq_index].cmdFlag 2420 & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false; 2421 arcmsr_drain_donequeue(acb, ccb, error); 2422 doneq_index++; 2423 if (doneq_index >= acb->completionQ_entry) 2424 doneq_index = 0; 2425 } 2426 acb->doneq_index = doneq_index; 2427 writel(doneq_index, &pmu->reply_post_consumer_index); 2428 spin_unlock_irqrestore(&acb->doneq_lock, flags); 2429 } 2430 2431 /* 2432 ********************************************************************************** 2433 ** Handle a message interrupt 2434 ** 2435 ** The only message interrupt we expect is in response to a query for the current adapter config. 2436 ** We want this in order to compare the drivemap so that we can detect newly-attached drives. 2437 ********************************************************************************** 2438 */ 2439 static void arcmsr_hbaA_message_isr(struct AdapterControlBlock *acb) 2440 { 2441 struct MessageUnit_A __iomem *reg = acb->pmuA; 2442 /*clear interrupt and message state*/ 2443 writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT, ®->outbound_intstatus); 2444 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG) 2445 schedule_work(&acb->arcmsr_do_message_isr_bh); 2446 } 2447 static void arcmsr_hbaB_message_isr(struct AdapterControlBlock *acb) 2448 { 2449 struct MessageUnit_B *reg = acb->pmuB; 2450 2451 /*clear interrupt and message state*/ 2452 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); 2453 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG) 2454 schedule_work(&acb->arcmsr_do_message_isr_bh); 2455 } 2456 /* 2457 ********************************************************************************** 2458 ** Handle a message interrupt 2459 ** 2460 ** The only message interrupt we expect is in response to a query for the 2461 ** current adapter config. 2462 ** We want this in order to compare the drivemap so that we can detect newly-attached drives. 2463 ********************************************************************************** 2464 */ 2465 static void arcmsr_hbaC_message_isr(struct AdapterControlBlock *acb) 2466 { 2467 struct MessageUnit_C __iomem *reg = acb->pmuC; 2468 /*clear interrupt and message state*/ 2469 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, ®->outbound_doorbell_clear); 2470 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG) 2471 schedule_work(&acb->arcmsr_do_message_isr_bh); 2472 } 2473 2474 static void arcmsr_hbaD_message_isr(struct AdapterControlBlock *acb) 2475 { 2476 struct MessageUnit_D *reg = acb->pmuD; 2477 2478 writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE, reg->outbound_doorbell); 2479 readl(reg->outbound_doorbell); 2480 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG) 2481 schedule_work(&acb->arcmsr_do_message_isr_bh); 2482 } 2483 2484 static void arcmsr_hbaE_message_isr(struct AdapterControlBlock *acb) 2485 { 2486 struct MessageUnit_E __iomem *reg = acb->pmuE; 2487 2488 writel(0, ®->host_int_status); 2489 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG) 2490 schedule_work(&acb->arcmsr_do_message_isr_bh); 2491 } 2492 2493 static int arcmsr_hbaA_handle_isr(struct AdapterControlBlock *acb) 2494 { 2495 uint32_t outbound_intstatus; 2496 struct MessageUnit_A __iomem *reg = acb->pmuA; 2497 outbound_intstatus = readl(®->outbound_intstatus) & 2498 acb->outbound_int_enable; 2499 if (!(outbound_intstatus & ARCMSR_MU_OUTBOUND_HANDLE_INT)) 2500 return IRQ_NONE; 2501 do { 2502 writel(outbound_intstatus, ®->outbound_intstatus); 2503 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) 2504 arcmsr_hbaA_doorbell_isr(acb); 2505 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) 2506 arcmsr_hbaA_postqueue_isr(acb); 2507 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) 2508 arcmsr_hbaA_message_isr(acb); 2509 outbound_intstatus = readl(®->outbound_intstatus) & 2510 acb->outbound_int_enable; 2511 } while (outbound_intstatus & (ARCMSR_MU_OUTBOUND_DOORBELL_INT 2512 | ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 2513 | ARCMSR_MU_OUTBOUND_MESSAGE0_INT)); 2514 return IRQ_HANDLED; 2515 } 2516 2517 static int arcmsr_hbaB_handle_isr(struct AdapterControlBlock *acb) 2518 { 2519 uint32_t outbound_doorbell; 2520 struct MessageUnit_B *reg = acb->pmuB; 2521 outbound_doorbell = readl(reg->iop2drv_doorbell) & 2522 acb->outbound_int_enable; 2523 if (!outbound_doorbell) 2524 return IRQ_NONE; 2525 do { 2526 writel(~outbound_doorbell, reg->iop2drv_doorbell); 2527 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell); 2528 if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) 2529 arcmsr_iop2drv_data_wrote_handle(acb); 2530 if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) 2531 arcmsr_iop2drv_data_read_handle(acb); 2532 if (outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) 2533 arcmsr_hbaB_postqueue_isr(acb); 2534 if (outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) 2535 arcmsr_hbaB_message_isr(acb); 2536 outbound_doorbell = readl(reg->iop2drv_doorbell) & 2537 acb->outbound_int_enable; 2538 } while (outbound_doorbell & (ARCMSR_IOP2DRV_DATA_WRITE_OK 2539 | ARCMSR_IOP2DRV_DATA_READ_OK 2540 | ARCMSR_IOP2DRV_CDB_DONE 2541 | ARCMSR_IOP2DRV_MESSAGE_CMD_DONE)); 2542 return IRQ_HANDLED; 2543 } 2544 2545 static int arcmsr_hbaC_handle_isr(struct AdapterControlBlock *pACB) 2546 { 2547 uint32_t host_interrupt_status; 2548 struct MessageUnit_C __iomem *phbcmu = pACB->pmuC; 2549 /* 2550 ********************************************* 2551 ** check outbound intstatus 2552 ********************************************* 2553 */ 2554 host_interrupt_status = readl(&phbcmu->host_int_status) & 2555 (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | 2556 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR); 2557 if (!host_interrupt_status) 2558 return IRQ_NONE; 2559 do { 2560 if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) 2561 arcmsr_hbaC_doorbell_isr(pACB); 2562 /* MU post queue interrupts*/ 2563 if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) 2564 arcmsr_hbaC_postqueue_isr(pACB); 2565 host_interrupt_status = readl(&phbcmu->host_int_status); 2566 } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | 2567 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR)); 2568 return IRQ_HANDLED; 2569 } 2570 2571 static irqreturn_t arcmsr_hbaD_handle_isr(struct AdapterControlBlock *pACB) 2572 { 2573 u32 host_interrupt_status; 2574 struct MessageUnit_D *pmu = pACB->pmuD; 2575 2576 host_interrupt_status = readl(pmu->host_int_status) & 2577 (ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR | 2578 ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR); 2579 if (!host_interrupt_status) 2580 return IRQ_NONE; 2581 do { 2582 /* MU post queue interrupts*/ 2583 if (host_interrupt_status & 2584 ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR) 2585 arcmsr_hbaD_postqueue_isr(pACB); 2586 if (host_interrupt_status & 2587 ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR) 2588 arcmsr_hbaD_doorbell_isr(pACB); 2589 host_interrupt_status = readl(pmu->host_int_status); 2590 } while (host_interrupt_status & 2591 (ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR | 2592 ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR)); 2593 return IRQ_HANDLED; 2594 } 2595 2596 static irqreturn_t arcmsr_hbaE_handle_isr(struct AdapterControlBlock *pACB) 2597 { 2598 uint32_t host_interrupt_status; 2599 struct MessageUnit_E __iomem *pmu = pACB->pmuE; 2600 2601 host_interrupt_status = readl(&pmu->host_int_status) & 2602 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | 2603 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR); 2604 if (!host_interrupt_status) 2605 return IRQ_NONE; 2606 do { 2607 /* MU ioctl transfer doorbell interrupts*/ 2608 if (host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) { 2609 arcmsr_hbaE_doorbell_isr(pACB); 2610 } 2611 /* MU post queue interrupts*/ 2612 if (host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) { 2613 arcmsr_hbaE_postqueue_isr(pACB); 2614 } 2615 host_interrupt_status = readl(&pmu->host_int_status); 2616 } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | 2617 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR)); 2618 return IRQ_HANDLED; 2619 } 2620 2621 static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb) 2622 { 2623 switch (acb->adapter_type) { 2624 case ACB_ADAPTER_TYPE_A: 2625 return arcmsr_hbaA_handle_isr(acb); 2626 break; 2627 case ACB_ADAPTER_TYPE_B: 2628 return arcmsr_hbaB_handle_isr(acb); 2629 break; 2630 case ACB_ADAPTER_TYPE_C: 2631 return arcmsr_hbaC_handle_isr(acb); 2632 case ACB_ADAPTER_TYPE_D: 2633 return arcmsr_hbaD_handle_isr(acb); 2634 case ACB_ADAPTER_TYPE_E: 2635 return arcmsr_hbaE_handle_isr(acb); 2636 default: 2637 return IRQ_NONE; 2638 } 2639 } 2640 2641 static void arcmsr_iop_parking(struct AdapterControlBlock *acb) 2642 { 2643 if (acb) { 2644 /* stop adapter background rebuild */ 2645 if (acb->acb_flags & ACB_F_MSG_START_BGRB) { 2646 uint32_t intmask_org; 2647 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 2648 intmask_org = arcmsr_disable_outbound_ints(acb); 2649 arcmsr_stop_adapter_bgrb(acb); 2650 arcmsr_flush_adapter_cache(acb); 2651 arcmsr_enable_outbound_ints(acb, intmask_org); 2652 } 2653 } 2654 } 2655 2656 2657 void arcmsr_clear_iop2drv_rqueue_buffer(struct AdapterControlBlock *acb) 2658 { 2659 uint32_t i; 2660 2661 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2662 for (i = 0; i < 15; i++) { 2663 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2664 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2665 acb->rqbuf_getIndex = 0; 2666 acb->rqbuf_putIndex = 0; 2667 arcmsr_iop_message_read(acb); 2668 mdelay(30); 2669 } else if (acb->rqbuf_getIndex != 2670 acb->rqbuf_putIndex) { 2671 acb->rqbuf_getIndex = 0; 2672 acb->rqbuf_putIndex = 0; 2673 mdelay(30); 2674 } else 2675 break; 2676 } 2677 } 2678 } 2679 2680 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, 2681 struct scsi_cmnd *cmd) 2682 { 2683 char *buffer; 2684 unsigned short use_sg; 2685 int retvalue = 0, transfer_len = 0; 2686 unsigned long flags; 2687 struct CMD_MESSAGE_FIELD *pcmdmessagefld; 2688 uint32_t controlcode = (uint32_t)cmd->cmnd[5] << 24 | 2689 (uint32_t)cmd->cmnd[6] << 16 | 2690 (uint32_t)cmd->cmnd[7] << 8 | 2691 (uint32_t)cmd->cmnd[8]; 2692 struct scatterlist *sg; 2693 2694 use_sg = scsi_sg_count(cmd); 2695 sg = scsi_sglist(cmd); 2696 buffer = kmap_atomic(sg_page(sg)) + sg->offset; 2697 if (use_sg > 1) { 2698 retvalue = ARCMSR_MESSAGE_FAIL; 2699 goto message_out; 2700 } 2701 transfer_len += sg->length; 2702 if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) { 2703 retvalue = ARCMSR_MESSAGE_FAIL; 2704 pr_info("%s: ARCMSR_MESSAGE_FAIL!\n", __func__); 2705 goto message_out; 2706 } 2707 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *)buffer; 2708 switch (controlcode) { 2709 case ARCMSR_MESSAGE_READ_RQBUFFER: { 2710 unsigned char *ver_addr; 2711 uint8_t *ptmpQbuffer; 2712 uint32_t allxfer_len = 0; 2713 ver_addr = kmalloc(ARCMSR_API_DATA_BUFLEN, GFP_ATOMIC); 2714 if (!ver_addr) { 2715 retvalue = ARCMSR_MESSAGE_FAIL; 2716 pr_info("%s: memory not enough!\n", __func__); 2717 goto message_out; 2718 } 2719 ptmpQbuffer = ver_addr; 2720 spin_lock_irqsave(&acb->rqbuffer_lock, flags); 2721 if (acb->rqbuf_getIndex != acb->rqbuf_putIndex) { 2722 unsigned int tail = acb->rqbuf_getIndex; 2723 unsigned int head = acb->rqbuf_putIndex; 2724 unsigned int cnt_to_end = CIRC_CNT_TO_END(head, tail, ARCMSR_MAX_QBUFFER); 2725 2726 allxfer_len = CIRC_CNT(head, tail, ARCMSR_MAX_QBUFFER); 2727 if (allxfer_len > ARCMSR_API_DATA_BUFLEN) 2728 allxfer_len = ARCMSR_API_DATA_BUFLEN; 2729 2730 if (allxfer_len <= cnt_to_end) 2731 memcpy(ptmpQbuffer, acb->rqbuffer + tail, allxfer_len); 2732 else { 2733 memcpy(ptmpQbuffer, acb->rqbuffer + tail, cnt_to_end); 2734 memcpy(ptmpQbuffer + cnt_to_end, acb->rqbuffer, allxfer_len - cnt_to_end); 2735 } 2736 acb->rqbuf_getIndex = (acb->rqbuf_getIndex + allxfer_len) % ARCMSR_MAX_QBUFFER; 2737 } 2738 memcpy(pcmdmessagefld->messagedatabuffer, ver_addr, 2739 allxfer_len); 2740 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2741 struct QBUFFER __iomem *prbuffer; 2742 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2743 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2744 if (arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 2745 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2746 } 2747 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags); 2748 kfree(ver_addr); 2749 pcmdmessagefld->cmdmessage.Length = allxfer_len; 2750 if (acb->fw_flag == FW_DEADLOCK) 2751 pcmdmessagefld->cmdmessage.ReturnCode = 2752 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON; 2753 else 2754 pcmdmessagefld->cmdmessage.ReturnCode = 2755 ARCMSR_MESSAGE_RETURNCODE_OK; 2756 break; 2757 } 2758 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 2759 unsigned char *ver_addr; 2760 uint32_t user_len; 2761 int32_t cnt2end; 2762 uint8_t *pQbuffer, *ptmpuserbuffer; 2763 2764 user_len = pcmdmessagefld->cmdmessage.Length; 2765 if (user_len > ARCMSR_API_DATA_BUFLEN) { 2766 retvalue = ARCMSR_MESSAGE_FAIL; 2767 goto message_out; 2768 } 2769 2770 ver_addr = kmalloc(ARCMSR_API_DATA_BUFLEN, GFP_ATOMIC); 2771 if (!ver_addr) { 2772 retvalue = ARCMSR_MESSAGE_FAIL; 2773 goto message_out; 2774 } 2775 ptmpuserbuffer = ver_addr; 2776 2777 memcpy(ptmpuserbuffer, 2778 pcmdmessagefld->messagedatabuffer, user_len); 2779 spin_lock_irqsave(&acb->wqbuffer_lock, flags); 2780 if (acb->wqbuf_putIndex != acb->wqbuf_getIndex) { 2781 struct SENSE_DATA *sensebuffer = 2782 (struct SENSE_DATA *)cmd->sense_buffer; 2783 arcmsr_write_ioctldata2iop(acb); 2784 /* has error report sensedata */ 2785 sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS; 2786 sensebuffer->SenseKey = ILLEGAL_REQUEST; 2787 sensebuffer->AdditionalSenseLength = 0x0A; 2788 sensebuffer->AdditionalSenseCode = 0x20; 2789 sensebuffer->Valid = 1; 2790 retvalue = ARCMSR_MESSAGE_FAIL; 2791 } else { 2792 pQbuffer = &acb->wqbuffer[acb->wqbuf_putIndex]; 2793 cnt2end = ARCMSR_MAX_QBUFFER - acb->wqbuf_putIndex; 2794 if (user_len > cnt2end) { 2795 memcpy(pQbuffer, ptmpuserbuffer, cnt2end); 2796 ptmpuserbuffer += cnt2end; 2797 user_len -= cnt2end; 2798 acb->wqbuf_putIndex = 0; 2799 pQbuffer = acb->wqbuffer; 2800 } 2801 memcpy(pQbuffer, ptmpuserbuffer, user_len); 2802 acb->wqbuf_putIndex += user_len; 2803 acb->wqbuf_putIndex %= ARCMSR_MAX_QBUFFER; 2804 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 2805 acb->acb_flags &= 2806 ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 2807 arcmsr_write_ioctldata2iop(acb); 2808 } 2809 } 2810 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags); 2811 kfree(ver_addr); 2812 if (acb->fw_flag == FW_DEADLOCK) 2813 pcmdmessagefld->cmdmessage.ReturnCode = 2814 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON; 2815 else 2816 pcmdmessagefld->cmdmessage.ReturnCode = 2817 ARCMSR_MESSAGE_RETURNCODE_OK; 2818 break; 2819 } 2820 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 2821 uint8_t *pQbuffer = acb->rqbuffer; 2822 2823 arcmsr_clear_iop2drv_rqueue_buffer(acb); 2824 spin_lock_irqsave(&acb->rqbuffer_lock, flags); 2825 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2826 acb->rqbuf_getIndex = 0; 2827 acb->rqbuf_putIndex = 0; 2828 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2829 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags); 2830 if (acb->fw_flag == FW_DEADLOCK) 2831 pcmdmessagefld->cmdmessage.ReturnCode = 2832 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON; 2833 else 2834 pcmdmessagefld->cmdmessage.ReturnCode = 2835 ARCMSR_MESSAGE_RETURNCODE_OK; 2836 break; 2837 } 2838 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: { 2839 uint8_t *pQbuffer = acb->wqbuffer; 2840 spin_lock_irqsave(&acb->wqbuffer_lock, flags); 2841 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED | 2842 ACB_F_MESSAGE_WQBUFFER_READED); 2843 acb->wqbuf_getIndex = 0; 2844 acb->wqbuf_putIndex = 0; 2845 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2846 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags); 2847 if (acb->fw_flag == FW_DEADLOCK) 2848 pcmdmessagefld->cmdmessage.ReturnCode = 2849 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON; 2850 else 2851 pcmdmessagefld->cmdmessage.ReturnCode = 2852 ARCMSR_MESSAGE_RETURNCODE_OK; 2853 break; 2854 } 2855 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 2856 uint8_t *pQbuffer; 2857 arcmsr_clear_iop2drv_rqueue_buffer(acb); 2858 spin_lock_irqsave(&acb->rqbuffer_lock, flags); 2859 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2860 acb->rqbuf_getIndex = 0; 2861 acb->rqbuf_putIndex = 0; 2862 pQbuffer = acb->rqbuffer; 2863 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2864 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags); 2865 spin_lock_irqsave(&acb->wqbuffer_lock, flags); 2866 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED | 2867 ACB_F_MESSAGE_WQBUFFER_READED); 2868 acb->wqbuf_getIndex = 0; 2869 acb->wqbuf_putIndex = 0; 2870 pQbuffer = acb->wqbuffer; 2871 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2872 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags); 2873 if (acb->fw_flag == FW_DEADLOCK) 2874 pcmdmessagefld->cmdmessage.ReturnCode = 2875 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON; 2876 else 2877 pcmdmessagefld->cmdmessage.ReturnCode = 2878 ARCMSR_MESSAGE_RETURNCODE_OK; 2879 break; 2880 } 2881 case ARCMSR_MESSAGE_RETURN_CODE_3F: { 2882 if (acb->fw_flag == FW_DEADLOCK) 2883 pcmdmessagefld->cmdmessage.ReturnCode = 2884 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON; 2885 else 2886 pcmdmessagefld->cmdmessage.ReturnCode = 2887 ARCMSR_MESSAGE_RETURNCODE_3F; 2888 break; 2889 } 2890 case ARCMSR_MESSAGE_SAY_HELLO: { 2891 int8_t *hello_string = "Hello! I am ARCMSR"; 2892 if (acb->fw_flag == FW_DEADLOCK) 2893 pcmdmessagefld->cmdmessage.ReturnCode = 2894 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON; 2895 else 2896 pcmdmessagefld->cmdmessage.ReturnCode = 2897 ARCMSR_MESSAGE_RETURNCODE_OK; 2898 memcpy(pcmdmessagefld->messagedatabuffer, 2899 hello_string, (int16_t)strlen(hello_string)); 2900 break; 2901 } 2902 case ARCMSR_MESSAGE_SAY_GOODBYE: { 2903 if (acb->fw_flag == FW_DEADLOCK) 2904 pcmdmessagefld->cmdmessage.ReturnCode = 2905 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON; 2906 else 2907 pcmdmessagefld->cmdmessage.ReturnCode = 2908 ARCMSR_MESSAGE_RETURNCODE_OK; 2909 arcmsr_iop_parking(acb); 2910 break; 2911 } 2912 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: { 2913 if (acb->fw_flag == FW_DEADLOCK) 2914 pcmdmessagefld->cmdmessage.ReturnCode = 2915 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON; 2916 else 2917 pcmdmessagefld->cmdmessage.ReturnCode = 2918 ARCMSR_MESSAGE_RETURNCODE_OK; 2919 arcmsr_flush_adapter_cache(acb); 2920 break; 2921 } 2922 default: 2923 retvalue = ARCMSR_MESSAGE_FAIL; 2924 pr_info("%s: unknown controlcode!\n", __func__); 2925 } 2926 message_out: 2927 if (use_sg) { 2928 struct scatterlist *sg = scsi_sglist(cmd); 2929 kunmap_atomic(buffer - sg->offset); 2930 } 2931 return retvalue; 2932 } 2933 2934 static struct CommandControlBlock *arcmsr_get_freeccb(struct AdapterControlBlock *acb) 2935 { 2936 struct list_head *head = &acb->ccb_free_list; 2937 struct CommandControlBlock *ccb = NULL; 2938 unsigned long flags; 2939 spin_lock_irqsave(&acb->ccblist_lock, flags); 2940 if (!list_empty(head)) { 2941 ccb = list_entry(head->next, struct CommandControlBlock, list); 2942 list_del_init(&ccb->list); 2943 }else{ 2944 spin_unlock_irqrestore(&acb->ccblist_lock, flags); 2945 return NULL; 2946 } 2947 spin_unlock_irqrestore(&acb->ccblist_lock, flags); 2948 return ccb; 2949 } 2950 2951 static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb, 2952 struct scsi_cmnd *cmd) 2953 { 2954 switch (cmd->cmnd[0]) { 2955 case INQUIRY: { 2956 unsigned char inqdata[36]; 2957 char *buffer; 2958 struct scatterlist *sg; 2959 2960 if (cmd->device->lun) { 2961 cmd->result = (DID_TIME_OUT << 16); 2962 cmd->scsi_done(cmd); 2963 return; 2964 } 2965 inqdata[0] = TYPE_PROCESSOR; 2966 /* Periph Qualifier & Periph Dev Type */ 2967 inqdata[1] = 0; 2968 /* rem media bit & Dev Type Modifier */ 2969 inqdata[2] = 0; 2970 /* ISO, ECMA, & ANSI versions */ 2971 inqdata[4] = 31; 2972 /* length of additional data */ 2973 strncpy(&inqdata[8], "Areca ", 8); 2974 /* Vendor Identification */ 2975 strncpy(&inqdata[16], "RAID controller ", 16); 2976 /* Product Identification */ 2977 strncpy(&inqdata[32], "R001", 4); /* Product Revision */ 2978 2979 sg = scsi_sglist(cmd); 2980 buffer = kmap_atomic(sg_page(sg)) + sg->offset; 2981 2982 memcpy(buffer, inqdata, sizeof(inqdata)); 2983 sg = scsi_sglist(cmd); 2984 kunmap_atomic(buffer - sg->offset); 2985 2986 cmd->scsi_done(cmd); 2987 } 2988 break; 2989 case WRITE_BUFFER: 2990 case READ_BUFFER: { 2991 if (arcmsr_iop_message_xfer(acb, cmd)) 2992 cmd->result = (DID_ERROR << 16); 2993 cmd->scsi_done(cmd); 2994 } 2995 break; 2996 default: 2997 cmd->scsi_done(cmd); 2998 } 2999 } 3000 3001 static int arcmsr_queue_command_lck(struct scsi_cmnd *cmd, 3002 void (* done)(struct scsi_cmnd *)) 3003 { 3004 struct Scsi_Host *host = cmd->device->host; 3005 struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata; 3006 struct CommandControlBlock *ccb; 3007 int target = cmd->device->id; 3008 3009 if (acb->acb_flags & ACB_F_ADAPTER_REMOVED) { 3010 cmd->result = (DID_NO_CONNECT << 16); 3011 cmd->scsi_done(cmd); 3012 return 0; 3013 } 3014 cmd->scsi_done = done; 3015 cmd->host_scribble = NULL; 3016 cmd->result = 0; 3017 if (target == 16) { 3018 /* virtual device for iop message transfer */ 3019 arcmsr_handle_virtual_command(acb, cmd); 3020 return 0; 3021 } 3022 ccb = arcmsr_get_freeccb(acb); 3023 if (!ccb) 3024 return SCSI_MLQUEUE_HOST_BUSY; 3025 if (arcmsr_build_ccb( acb, ccb, cmd ) == FAILED) { 3026 cmd->result = (DID_ERROR << 16) | (RESERVATION_CONFLICT << 1); 3027 cmd->scsi_done(cmd); 3028 return 0; 3029 } 3030 arcmsr_post_ccb(acb, ccb); 3031 return 0; 3032 } 3033 3034 static DEF_SCSI_QCMD(arcmsr_queue_command) 3035 3036 static void arcmsr_get_adapter_config(struct AdapterControlBlock *pACB, uint32_t *rwbuffer) 3037 { 3038 int count; 3039 uint32_t *acb_firm_model = (uint32_t *)pACB->firm_model; 3040 uint32_t *acb_firm_version = (uint32_t *)pACB->firm_version; 3041 uint32_t *acb_device_map = (uint32_t *)pACB->device_map; 3042 uint32_t *firm_model = &rwbuffer[15]; 3043 uint32_t *firm_version = &rwbuffer[17]; 3044 uint32_t *device_map = &rwbuffer[21]; 3045 3046 count = 2; 3047 while (count) { 3048 *acb_firm_model = readl(firm_model); 3049 acb_firm_model++; 3050 firm_model++; 3051 count--; 3052 } 3053 count = 4; 3054 while (count) { 3055 *acb_firm_version = readl(firm_version); 3056 acb_firm_version++; 3057 firm_version++; 3058 count--; 3059 } 3060 count = 4; 3061 while (count) { 3062 *acb_device_map = readl(device_map); 3063 acb_device_map++; 3064 device_map++; 3065 count--; 3066 } 3067 pACB->signature = readl(&rwbuffer[0]); 3068 pACB->firm_request_len = readl(&rwbuffer[1]); 3069 pACB->firm_numbers_queue = readl(&rwbuffer[2]); 3070 pACB->firm_sdram_size = readl(&rwbuffer[3]); 3071 pACB->firm_hd_channels = readl(&rwbuffer[4]); 3072 pACB->firm_cfg_version = readl(&rwbuffer[25]); 3073 pr_notice("Areca RAID Controller%d: Model %s, F/W %s\n", 3074 pACB->host->host_no, 3075 pACB->firm_model, 3076 pACB->firm_version); 3077 } 3078 3079 static bool arcmsr_hbaA_get_config(struct AdapterControlBlock *acb) 3080 { 3081 struct MessageUnit_A __iomem *reg = acb->pmuA; 3082 3083 arcmsr_wait_firmware_ready(acb); 3084 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0); 3085 if (!arcmsr_hbaA_wait_msgint_ready(acb)) { 3086 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \ 3087 miscellaneous data' timeout \n", acb->host->host_no); 3088 return false; 3089 } 3090 arcmsr_get_adapter_config(acb, reg->message_rwbuffer); 3091 return true; 3092 } 3093 static bool arcmsr_hbaB_get_config(struct AdapterControlBlock *acb) 3094 { 3095 struct MessageUnit_B *reg = acb->pmuB; 3096 3097 arcmsr_wait_firmware_ready(acb); 3098 writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell); 3099 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 3100 printk(KERN_ERR "arcmsr%d: can't set driver mode.\n", acb->host->host_no); 3101 return false; 3102 } 3103 writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell); 3104 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 3105 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \ 3106 miscellaneous data' timeout \n", acb->host->host_no); 3107 return false; 3108 } 3109 arcmsr_get_adapter_config(acb, reg->message_rwbuffer); 3110 return true; 3111 } 3112 3113 static bool arcmsr_hbaC_get_config(struct AdapterControlBlock *pACB) 3114 { 3115 uint32_t intmask_org; 3116 struct MessageUnit_C __iomem *reg = pACB->pmuC; 3117 3118 /* disable all outbound interrupt */ 3119 intmask_org = readl(®->host_int_mask); /* disable outbound message0 int */ 3120 writel(intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE, ®->host_int_mask); 3121 /* wait firmware ready */ 3122 arcmsr_wait_firmware_ready(pACB); 3123 /* post "get config" instruction */ 3124 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0); 3125 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell); 3126 /* wait message ready */ 3127 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) { 3128 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \ 3129 miscellaneous data' timeout \n", pACB->host->host_no); 3130 return false; 3131 } 3132 arcmsr_get_adapter_config(pACB, reg->msgcode_rwbuffer); 3133 return true; 3134 } 3135 3136 static bool arcmsr_hbaD_get_config(struct AdapterControlBlock *acb) 3137 { 3138 struct MessageUnit_D *reg = acb->pmuD; 3139 3140 if (readl(acb->pmuD->outbound_doorbell) & 3141 ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE) { 3142 writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE, 3143 acb->pmuD->outbound_doorbell);/*clear interrupt*/ 3144 } 3145 arcmsr_wait_firmware_ready(acb); 3146 /* post "get config" instruction */ 3147 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, reg->inbound_msgaddr0); 3148 /* wait message ready */ 3149 if (!arcmsr_hbaD_wait_msgint_ready(acb)) { 3150 pr_notice("arcmsr%d: wait get adapter firmware " 3151 "miscellaneous data timeout\n", acb->host->host_no); 3152 return false; 3153 } 3154 arcmsr_get_adapter_config(acb, reg->msgcode_rwbuffer); 3155 return true; 3156 } 3157 3158 static bool arcmsr_hbaE_get_config(struct AdapterControlBlock *pACB) 3159 { 3160 struct MessageUnit_E __iomem *reg = pACB->pmuE; 3161 uint32_t intmask_org; 3162 3163 /* disable all outbound interrupt */ 3164 intmask_org = readl(®->host_int_mask); /* disable outbound message0 int */ 3165 writel(intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE, ®->host_int_mask); 3166 /* wait firmware ready */ 3167 arcmsr_wait_firmware_ready(pACB); 3168 mdelay(20); 3169 /* post "get config" instruction */ 3170 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0); 3171 3172 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 3173 writel(pACB->out_doorbell, ®->iobound_doorbell); 3174 /* wait message ready */ 3175 if (!arcmsr_hbaE_wait_msgint_ready(pACB)) { 3176 pr_notice("arcmsr%d: wait get adapter firmware " 3177 "miscellaneous data timeout\n", pACB->host->host_no); 3178 return false; 3179 } 3180 arcmsr_get_adapter_config(pACB, reg->msgcode_rwbuffer); 3181 return true; 3182 } 3183 3184 static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb) 3185 { 3186 bool rtn = false; 3187 3188 switch (acb->adapter_type) { 3189 case ACB_ADAPTER_TYPE_A: 3190 rtn = arcmsr_hbaA_get_config(acb); 3191 break; 3192 case ACB_ADAPTER_TYPE_B: 3193 rtn = arcmsr_hbaB_get_config(acb); 3194 break; 3195 case ACB_ADAPTER_TYPE_C: 3196 rtn = arcmsr_hbaC_get_config(acb); 3197 break; 3198 case ACB_ADAPTER_TYPE_D: 3199 rtn = arcmsr_hbaD_get_config(acb); 3200 break; 3201 case ACB_ADAPTER_TYPE_E: 3202 rtn = arcmsr_hbaE_get_config(acb); 3203 break; 3204 default: 3205 break; 3206 } 3207 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3208 if (acb->host->can_queue >= acb->firm_numbers_queue) 3209 acb->host->can_queue = acb->maxOutstanding; 3210 else 3211 acb->maxOutstanding = acb->host->can_queue; 3212 acb->maxFreeCCB = acb->host->can_queue; 3213 if (acb->maxFreeCCB < ARCMSR_MAX_FREECCB_NUM) 3214 acb->maxFreeCCB += 64; 3215 return rtn; 3216 } 3217 3218 static int arcmsr_hbaA_polling_ccbdone(struct AdapterControlBlock *acb, 3219 struct CommandControlBlock *poll_ccb) 3220 { 3221 struct MessageUnit_A __iomem *reg = acb->pmuA; 3222 struct CommandControlBlock *ccb; 3223 struct ARCMSR_CDB *arcmsr_cdb; 3224 uint32_t flag_ccb, outbound_intstatus, poll_ccb_done = 0, poll_count = 0; 3225 int rtn; 3226 bool error; 3227 polling_hba_ccb_retry: 3228 poll_count++; 3229 outbound_intstatus = readl(®->outbound_intstatus) & acb->outbound_int_enable; 3230 writel(outbound_intstatus, ®->outbound_intstatus);/*clear interrupt*/ 3231 while (1) { 3232 if ((flag_ccb = readl(®->outbound_queueport)) == 0xFFFFFFFF) { 3233 if (poll_ccb_done){ 3234 rtn = SUCCESS; 3235 break; 3236 }else { 3237 msleep(25); 3238 if (poll_count > 100){ 3239 rtn = FAILED; 3240 break; 3241 } 3242 goto polling_hba_ccb_retry; 3243 } 3244 } 3245 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5)); 3246 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb); 3247 poll_ccb_done |= (ccb == poll_ccb) ? 1 : 0; 3248 if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) { 3249 if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) { 3250 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'" 3251 " poll command abort successfully \n" 3252 , acb->host->host_no 3253 , ccb->pcmd->device->id 3254 , (u32)ccb->pcmd->device->lun 3255 , ccb); 3256 ccb->pcmd->result = DID_ABORT << 16; 3257 arcmsr_ccb_complete(ccb); 3258 continue; 3259 } 3260 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb" 3261 " command done ccb = '0x%p'" 3262 "ccboutstandingcount = %d \n" 3263 , acb->host->host_no 3264 , ccb 3265 , atomic_read(&acb->ccboutstandingcount)); 3266 continue; 3267 } 3268 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false; 3269 arcmsr_report_ccb_state(acb, ccb, error); 3270 } 3271 return rtn; 3272 } 3273 3274 static int arcmsr_hbaB_polling_ccbdone(struct AdapterControlBlock *acb, 3275 struct CommandControlBlock *poll_ccb) 3276 { 3277 struct MessageUnit_B *reg = acb->pmuB; 3278 struct ARCMSR_CDB *arcmsr_cdb; 3279 struct CommandControlBlock *ccb; 3280 uint32_t flag_ccb, poll_ccb_done = 0, poll_count = 0; 3281 int index, rtn; 3282 bool error; 3283 polling_hbb_ccb_retry: 3284 3285 poll_count++; 3286 /* clear doorbell interrupt */ 3287 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); 3288 while(1){ 3289 index = reg->doneq_index; 3290 flag_ccb = reg->done_qbuffer[index]; 3291 if (flag_ccb == 0) { 3292 if (poll_ccb_done){ 3293 rtn = SUCCESS; 3294 break; 3295 }else { 3296 msleep(25); 3297 if (poll_count > 100){ 3298 rtn = FAILED; 3299 break; 3300 } 3301 goto polling_hbb_ccb_retry; 3302 } 3303 } 3304 reg->done_qbuffer[index] = 0; 3305 index++; 3306 /*if last index number set it to 0 */ 3307 index %= ARCMSR_MAX_HBB_POSTQUEUE; 3308 reg->doneq_index = index; 3309 /* check if command done with no error*/ 3310 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5)); 3311 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb); 3312 poll_ccb_done |= (ccb == poll_ccb) ? 1 : 0; 3313 if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) { 3314 if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) { 3315 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'" 3316 " poll command abort successfully \n" 3317 ,acb->host->host_no 3318 ,ccb->pcmd->device->id 3319 ,(u32)ccb->pcmd->device->lun 3320 ,ccb); 3321 ccb->pcmd->result = DID_ABORT << 16; 3322 arcmsr_ccb_complete(ccb); 3323 continue; 3324 } 3325 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb" 3326 " command done ccb = '0x%p'" 3327 "ccboutstandingcount = %d \n" 3328 , acb->host->host_no 3329 , ccb 3330 , atomic_read(&acb->ccboutstandingcount)); 3331 continue; 3332 } 3333 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false; 3334 arcmsr_report_ccb_state(acb, ccb, error); 3335 } 3336 return rtn; 3337 } 3338 3339 static int arcmsr_hbaC_polling_ccbdone(struct AdapterControlBlock *acb, 3340 struct CommandControlBlock *poll_ccb) 3341 { 3342 struct MessageUnit_C __iomem *reg = acb->pmuC; 3343 uint32_t flag_ccb, ccb_cdb_phy; 3344 struct ARCMSR_CDB *arcmsr_cdb; 3345 bool error; 3346 struct CommandControlBlock *pCCB; 3347 uint32_t poll_ccb_done = 0, poll_count = 0; 3348 int rtn; 3349 polling_hbc_ccb_retry: 3350 poll_count++; 3351 while (1) { 3352 if ((readl(®->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) == 0) { 3353 if (poll_ccb_done) { 3354 rtn = SUCCESS; 3355 break; 3356 } else { 3357 msleep(25); 3358 if (poll_count > 100) { 3359 rtn = FAILED; 3360 break; 3361 } 3362 goto polling_hbc_ccb_retry; 3363 } 3364 } 3365 flag_ccb = readl(®->outbound_queueport_low); 3366 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0); 3367 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);/*frame must be 32 bytes aligned*/ 3368 pCCB = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb); 3369 poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0; 3370 /* check ifcommand done with no error*/ 3371 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) { 3372 if (pCCB->startdone == ARCMSR_CCB_ABORTED) { 3373 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'" 3374 " poll command abort successfully \n" 3375 , acb->host->host_no 3376 , pCCB->pcmd->device->id 3377 , (u32)pCCB->pcmd->device->lun 3378 , pCCB); 3379 pCCB->pcmd->result = DID_ABORT << 16; 3380 arcmsr_ccb_complete(pCCB); 3381 continue; 3382 } 3383 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb" 3384 " command done ccb = '0x%p'" 3385 "ccboutstandingcount = %d \n" 3386 , acb->host->host_no 3387 , pCCB 3388 , atomic_read(&acb->ccboutstandingcount)); 3389 continue; 3390 } 3391 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false; 3392 arcmsr_report_ccb_state(acb, pCCB, error); 3393 } 3394 return rtn; 3395 } 3396 3397 static int arcmsr_hbaD_polling_ccbdone(struct AdapterControlBlock *acb, 3398 struct CommandControlBlock *poll_ccb) 3399 { 3400 bool error; 3401 uint32_t poll_ccb_done = 0, poll_count = 0, flag_ccb, ccb_cdb_phy; 3402 int rtn, doneq_index, index_stripped, outbound_write_pointer, toggle; 3403 unsigned long flags; 3404 struct ARCMSR_CDB *arcmsr_cdb; 3405 struct CommandControlBlock *pCCB; 3406 struct MessageUnit_D *pmu = acb->pmuD; 3407 3408 polling_hbaD_ccb_retry: 3409 poll_count++; 3410 while (1) { 3411 spin_lock_irqsave(&acb->doneq_lock, flags); 3412 outbound_write_pointer = pmu->done_qbuffer[0].addressLow + 1; 3413 doneq_index = pmu->doneq_index; 3414 if ((outbound_write_pointer & 0xFFF) == (doneq_index & 0xFFF)) { 3415 spin_unlock_irqrestore(&acb->doneq_lock, flags); 3416 if (poll_ccb_done) { 3417 rtn = SUCCESS; 3418 break; 3419 } else { 3420 msleep(25); 3421 if (poll_count > 40) { 3422 rtn = FAILED; 3423 break; 3424 } 3425 goto polling_hbaD_ccb_retry; 3426 } 3427 } 3428 toggle = doneq_index & 0x4000; 3429 index_stripped = (doneq_index & 0xFFF) + 1; 3430 index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE; 3431 pmu->doneq_index = index_stripped ? (index_stripped | toggle) : 3432 ((toggle ^ 0x4000) + 1); 3433 doneq_index = pmu->doneq_index; 3434 spin_unlock_irqrestore(&acb->doneq_lock, flags); 3435 flag_ccb = pmu->done_qbuffer[doneq_index & 0xFFF].addressLow; 3436 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0); 3437 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + 3438 ccb_cdb_phy); 3439 pCCB = container_of(arcmsr_cdb, struct CommandControlBlock, 3440 arcmsr_cdb); 3441 poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0; 3442 if ((pCCB->acb != acb) || 3443 (pCCB->startdone != ARCMSR_CCB_START)) { 3444 if (pCCB->startdone == ARCMSR_CCB_ABORTED) { 3445 pr_notice("arcmsr%d: scsi id = %d " 3446 "lun = %d ccb = '0x%p' poll command " 3447 "abort successfully\n" 3448 , acb->host->host_no 3449 , pCCB->pcmd->device->id 3450 , (u32)pCCB->pcmd->device->lun 3451 , pCCB); 3452 pCCB->pcmd->result = DID_ABORT << 16; 3453 arcmsr_ccb_complete(pCCB); 3454 continue; 3455 } 3456 pr_notice("arcmsr%d: polling an illegal " 3457 "ccb command done ccb = '0x%p' " 3458 "ccboutstandingcount = %d\n" 3459 , acb->host->host_no 3460 , pCCB 3461 , atomic_read(&acb->ccboutstandingcount)); 3462 continue; 3463 } 3464 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) 3465 ? true : false; 3466 arcmsr_report_ccb_state(acb, pCCB, error); 3467 } 3468 return rtn; 3469 } 3470 3471 static int arcmsr_hbaE_polling_ccbdone(struct AdapterControlBlock *acb, 3472 struct CommandControlBlock *poll_ccb) 3473 { 3474 bool error; 3475 uint32_t poll_ccb_done = 0, poll_count = 0, doneq_index; 3476 uint16_t cmdSMID; 3477 unsigned long flags; 3478 int rtn; 3479 struct CommandControlBlock *pCCB; 3480 struct MessageUnit_E __iomem *reg = acb->pmuE; 3481 3482 polling_hbaC_ccb_retry: 3483 poll_count++; 3484 while (1) { 3485 spin_lock_irqsave(&acb->doneq_lock, flags); 3486 doneq_index = acb->doneq_index; 3487 if ((readl(®->reply_post_producer_index) & 0xFFFF) == 3488 doneq_index) { 3489 spin_unlock_irqrestore(&acb->doneq_lock, flags); 3490 if (poll_ccb_done) { 3491 rtn = SUCCESS; 3492 break; 3493 } else { 3494 msleep(25); 3495 if (poll_count > 40) { 3496 rtn = FAILED; 3497 break; 3498 } 3499 goto polling_hbaC_ccb_retry; 3500 } 3501 } 3502 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID; 3503 doneq_index++; 3504 if (doneq_index >= acb->completionQ_entry) 3505 doneq_index = 0; 3506 acb->doneq_index = doneq_index; 3507 spin_unlock_irqrestore(&acb->doneq_lock, flags); 3508 pCCB = acb->pccb_pool[cmdSMID]; 3509 poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0; 3510 /* check if command done with no error*/ 3511 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) { 3512 if (pCCB->startdone == ARCMSR_CCB_ABORTED) { 3513 pr_notice("arcmsr%d: scsi id = %d " 3514 "lun = %d ccb = '0x%p' poll command " 3515 "abort successfully\n" 3516 , acb->host->host_no 3517 , pCCB->pcmd->device->id 3518 , (u32)pCCB->pcmd->device->lun 3519 , pCCB); 3520 pCCB->pcmd->result = DID_ABORT << 16; 3521 arcmsr_ccb_complete(pCCB); 3522 continue; 3523 } 3524 pr_notice("arcmsr%d: polling an illegal " 3525 "ccb command done ccb = '0x%p' " 3526 "ccboutstandingcount = %d\n" 3527 , acb->host->host_no 3528 , pCCB 3529 , atomic_read(&acb->ccboutstandingcount)); 3530 continue; 3531 } 3532 error = (acb->pCompletionQ[doneq_index].cmdFlag & 3533 ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false; 3534 arcmsr_report_ccb_state(acb, pCCB, error); 3535 } 3536 writel(doneq_index, ®->reply_post_consumer_index); 3537 return rtn; 3538 } 3539 3540 static int arcmsr_polling_ccbdone(struct AdapterControlBlock *acb, 3541 struct CommandControlBlock *poll_ccb) 3542 { 3543 int rtn = 0; 3544 switch (acb->adapter_type) { 3545 3546 case ACB_ADAPTER_TYPE_A: { 3547 rtn = arcmsr_hbaA_polling_ccbdone(acb, poll_ccb); 3548 } 3549 break; 3550 3551 case ACB_ADAPTER_TYPE_B: { 3552 rtn = arcmsr_hbaB_polling_ccbdone(acb, poll_ccb); 3553 } 3554 break; 3555 case ACB_ADAPTER_TYPE_C: { 3556 rtn = arcmsr_hbaC_polling_ccbdone(acb, poll_ccb); 3557 } 3558 break; 3559 case ACB_ADAPTER_TYPE_D: 3560 rtn = arcmsr_hbaD_polling_ccbdone(acb, poll_ccb); 3561 break; 3562 case ACB_ADAPTER_TYPE_E: 3563 rtn = arcmsr_hbaE_polling_ccbdone(acb, poll_ccb); 3564 break; 3565 } 3566 return rtn; 3567 } 3568 3569 static void arcmsr_set_iop_datetime(struct timer_list *t) 3570 { 3571 struct AdapterControlBlock *pacb = from_timer(pacb, t, refresh_timer); 3572 unsigned int next_time; 3573 struct tm tm; 3574 3575 union { 3576 struct { 3577 uint16_t signature; 3578 uint8_t year; 3579 uint8_t month; 3580 uint8_t date; 3581 uint8_t hour; 3582 uint8_t minute; 3583 uint8_t second; 3584 } a; 3585 struct { 3586 uint32_t msg_time[2]; 3587 } b; 3588 } datetime; 3589 3590 time64_to_tm(ktime_get_real_seconds(), -sys_tz.tz_minuteswest * 60, &tm); 3591 3592 datetime.a.signature = 0x55AA; 3593 datetime.a.year = tm.tm_year - 100; /* base 2000 instead of 1900 */ 3594 datetime.a.month = tm.tm_mon; 3595 datetime.a.date = tm.tm_mday; 3596 datetime.a.hour = tm.tm_hour; 3597 datetime.a.minute = tm.tm_min; 3598 datetime.a.second = tm.tm_sec; 3599 3600 switch (pacb->adapter_type) { 3601 case ACB_ADAPTER_TYPE_A: { 3602 struct MessageUnit_A __iomem *reg = pacb->pmuA; 3603 writel(datetime.b.msg_time[0], ®->message_rwbuffer[0]); 3604 writel(datetime.b.msg_time[1], ®->message_rwbuffer[1]); 3605 writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, ®->inbound_msgaddr0); 3606 break; 3607 } 3608 case ACB_ADAPTER_TYPE_B: { 3609 uint32_t __iomem *rwbuffer; 3610 struct MessageUnit_B *reg = pacb->pmuB; 3611 rwbuffer = reg->message_rwbuffer; 3612 writel(datetime.b.msg_time[0], rwbuffer++); 3613 writel(datetime.b.msg_time[1], rwbuffer++); 3614 writel(ARCMSR_MESSAGE_SYNC_TIMER, reg->drv2iop_doorbell); 3615 break; 3616 } 3617 case ACB_ADAPTER_TYPE_C: { 3618 struct MessageUnit_C __iomem *reg = pacb->pmuC; 3619 writel(datetime.b.msg_time[0], ®->msgcode_rwbuffer[0]); 3620 writel(datetime.b.msg_time[1], ®->msgcode_rwbuffer[1]); 3621 writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, ®->inbound_msgaddr0); 3622 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell); 3623 break; 3624 } 3625 case ACB_ADAPTER_TYPE_D: { 3626 uint32_t __iomem *rwbuffer; 3627 struct MessageUnit_D *reg = pacb->pmuD; 3628 rwbuffer = reg->msgcode_rwbuffer; 3629 writel(datetime.b.msg_time[0], rwbuffer++); 3630 writel(datetime.b.msg_time[1], rwbuffer++); 3631 writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, reg->inbound_msgaddr0); 3632 break; 3633 } 3634 case ACB_ADAPTER_TYPE_E: { 3635 struct MessageUnit_E __iomem *reg = pacb->pmuE; 3636 writel(datetime.b.msg_time[0], ®->msgcode_rwbuffer[0]); 3637 writel(datetime.b.msg_time[1], ®->msgcode_rwbuffer[1]); 3638 writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, ®->inbound_msgaddr0); 3639 pacb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 3640 writel(pacb->out_doorbell, ®->iobound_doorbell); 3641 break; 3642 } 3643 } 3644 if (sys_tz.tz_minuteswest) 3645 next_time = ARCMSR_HOURS; 3646 else 3647 next_time = ARCMSR_MINUTES; 3648 mod_timer(&pacb->refresh_timer, jiffies + msecs_to_jiffies(next_time)); 3649 } 3650 3651 static int arcmsr_iop_confirm(struct AdapterControlBlock *acb) 3652 { 3653 uint32_t cdb_phyaddr, cdb_phyaddr_hi32; 3654 dma_addr_t dma_coherent_handle; 3655 3656 /* 3657 ******************************************************************** 3658 ** here we need to tell iop 331 our freeccb.HighPart 3659 ** if freeccb.HighPart is not zero 3660 ******************************************************************** 3661 */ 3662 switch (acb->adapter_type) { 3663 case ACB_ADAPTER_TYPE_B: 3664 case ACB_ADAPTER_TYPE_D: 3665 dma_coherent_handle = acb->dma_coherent_handle2; 3666 break; 3667 case ACB_ADAPTER_TYPE_E: 3668 dma_coherent_handle = acb->dma_coherent_handle + 3669 offsetof(struct CommandControlBlock, arcmsr_cdb); 3670 break; 3671 default: 3672 dma_coherent_handle = acb->dma_coherent_handle; 3673 break; 3674 } 3675 cdb_phyaddr = lower_32_bits(dma_coherent_handle); 3676 cdb_phyaddr_hi32 = upper_32_bits(dma_coherent_handle); 3677 acb->cdb_phyaddr_hi32 = cdb_phyaddr_hi32; 3678 /* 3679 *********************************************************************** 3680 ** if adapter type B, set window of "post command Q" 3681 *********************************************************************** 3682 */ 3683 switch (acb->adapter_type) { 3684 3685 case ACB_ADAPTER_TYPE_A: { 3686 if (cdb_phyaddr_hi32 != 0) { 3687 struct MessageUnit_A __iomem *reg = acb->pmuA; 3688 writel(ARCMSR_SIGNATURE_SET_CONFIG, \ 3689 ®->message_rwbuffer[0]); 3690 writel(cdb_phyaddr_hi32, ®->message_rwbuffer[1]); 3691 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, \ 3692 ®->inbound_msgaddr0); 3693 if (!arcmsr_hbaA_wait_msgint_ready(acb)) { 3694 printk(KERN_NOTICE "arcmsr%d: ""set ccb high \ 3695 part physical address timeout\n", 3696 acb->host->host_no); 3697 return 1; 3698 } 3699 } 3700 } 3701 break; 3702 3703 case ACB_ADAPTER_TYPE_B: { 3704 uint32_t __iomem *rwbuffer; 3705 3706 struct MessageUnit_B *reg = acb->pmuB; 3707 reg->postq_index = 0; 3708 reg->doneq_index = 0; 3709 writel(ARCMSR_MESSAGE_SET_POST_WINDOW, reg->drv2iop_doorbell); 3710 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 3711 printk(KERN_NOTICE "arcmsr%d: cannot set driver mode\n", \ 3712 acb->host->host_no); 3713 return 1; 3714 } 3715 rwbuffer = reg->message_rwbuffer; 3716 /* driver "set config" signature */ 3717 writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++); 3718 /* normal should be zero */ 3719 writel(cdb_phyaddr_hi32, rwbuffer++); 3720 /* postQ size (256 + 8)*4 */ 3721 writel(cdb_phyaddr, rwbuffer++); 3722 /* doneQ size (256 + 8)*4 */ 3723 writel(cdb_phyaddr + 1056, rwbuffer++); 3724 /* ccb maxQ size must be --> [(256 + 8)*4]*/ 3725 writel(1056, rwbuffer); 3726 3727 writel(ARCMSR_MESSAGE_SET_CONFIG, reg->drv2iop_doorbell); 3728 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 3729 printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \ 3730 timeout \n",acb->host->host_no); 3731 return 1; 3732 } 3733 writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell); 3734 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 3735 pr_err("arcmsr%d: can't set driver mode.\n", 3736 acb->host->host_no); 3737 return 1; 3738 } 3739 } 3740 break; 3741 case ACB_ADAPTER_TYPE_C: { 3742 if (cdb_phyaddr_hi32 != 0) { 3743 struct MessageUnit_C __iomem *reg = acb->pmuC; 3744 3745 printk(KERN_NOTICE "arcmsr%d: cdb_phyaddr_hi32=0x%x\n", 3746 acb->adapter_index, cdb_phyaddr_hi32); 3747 writel(ARCMSR_SIGNATURE_SET_CONFIG, ®->msgcode_rwbuffer[0]); 3748 writel(cdb_phyaddr_hi32, ®->msgcode_rwbuffer[1]); 3749 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, ®->inbound_msgaddr0); 3750 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell); 3751 if (!arcmsr_hbaC_wait_msgint_ready(acb)) { 3752 printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \ 3753 timeout \n", acb->host->host_no); 3754 return 1; 3755 } 3756 } 3757 } 3758 break; 3759 case ACB_ADAPTER_TYPE_D: { 3760 uint32_t __iomem *rwbuffer; 3761 struct MessageUnit_D *reg = acb->pmuD; 3762 reg->postq_index = 0; 3763 reg->doneq_index = 0; 3764 rwbuffer = reg->msgcode_rwbuffer; 3765 writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++); 3766 writel(cdb_phyaddr_hi32, rwbuffer++); 3767 writel(cdb_phyaddr, rwbuffer++); 3768 writel(cdb_phyaddr + (ARCMSR_MAX_ARC1214_POSTQUEUE * 3769 sizeof(struct InBound_SRB)), rwbuffer++); 3770 writel(0x100, rwbuffer); 3771 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, reg->inbound_msgaddr0); 3772 if (!arcmsr_hbaD_wait_msgint_ready(acb)) { 3773 pr_notice("arcmsr%d: 'set command Q window' timeout\n", 3774 acb->host->host_no); 3775 return 1; 3776 } 3777 } 3778 break; 3779 case ACB_ADAPTER_TYPE_E: { 3780 struct MessageUnit_E __iomem *reg = acb->pmuE; 3781 writel(ARCMSR_SIGNATURE_SET_CONFIG, ®->msgcode_rwbuffer[0]); 3782 writel(ARCMSR_SIGNATURE_1884, ®->msgcode_rwbuffer[1]); 3783 writel(cdb_phyaddr, ®->msgcode_rwbuffer[2]); 3784 writel(cdb_phyaddr_hi32, ®->msgcode_rwbuffer[3]); 3785 writel(acb->ccbsize, ®->msgcode_rwbuffer[4]); 3786 dma_coherent_handle = acb->dma_coherent_handle2; 3787 cdb_phyaddr = (uint32_t)(dma_coherent_handle & 0xffffffff); 3788 cdb_phyaddr_hi32 = (uint32_t)((dma_coherent_handle >> 16) >> 16); 3789 writel(cdb_phyaddr, ®->msgcode_rwbuffer[5]); 3790 writel(cdb_phyaddr_hi32, ®->msgcode_rwbuffer[6]); 3791 writel(acb->roundup_ccbsize, ®->msgcode_rwbuffer[7]); 3792 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, ®->inbound_msgaddr0); 3793 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 3794 writel(acb->out_doorbell, ®->iobound_doorbell); 3795 if (!arcmsr_hbaE_wait_msgint_ready(acb)) { 3796 pr_notice("arcmsr%d: 'set command Q window' timeout \n", 3797 acb->host->host_no); 3798 return 1; 3799 } 3800 } 3801 break; 3802 } 3803 return 0; 3804 } 3805 3806 static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb) 3807 { 3808 uint32_t firmware_state = 0; 3809 switch (acb->adapter_type) { 3810 3811 case ACB_ADAPTER_TYPE_A: { 3812 struct MessageUnit_A __iomem *reg = acb->pmuA; 3813 do { 3814 if (!(acb->acb_flags & ACB_F_IOP_INITED)) 3815 msleep(20); 3816 firmware_state = readl(®->outbound_msgaddr1); 3817 } while ((firmware_state & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0); 3818 } 3819 break; 3820 3821 case ACB_ADAPTER_TYPE_B: { 3822 struct MessageUnit_B *reg = acb->pmuB; 3823 do { 3824 if (!(acb->acb_flags & ACB_F_IOP_INITED)) 3825 msleep(20); 3826 firmware_state = readl(reg->iop2drv_doorbell); 3827 } while ((firmware_state & ARCMSR_MESSAGE_FIRMWARE_OK) == 0); 3828 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell); 3829 } 3830 break; 3831 case ACB_ADAPTER_TYPE_C: { 3832 struct MessageUnit_C __iomem *reg = acb->pmuC; 3833 do { 3834 if (!(acb->acb_flags & ACB_F_IOP_INITED)) 3835 msleep(20); 3836 firmware_state = readl(®->outbound_msgaddr1); 3837 } while ((firmware_state & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0); 3838 } 3839 break; 3840 case ACB_ADAPTER_TYPE_D: { 3841 struct MessageUnit_D *reg = acb->pmuD; 3842 do { 3843 if (!(acb->acb_flags & ACB_F_IOP_INITED)) 3844 msleep(20); 3845 firmware_state = readl(reg->outbound_msgaddr1); 3846 } while ((firmware_state & 3847 ARCMSR_ARC1214_MESSAGE_FIRMWARE_OK) == 0); 3848 } 3849 break; 3850 case ACB_ADAPTER_TYPE_E: { 3851 struct MessageUnit_E __iomem *reg = acb->pmuE; 3852 do { 3853 if (!(acb->acb_flags & ACB_F_IOP_INITED)) 3854 msleep(20); 3855 firmware_state = readl(®->outbound_msgaddr1); 3856 } while ((firmware_state & ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK) == 0); 3857 } 3858 break; 3859 } 3860 } 3861 3862 static void arcmsr_request_device_map(struct timer_list *t) 3863 { 3864 struct AdapterControlBlock *acb = from_timer(acb, t, eternal_timer); 3865 if (unlikely(atomic_read(&acb->rq_map_token) == 0) || 3866 (acb->acb_flags & ACB_F_BUS_RESET) || 3867 (acb->acb_flags & ACB_F_ABORT)) { 3868 mod_timer(&acb->eternal_timer, 3869 jiffies + msecs_to_jiffies(6 * HZ)); 3870 } else { 3871 acb->fw_flag = FW_NORMAL; 3872 if (atomic_read(&acb->ante_token_value) == 3873 atomic_read(&acb->rq_map_token)) { 3874 atomic_set(&acb->rq_map_token, 16); 3875 } 3876 atomic_set(&acb->ante_token_value, 3877 atomic_read(&acb->rq_map_token)); 3878 if (atomic_dec_and_test(&acb->rq_map_token)) { 3879 mod_timer(&acb->eternal_timer, jiffies + 3880 msecs_to_jiffies(6 * HZ)); 3881 return; 3882 } 3883 switch (acb->adapter_type) { 3884 case ACB_ADAPTER_TYPE_A: { 3885 struct MessageUnit_A __iomem *reg = acb->pmuA; 3886 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0); 3887 break; 3888 } 3889 case ACB_ADAPTER_TYPE_B: { 3890 struct MessageUnit_B *reg = acb->pmuB; 3891 writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell); 3892 break; 3893 } 3894 case ACB_ADAPTER_TYPE_C: { 3895 struct MessageUnit_C __iomem *reg = acb->pmuC; 3896 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0); 3897 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell); 3898 break; 3899 } 3900 case ACB_ADAPTER_TYPE_D: { 3901 struct MessageUnit_D *reg = acb->pmuD; 3902 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, reg->inbound_msgaddr0); 3903 break; 3904 } 3905 case ACB_ADAPTER_TYPE_E: { 3906 struct MessageUnit_E __iomem *reg = acb->pmuE; 3907 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0); 3908 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 3909 writel(acb->out_doorbell, ®->iobound_doorbell); 3910 break; 3911 } 3912 default: 3913 return; 3914 } 3915 acb->acb_flags |= ACB_F_MSG_GET_CONFIG; 3916 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ)); 3917 } 3918 } 3919 3920 static void arcmsr_hbaA_start_bgrb(struct AdapterControlBlock *acb) 3921 { 3922 struct MessageUnit_A __iomem *reg = acb->pmuA; 3923 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3924 writel(ARCMSR_INBOUND_MESG0_START_BGRB, ®->inbound_msgaddr0); 3925 if (!arcmsr_hbaA_wait_msgint_ready(acb)) { 3926 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \ 3927 rebuild' timeout \n", acb->host->host_no); 3928 } 3929 } 3930 3931 static void arcmsr_hbaB_start_bgrb(struct AdapterControlBlock *acb) 3932 { 3933 struct MessageUnit_B *reg = acb->pmuB; 3934 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3935 writel(ARCMSR_MESSAGE_START_BGRB, reg->drv2iop_doorbell); 3936 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 3937 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \ 3938 rebuild' timeout \n",acb->host->host_no); 3939 } 3940 } 3941 3942 static void arcmsr_hbaC_start_bgrb(struct AdapterControlBlock *pACB) 3943 { 3944 struct MessageUnit_C __iomem *phbcmu = pACB->pmuC; 3945 pACB->acb_flags |= ACB_F_MSG_START_BGRB; 3946 writel(ARCMSR_INBOUND_MESG0_START_BGRB, &phbcmu->inbound_msgaddr0); 3947 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &phbcmu->inbound_doorbell); 3948 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) { 3949 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \ 3950 rebuild' timeout \n", pACB->host->host_no); 3951 } 3952 return; 3953 } 3954 3955 static void arcmsr_hbaD_start_bgrb(struct AdapterControlBlock *pACB) 3956 { 3957 struct MessageUnit_D *pmu = pACB->pmuD; 3958 3959 pACB->acb_flags |= ACB_F_MSG_START_BGRB; 3960 writel(ARCMSR_INBOUND_MESG0_START_BGRB, pmu->inbound_msgaddr0); 3961 if (!arcmsr_hbaD_wait_msgint_ready(pACB)) { 3962 pr_notice("arcmsr%d: wait 'start adapter " 3963 "background rebuild' timeout\n", pACB->host->host_no); 3964 } 3965 } 3966 3967 static void arcmsr_hbaE_start_bgrb(struct AdapterControlBlock *pACB) 3968 { 3969 struct MessageUnit_E __iomem *pmu = pACB->pmuE; 3970 3971 pACB->acb_flags |= ACB_F_MSG_START_BGRB; 3972 writel(ARCMSR_INBOUND_MESG0_START_BGRB, &pmu->inbound_msgaddr0); 3973 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 3974 writel(pACB->out_doorbell, &pmu->iobound_doorbell); 3975 if (!arcmsr_hbaE_wait_msgint_ready(pACB)) { 3976 pr_notice("arcmsr%d: wait 'start adapter " 3977 "background rebuild' timeout \n", pACB->host->host_no); 3978 } 3979 } 3980 3981 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb) 3982 { 3983 switch (acb->adapter_type) { 3984 case ACB_ADAPTER_TYPE_A: 3985 arcmsr_hbaA_start_bgrb(acb); 3986 break; 3987 case ACB_ADAPTER_TYPE_B: 3988 arcmsr_hbaB_start_bgrb(acb); 3989 break; 3990 case ACB_ADAPTER_TYPE_C: 3991 arcmsr_hbaC_start_bgrb(acb); 3992 break; 3993 case ACB_ADAPTER_TYPE_D: 3994 arcmsr_hbaD_start_bgrb(acb); 3995 break; 3996 case ACB_ADAPTER_TYPE_E: 3997 arcmsr_hbaE_start_bgrb(acb); 3998 break; 3999 } 4000 } 4001 4002 static void arcmsr_clear_doorbell_queue_buffer(struct AdapterControlBlock *acb) 4003 { 4004 switch (acb->adapter_type) { 4005 case ACB_ADAPTER_TYPE_A: { 4006 struct MessageUnit_A __iomem *reg = acb->pmuA; 4007 uint32_t outbound_doorbell; 4008 /* empty doorbell Qbuffer if door bell ringed */ 4009 outbound_doorbell = readl(®->outbound_doorbell); 4010 /*clear doorbell interrupt */ 4011 writel(outbound_doorbell, ®->outbound_doorbell); 4012 writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, ®->inbound_doorbell); 4013 } 4014 break; 4015 4016 case ACB_ADAPTER_TYPE_B: { 4017 struct MessageUnit_B *reg = acb->pmuB; 4018 uint32_t outbound_doorbell, i; 4019 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); 4020 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell); 4021 /* let IOP know data has been read */ 4022 for(i=0; i < 200; i++) { 4023 msleep(20); 4024 outbound_doorbell = readl(reg->iop2drv_doorbell); 4025 if( outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) { 4026 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); 4027 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell); 4028 } else 4029 break; 4030 } 4031 } 4032 break; 4033 case ACB_ADAPTER_TYPE_C: { 4034 struct MessageUnit_C __iomem *reg = acb->pmuC; 4035 uint32_t outbound_doorbell, i; 4036 /* empty doorbell Qbuffer if door bell ringed */ 4037 outbound_doorbell = readl(®->outbound_doorbell); 4038 writel(outbound_doorbell, ®->outbound_doorbell_clear); 4039 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, ®->inbound_doorbell); 4040 for (i = 0; i < 200; i++) { 4041 msleep(20); 4042 outbound_doorbell = readl(®->outbound_doorbell); 4043 if (outbound_doorbell & 4044 ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) { 4045 writel(outbound_doorbell, 4046 ®->outbound_doorbell_clear); 4047 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, 4048 ®->inbound_doorbell); 4049 } else 4050 break; 4051 } 4052 } 4053 break; 4054 case ACB_ADAPTER_TYPE_D: { 4055 struct MessageUnit_D *reg = acb->pmuD; 4056 uint32_t outbound_doorbell, i; 4057 /* empty doorbell Qbuffer if door bell ringed */ 4058 outbound_doorbell = readl(reg->outbound_doorbell); 4059 writel(outbound_doorbell, reg->outbound_doorbell); 4060 writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ, 4061 reg->inbound_doorbell); 4062 for (i = 0; i < 200; i++) { 4063 msleep(20); 4064 outbound_doorbell = readl(reg->outbound_doorbell); 4065 if (outbound_doorbell & 4066 ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK) { 4067 writel(outbound_doorbell, 4068 reg->outbound_doorbell); 4069 writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ, 4070 reg->inbound_doorbell); 4071 } else 4072 break; 4073 } 4074 } 4075 break; 4076 case ACB_ADAPTER_TYPE_E: { 4077 struct MessageUnit_E __iomem *reg = acb->pmuE; 4078 uint32_t i, tmp; 4079 4080 acb->in_doorbell = readl(®->iobound_doorbell); 4081 writel(0, ®->host_int_status); /*clear interrupt*/ 4082 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK; 4083 writel(acb->out_doorbell, ®->iobound_doorbell); 4084 for(i=0; i < 200; i++) { 4085 msleep(20); 4086 tmp = acb->in_doorbell; 4087 acb->in_doorbell = readl(®->iobound_doorbell); 4088 if((tmp ^ acb->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) { 4089 writel(0, ®->host_int_status); /*clear interrupt*/ 4090 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK; 4091 writel(acb->out_doorbell, ®->iobound_doorbell); 4092 } else 4093 break; 4094 } 4095 } 4096 break; 4097 } 4098 } 4099 4100 static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb) 4101 { 4102 switch (acb->adapter_type) { 4103 case ACB_ADAPTER_TYPE_A: 4104 return; 4105 case ACB_ADAPTER_TYPE_B: 4106 { 4107 struct MessageUnit_B *reg = acb->pmuB; 4108 writel(ARCMSR_MESSAGE_ACTIVE_EOI_MODE, reg->drv2iop_doorbell); 4109 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 4110 printk(KERN_NOTICE "ARCMSR IOP enables EOI_MODE TIMEOUT"); 4111 return; 4112 } 4113 } 4114 break; 4115 case ACB_ADAPTER_TYPE_C: 4116 return; 4117 } 4118 return; 4119 } 4120 4121 static void arcmsr_hardware_reset(struct AdapterControlBlock *acb) 4122 { 4123 uint8_t value[64]; 4124 int i, count = 0; 4125 struct MessageUnit_A __iomem *pmuA = acb->pmuA; 4126 struct MessageUnit_C __iomem *pmuC = acb->pmuC; 4127 struct MessageUnit_D *pmuD = acb->pmuD; 4128 4129 /* backup pci config data */ 4130 printk(KERN_NOTICE "arcmsr%d: executing hw bus reset .....\n", acb->host->host_no); 4131 for (i = 0; i < 64; i++) { 4132 pci_read_config_byte(acb->pdev, i, &value[i]); 4133 } 4134 /* hardware reset signal */ 4135 if (acb->dev_id == 0x1680) { 4136 writel(ARCMSR_ARC1680_BUS_RESET, &pmuA->reserved1[0]); 4137 } else if (acb->dev_id == 0x1880) { 4138 do { 4139 count++; 4140 writel(0xF, &pmuC->write_sequence); 4141 writel(0x4, &pmuC->write_sequence); 4142 writel(0xB, &pmuC->write_sequence); 4143 writel(0x2, &pmuC->write_sequence); 4144 writel(0x7, &pmuC->write_sequence); 4145 writel(0xD, &pmuC->write_sequence); 4146 } while (((readl(&pmuC->host_diagnostic) & ARCMSR_ARC1880_DiagWrite_ENABLE) == 0) && (count < 5)); 4147 writel(ARCMSR_ARC1880_RESET_ADAPTER, &pmuC->host_diagnostic); 4148 } else if (acb->dev_id == 0x1884) { 4149 struct MessageUnit_E __iomem *pmuE = acb->pmuE; 4150 do { 4151 count++; 4152 writel(0x4, &pmuE->write_sequence_3xxx); 4153 writel(0xB, &pmuE->write_sequence_3xxx); 4154 writel(0x2, &pmuE->write_sequence_3xxx); 4155 writel(0x7, &pmuE->write_sequence_3xxx); 4156 writel(0xD, &pmuE->write_sequence_3xxx); 4157 mdelay(10); 4158 } while (((readl(&pmuE->host_diagnostic_3xxx) & 4159 ARCMSR_ARC1884_DiagWrite_ENABLE) == 0) && (count < 5)); 4160 writel(ARCMSR_ARC188X_RESET_ADAPTER, &pmuE->host_diagnostic_3xxx); 4161 } else if (acb->dev_id == 0x1214) { 4162 writel(0x20, pmuD->reset_request); 4163 } else { 4164 pci_write_config_byte(acb->pdev, 0x84, 0x20); 4165 } 4166 msleep(2000); 4167 /* write back pci config data */ 4168 for (i = 0; i < 64; i++) { 4169 pci_write_config_byte(acb->pdev, i, value[i]); 4170 } 4171 msleep(1000); 4172 return; 4173 } 4174 4175 static bool arcmsr_reset_in_progress(struct AdapterControlBlock *acb) 4176 { 4177 bool rtn = true; 4178 4179 switch(acb->adapter_type) { 4180 case ACB_ADAPTER_TYPE_A:{ 4181 struct MessageUnit_A __iomem *reg = acb->pmuA; 4182 rtn = ((readl(®->outbound_msgaddr1) & 4183 ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) ? true : false; 4184 } 4185 break; 4186 case ACB_ADAPTER_TYPE_B:{ 4187 struct MessageUnit_B *reg = acb->pmuB; 4188 rtn = ((readl(reg->iop2drv_doorbell) & 4189 ARCMSR_MESSAGE_FIRMWARE_OK) == 0) ? true : false; 4190 } 4191 break; 4192 case ACB_ADAPTER_TYPE_C:{ 4193 struct MessageUnit_C __iomem *reg = acb->pmuC; 4194 rtn = (readl(®->host_diagnostic) & 0x04) ? true : false; 4195 } 4196 break; 4197 case ACB_ADAPTER_TYPE_D:{ 4198 struct MessageUnit_D *reg = acb->pmuD; 4199 rtn = ((readl(reg->sample_at_reset) & 0x80) == 0) ? 4200 true : false; 4201 } 4202 break; 4203 case ACB_ADAPTER_TYPE_E:{ 4204 struct MessageUnit_E __iomem *reg = acb->pmuE; 4205 rtn = (readl(®->host_diagnostic_3xxx) & 4206 ARCMSR_ARC188X_RESET_ADAPTER) ? true : false; 4207 } 4208 break; 4209 } 4210 return rtn; 4211 } 4212 4213 static void arcmsr_iop_init(struct AdapterControlBlock *acb) 4214 { 4215 uint32_t intmask_org; 4216 /* disable all outbound interrupt */ 4217 intmask_org = arcmsr_disable_outbound_ints(acb); 4218 arcmsr_wait_firmware_ready(acb); 4219 arcmsr_iop_confirm(acb); 4220 /*start background rebuild*/ 4221 arcmsr_start_adapter_bgrb(acb); 4222 /* empty doorbell Qbuffer if door bell ringed */ 4223 arcmsr_clear_doorbell_queue_buffer(acb); 4224 arcmsr_enable_eoi_mode(acb); 4225 /* enable outbound Post Queue,outbound doorbell Interrupt */ 4226 arcmsr_enable_outbound_ints(acb, intmask_org); 4227 acb->acb_flags |= ACB_F_IOP_INITED; 4228 } 4229 4230 static uint8_t arcmsr_iop_reset(struct AdapterControlBlock *acb) 4231 { 4232 struct CommandControlBlock *ccb; 4233 uint32_t intmask_org; 4234 uint8_t rtnval = 0x00; 4235 int i = 0; 4236 unsigned long flags; 4237 4238 if (atomic_read(&acb->ccboutstandingcount) != 0) { 4239 /* disable all outbound interrupt */ 4240 intmask_org = arcmsr_disable_outbound_ints(acb); 4241 /* talk to iop 331 outstanding command aborted */ 4242 rtnval = arcmsr_abort_allcmd(acb); 4243 /* clear all outbound posted Q */ 4244 arcmsr_done4abort_postqueue(acb); 4245 for (i = 0; i < acb->maxFreeCCB; i++) { 4246 ccb = acb->pccb_pool[i]; 4247 if (ccb->startdone == ARCMSR_CCB_START) { 4248 scsi_dma_unmap(ccb->pcmd); 4249 ccb->startdone = ARCMSR_CCB_DONE; 4250 ccb->ccb_flags = 0; 4251 spin_lock_irqsave(&acb->ccblist_lock, flags); 4252 list_add_tail(&ccb->list, &acb->ccb_free_list); 4253 spin_unlock_irqrestore(&acb->ccblist_lock, flags); 4254 } 4255 } 4256 atomic_set(&acb->ccboutstandingcount, 0); 4257 /* enable all outbound interrupt */ 4258 arcmsr_enable_outbound_ints(acb, intmask_org); 4259 return rtnval; 4260 } 4261 return rtnval; 4262 } 4263 4264 static int arcmsr_bus_reset(struct scsi_cmnd *cmd) 4265 { 4266 struct AdapterControlBlock *acb; 4267 int retry_count = 0; 4268 int rtn = FAILED; 4269 acb = (struct AdapterControlBlock *) cmd->device->host->hostdata; 4270 if (acb->acb_flags & ACB_F_ADAPTER_REMOVED) 4271 return SUCCESS; 4272 pr_notice("arcmsr: executing bus reset eh.....num_resets = %d," 4273 " num_aborts = %d \n", acb->num_resets, acb->num_aborts); 4274 acb->num_resets++; 4275 4276 if (acb->acb_flags & ACB_F_BUS_RESET) { 4277 long timeout; 4278 pr_notice("arcmsr: there is a bus reset eh proceeding...\n"); 4279 timeout = wait_event_timeout(wait_q, (acb->acb_flags 4280 & ACB_F_BUS_RESET) == 0, 220 * HZ); 4281 if (timeout) 4282 return SUCCESS; 4283 } 4284 acb->acb_flags |= ACB_F_BUS_RESET; 4285 if (!arcmsr_iop_reset(acb)) { 4286 arcmsr_hardware_reset(acb); 4287 acb->acb_flags &= ~ACB_F_IOP_INITED; 4288 wait_reset_done: 4289 ssleep(ARCMSR_SLEEPTIME); 4290 if (arcmsr_reset_in_progress(acb)) { 4291 if (retry_count > ARCMSR_RETRYCOUNT) { 4292 acb->fw_flag = FW_DEADLOCK; 4293 pr_notice("arcmsr%d: waiting for hw bus reset" 4294 " return, RETRY TERMINATED!!\n", 4295 acb->host->host_no); 4296 return FAILED; 4297 } 4298 retry_count++; 4299 goto wait_reset_done; 4300 } 4301 arcmsr_iop_init(acb); 4302 atomic_set(&acb->rq_map_token, 16); 4303 atomic_set(&acb->ante_token_value, 16); 4304 acb->fw_flag = FW_NORMAL; 4305 mod_timer(&acb->eternal_timer, jiffies + 4306 msecs_to_jiffies(6 * HZ)); 4307 acb->acb_flags &= ~ACB_F_BUS_RESET; 4308 rtn = SUCCESS; 4309 pr_notice("arcmsr: scsi bus reset eh returns with success\n"); 4310 } else { 4311 acb->acb_flags &= ~ACB_F_BUS_RESET; 4312 atomic_set(&acb->rq_map_token, 16); 4313 atomic_set(&acb->ante_token_value, 16); 4314 acb->fw_flag = FW_NORMAL; 4315 mod_timer(&acb->eternal_timer, jiffies + 4316 msecs_to_jiffies(6 * HZ)); 4317 rtn = SUCCESS; 4318 } 4319 return rtn; 4320 } 4321 4322 static int arcmsr_abort_one_cmd(struct AdapterControlBlock *acb, 4323 struct CommandControlBlock *ccb) 4324 { 4325 int rtn; 4326 rtn = arcmsr_polling_ccbdone(acb, ccb); 4327 return rtn; 4328 } 4329 4330 static int arcmsr_abort(struct scsi_cmnd *cmd) 4331 { 4332 struct AdapterControlBlock *acb = 4333 (struct AdapterControlBlock *)cmd->device->host->hostdata; 4334 int i = 0; 4335 int rtn = FAILED; 4336 uint32_t intmask_org; 4337 4338 if (acb->acb_flags & ACB_F_ADAPTER_REMOVED) 4339 return SUCCESS; 4340 printk(KERN_NOTICE 4341 "arcmsr%d: abort device command of scsi id = %d lun = %d\n", 4342 acb->host->host_no, cmd->device->id, (u32)cmd->device->lun); 4343 acb->acb_flags |= ACB_F_ABORT; 4344 acb->num_aborts++; 4345 /* 4346 ************************************************ 4347 ** the all interrupt service routine is locked 4348 ** we need to handle it as soon as possible and exit 4349 ************************************************ 4350 */ 4351 if (!atomic_read(&acb->ccboutstandingcount)) { 4352 acb->acb_flags &= ~ACB_F_ABORT; 4353 return rtn; 4354 } 4355 4356 intmask_org = arcmsr_disable_outbound_ints(acb); 4357 for (i = 0; i < acb->maxFreeCCB; i++) { 4358 struct CommandControlBlock *ccb = acb->pccb_pool[i]; 4359 if (ccb->startdone == ARCMSR_CCB_START && ccb->pcmd == cmd) { 4360 ccb->startdone = ARCMSR_CCB_ABORTED; 4361 rtn = arcmsr_abort_one_cmd(acb, ccb); 4362 break; 4363 } 4364 } 4365 acb->acb_flags &= ~ACB_F_ABORT; 4366 arcmsr_enable_outbound_ints(acb, intmask_org); 4367 return rtn; 4368 } 4369 4370 static const char *arcmsr_info(struct Scsi_Host *host) 4371 { 4372 struct AdapterControlBlock *acb = 4373 (struct AdapterControlBlock *) host->hostdata; 4374 static char buf[256]; 4375 char *type; 4376 int raid6 = 1; 4377 switch (acb->pdev->device) { 4378 case PCI_DEVICE_ID_ARECA_1110: 4379 case PCI_DEVICE_ID_ARECA_1200: 4380 case PCI_DEVICE_ID_ARECA_1202: 4381 case PCI_DEVICE_ID_ARECA_1210: 4382 raid6 = 0; 4383 /*FALLTHRU*/ 4384 case PCI_DEVICE_ID_ARECA_1120: 4385 case PCI_DEVICE_ID_ARECA_1130: 4386 case PCI_DEVICE_ID_ARECA_1160: 4387 case PCI_DEVICE_ID_ARECA_1170: 4388 case PCI_DEVICE_ID_ARECA_1201: 4389 case PCI_DEVICE_ID_ARECA_1203: 4390 case PCI_DEVICE_ID_ARECA_1220: 4391 case PCI_DEVICE_ID_ARECA_1230: 4392 case PCI_DEVICE_ID_ARECA_1260: 4393 case PCI_DEVICE_ID_ARECA_1270: 4394 case PCI_DEVICE_ID_ARECA_1280: 4395 type = "SATA"; 4396 break; 4397 case PCI_DEVICE_ID_ARECA_1214: 4398 case PCI_DEVICE_ID_ARECA_1380: 4399 case PCI_DEVICE_ID_ARECA_1381: 4400 case PCI_DEVICE_ID_ARECA_1680: 4401 case PCI_DEVICE_ID_ARECA_1681: 4402 case PCI_DEVICE_ID_ARECA_1880: 4403 case PCI_DEVICE_ID_ARECA_1884: 4404 type = "SAS/SATA"; 4405 break; 4406 default: 4407 type = "unknown"; 4408 raid6 = 0; 4409 break; 4410 } 4411 sprintf(buf, "Areca %s RAID Controller %s\narcmsr version %s\n", 4412 type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION); 4413 return buf; 4414 } 4415