1 /* 2 ******************************************************************************* 3 ** O.S : Linux 4 ** FILE NAME : arcmsr_hba.c 5 ** BY : Nick Cheng, C.L. Huang 6 ** Description: SCSI RAID Device Driver for Areca RAID Controller 7 ******************************************************************************* 8 ** Copyright (C) 2002 - 2014, Areca Technology Corporation All rights reserved 9 ** 10 ** Web site: www.areca.com.tw 11 ** E-mail: support@areca.com.tw 12 ** 13 ** This program is free software; you can redistribute it and/or modify 14 ** it under the terms of the GNU General Public License version 2 as 15 ** published by the Free Software Foundation. 16 ** This program is distributed in the hope that it will be useful, 17 ** but WITHOUT ANY WARRANTY; without even the implied warranty of 18 ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 ** GNU General Public License for more details. 20 ******************************************************************************* 21 ** Redistribution and use in source and binary forms, with or without 22 ** modification, are permitted provided that the following conditions 23 ** are met: 24 ** 1. Redistributions of source code must retain the above copyright 25 ** notice, this list of conditions and the following disclaimer. 26 ** 2. Redistributions in binary form must reproduce the above copyright 27 ** notice, this list of conditions and the following disclaimer in the 28 ** documentation and/or other materials provided with the distribution. 29 ** 3. The name of the author may not be used to endorse or promote products 30 ** derived from this software without specific prior written permission. 31 ** 32 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 33 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 34 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 35 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 36 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT 37 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 38 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 39 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 40 ** (INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 41 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 ******************************************************************************* 43 ** For history of changes, see Documentation/scsi/ChangeLog.arcmsr 44 ** Firmware Specification, see Documentation/scsi/arcmsr_spec.txt 45 ******************************************************************************* 46 */ 47 #include <linux/module.h> 48 #include <linux/reboot.h> 49 #include <linux/spinlock.h> 50 #include <linux/pci_ids.h> 51 #include <linux/interrupt.h> 52 #include <linux/moduleparam.h> 53 #include <linux/errno.h> 54 #include <linux/types.h> 55 #include <linux/delay.h> 56 #include <linux/dma-mapping.h> 57 #include <linux/timer.h> 58 #include <linux/slab.h> 59 #include <linux/pci.h> 60 #include <linux/aer.h> 61 #include <linux/circ_buf.h> 62 #include <asm/dma.h> 63 #include <asm/io.h> 64 #include <linux/uaccess.h> 65 #include <scsi/scsi_host.h> 66 #include <scsi/scsi.h> 67 #include <scsi/scsi_cmnd.h> 68 #include <scsi/scsi_tcq.h> 69 #include <scsi/scsi_device.h> 70 #include <scsi/scsi_transport.h> 71 #include <scsi/scsicam.h> 72 #include "arcmsr.h" 73 MODULE_AUTHOR("Nick Cheng, C.L. Huang <support@areca.com.tw>"); 74 MODULE_DESCRIPTION("Areca ARC11xx/12xx/16xx/188x SAS/SATA RAID Controller Driver"); 75 MODULE_LICENSE("Dual BSD/GPL"); 76 MODULE_VERSION(ARCMSR_DRIVER_VERSION); 77 78 static int msix_enable = 1; 79 module_param(msix_enable, int, S_IRUGO); 80 MODULE_PARM_DESC(msix_enable, "Enable MSI-X interrupt(0 ~ 1), msix_enable=1(enable), =0(disable)"); 81 82 static int msi_enable = 1; 83 module_param(msi_enable, int, S_IRUGO); 84 MODULE_PARM_DESC(msi_enable, "Enable MSI interrupt(0 ~ 1), msi_enable=1(enable), =0(disable)"); 85 86 static int host_can_queue = ARCMSR_DEFAULT_OUTSTANDING_CMD; 87 module_param(host_can_queue, int, S_IRUGO); 88 MODULE_PARM_DESC(host_can_queue, " adapter queue depth(32 ~ 1024), default is 128"); 89 90 static int cmd_per_lun = ARCMSR_DEFAULT_CMD_PERLUN; 91 module_param(cmd_per_lun, int, S_IRUGO); 92 MODULE_PARM_DESC(cmd_per_lun, " device queue depth(1 ~ 128), default is 32"); 93 94 static int set_date_time = 0; 95 module_param(set_date_time, int, S_IRUGO); 96 MODULE_PARM_DESC(set_date_time, " send date, time to iop(0 ~ 1), set_date_time=1(enable), default(=0) is disable"); 97 98 #define ARCMSR_SLEEPTIME 10 99 #define ARCMSR_RETRYCOUNT 12 100 101 static wait_queue_head_t wait_q; 102 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, 103 struct scsi_cmnd *cmd); 104 static int arcmsr_iop_confirm(struct AdapterControlBlock *acb); 105 static int arcmsr_abort(struct scsi_cmnd *); 106 static int arcmsr_bus_reset(struct scsi_cmnd *); 107 static int arcmsr_bios_param(struct scsi_device *sdev, 108 struct block_device *bdev, sector_t capacity, int *info); 109 static int arcmsr_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd); 110 static int arcmsr_probe(struct pci_dev *pdev, 111 const struct pci_device_id *id); 112 static int arcmsr_suspend(struct pci_dev *pdev, pm_message_t state); 113 static int arcmsr_resume(struct pci_dev *pdev); 114 static void arcmsr_remove(struct pci_dev *pdev); 115 static void arcmsr_shutdown(struct pci_dev *pdev); 116 static void arcmsr_iop_init(struct AdapterControlBlock *acb); 117 static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb); 118 static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb); 119 static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb, 120 u32 intmask_org); 121 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb); 122 static void arcmsr_hbaA_flush_cache(struct AdapterControlBlock *acb); 123 static void arcmsr_hbaB_flush_cache(struct AdapterControlBlock *acb); 124 static void arcmsr_request_device_map(struct timer_list *t); 125 static void arcmsr_message_isr_bh_fn(struct work_struct *work); 126 static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb); 127 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb); 128 static void arcmsr_hbaC_message_isr(struct AdapterControlBlock *pACB); 129 static void arcmsr_hbaD_message_isr(struct AdapterControlBlock *acb); 130 static void arcmsr_hbaE_message_isr(struct AdapterControlBlock *acb); 131 static void arcmsr_hbaE_postqueue_isr(struct AdapterControlBlock *acb); 132 static void arcmsr_hardware_reset(struct AdapterControlBlock *acb); 133 static const char *arcmsr_info(struct Scsi_Host *); 134 static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb); 135 static void arcmsr_free_irq(struct pci_dev *, struct AdapterControlBlock *); 136 static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb); 137 static void arcmsr_set_iop_datetime(struct timer_list *); 138 static int arcmsr_adjust_disk_queue_depth(struct scsi_device *sdev, int queue_depth) 139 { 140 if (queue_depth > ARCMSR_MAX_CMD_PERLUN) 141 queue_depth = ARCMSR_MAX_CMD_PERLUN; 142 return scsi_change_queue_depth(sdev, queue_depth); 143 } 144 145 static struct scsi_host_template arcmsr_scsi_host_template = { 146 .module = THIS_MODULE, 147 .name = "Areca SAS/SATA RAID driver", 148 .info = arcmsr_info, 149 .queuecommand = arcmsr_queue_command, 150 .eh_abort_handler = arcmsr_abort, 151 .eh_bus_reset_handler = arcmsr_bus_reset, 152 .bios_param = arcmsr_bios_param, 153 .change_queue_depth = arcmsr_adjust_disk_queue_depth, 154 .can_queue = ARCMSR_DEFAULT_OUTSTANDING_CMD, 155 .this_id = ARCMSR_SCSI_INITIATOR_ID, 156 .sg_tablesize = ARCMSR_DEFAULT_SG_ENTRIES, 157 .max_sectors = ARCMSR_MAX_XFER_SECTORS_C, 158 .cmd_per_lun = ARCMSR_DEFAULT_CMD_PERLUN, 159 .shost_attrs = arcmsr_host_attrs, 160 .no_write_same = 1, 161 }; 162 163 static struct pci_device_id arcmsr_device_id_table[] = { 164 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1110), 165 .driver_data = ACB_ADAPTER_TYPE_A}, 166 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1120), 167 .driver_data = ACB_ADAPTER_TYPE_A}, 168 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1130), 169 .driver_data = ACB_ADAPTER_TYPE_A}, 170 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1160), 171 .driver_data = ACB_ADAPTER_TYPE_A}, 172 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1170), 173 .driver_data = ACB_ADAPTER_TYPE_A}, 174 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1200), 175 .driver_data = ACB_ADAPTER_TYPE_B}, 176 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1201), 177 .driver_data = ACB_ADAPTER_TYPE_B}, 178 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1202), 179 .driver_data = ACB_ADAPTER_TYPE_B}, 180 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1203), 181 .driver_data = ACB_ADAPTER_TYPE_B}, 182 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1210), 183 .driver_data = ACB_ADAPTER_TYPE_A}, 184 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1214), 185 .driver_data = ACB_ADAPTER_TYPE_D}, 186 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1220), 187 .driver_data = ACB_ADAPTER_TYPE_A}, 188 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1230), 189 .driver_data = ACB_ADAPTER_TYPE_A}, 190 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1260), 191 .driver_data = ACB_ADAPTER_TYPE_A}, 192 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1270), 193 .driver_data = ACB_ADAPTER_TYPE_A}, 194 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1280), 195 .driver_data = ACB_ADAPTER_TYPE_A}, 196 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1380), 197 .driver_data = ACB_ADAPTER_TYPE_A}, 198 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1381), 199 .driver_data = ACB_ADAPTER_TYPE_A}, 200 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1680), 201 .driver_data = ACB_ADAPTER_TYPE_A}, 202 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1681), 203 .driver_data = ACB_ADAPTER_TYPE_A}, 204 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1880), 205 .driver_data = ACB_ADAPTER_TYPE_C}, 206 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1884), 207 .driver_data = ACB_ADAPTER_TYPE_E}, 208 {0, 0}, /* Terminating entry */ 209 }; 210 MODULE_DEVICE_TABLE(pci, arcmsr_device_id_table); 211 212 static struct pci_driver arcmsr_pci_driver = { 213 .name = "arcmsr", 214 .id_table = arcmsr_device_id_table, 215 .probe = arcmsr_probe, 216 .remove = arcmsr_remove, 217 .suspend = arcmsr_suspend, 218 .resume = arcmsr_resume, 219 .shutdown = arcmsr_shutdown, 220 }; 221 /* 222 **************************************************************************** 223 **************************************************************************** 224 */ 225 226 static void arcmsr_free_mu(struct AdapterControlBlock *acb) 227 { 228 switch (acb->adapter_type) { 229 case ACB_ADAPTER_TYPE_B: 230 case ACB_ADAPTER_TYPE_D: 231 case ACB_ADAPTER_TYPE_E: { 232 dma_free_coherent(&acb->pdev->dev, acb->roundup_ccbsize, 233 acb->dma_coherent2, acb->dma_coherent_handle2); 234 break; 235 } 236 } 237 } 238 239 static bool arcmsr_remap_pciregion(struct AdapterControlBlock *acb) 240 { 241 struct pci_dev *pdev = acb->pdev; 242 switch (acb->adapter_type){ 243 case ACB_ADAPTER_TYPE_A:{ 244 acb->pmuA = ioremap(pci_resource_start(pdev,0), pci_resource_len(pdev,0)); 245 if (!acb->pmuA) { 246 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no); 247 return false; 248 } 249 break; 250 } 251 case ACB_ADAPTER_TYPE_B:{ 252 void __iomem *mem_base0, *mem_base1; 253 mem_base0 = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0)); 254 if (!mem_base0) { 255 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no); 256 return false; 257 } 258 mem_base1 = ioremap(pci_resource_start(pdev, 2), pci_resource_len(pdev, 2)); 259 if (!mem_base1) { 260 iounmap(mem_base0); 261 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no); 262 return false; 263 } 264 acb->mem_base0 = mem_base0; 265 acb->mem_base1 = mem_base1; 266 break; 267 } 268 case ACB_ADAPTER_TYPE_C:{ 269 acb->pmuC = ioremap_nocache(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1)); 270 if (!acb->pmuC) { 271 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no); 272 return false; 273 } 274 if (readl(&acb->pmuC->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 275 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &acb->pmuC->outbound_doorbell_clear);/*clear interrupt*/ 276 return true; 277 } 278 break; 279 } 280 case ACB_ADAPTER_TYPE_D: { 281 void __iomem *mem_base0; 282 unsigned long addr, range, flags; 283 284 addr = (unsigned long)pci_resource_start(pdev, 0); 285 range = pci_resource_len(pdev, 0); 286 flags = pci_resource_flags(pdev, 0); 287 mem_base0 = ioremap(addr, range); 288 if (!mem_base0) { 289 pr_notice("arcmsr%d: memory mapping region fail\n", 290 acb->host->host_no); 291 return false; 292 } 293 acb->mem_base0 = mem_base0; 294 break; 295 } 296 case ACB_ADAPTER_TYPE_E: { 297 acb->pmuE = ioremap(pci_resource_start(pdev, 1), 298 pci_resource_len(pdev, 1)); 299 if (!acb->pmuE) { 300 pr_notice("arcmsr%d: memory mapping region fail \n", 301 acb->host->host_no); 302 return false; 303 } 304 writel(0, &acb->pmuE->host_int_status); /*clear interrupt*/ 305 writel(ARCMSR_HBEMU_DOORBELL_SYNC, &acb->pmuE->iobound_doorbell); /* synchronize doorbell to 0 */ 306 acb->in_doorbell = 0; 307 acb->out_doorbell = 0; 308 break; 309 } 310 } 311 return true; 312 } 313 314 static void arcmsr_unmap_pciregion(struct AdapterControlBlock *acb) 315 { 316 switch (acb->adapter_type) { 317 case ACB_ADAPTER_TYPE_A:{ 318 iounmap(acb->pmuA); 319 } 320 break; 321 case ACB_ADAPTER_TYPE_B:{ 322 iounmap(acb->mem_base0); 323 iounmap(acb->mem_base1); 324 } 325 326 break; 327 case ACB_ADAPTER_TYPE_C:{ 328 iounmap(acb->pmuC); 329 } 330 break; 331 case ACB_ADAPTER_TYPE_D: 332 iounmap(acb->mem_base0); 333 break; 334 case ACB_ADAPTER_TYPE_E: 335 iounmap(acb->pmuE); 336 break; 337 } 338 } 339 340 static irqreturn_t arcmsr_do_interrupt(int irq, void *dev_id) 341 { 342 irqreturn_t handle_state; 343 struct AdapterControlBlock *acb = dev_id; 344 345 handle_state = arcmsr_interrupt(acb); 346 return handle_state; 347 } 348 349 static int arcmsr_bios_param(struct scsi_device *sdev, 350 struct block_device *bdev, sector_t capacity, int *geom) 351 { 352 int ret, heads, sectors, cylinders, total_capacity; 353 unsigned char *buffer;/* return copy of block device's partition table */ 354 355 buffer = scsi_bios_ptable(bdev); 356 if (buffer) { 357 ret = scsi_partsize(buffer, capacity, &geom[2], &geom[0], &geom[1]); 358 kfree(buffer); 359 if (ret != -1) 360 return ret; 361 } 362 total_capacity = capacity; 363 heads = 64; 364 sectors = 32; 365 cylinders = total_capacity / (heads * sectors); 366 if (cylinders > 1024) { 367 heads = 255; 368 sectors = 63; 369 cylinders = total_capacity / (heads * sectors); 370 } 371 geom[0] = heads; 372 geom[1] = sectors; 373 geom[2] = cylinders; 374 return 0; 375 } 376 377 static uint8_t arcmsr_hbaA_wait_msgint_ready(struct AdapterControlBlock *acb) 378 { 379 struct MessageUnit_A __iomem *reg = acb->pmuA; 380 int i; 381 382 for (i = 0; i < 2000; i++) { 383 if (readl(®->outbound_intstatus) & 384 ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 385 writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT, 386 ®->outbound_intstatus); 387 return true; 388 } 389 msleep(10); 390 } /* max 20 seconds */ 391 392 return false; 393 } 394 395 static uint8_t arcmsr_hbaB_wait_msgint_ready(struct AdapterControlBlock *acb) 396 { 397 struct MessageUnit_B *reg = acb->pmuB; 398 int i; 399 400 for (i = 0; i < 2000; i++) { 401 if (readl(reg->iop2drv_doorbell) 402 & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 403 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, 404 reg->iop2drv_doorbell); 405 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, 406 reg->drv2iop_doorbell); 407 return true; 408 } 409 msleep(10); 410 } /* max 20 seconds */ 411 412 return false; 413 } 414 415 static uint8_t arcmsr_hbaC_wait_msgint_ready(struct AdapterControlBlock *pACB) 416 { 417 struct MessageUnit_C __iomem *phbcmu = pACB->pmuC; 418 int i; 419 420 for (i = 0; i < 2000; i++) { 421 if (readl(&phbcmu->outbound_doorbell) 422 & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 423 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, 424 &phbcmu->outbound_doorbell_clear); /*clear interrupt*/ 425 return true; 426 } 427 msleep(10); 428 } /* max 20 seconds */ 429 430 return false; 431 } 432 433 static bool arcmsr_hbaD_wait_msgint_ready(struct AdapterControlBlock *pACB) 434 { 435 struct MessageUnit_D *reg = pACB->pmuD; 436 int i; 437 438 for (i = 0; i < 2000; i++) { 439 if (readl(reg->outbound_doorbell) 440 & ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE) { 441 writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE, 442 reg->outbound_doorbell); 443 return true; 444 } 445 msleep(10); 446 } /* max 20 seconds */ 447 return false; 448 } 449 450 static bool arcmsr_hbaE_wait_msgint_ready(struct AdapterControlBlock *pACB) 451 { 452 int i; 453 uint32_t read_doorbell; 454 struct MessageUnit_E __iomem *phbcmu = pACB->pmuE; 455 456 for (i = 0; i < 2000; i++) { 457 read_doorbell = readl(&phbcmu->iobound_doorbell); 458 if ((read_doorbell ^ pACB->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) { 459 writel(0, &phbcmu->host_int_status); /*clear interrupt*/ 460 pACB->in_doorbell = read_doorbell; 461 return true; 462 } 463 msleep(10); 464 } /* max 20 seconds */ 465 return false; 466 } 467 468 static void arcmsr_hbaA_flush_cache(struct AdapterControlBlock *acb) 469 { 470 struct MessageUnit_A __iomem *reg = acb->pmuA; 471 int retry_count = 30; 472 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, ®->inbound_msgaddr0); 473 do { 474 if (arcmsr_hbaA_wait_msgint_ready(acb)) 475 break; 476 else { 477 retry_count--; 478 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \ 479 timeout, retry count down = %d \n", acb->host->host_no, retry_count); 480 } 481 } while (retry_count != 0); 482 } 483 484 static void arcmsr_hbaB_flush_cache(struct AdapterControlBlock *acb) 485 { 486 struct MessageUnit_B *reg = acb->pmuB; 487 int retry_count = 30; 488 writel(ARCMSR_MESSAGE_FLUSH_CACHE, reg->drv2iop_doorbell); 489 do { 490 if (arcmsr_hbaB_wait_msgint_ready(acb)) 491 break; 492 else { 493 retry_count--; 494 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \ 495 timeout,retry count down = %d \n", acb->host->host_no, retry_count); 496 } 497 } while (retry_count != 0); 498 } 499 500 static void arcmsr_hbaC_flush_cache(struct AdapterControlBlock *pACB) 501 { 502 struct MessageUnit_C __iomem *reg = pACB->pmuC; 503 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 504 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, ®->inbound_msgaddr0); 505 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell); 506 do { 507 if (arcmsr_hbaC_wait_msgint_ready(pACB)) { 508 break; 509 } else { 510 retry_count--; 511 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \ 512 timeout,retry count down = %d \n", pACB->host->host_no, retry_count); 513 } 514 } while (retry_count != 0); 515 return; 516 } 517 518 static void arcmsr_hbaD_flush_cache(struct AdapterControlBlock *pACB) 519 { 520 int retry_count = 15; 521 struct MessageUnit_D *reg = pACB->pmuD; 522 523 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, reg->inbound_msgaddr0); 524 do { 525 if (arcmsr_hbaD_wait_msgint_ready(pACB)) 526 break; 527 528 retry_count--; 529 pr_notice("arcmsr%d: wait 'flush adapter " 530 "cache' timeout, retry count down = %d\n", 531 pACB->host->host_no, retry_count); 532 } while (retry_count != 0); 533 } 534 535 static void arcmsr_hbaE_flush_cache(struct AdapterControlBlock *pACB) 536 { 537 int retry_count = 30; 538 struct MessageUnit_E __iomem *reg = pACB->pmuE; 539 540 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, ®->inbound_msgaddr0); 541 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 542 writel(pACB->out_doorbell, ®->iobound_doorbell); 543 do { 544 if (arcmsr_hbaE_wait_msgint_ready(pACB)) 545 break; 546 retry_count--; 547 pr_notice("arcmsr%d: wait 'flush adapter " 548 "cache' timeout, retry count down = %d\n", 549 pACB->host->host_no, retry_count); 550 } while (retry_count != 0); 551 } 552 553 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb) 554 { 555 switch (acb->adapter_type) { 556 557 case ACB_ADAPTER_TYPE_A: { 558 arcmsr_hbaA_flush_cache(acb); 559 } 560 break; 561 562 case ACB_ADAPTER_TYPE_B: { 563 arcmsr_hbaB_flush_cache(acb); 564 } 565 break; 566 case ACB_ADAPTER_TYPE_C: { 567 arcmsr_hbaC_flush_cache(acb); 568 } 569 break; 570 case ACB_ADAPTER_TYPE_D: 571 arcmsr_hbaD_flush_cache(acb); 572 break; 573 case ACB_ADAPTER_TYPE_E: 574 arcmsr_hbaE_flush_cache(acb); 575 break; 576 } 577 } 578 579 static bool arcmsr_alloc_io_queue(struct AdapterControlBlock *acb) 580 { 581 bool rtn = true; 582 void *dma_coherent; 583 dma_addr_t dma_coherent_handle; 584 struct pci_dev *pdev = acb->pdev; 585 586 switch (acb->adapter_type) { 587 case ACB_ADAPTER_TYPE_B: { 588 struct MessageUnit_B *reg; 589 acb->roundup_ccbsize = roundup(sizeof(struct MessageUnit_B), 32); 590 dma_coherent = dma_alloc_coherent(&pdev->dev, 591 acb->roundup_ccbsize, 592 &dma_coherent_handle, 593 GFP_KERNEL); 594 if (!dma_coherent) { 595 pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no); 596 return false; 597 } 598 acb->dma_coherent_handle2 = dma_coherent_handle; 599 acb->dma_coherent2 = dma_coherent; 600 reg = (struct MessageUnit_B *)dma_coherent; 601 acb->pmuB = reg; 602 if (acb->pdev->device == PCI_DEVICE_ID_ARECA_1203) { 603 reg->drv2iop_doorbell = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_1203); 604 reg->drv2iop_doorbell_mask = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_MASK_1203); 605 reg->iop2drv_doorbell = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_1203); 606 reg->iop2drv_doorbell_mask = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_MASK_1203); 607 } else { 608 reg->drv2iop_doorbell = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL); 609 reg->drv2iop_doorbell_mask = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_MASK); 610 reg->iop2drv_doorbell = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL); 611 reg->iop2drv_doorbell_mask = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_MASK); 612 } 613 reg->message_wbuffer = MEM_BASE1(ARCMSR_MESSAGE_WBUFFER); 614 reg->message_rbuffer = MEM_BASE1(ARCMSR_MESSAGE_RBUFFER); 615 reg->message_rwbuffer = MEM_BASE1(ARCMSR_MESSAGE_RWBUFFER); 616 } 617 break; 618 case ACB_ADAPTER_TYPE_D: { 619 struct MessageUnit_D *reg; 620 621 acb->roundup_ccbsize = roundup(sizeof(struct MessageUnit_D), 32); 622 dma_coherent = dma_alloc_coherent(&pdev->dev, 623 acb->roundup_ccbsize, 624 &dma_coherent_handle, 625 GFP_KERNEL); 626 if (!dma_coherent) { 627 pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no); 628 return false; 629 } 630 acb->dma_coherent_handle2 = dma_coherent_handle; 631 acb->dma_coherent2 = dma_coherent; 632 reg = (struct MessageUnit_D *)dma_coherent; 633 acb->pmuD = reg; 634 reg->chip_id = MEM_BASE0(ARCMSR_ARC1214_CHIP_ID); 635 reg->cpu_mem_config = MEM_BASE0(ARCMSR_ARC1214_CPU_MEMORY_CONFIGURATION); 636 reg->i2o_host_interrupt_mask = MEM_BASE0(ARCMSR_ARC1214_I2_HOST_INTERRUPT_MASK); 637 reg->sample_at_reset = MEM_BASE0(ARCMSR_ARC1214_SAMPLE_RESET); 638 reg->reset_request = MEM_BASE0(ARCMSR_ARC1214_RESET_REQUEST); 639 reg->host_int_status = MEM_BASE0(ARCMSR_ARC1214_MAIN_INTERRUPT_STATUS); 640 reg->pcief0_int_enable = MEM_BASE0(ARCMSR_ARC1214_PCIE_F0_INTERRUPT_ENABLE); 641 reg->inbound_msgaddr0 = MEM_BASE0(ARCMSR_ARC1214_INBOUND_MESSAGE0); 642 reg->inbound_msgaddr1 = MEM_BASE0(ARCMSR_ARC1214_INBOUND_MESSAGE1); 643 reg->outbound_msgaddr0 = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_MESSAGE0); 644 reg->outbound_msgaddr1 = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_MESSAGE1); 645 reg->inbound_doorbell = MEM_BASE0(ARCMSR_ARC1214_INBOUND_DOORBELL); 646 reg->outbound_doorbell = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_DOORBELL); 647 reg->outbound_doorbell_enable = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_DOORBELL_ENABLE); 648 reg->inboundlist_base_low = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_BASE_LOW); 649 reg->inboundlist_base_high = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_BASE_HIGH); 650 reg->inboundlist_write_pointer = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_WRITE_POINTER); 651 reg->outboundlist_base_low = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_BASE_LOW); 652 reg->outboundlist_base_high = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_BASE_HIGH); 653 reg->outboundlist_copy_pointer = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_COPY_POINTER); 654 reg->outboundlist_read_pointer = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_READ_POINTER); 655 reg->outboundlist_interrupt_cause = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_INTERRUPT_CAUSE); 656 reg->outboundlist_interrupt_enable = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_INTERRUPT_ENABLE); 657 reg->message_wbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_WBUFFER); 658 reg->message_rbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_RBUFFER); 659 reg->msgcode_rwbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_RWBUFFER); 660 } 661 break; 662 case ACB_ADAPTER_TYPE_E: { 663 uint32_t completeQ_size; 664 completeQ_size = sizeof(struct deliver_completeQ) * ARCMSR_MAX_HBE_DONEQUEUE + 128; 665 acb->roundup_ccbsize = roundup(completeQ_size, 32); 666 dma_coherent = dma_alloc_coherent(&pdev->dev, 667 acb->roundup_ccbsize, 668 &dma_coherent_handle, 669 GFP_KERNEL); 670 if (!dma_coherent){ 671 pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no); 672 return false; 673 } 674 acb->dma_coherent_handle2 = dma_coherent_handle; 675 acb->dma_coherent2 = dma_coherent; 676 acb->pCompletionQ = dma_coherent; 677 acb->completionQ_entry = acb->roundup_ccbsize / sizeof(struct deliver_completeQ); 678 acb->doneq_index = 0; 679 } 680 break; 681 default: 682 break; 683 } 684 return rtn; 685 } 686 687 static int arcmsr_alloc_ccb_pool(struct AdapterControlBlock *acb) 688 { 689 struct pci_dev *pdev = acb->pdev; 690 void *dma_coherent; 691 dma_addr_t dma_coherent_handle; 692 struct CommandControlBlock *ccb_tmp; 693 int i = 0, j = 0; 694 dma_addr_t cdb_phyaddr; 695 unsigned long roundup_ccbsize; 696 unsigned long max_xfer_len; 697 unsigned long max_sg_entrys; 698 uint32_t firm_config_version; 699 700 for (i = 0; i < ARCMSR_MAX_TARGETID; i++) 701 for (j = 0; j < ARCMSR_MAX_TARGETLUN; j++) 702 acb->devstate[i][j] = ARECA_RAID_GONE; 703 704 max_xfer_len = ARCMSR_MAX_XFER_LEN; 705 max_sg_entrys = ARCMSR_DEFAULT_SG_ENTRIES; 706 firm_config_version = acb->firm_cfg_version; 707 if((firm_config_version & 0xFF) >= 3){ 708 max_xfer_len = (ARCMSR_CDB_SG_PAGE_LENGTH << ((firm_config_version >> 8) & 0xFF)) * 1024;/* max 4M byte */ 709 max_sg_entrys = (max_xfer_len/4096); 710 } 711 acb->host->max_sectors = max_xfer_len/512; 712 acb->host->sg_tablesize = max_sg_entrys; 713 roundup_ccbsize = roundup(sizeof(struct CommandControlBlock) + (max_sg_entrys - 1) * sizeof(struct SG64ENTRY), 32); 714 acb->uncache_size = roundup_ccbsize * acb->maxFreeCCB; 715 dma_coherent = dma_alloc_coherent(&pdev->dev, acb->uncache_size, &dma_coherent_handle, GFP_KERNEL); 716 if(!dma_coherent){ 717 printk(KERN_NOTICE "arcmsr%d: dma_alloc_coherent got error\n", acb->host->host_no); 718 return -ENOMEM; 719 } 720 acb->dma_coherent = dma_coherent; 721 acb->dma_coherent_handle = dma_coherent_handle; 722 memset(dma_coherent, 0, acb->uncache_size); 723 acb->ccbsize = roundup_ccbsize; 724 ccb_tmp = dma_coherent; 725 acb->vir2phy_offset = (unsigned long)dma_coherent - (unsigned long)dma_coherent_handle; 726 for(i = 0; i < acb->maxFreeCCB; i++){ 727 cdb_phyaddr = dma_coherent_handle + offsetof(struct CommandControlBlock, arcmsr_cdb); 728 switch (acb->adapter_type) { 729 case ACB_ADAPTER_TYPE_A: 730 case ACB_ADAPTER_TYPE_B: 731 ccb_tmp->cdb_phyaddr = cdb_phyaddr >> 5; 732 break; 733 case ACB_ADAPTER_TYPE_C: 734 case ACB_ADAPTER_TYPE_D: 735 case ACB_ADAPTER_TYPE_E: 736 ccb_tmp->cdb_phyaddr = cdb_phyaddr; 737 break; 738 } 739 acb->pccb_pool[i] = ccb_tmp; 740 ccb_tmp->acb = acb; 741 ccb_tmp->smid = (u32)i << 16; 742 INIT_LIST_HEAD(&ccb_tmp->list); 743 list_add_tail(&ccb_tmp->list, &acb->ccb_free_list); 744 ccb_tmp = (struct CommandControlBlock *)((unsigned long)ccb_tmp + roundup_ccbsize); 745 dma_coherent_handle = dma_coherent_handle + roundup_ccbsize; 746 } 747 return 0; 748 } 749 750 static void arcmsr_message_isr_bh_fn(struct work_struct *work) 751 { 752 struct AdapterControlBlock *acb = container_of(work, 753 struct AdapterControlBlock, arcmsr_do_message_isr_bh); 754 char *acb_dev_map = (char *)acb->device_map; 755 uint32_t __iomem *signature = NULL; 756 char __iomem *devicemap = NULL; 757 int target, lun; 758 struct scsi_device *psdev; 759 char diff, temp; 760 761 acb->acb_flags &= ~ACB_F_MSG_GET_CONFIG; 762 switch (acb->adapter_type) { 763 case ACB_ADAPTER_TYPE_A: { 764 struct MessageUnit_A __iomem *reg = acb->pmuA; 765 766 signature = (uint32_t __iomem *)(®->message_rwbuffer[0]); 767 devicemap = (char __iomem *)(®->message_rwbuffer[21]); 768 break; 769 } 770 case ACB_ADAPTER_TYPE_B: { 771 struct MessageUnit_B *reg = acb->pmuB; 772 773 signature = (uint32_t __iomem *)(®->message_rwbuffer[0]); 774 devicemap = (char __iomem *)(®->message_rwbuffer[21]); 775 break; 776 } 777 case ACB_ADAPTER_TYPE_C: { 778 struct MessageUnit_C __iomem *reg = acb->pmuC; 779 780 signature = (uint32_t __iomem *)(®->msgcode_rwbuffer[0]); 781 devicemap = (char __iomem *)(®->msgcode_rwbuffer[21]); 782 break; 783 } 784 case ACB_ADAPTER_TYPE_D: { 785 struct MessageUnit_D *reg = acb->pmuD; 786 787 signature = (uint32_t __iomem *)(®->msgcode_rwbuffer[0]); 788 devicemap = (char __iomem *)(®->msgcode_rwbuffer[21]); 789 break; 790 } 791 case ACB_ADAPTER_TYPE_E: { 792 struct MessageUnit_E __iomem *reg = acb->pmuE; 793 794 signature = (uint32_t __iomem *)(®->msgcode_rwbuffer[0]); 795 devicemap = (char __iomem *)(®->msgcode_rwbuffer[21]); 796 break; 797 } 798 } 799 atomic_inc(&acb->rq_map_token); 800 if (readl(signature) != ARCMSR_SIGNATURE_GET_CONFIG) 801 return; 802 for (target = 0; target < ARCMSR_MAX_TARGETID - 1; 803 target++) { 804 temp = readb(devicemap); 805 diff = (*acb_dev_map) ^ temp; 806 if (diff != 0) { 807 *acb_dev_map = temp; 808 for (lun = 0; lun < ARCMSR_MAX_TARGETLUN; 809 lun++) { 810 if ((diff & 0x01) == 1 && 811 (temp & 0x01) == 1) { 812 scsi_add_device(acb->host, 813 0, target, lun); 814 } else if ((diff & 0x01) == 1 815 && (temp & 0x01) == 0) { 816 psdev = scsi_device_lookup(acb->host, 817 0, target, lun); 818 if (psdev != NULL) { 819 scsi_remove_device(psdev); 820 scsi_device_put(psdev); 821 } 822 } 823 temp >>= 1; 824 diff >>= 1; 825 } 826 } 827 devicemap++; 828 acb_dev_map++; 829 } 830 } 831 832 static int 833 arcmsr_request_irq(struct pci_dev *pdev, struct AdapterControlBlock *acb) 834 { 835 unsigned long flags; 836 int nvec, i; 837 838 if (msix_enable == 0) 839 goto msi_int0; 840 nvec = pci_alloc_irq_vectors(pdev, 1, ARCMST_NUM_MSIX_VECTORS, 841 PCI_IRQ_MSIX); 842 if (nvec > 0) { 843 pr_info("arcmsr%d: msi-x enabled\n", acb->host->host_no); 844 flags = 0; 845 } else { 846 msi_int0: 847 if (msi_enable == 1) { 848 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); 849 if (nvec == 1) { 850 dev_info(&pdev->dev, "msi enabled\n"); 851 goto msi_int1; 852 } 853 } 854 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_LEGACY); 855 if (nvec < 1) 856 return FAILED; 857 msi_int1: 858 flags = IRQF_SHARED; 859 } 860 861 acb->vector_count = nvec; 862 for (i = 0; i < nvec; i++) { 863 if (request_irq(pci_irq_vector(pdev, i), arcmsr_do_interrupt, 864 flags, "arcmsr", acb)) { 865 pr_warn("arcmsr%d: request_irq =%d failed!\n", 866 acb->host->host_no, pci_irq_vector(pdev, i)); 867 goto out_free_irq; 868 } 869 } 870 871 return SUCCESS; 872 out_free_irq: 873 while (--i >= 0) 874 free_irq(pci_irq_vector(pdev, i), acb); 875 pci_free_irq_vectors(pdev); 876 return FAILED; 877 } 878 879 static void arcmsr_init_get_devmap_timer(struct AdapterControlBlock *pacb) 880 { 881 INIT_WORK(&pacb->arcmsr_do_message_isr_bh, arcmsr_message_isr_bh_fn); 882 atomic_set(&pacb->rq_map_token, 16); 883 atomic_set(&pacb->ante_token_value, 16); 884 pacb->fw_flag = FW_NORMAL; 885 timer_setup(&pacb->eternal_timer, arcmsr_request_device_map, 0); 886 pacb->eternal_timer.expires = jiffies + msecs_to_jiffies(6 * HZ); 887 add_timer(&pacb->eternal_timer); 888 } 889 890 static void arcmsr_init_set_datetime_timer(struct AdapterControlBlock *pacb) 891 { 892 timer_setup(&pacb->refresh_timer, arcmsr_set_iop_datetime, 0); 893 pacb->refresh_timer.expires = jiffies + msecs_to_jiffies(60 * 1000); 894 add_timer(&pacb->refresh_timer); 895 } 896 897 static int arcmsr_probe(struct pci_dev *pdev, const struct pci_device_id *id) 898 { 899 struct Scsi_Host *host; 900 struct AdapterControlBlock *acb; 901 uint8_t bus,dev_fun; 902 int error; 903 error = pci_enable_device(pdev); 904 if(error){ 905 return -ENODEV; 906 } 907 host = scsi_host_alloc(&arcmsr_scsi_host_template, sizeof(struct AdapterControlBlock)); 908 if(!host){ 909 goto pci_disable_dev; 910 } 911 error = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); 912 if(error){ 913 error = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 914 if(error){ 915 printk(KERN_WARNING 916 "scsi%d: No suitable DMA mask available\n", 917 host->host_no); 918 goto scsi_host_release; 919 } 920 } 921 init_waitqueue_head(&wait_q); 922 bus = pdev->bus->number; 923 dev_fun = pdev->devfn; 924 acb = (struct AdapterControlBlock *) host->hostdata; 925 memset(acb,0,sizeof(struct AdapterControlBlock)); 926 acb->pdev = pdev; 927 acb->host = host; 928 host->max_lun = ARCMSR_MAX_TARGETLUN; 929 host->max_id = ARCMSR_MAX_TARGETID; /*16:8*/ 930 host->max_cmd_len = 16; /*this is issue of 64bit LBA ,over 2T byte*/ 931 if ((host_can_queue < ARCMSR_MIN_OUTSTANDING_CMD) || (host_can_queue > ARCMSR_MAX_OUTSTANDING_CMD)) 932 host_can_queue = ARCMSR_DEFAULT_OUTSTANDING_CMD; 933 host->can_queue = host_can_queue; /* max simultaneous cmds */ 934 if ((cmd_per_lun < ARCMSR_MIN_CMD_PERLUN) || (cmd_per_lun > ARCMSR_MAX_CMD_PERLUN)) 935 cmd_per_lun = ARCMSR_DEFAULT_CMD_PERLUN; 936 host->cmd_per_lun = cmd_per_lun; 937 host->this_id = ARCMSR_SCSI_INITIATOR_ID; 938 host->unique_id = (bus << 8) | dev_fun; 939 pci_set_drvdata(pdev, host); 940 pci_set_master(pdev); 941 error = pci_request_regions(pdev, "arcmsr"); 942 if(error){ 943 goto scsi_host_release; 944 } 945 spin_lock_init(&acb->eh_lock); 946 spin_lock_init(&acb->ccblist_lock); 947 spin_lock_init(&acb->postq_lock); 948 spin_lock_init(&acb->doneq_lock); 949 spin_lock_init(&acb->rqbuffer_lock); 950 spin_lock_init(&acb->wqbuffer_lock); 951 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED | 952 ACB_F_MESSAGE_RQBUFFER_CLEARED | 953 ACB_F_MESSAGE_WQBUFFER_READED); 954 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER; 955 INIT_LIST_HEAD(&acb->ccb_free_list); 956 acb->adapter_type = id->driver_data; 957 error = arcmsr_remap_pciregion(acb); 958 if(!error){ 959 goto pci_release_regs; 960 } 961 error = arcmsr_alloc_io_queue(acb); 962 if (!error) 963 goto unmap_pci_region; 964 error = arcmsr_get_firmware_spec(acb); 965 if(!error){ 966 goto free_hbb_mu; 967 } 968 error = arcmsr_alloc_ccb_pool(acb); 969 if(error){ 970 goto free_hbb_mu; 971 } 972 error = scsi_add_host(host, &pdev->dev); 973 if(error){ 974 goto free_ccb_pool; 975 } 976 if (arcmsr_request_irq(pdev, acb) == FAILED) 977 goto scsi_host_remove; 978 arcmsr_iop_init(acb); 979 arcmsr_init_get_devmap_timer(acb); 980 if (set_date_time) 981 arcmsr_init_set_datetime_timer(acb); 982 if(arcmsr_alloc_sysfs_attr(acb)) 983 goto out_free_sysfs; 984 scsi_scan_host(host); 985 return 0; 986 out_free_sysfs: 987 if (set_date_time) 988 del_timer_sync(&acb->refresh_timer); 989 del_timer_sync(&acb->eternal_timer); 990 flush_work(&acb->arcmsr_do_message_isr_bh); 991 arcmsr_stop_adapter_bgrb(acb); 992 arcmsr_flush_adapter_cache(acb); 993 arcmsr_free_irq(pdev, acb); 994 scsi_host_remove: 995 scsi_remove_host(host); 996 free_ccb_pool: 997 arcmsr_free_ccb_pool(acb); 998 free_hbb_mu: 999 arcmsr_free_mu(acb); 1000 unmap_pci_region: 1001 arcmsr_unmap_pciregion(acb); 1002 pci_release_regs: 1003 pci_release_regions(pdev); 1004 scsi_host_release: 1005 scsi_host_put(host); 1006 pci_disable_dev: 1007 pci_disable_device(pdev); 1008 return -ENODEV; 1009 } 1010 1011 static void arcmsr_free_irq(struct pci_dev *pdev, 1012 struct AdapterControlBlock *acb) 1013 { 1014 int i; 1015 1016 for (i = 0; i < acb->vector_count; i++) 1017 free_irq(pci_irq_vector(pdev, i), acb); 1018 pci_free_irq_vectors(pdev); 1019 } 1020 1021 static int arcmsr_suspend(struct pci_dev *pdev, pm_message_t state) 1022 { 1023 uint32_t intmask_org; 1024 struct Scsi_Host *host = pci_get_drvdata(pdev); 1025 struct AdapterControlBlock *acb = 1026 (struct AdapterControlBlock *)host->hostdata; 1027 1028 intmask_org = arcmsr_disable_outbound_ints(acb); 1029 arcmsr_free_irq(pdev, acb); 1030 del_timer_sync(&acb->eternal_timer); 1031 if (set_date_time) 1032 del_timer_sync(&acb->refresh_timer); 1033 flush_work(&acb->arcmsr_do_message_isr_bh); 1034 arcmsr_stop_adapter_bgrb(acb); 1035 arcmsr_flush_adapter_cache(acb); 1036 pci_set_drvdata(pdev, host); 1037 pci_save_state(pdev); 1038 pci_disable_device(pdev); 1039 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1040 return 0; 1041 } 1042 1043 static int arcmsr_resume(struct pci_dev *pdev) 1044 { 1045 int error; 1046 struct Scsi_Host *host = pci_get_drvdata(pdev); 1047 struct AdapterControlBlock *acb = 1048 (struct AdapterControlBlock *)host->hostdata; 1049 1050 pci_set_power_state(pdev, PCI_D0); 1051 pci_enable_wake(pdev, PCI_D0, 0); 1052 pci_restore_state(pdev); 1053 if (pci_enable_device(pdev)) { 1054 pr_warn("%s: pci_enable_device error\n", __func__); 1055 return -ENODEV; 1056 } 1057 error = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); 1058 if (error) { 1059 error = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 1060 if (error) { 1061 pr_warn("scsi%d: No suitable DMA mask available\n", 1062 host->host_no); 1063 goto controller_unregister; 1064 } 1065 } 1066 pci_set_master(pdev); 1067 if (arcmsr_request_irq(pdev, acb) == FAILED) 1068 goto controller_stop; 1069 if (acb->adapter_type == ACB_ADAPTER_TYPE_E) { 1070 writel(0, &acb->pmuE->host_int_status); 1071 writel(ARCMSR_HBEMU_DOORBELL_SYNC, &acb->pmuE->iobound_doorbell); 1072 acb->in_doorbell = 0; 1073 acb->out_doorbell = 0; 1074 acb->doneq_index = 0; 1075 } 1076 arcmsr_iop_init(acb); 1077 arcmsr_init_get_devmap_timer(acb); 1078 if (set_date_time) 1079 arcmsr_init_set_datetime_timer(acb); 1080 return 0; 1081 controller_stop: 1082 arcmsr_stop_adapter_bgrb(acb); 1083 arcmsr_flush_adapter_cache(acb); 1084 controller_unregister: 1085 scsi_remove_host(host); 1086 arcmsr_free_ccb_pool(acb); 1087 arcmsr_unmap_pciregion(acb); 1088 pci_release_regions(pdev); 1089 scsi_host_put(host); 1090 pci_disable_device(pdev); 1091 return -ENODEV; 1092 } 1093 1094 static uint8_t arcmsr_hbaA_abort_allcmd(struct AdapterControlBlock *acb) 1095 { 1096 struct MessageUnit_A __iomem *reg = acb->pmuA; 1097 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, ®->inbound_msgaddr0); 1098 if (!arcmsr_hbaA_wait_msgint_ready(acb)) { 1099 printk(KERN_NOTICE 1100 "arcmsr%d: wait 'abort all outstanding command' timeout\n" 1101 , acb->host->host_no); 1102 return false; 1103 } 1104 return true; 1105 } 1106 1107 static uint8_t arcmsr_hbaB_abort_allcmd(struct AdapterControlBlock *acb) 1108 { 1109 struct MessageUnit_B *reg = acb->pmuB; 1110 1111 writel(ARCMSR_MESSAGE_ABORT_CMD, reg->drv2iop_doorbell); 1112 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 1113 printk(KERN_NOTICE 1114 "arcmsr%d: wait 'abort all outstanding command' timeout\n" 1115 , acb->host->host_no); 1116 return false; 1117 } 1118 return true; 1119 } 1120 static uint8_t arcmsr_hbaC_abort_allcmd(struct AdapterControlBlock *pACB) 1121 { 1122 struct MessageUnit_C __iomem *reg = pACB->pmuC; 1123 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, ®->inbound_msgaddr0); 1124 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell); 1125 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) { 1126 printk(KERN_NOTICE 1127 "arcmsr%d: wait 'abort all outstanding command' timeout\n" 1128 , pACB->host->host_no); 1129 return false; 1130 } 1131 return true; 1132 } 1133 1134 static uint8_t arcmsr_hbaD_abort_allcmd(struct AdapterControlBlock *pACB) 1135 { 1136 struct MessageUnit_D *reg = pACB->pmuD; 1137 1138 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, reg->inbound_msgaddr0); 1139 if (!arcmsr_hbaD_wait_msgint_ready(pACB)) { 1140 pr_notice("arcmsr%d: wait 'abort all outstanding " 1141 "command' timeout\n", pACB->host->host_no); 1142 return false; 1143 } 1144 return true; 1145 } 1146 1147 static uint8_t arcmsr_hbaE_abort_allcmd(struct AdapterControlBlock *pACB) 1148 { 1149 struct MessageUnit_E __iomem *reg = pACB->pmuE; 1150 1151 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, ®->inbound_msgaddr0); 1152 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 1153 writel(pACB->out_doorbell, ®->iobound_doorbell); 1154 if (!arcmsr_hbaE_wait_msgint_ready(pACB)) { 1155 pr_notice("arcmsr%d: wait 'abort all outstanding " 1156 "command' timeout\n", pACB->host->host_no); 1157 return false; 1158 } 1159 return true; 1160 } 1161 1162 static uint8_t arcmsr_abort_allcmd(struct AdapterControlBlock *acb) 1163 { 1164 uint8_t rtnval = 0; 1165 switch (acb->adapter_type) { 1166 case ACB_ADAPTER_TYPE_A: { 1167 rtnval = arcmsr_hbaA_abort_allcmd(acb); 1168 } 1169 break; 1170 1171 case ACB_ADAPTER_TYPE_B: { 1172 rtnval = arcmsr_hbaB_abort_allcmd(acb); 1173 } 1174 break; 1175 1176 case ACB_ADAPTER_TYPE_C: { 1177 rtnval = arcmsr_hbaC_abort_allcmd(acb); 1178 } 1179 break; 1180 1181 case ACB_ADAPTER_TYPE_D: 1182 rtnval = arcmsr_hbaD_abort_allcmd(acb); 1183 break; 1184 case ACB_ADAPTER_TYPE_E: 1185 rtnval = arcmsr_hbaE_abort_allcmd(acb); 1186 break; 1187 } 1188 return rtnval; 1189 } 1190 1191 static void arcmsr_pci_unmap_dma(struct CommandControlBlock *ccb) 1192 { 1193 struct scsi_cmnd *pcmd = ccb->pcmd; 1194 1195 scsi_dma_unmap(pcmd); 1196 } 1197 1198 static void arcmsr_ccb_complete(struct CommandControlBlock *ccb) 1199 { 1200 struct AdapterControlBlock *acb = ccb->acb; 1201 struct scsi_cmnd *pcmd = ccb->pcmd; 1202 unsigned long flags; 1203 atomic_dec(&acb->ccboutstandingcount); 1204 arcmsr_pci_unmap_dma(ccb); 1205 ccb->startdone = ARCMSR_CCB_DONE; 1206 spin_lock_irqsave(&acb->ccblist_lock, flags); 1207 list_add_tail(&ccb->list, &acb->ccb_free_list); 1208 spin_unlock_irqrestore(&acb->ccblist_lock, flags); 1209 pcmd->scsi_done(pcmd); 1210 } 1211 1212 static void arcmsr_report_sense_info(struct CommandControlBlock *ccb) 1213 { 1214 1215 struct scsi_cmnd *pcmd = ccb->pcmd; 1216 struct SENSE_DATA *sensebuffer = (struct SENSE_DATA *)pcmd->sense_buffer; 1217 pcmd->result = (DID_OK << 16) | (CHECK_CONDITION << 1); 1218 if (sensebuffer) { 1219 int sense_data_length = 1220 sizeof(struct SENSE_DATA) < SCSI_SENSE_BUFFERSIZE 1221 ? sizeof(struct SENSE_DATA) : SCSI_SENSE_BUFFERSIZE; 1222 memset(sensebuffer, 0, SCSI_SENSE_BUFFERSIZE); 1223 memcpy(sensebuffer, ccb->arcmsr_cdb.SenseData, sense_data_length); 1224 sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS; 1225 sensebuffer->Valid = 1; 1226 pcmd->result |= (DRIVER_SENSE << 24); 1227 } 1228 } 1229 1230 static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb) 1231 { 1232 u32 orig_mask = 0; 1233 switch (acb->adapter_type) { 1234 case ACB_ADAPTER_TYPE_A : { 1235 struct MessageUnit_A __iomem *reg = acb->pmuA; 1236 orig_mask = readl(®->outbound_intmask); 1237 writel(orig_mask|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE, \ 1238 ®->outbound_intmask); 1239 } 1240 break; 1241 case ACB_ADAPTER_TYPE_B : { 1242 struct MessageUnit_B *reg = acb->pmuB; 1243 orig_mask = readl(reg->iop2drv_doorbell_mask); 1244 writel(0, reg->iop2drv_doorbell_mask); 1245 } 1246 break; 1247 case ACB_ADAPTER_TYPE_C:{ 1248 struct MessageUnit_C __iomem *reg = acb->pmuC; 1249 /* disable all outbound interrupt */ 1250 orig_mask = readl(®->host_int_mask); /* disable outbound message0 int */ 1251 writel(orig_mask|ARCMSR_HBCMU_ALL_INTMASKENABLE, ®->host_int_mask); 1252 } 1253 break; 1254 case ACB_ADAPTER_TYPE_D: { 1255 struct MessageUnit_D *reg = acb->pmuD; 1256 /* disable all outbound interrupt */ 1257 writel(ARCMSR_ARC1214_ALL_INT_DISABLE, reg->pcief0_int_enable); 1258 } 1259 break; 1260 case ACB_ADAPTER_TYPE_E: { 1261 struct MessageUnit_E __iomem *reg = acb->pmuE; 1262 orig_mask = readl(®->host_int_mask); 1263 writel(orig_mask | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR, ®->host_int_mask); 1264 readl(®->host_int_mask); /* Dummy readl to force pci flush */ 1265 } 1266 break; 1267 } 1268 return orig_mask; 1269 } 1270 1271 static void arcmsr_report_ccb_state(struct AdapterControlBlock *acb, 1272 struct CommandControlBlock *ccb, bool error) 1273 { 1274 uint8_t id, lun; 1275 id = ccb->pcmd->device->id; 1276 lun = ccb->pcmd->device->lun; 1277 if (!error) { 1278 if (acb->devstate[id][lun] == ARECA_RAID_GONE) 1279 acb->devstate[id][lun] = ARECA_RAID_GOOD; 1280 ccb->pcmd->result = DID_OK << 16; 1281 arcmsr_ccb_complete(ccb); 1282 }else{ 1283 switch (ccb->arcmsr_cdb.DeviceStatus) { 1284 case ARCMSR_DEV_SELECT_TIMEOUT: { 1285 acb->devstate[id][lun] = ARECA_RAID_GONE; 1286 ccb->pcmd->result = DID_NO_CONNECT << 16; 1287 arcmsr_ccb_complete(ccb); 1288 } 1289 break; 1290 1291 case ARCMSR_DEV_ABORTED: 1292 1293 case ARCMSR_DEV_INIT_FAIL: { 1294 acb->devstate[id][lun] = ARECA_RAID_GONE; 1295 ccb->pcmd->result = DID_BAD_TARGET << 16; 1296 arcmsr_ccb_complete(ccb); 1297 } 1298 break; 1299 1300 case ARCMSR_DEV_CHECK_CONDITION: { 1301 acb->devstate[id][lun] = ARECA_RAID_GOOD; 1302 arcmsr_report_sense_info(ccb); 1303 arcmsr_ccb_complete(ccb); 1304 } 1305 break; 1306 1307 default: 1308 printk(KERN_NOTICE 1309 "arcmsr%d: scsi id = %d lun = %d isr get command error done, \ 1310 but got unknown DeviceStatus = 0x%x \n" 1311 , acb->host->host_no 1312 , id 1313 , lun 1314 , ccb->arcmsr_cdb.DeviceStatus); 1315 acb->devstate[id][lun] = ARECA_RAID_GONE; 1316 ccb->pcmd->result = DID_NO_CONNECT << 16; 1317 arcmsr_ccb_complete(ccb); 1318 break; 1319 } 1320 } 1321 } 1322 1323 static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, struct CommandControlBlock *pCCB, bool error) 1324 { 1325 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) { 1326 if (pCCB->startdone == ARCMSR_CCB_ABORTED) { 1327 struct scsi_cmnd *abortcmd = pCCB->pcmd; 1328 if (abortcmd) { 1329 abortcmd->result |= DID_ABORT << 16; 1330 arcmsr_ccb_complete(pCCB); 1331 printk(KERN_NOTICE "arcmsr%d: pCCB ='0x%p' isr got aborted command \n", 1332 acb->host->host_no, pCCB); 1333 } 1334 return; 1335 } 1336 printk(KERN_NOTICE "arcmsr%d: isr get an illegal ccb command \ 1337 done acb = '0x%p'" 1338 "ccb = '0x%p' ccbacb = '0x%p' startdone = 0x%x" 1339 " ccboutstandingcount = %d \n" 1340 , acb->host->host_no 1341 , acb 1342 , pCCB 1343 , pCCB->acb 1344 , pCCB->startdone 1345 , atomic_read(&acb->ccboutstandingcount)); 1346 return; 1347 } 1348 arcmsr_report_ccb_state(acb, pCCB, error); 1349 } 1350 1351 static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb) 1352 { 1353 int i = 0; 1354 uint32_t flag_ccb, ccb_cdb_phy; 1355 struct ARCMSR_CDB *pARCMSR_CDB; 1356 bool error; 1357 struct CommandControlBlock *pCCB; 1358 switch (acb->adapter_type) { 1359 1360 case ACB_ADAPTER_TYPE_A: { 1361 struct MessageUnit_A __iomem *reg = acb->pmuA; 1362 uint32_t outbound_intstatus; 1363 outbound_intstatus = readl(®->outbound_intstatus) & 1364 acb->outbound_int_enable; 1365 /*clear and abort all outbound posted Q*/ 1366 writel(outbound_intstatus, ®->outbound_intstatus);/*clear interrupt*/ 1367 while(((flag_ccb = readl(®->outbound_queueport)) != 0xFFFFFFFF) 1368 && (i++ < acb->maxOutstanding)) { 1369 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));/*frame must be 32 bytes aligned*/ 1370 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb); 1371 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false; 1372 arcmsr_drain_donequeue(acb, pCCB, error); 1373 } 1374 } 1375 break; 1376 1377 case ACB_ADAPTER_TYPE_B: { 1378 struct MessageUnit_B *reg = acb->pmuB; 1379 /*clear all outbound posted Q*/ 1380 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); /* clear doorbell interrupt */ 1381 for (i = 0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) { 1382 flag_ccb = reg->done_qbuffer[i]; 1383 if (flag_ccb != 0) { 1384 reg->done_qbuffer[i] = 0; 1385 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+(flag_ccb << 5));/*frame must be 32 bytes aligned*/ 1386 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb); 1387 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false; 1388 arcmsr_drain_donequeue(acb, pCCB, error); 1389 } 1390 reg->post_qbuffer[i] = 0; 1391 } 1392 reg->doneq_index = 0; 1393 reg->postq_index = 0; 1394 } 1395 break; 1396 case ACB_ADAPTER_TYPE_C: { 1397 struct MessageUnit_C __iomem *reg = acb->pmuC; 1398 while ((readl(®->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < acb->maxOutstanding)) { 1399 /*need to do*/ 1400 flag_ccb = readl(®->outbound_queueport_low); 1401 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0); 1402 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+ccb_cdb_phy);/*frame must be 32 bytes aligned*/ 1403 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb); 1404 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false; 1405 arcmsr_drain_donequeue(acb, pCCB, error); 1406 } 1407 } 1408 break; 1409 case ACB_ADAPTER_TYPE_D: { 1410 struct MessageUnit_D *pmu = acb->pmuD; 1411 uint32_t outbound_write_pointer; 1412 uint32_t doneq_index, index_stripped, addressLow, residual, toggle; 1413 unsigned long flags; 1414 1415 residual = atomic_read(&acb->ccboutstandingcount); 1416 for (i = 0; i < residual; i++) { 1417 spin_lock_irqsave(&acb->doneq_lock, flags); 1418 outbound_write_pointer = 1419 pmu->done_qbuffer[0].addressLow + 1; 1420 doneq_index = pmu->doneq_index; 1421 if ((doneq_index & 0xFFF) != 1422 (outbound_write_pointer & 0xFFF)) { 1423 toggle = doneq_index & 0x4000; 1424 index_stripped = (doneq_index & 0xFFF) + 1; 1425 index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE; 1426 pmu->doneq_index = index_stripped ? (index_stripped | toggle) : 1427 ((toggle ^ 0x4000) + 1); 1428 doneq_index = pmu->doneq_index; 1429 spin_unlock_irqrestore(&acb->doneq_lock, flags); 1430 addressLow = pmu->done_qbuffer[doneq_index & 1431 0xFFF].addressLow; 1432 ccb_cdb_phy = (addressLow & 0xFFFFFFF0); 1433 pARCMSR_CDB = (struct ARCMSR_CDB *) 1434 (acb->vir2phy_offset + ccb_cdb_phy); 1435 pCCB = container_of(pARCMSR_CDB, 1436 struct CommandControlBlock, arcmsr_cdb); 1437 error = (addressLow & 1438 ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? 1439 true : false; 1440 arcmsr_drain_donequeue(acb, pCCB, error); 1441 writel(doneq_index, 1442 pmu->outboundlist_read_pointer); 1443 } else { 1444 spin_unlock_irqrestore(&acb->doneq_lock, flags); 1445 mdelay(10); 1446 } 1447 } 1448 pmu->postq_index = 0; 1449 pmu->doneq_index = 0x40FF; 1450 } 1451 break; 1452 case ACB_ADAPTER_TYPE_E: 1453 arcmsr_hbaE_postqueue_isr(acb); 1454 break; 1455 } 1456 } 1457 1458 static void arcmsr_remove_scsi_devices(struct AdapterControlBlock *acb) 1459 { 1460 char *acb_dev_map = (char *)acb->device_map; 1461 int target, lun, i; 1462 struct scsi_device *psdev; 1463 struct CommandControlBlock *ccb; 1464 char temp; 1465 1466 for (i = 0; i < acb->maxFreeCCB; i++) { 1467 ccb = acb->pccb_pool[i]; 1468 if (ccb->startdone == ARCMSR_CCB_START) { 1469 ccb->pcmd->result = DID_NO_CONNECT << 16; 1470 arcmsr_pci_unmap_dma(ccb); 1471 ccb->pcmd->scsi_done(ccb->pcmd); 1472 } 1473 } 1474 for (target = 0; target < ARCMSR_MAX_TARGETID; target++) { 1475 temp = *acb_dev_map; 1476 if (temp) { 1477 for (lun = 0; lun < ARCMSR_MAX_TARGETLUN; lun++) { 1478 if (temp & 1) { 1479 psdev = scsi_device_lookup(acb->host, 1480 0, target, lun); 1481 if (psdev != NULL) { 1482 scsi_remove_device(psdev); 1483 scsi_device_put(psdev); 1484 } 1485 } 1486 temp >>= 1; 1487 } 1488 *acb_dev_map = 0; 1489 } 1490 acb_dev_map++; 1491 } 1492 } 1493 1494 static void arcmsr_free_pcidev(struct AdapterControlBlock *acb) 1495 { 1496 struct pci_dev *pdev; 1497 struct Scsi_Host *host; 1498 1499 host = acb->host; 1500 arcmsr_free_sysfs_attr(acb); 1501 scsi_remove_host(host); 1502 flush_work(&acb->arcmsr_do_message_isr_bh); 1503 del_timer_sync(&acb->eternal_timer); 1504 if (set_date_time) 1505 del_timer_sync(&acb->refresh_timer); 1506 pdev = acb->pdev; 1507 arcmsr_free_irq(pdev, acb); 1508 arcmsr_free_ccb_pool(acb); 1509 arcmsr_free_mu(acb); 1510 arcmsr_unmap_pciregion(acb); 1511 pci_release_regions(pdev); 1512 scsi_host_put(host); 1513 pci_disable_device(pdev); 1514 } 1515 1516 static void arcmsr_remove(struct pci_dev *pdev) 1517 { 1518 struct Scsi_Host *host = pci_get_drvdata(pdev); 1519 struct AdapterControlBlock *acb = 1520 (struct AdapterControlBlock *) host->hostdata; 1521 int poll_count = 0; 1522 uint16_t dev_id; 1523 1524 pci_read_config_word(pdev, PCI_DEVICE_ID, &dev_id); 1525 if (dev_id == 0xffff) { 1526 acb->acb_flags &= ~ACB_F_IOP_INITED; 1527 acb->acb_flags |= ACB_F_ADAPTER_REMOVED; 1528 arcmsr_remove_scsi_devices(acb); 1529 arcmsr_free_pcidev(acb); 1530 return; 1531 } 1532 arcmsr_free_sysfs_attr(acb); 1533 scsi_remove_host(host); 1534 flush_work(&acb->arcmsr_do_message_isr_bh); 1535 del_timer_sync(&acb->eternal_timer); 1536 if (set_date_time) 1537 del_timer_sync(&acb->refresh_timer); 1538 arcmsr_disable_outbound_ints(acb); 1539 arcmsr_stop_adapter_bgrb(acb); 1540 arcmsr_flush_adapter_cache(acb); 1541 acb->acb_flags |= ACB_F_SCSISTOPADAPTER; 1542 acb->acb_flags &= ~ACB_F_IOP_INITED; 1543 1544 for (poll_count = 0; poll_count < acb->maxOutstanding; poll_count++){ 1545 if (!atomic_read(&acb->ccboutstandingcount)) 1546 break; 1547 arcmsr_interrupt(acb);/* FIXME: need spinlock */ 1548 msleep(25); 1549 } 1550 1551 if (atomic_read(&acb->ccboutstandingcount)) { 1552 int i; 1553 1554 arcmsr_abort_allcmd(acb); 1555 arcmsr_done4abort_postqueue(acb); 1556 for (i = 0; i < acb->maxFreeCCB; i++) { 1557 struct CommandControlBlock *ccb = acb->pccb_pool[i]; 1558 if (ccb->startdone == ARCMSR_CCB_START) { 1559 ccb->startdone = ARCMSR_CCB_ABORTED; 1560 ccb->pcmd->result = DID_ABORT << 16; 1561 arcmsr_ccb_complete(ccb); 1562 } 1563 } 1564 } 1565 arcmsr_free_irq(pdev, acb); 1566 arcmsr_free_ccb_pool(acb); 1567 arcmsr_free_mu(acb); 1568 arcmsr_unmap_pciregion(acb); 1569 pci_release_regions(pdev); 1570 scsi_host_put(host); 1571 pci_disable_device(pdev); 1572 } 1573 1574 static void arcmsr_shutdown(struct pci_dev *pdev) 1575 { 1576 struct Scsi_Host *host = pci_get_drvdata(pdev); 1577 struct AdapterControlBlock *acb = 1578 (struct AdapterControlBlock *)host->hostdata; 1579 if (acb->acb_flags & ACB_F_ADAPTER_REMOVED) 1580 return; 1581 del_timer_sync(&acb->eternal_timer); 1582 if (set_date_time) 1583 del_timer_sync(&acb->refresh_timer); 1584 arcmsr_disable_outbound_ints(acb); 1585 arcmsr_free_irq(pdev, acb); 1586 flush_work(&acb->arcmsr_do_message_isr_bh); 1587 arcmsr_stop_adapter_bgrb(acb); 1588 arcmsr_flush_adapter_cache(acb); 1589 } 1590 1591 static int arcmsr_module_init(void) 1592 { 1593 int error = 0; 1594 error = pci_register_driver(&arcmsr_pci_driver); 1595 return error; 1596 } 1597 1598 static void arcmsr_module_exit(void) 1599 { 1600 pci_unregister_driver(&arcmsr_pci_driver); 1601 } 1602 module_init(arcmsr_module_init); 1603 module_exit(arcmsr_module_exit); 1604 1605 static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb, 1606 u32 intmask_org) 1607 { 1608 u32 mask; 1609 switch (acb->adapter_type) { 1610 1611 case ACB_ADAPTER_TYPE_A: { 1612 struct MessageUnit_A __iomem *reg = acb->pmuA; 1613 mask = intmask_org & ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE | 1614 ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE| 1615 ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE); 1616 writel(mask, ®->outbound_intmask); 1617 acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff; 1618 } 1619 break; 1620 1621 case ACB_ADAPTER_TYPE_B: { 1622 struct MessageUnit_B *reg = acb->pmuB; 1623 mask = intmask_org | (ARCMSR_IOP2DRV_DATA_WRITE_OK | 1624 ARCMSR_IOP2DRV_DATA_READ_OK | 1625 ARCMSR_IOP2DRV_CDB_DONE | 1626 ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); 1627 writel(mask, reg->iop2drv_doorbell_mask); 1628 acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f; 1629 } 1630 break; 1631 case ACB_ADAPTER_TYPE_C: { 1632 struct MessageUnit_C __iomem *reg = acb->pmuC; 1633 mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK|ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK); 1634 writel(intmask_org & mask, ®->host_int_mask); 1635 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f; 1636 } 1637 break; 1638 case ACB_ADAPTER_TYPE_D: { 1639 struct MessageUnit_D *reg = acb->pmuD; 1640 1641 mask = ARCMSR_ARC1214_ALL_INT_ENABLE; 1642 writel(intmask_org | mask, reg->pcief0_int_enable); 1643 break; 1644 } 1645 case ACB_ADAPTER_TYPE_E: { 1646 struct MessageUnit_E __iomem *reg = acb->pmuE; 1647 1648 mask = ~(ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR); 1649 writel(intmask_org & mask, ®->host_int_mask); 1650 break; 1651 } 1652 } 1653 } 1654 1655 static int arcmsr_build_ccb(struct AdapterControlBlock *acb, 1656 struct CommandControlBlock *ccb, struct scsi_cmnd *pcmd) 1657 { 1658 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb; 1659 int8_t *psge = (int8_t *)&arcmsr_cdb->u; 1660 __le32 address_lo, address_hi; 1661 int arccdbsize = 0x30; 1662 __le32 length = 0; 1663 int i; 1664 struct scatterlist *sg; 1665 int nseg; 1666 ccb->pcmd = pcmd; 1667 memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB)); 1668 arcmsr_cdb->TargetID = pcmd->device->id; 1669 arcmsr_cdb->LUN = pcmd->device->lun; 1670 arcmsr_cdb->Function = 1; 1671 arcmsr_cdb->msgContext = 0; 1672 memcpy(arcmsr_cdb->Cdb, pcmd->cmnd, pcmd->cmd_len); 1673 1674 nseg = scsi_dma_map(pcmd); 1675 if (unlikely(nseg > acb->host->sg_tablesize || nseg < 0)) 1676 return FAILED; 1677 scsi_for_each_sg(pcmd, sg, nseg, i) { 1678 /* Get the physical address of the current data pointer */ 1679 length = cpu_to_le32(sg_dma_len(sg)); 1680 address_lo = cpu_to_le32(dma_addr_lo32(sg_dma_address(sg))); 1681 address_hi = cpu_to_le32(dma_addr_hi32(sg_dma_address(sg))); 1682 if (address_hi == 0) { 1683 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge; 1684 1685 pdma_sg->address = address_lo; 1686 pdma_sg->length = length; 1687 psge += sizeof (struct SG32ENTRY); 1688 arccdbsize += sizeof (struct SG32ENTRY); 1689 } else { 1690 struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge; 1691 1692 pdma_sg->addresshigh = address_hi; 1693 pdma_sg->address = address_lo; 1694 pdma_sg->length = length|cpu_to_le32(IS_SG64_ADDR); 1695 psge += sizeof (struct SG64ENTRY); 1696 arccdbsize += sizeof (struct SG64ENTRY); 1697 } 1698 } 1699 arcmsr_cdb->sgcount = (uint8_t)nseg; 1700 arcmsr_cdb->DataLength = scsi_bufflen(pcmd); 1701 arcmsr_cdb->msgPages = arccdbsize/0x100 + (arccdbsize % 0x100 ? 1 : 0); 1702 if ( arccdbsize > 256) 1703 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE; 1704 if (pcmd->sc_data_direction == DMA_TO_DEVICE) 1705 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE; 1706 ccb->arc_cdb_size = arccdbsize; 1707 return SUCCESS; 1708 } 1709 1710 static void arcmsr_post_ccb(struct AdapterControlBlock *acb, struct CommandControlBlock *ccb) 1711 { 1712 uint32_t cdb_phyaddr = ccb->cdb_phyaddr; 1713 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb; 1714 atomic_inc(&acb->ccboutstandingcount); 1715 ccb->startdone = ARCMSR_CCB_START; 1716 switch (acb->adapter_type) { 1717 case ACB_ADAPTER_TYPE_A: { 1718 struct MessageUnit_A __iomem *reg = acb->pmuA; 1719 1720 if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) 1721 writel(cdb_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE, 1722 ®->inbound_queueport); 1723 else 1724 writel(cdb_phyaddr, ®->inbound_queueport); 1725 break; 1726 } 1727 1728 case ACB_ADAPTER_TYPE_B: { 1729 struct MessageUnit_B *reg = acb->pmuB; 1730 uint32_t ending_index, index = reg->postq_index; 1731 1732 ending_index = ((index + 1) % ARCMSR_MAX_HBB_POSTQUEUE); 1733 reg->post_qbuffer[ending_index] = 0; 1734 if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1735 reg->post_qbuffer[index] = 1736 cdb_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE; 1737 } else { 1738 reg->post_qbuffer[index] = cdb_phyaddr; 1739 } 1740 index++; 1741 index %= ARCMSR_MAX_HBB_POSTQUEUE;/*if last index number set it to 0 */ 1742 reg->postq_index = index; 1743 writel(ARCMSR_DRV2IOP_CDB_POSTED, reg->drv2iop_doorbell); 1744 } 1745 break; 1746 case ACB_ADAPTER_TYPE_C: { 1747 struct MessageUnit_C __iomem *phbcmu = acb->pmuC; 1748 uint32_t ccb_post_stamp, arc_cdb_size; 1749 1750 arc_cdb_size = (ccb->arc_cdb_size > 0x300) ? 0x300 : ccb->arc_cdb_size; 1751 ccb_post_stamp = (cdb_phyaddr | ((arc_cdb_size - 1) >> 6) | 1); 1752 if (acb->cdb_phyaddr_hi32) { 1753 writel(acb->cdb_phyaddr_hi32, &phbcmu->inbound_queueport_high); 1754 writel(ccb_post_stamp, &phbcmu->inbound_queueport_low); 1755 } else { 1756 writel(ccb_post_stamp, &phbcmu->inbound_queueport_low); 1757 } 1758 } 1759 break; 1760 case ACB_ADAPTER_TYPE_D: { 1761 struct MessageUnit_D *pmu = acb->pmuD; 1762 u16 index_stripped; 1763 u16 postq_index, toggle; 1764 unsigned long flags; 1765 struct InBound_SRB *pinbound_srb; 1766 1767 spin_lock_irqsave(&acb->postq_lock, flags); 1768 postq_index = pmu->postq_index; 1769 pinbound_srb = (struct InBound_SRB *)&(pmu->post_qbuffer[postq_index & 0xFF]); 1770 pinbound_srb->addressHigh = dma_addr_hi32(cdb_phyaddr); 1771 pinbound_srb->addressLow = dma_addr_lo32(cdb_phyaddr); 1772 pinbound_srb->length = ccb->arc_cdb_size >> 2; 1773 arcmsr_cdb->msgContext = dma_addr_lo32(cdb_phyaddr); 1774 toggle = postq_index & 0x4000; 1775 index_stripped = postq_index + 1; 1776 index_stripped &= (ARCMSR_MAX_ARC1214_POSTQUEUE - 1); 1777 pmu->postq_index = index_stripped ? (index_stripped | toggle) : 1778 (toggle ^ 0x4000); 1779 writel(postq_index, pmu->inboundlist_write_pointer); 1780 spin_unlock_irqrestore(&acb->postq_lock, flags); 1781 break; 1782 } 1783 case ACB_ADAPTER_TYPE_E: { 1784 struct MessageUnit_E __iomem *pmu = acb->pmuE; 1785 u32 ccb_post_stamp, arc_cdb_size; 1786 1787 arc_cdb_size = (ccb->arc_cdb_size > 0x300) ? 0x300 : ccb->arc_cdb_size; 1788 ccb_post_stamp = (ccb->smid | ((arc_cdb_size - 1) >> 6)); 1789 writel(0, &pmu->inbound_queueport_high); 1790 writel(ccb_post_stamp, &pmu->inbound_queueport_low); 1791 break; 1792 } 1793 } 1794 } 1795 1796 static void arcmsr_hbaA_stop_bgrb(struct AdapterControlBlock *acb) 1797 { 1798 struct MessageUnit_A __iomem *reg = acb->pmuA; 1799 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1800 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, ®->inbound_msgaddr0); 1801 if (!arcmsr_hbaA_wait_msgint_ready(acb)) { 1802 printk(KERN_NOTICE 1803 "arcmsr%d: wait 'stop adapter background rebuild' timeout\n" 1804 , acb->host->host_no); 1805 } 1806 } 1807 1808 static void arcmsr_hbaB_stop_bgrb(struct AdapterControlBlock *acb) 1809 { 1810 struct MessageUnit_B *reg = acb->pmuB; 1811 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1812 writel(ARCMSR_MESSAGE_STOP_BGRB, reg->drv2iop_doorbell); 1813 1814 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 1815 printk(KERN_NOTICE 1816 "arcmsr%d: wait 'stop adapter background rebuild' timeout\n" 1817 , acb->host->host_no); 1818 } 1819 } 1820 1821 static void arcmsr_hbaC_stop_bgrb(struct AdapterControlBlock *pACB) 1822 { 1823 struct MessageUnit_C __iomem *reg = pACB->pmuC; 1824 pACB->acb_flags &= ~ACB_F_MSG_START_BGRB; 1825 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, ®->inbound_msgaddr0); 1826 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell); 1827 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) { 1828 printk(KERN_NOTICE 1829 "arcmsr%d: wait 'stop adapter background rebuild' timeout\n" 1830 , pACB->host->host_no); 1831 } 1832 return; 1833 } 1834 1835 static void arcmsr_hbaD_stop_bgrb(struct AdapterControlBlock *pACB) 1836 { 1837 struct MessageUnit_D *reg = pACB->pmuD; 1838 1839 pACB->acb_flags &= ~ACB_F_MSG_START_BGRB; 1840 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, reg->inbound_msgaddr0); 1841 if (!arcmsr_hbaD_wait_msgint_ready(pACB)) 1842 pr_notice("arcmsr%d: wait 'stop adapter background rebuild' " 1843 "timeout\n", pACB->host->host_no); 1844 } 1845 1846 static void arcmsr_hbaE_stop_bgrb(struct AdapterControlBlock *pACB) 1847 { 1848 struct MessageUnit_E __iomem *reg = pACB->pmuE; 1849 1850 pACB->acb_flags &= ~ACB_F_MSG_START_BGRB; 1851 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, ®->inbound_msgaddr0); 1852 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 1853 writel(pACB->out_doorbell, ®->iobound_doorbell); 1854 if (!arcmsr_hbaE_wait_msgint_ready(pACB)) { 1855 pr_notice("arcmsr%d: wait 'stop adapter background rebuild' " 1856 "timeout\n", pACB->host->host_no); 1857 } 1858 } 1859 1860 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb) 1861 { 1862 switch (acb->adapter_type) { 1863 case ACB_ADAPTER_TYPE_A: { 1864 arcmsr_hbaA_stop_bgrb(acb); 1865 } 1866 break; 1867 1868 case ACB_ADAPTER_TYPE_B: { 1869 arcmsr_hbaB_stop_bgrb(acb); 1870 } 1871 break; 1872 case ACB_ADAPTER_TYPE_C: { 1873 arcmsr_hbaC_stop_bgrb(acb); 1874 } 1875 break; 1876 case ACB_ADAPTER_TYPE_D: 1877 arcmsr_hbaD_stop_bgrb(acb); 1878 break; 1879 case ACB_ADAPTER_TYPE_E: 1880 arcmsr_hbaE_stop_bgrb(acb); 1881 break; 1882 } 1883 } 1884 1885 static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb) 1886 { 1887 dma_free_coherent(&acb->pdev->dev, acb->uncache_size, acb->dma_coherent, acb->dma_coherent_handle); 1888 } 1889 1890 static void arcmsr_iop_message_read(struct AdapterControlBlock *acb) 1891 { 1892 switch (acb->adapter_type) { 1893 case ACB_ADAPTER_TYPE_A: { 1894 struct MessageUnit_A __iomem *reg = acb->pmuA; 1895 writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, ®->inbound_doorbell); 1896 } 1897 break; 1898 1899 case ACB_ADAPTER_TYPE_B: { 1900 struct MessageUnit_B *reg = acb->pmuB; 1901 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell); 1902 } 1903 break; 1904 case ACB_ADAPTER_TYPE_C: { 1905 struct MessageUnit_C __iomem *reg = acb->pmuC; 1906 1907 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, ®->inbound_doorbell); 1908 } 1909 break; 1910 case ACB_ADAPTER_TYPE_D: { 1911 struct MessageUnit_D *reg = acb->pmuD; 1912 writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ, 1913 reg->inbound_doorbell); 1914 } 1915 break; 1916 case ACB_ADAPTER_TYPE_E: { 1917 struct MessageUnit_E __iomem *reg = acb->pmuE; 1918 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK; 1919 writel(acb->out_doorbell, ®->iobound_doorbell); 1920 } 1921 break; 1922 } 1923 } 1924 1925 static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb) 1926 { 1927 switch (acb->adapter_type) { 1928 case ACB_ADAPTER_TYPE_A: { 1929 struct MessageUnit_A __iomem *reg = acb->pmuA; 1930 /* 1931 ** push inbound doorbell tell iop, driver data write ok 1932 ** and wait reply on next hwinterrupt for next Qbuffer post 1933 */ 1934 writel(ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK, ®->inbound_doorbell); 1935 } 1936 break; 1937 1938 case ACB_ADAPTER_TYPE_B: { 1939 struct MessageUnit_B *reg = acb->pmuB; 1940 /* 1941 ** push inbound doorbell tell iop, driver data write ok 1942 ** and wait reply on next hwinterrupt for next Qbuffer post 1943 */ 1944 writel(ARCMSR_DRV2IOP_DATA_WRITE_OK, reg->drv2iop_doorbell); 1945 } 1946 break; 1947 case ACB_ADAPTER_TYPE_C: { 1948 struct MessageUnit_C __iomem *reg = acb->pmuC; 1949 /* 1950 ** push inbound doorbell tell iop, driver data write ok 1951 ** and wait reply on next hwinterrupt for next Qbuffer post 1952 */ 1953 writel(ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK, ®->inbound_doorbell); 1954 } 1955 break; 1956 case ACB_ADAPTER_TYPE_D: { 1957 struct MessageUnit_D *reg = acb->pmuD; 1958 writel(ARCMSR_ARC1214_DRV2IOP_DATA_IN_READY, 1959 reg->inbound_doorbell); 1960 } 1961 break; 1962 case ACB_ADAPTER_TYPE_E: { 1963 struct MessageUnit_E __iomem *reg = acb->pmuE; 1964 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK; 1965 writel(acb->out_doorbell, ®->iobound_doorbell); 1966 } 1967 break; 1968 } 1969 } 1970 1971 struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *acb) 1972 { 1973 struct QBUFFER __iomem *qbuffer = NULL; 1974 switch (acb->adapter_type) { 1975 1976 case ACB_ADAPTER_TYPE_A: { 1977 struct MessageUnit_A __iomem *reg = acb->pmuA; 1978 qbuffer = (struct QBUFFER __iomem *)®->message_rbuffer; 1979 } 1980 break; 1981 1982 case ACB_ADAPTER_TYPE_B: { 1983 struct MessageUnit_B *reg = acb->pmuB; 1984 qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer; 1985 } 1986 break; 1987 case ACB_ADAPTER_TYPE_C: { 1988 struct MessageUnit_C __iomem *phbcmu = acb->pmuC; 1989 qbuffer = (struct QBUFFER __iomem *)&phbcmu->message_rbuffer; 1990 } 1991 break; 1992 case ACB_ADAPTER_TYPE_D: { 1993 struct MessageUnit_D *reg = acb->pmuD; 1994 qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer; 1995 } 1996 break; 1997 case ACB_ADAPTER_TYPE_E: { 1998 struct MessageUnit_E __iomem *reg = acb->pmuE; 1999 qbuffer = (struct QBUFFER __iomem *)®->message_rbuffer; 2000 } 2001 break; 2002 } 2003 return qbuffer; 2004 } 2005 2006 static struct QBUFFER __iomem *arcmsr_get_iop_wqbuffer(struct AdapterControlBlock *acb) 2007 { 2008 struct QBUFFER __iomem *pqbuffer = NULL; 2009 switch (acb->adapter_type) { 2010 2011 case ACB_ADAPTER_TYPE_A: { 2012 struct MessageUnit_A __iomem *reg = acb->pmuA; 2013 pqbuffer = (struct QBUFFER __iomem *) ®->message_wbuffer; 2014 } 2015 break; 2016 2017 case ACB_ADAPTER_TYPE_B: { 2018 struct MessageUnit_B *reg = acb->pmuB; 2019 pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer; 2020 } 2021 break; 2022 case ACB_ADAPTER_TYPE_C: { 2023 struct MessageUnit_C __iomem *reg = acb->pmuC; 2024 pqbuffer = (struct QBUFFER __iomem *)®->message_wbuffer; 2025 } 2026 break; 2027 case ACB_ADAPTER_TYPE_D: { 2028 struct MessageUnit_D *reg = acb->pmuD; 2029 pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer; 2030 } 2031 break; 2032 case ACB_ADAPTER_TYPE_E: { 2033 struct MessageUnit_E __iomem *reg = acb->pmuE; 2034 pqbuffer = (struct QBUFFER __iomem *)®->message_wbuffer; 2035 } 2036 break; 2037 } 2038 return pqbuffer; 2039 } 2040 2041 static uint32_t 2042 arcmsr_Read_iop_rqbuffer_in_DWORD(struct AdapterControlBlock *acb, 2043 struct QBUFFER __iomem *prbuffer) 2044 { 2045 uint8_t *pQbuffer; 2046 uint8_t *buf1 = NULL; 2047 uint32_t __iomem *iop_data; 2048 uint32_t iop_len, data_len, *buf2 = NULL; 2049 2050 iop_data = (uint32_t __iomem *)prbuffer->data; 2051 iop_len = readl(&prbuffer->data_len); 2052 if (iop_len > 0) { 2053 buf1 = kmalloc(128, GFP_ATOMIC); 2054 buf2 = (uint32_t *)buf1; 2055 if (buf1 == NULL) 2056 return 0; 2057 data_len = iop_len; 2058 while (data_len >= 4) { 2059 *buf2++ = readl(iop_data); 2060 iop_data++; 2061 data_len -= 4; 2062 } 2063 if (data_len) 2064 *buf2 = readl(iop_data); 2065 buf2 = (uint32_t *)buf1; 2066 } 2067 while (iop_len > 0) { 2068 pQbuffer = &acb->rqbuffer[acb->rqbuf_putIndex]; 2069 *pQbuffer = *buf1; 2070 acb->rqbuf_putIndex++; 2071 /* if last, index number set it to 0 */ 2072 acb->rqbuf_putIndex %= ARCMSR_MAX_QBUFFER; 2073 buf1++; 2074 iop_len--; 2075 } 2076 kfree(buf2); 2077 /* let IOP know data has been read */ 2078 arcmsr_iop_message_read(acb); 2079 return 1; 2080 } 2081 2082 uint32_t 2083 arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, 2084 struct QBUFFER __iomem *prbuffer) { 2085 2086 uint8_t *pQbuffer; 2087 uint8_t __iomem *iop_data; 2088 uint32_t iop_len; 2089 2090 if (acb->adapter_type > ACB_ADAPTER_TYPE_B) 2091 return arcmsr_Read_iop_rqbuffer_in_DWORD(acb, prbuffer); 2092 iop_data = (uint8_t __iomem *)prbuffer->data; 2093 iop_len = readl(&prbuffer->data_len); 2094 while (iop_len > 0) { 2095 pQbuffer = &acb->rqbuffer[acb->rqbuf_putIndex]; 2096 *pQbuffer = readb(iop_data); 2097 acb->rqbuf_putIndex++; 2098 acb->rqbuf_putIndex %= ARCMSR_MAX_QBUFFER; 2099 iop_data++; 2100 iop_len--; 2101 } 2102 arcmsr_iop_message_read(acb); 2103 return 1; 2104 } 2105 2106 static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb) 2107 { 2108 unsigned long flags; 2109 struct QBUFFER __iomem *prbuffer; 2110 int32_t buf_empty_len; 2111 2112 spin_lock_irqsave(&acb->rqbuffer_lock, flags); 2113 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2114 buf_empty_len = (acb->rqbuf_putIndex - acb->rqbuf_getIndex - 1) & 2115 (ARCMSR_MAX_QBUFFER - 1); 2116 if (buf_empty_len >= readl(&prbuffer->data_len)) { 2117 if (arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 2118 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2119 } else 2120 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2121 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags); 2122 } 2123 2124 static void arcmsr_write_ioctldata2iop_in_DWORD(struct AdapterControlBlock *acb) 2125 { 2126 uint8_t *pQbuffer; 2127 struct QBUFFER __iomem *pwbuffer; 2128 uint8_t *buf1 = NULL; 2129 uint32_t __iomem *iop_data; 2130 uint32_t allxfer_len = 0, data_len, *buf2 = NULL, data; 2131 2132 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) { 2133 buf1 = kmalloc(128, GFP_ATOMIC); 2134 buf2 = (uint32_t *)buf1; 2135 if (buf1 == NULL) 2136 return; 2137 2138 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED); 2139 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 2140 iop_data = (uint32_t __iomem *)pwbuffer->data; 2141 while ((acb->wqbuf_getIndex != acb->wqbuf_putIndex) 2142 && (allxfer_len < 124)) { 2143 pQbuffer = &acb->wqbuffer[acb->wqbuf_getIndex]; 2144 *buf1 = *pQbuffer; 2145 acb->wqbuf_getIndex++; 2146 acb->wqbuf_getIndex %= ARCMSR_MAX_QBUFFER; 2147 buf1++; 2148 allxfer_len++; 2149 } 2150 data_len = allxfer_len; 2151 buf1 = (uint8_t *)buf2; 2152 while (data_len >= 4) { 2153 data = *buf2++; 2154 writel(data, iop_data); 2155 iop_data++; 2156 data_len -= 4; 2157 } 2158 if (data_len) { 2159 data = *buf2; 2160 writel(data, iop_data); 2161 } 2162 writel(allxfer_len, &pwbuffer->data_len); 2163 kfree(buf1); 2164 arcmsr_iop_message_wrote(acb); 2165 } 2166 } 2167 2168 void 2169 arcmsr_write_ioctldata2iop(struct AdapterControlBlock *acb) 2170 { 2171 uint8_t *pQbuffer; 2172 struct QBUFFER __iomem *pwbuffer; 2173 uint8_t __iomem *iop_data; 2174 int32_t allxfer_len = 0; 2175 2176 if (acb->adapter_type > ACB_ADAPTER_TYPE_B) { 2177 arcmsr_write_ioctldata2iop_in_DWORD(acb); 2178 return; 2179 } 2180 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) { 2181 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED); 2182 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 2183 iop_data = (uint8_t __iomem *)pwbuffer->data; 2184 while ((acb->wqbuf_getIndex != acb->wqbuf_putIndex) 2185 && (allxfer_len < 124)) { 2186 pQbuffer = &acb->wqbuffer[acb->wqbuf_getIndex]; 2187 writeb(*pQbuffer, iop_data); 2188 acb->wqbuf_getIndex++; 2189 acb->wqbuf_getIndex %= ARCMSR_MAX_QBUFFER; 2190 iop_data++; 2191 allxfer_len++; 2192 } 2193 writel(allxfer_len, &pwbuffer->data_len); 2194 arcmsr_iop_message_wrote(acb); 2195 } 2196 } 2197 2198 static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb) 2199 { 2200 unsigned long flags; 2201 2202 spin_lock_irqsave(&acb->wqbuffer_lock, flags); 2203 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READED; 2204 if (acb->wqbuf_getIndex != acb->wqbuf_putIndex) 2205 arcmsr_write_ioctldata2iop(acb); 2206 if (acb->wqbuf_getIndex == acb->wqbuf_putIndex) 2207 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED; 2208 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags); 2209 } 2210 2211 static void arcmsr_hbaA_doorbell_isr(struct AdapterControlBlock *acb) 2212 { 2213 uint32_t outbound_doorbell; 2214 struct MessageUnit_A __iomem *reg = acb->pmuA; 2215 outbound_doorbell = readl(®->outbound_doorbell); 2216 do { 2217 writel(outbound_doorbell, ®->outbound_doorbell); 2218 if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) 2219 arcmsr_iop2drv_data_wrote_handle(acb); 2220 if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) 2221 arcmsr_iop2drv_data_read_handle(acb); 2222 outbound_doorbell = readl(®->outbound_doorbell); 2223 } while (outbound_doorbell & (ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 2224 | ARCMSR_OUTBOUND_IOP331_DATA_READ_OK)); 2225 } 2226 static void arcmsr_hbaC_doorbell_isr(struct AdapterControlBlock *pACB) 2227 { 2228 uint32_t outbound_doorbell; 2229 struct MessageUnit_C __iomem *reg = pACB->pmuC; 2230 /* 2231 ******************************************************************* 2232 ** Maybe here we need to check wrqbuffer_lock is lock or not 2233 ** DOORBELL: din! don! 2234 ** check if there are any mail need to pack from firmware 2235 ******************************************************************* 2236 */ 2237 outbound_doorbell = readl(®->outbound_doorbell); 2238 do { 2239 writel(outbound_doorbell, ®->outbound_doorbell_clear); 2240 readl(®->outbound_doorbell_clear); 2241 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) 2242 arcmsr_iop2drv_data_wrote_handle(pACB); 2243 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) 2244 arcmsr_iop2drv_data_read_handle(pACB); 2245 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) 2246 arcmsr_hbaC_message_isr(pACB); 2247 outbound_doorbell = readl(®->outbound_doorbell); 2248 } while (outbound_doorbell & (ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 2249 | ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 2250 | ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE)); 2251 } 2252 2253 static void arcmsr_hbaD_doorbell_isr(struct AdapterControlBlock *pACB) 2254 { 2255 uint32_t outbound_doorbell; 2256 struct MessageUnit_D *pmu = pACB->pmuD; 2257 2258 outbound_doorbell = readl(pmu->outbound_doorbell); 2259 do { 2260 writel(outbound_doorbell, pmu->outbound_doorbell); 2261 if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE) 2262 arcmsr_hbaD_message_isr(pACB); 2263 if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK) 2264 arcmsr_iop2drv_data_wrote_handle(pACB); 2265 if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK) 2266 arcmsr_iop2drv_data_read_handle(pACB); 2267 outbound_doorbell = readl(pmu->outbound_doorbell); 2268 } while (outbound_doorbell & (ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK 2269 | ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK 2270 | ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE)); 2271 } 2272 2273 static void arcmsr_hbaE_doorbell_isr(struct AdapterControlBlock *pACB) 2274 { 2275 uint32_t outbound_doorbell, in_doorbell, tmp; 2276 struct MessageUnit_E __iomem *reg = pACB->pmuE; 2277 2278 in_doorbell = readl(®->iobound_doorbell); 2279 outbound_doorbell = in_doorbell ^ pACB->in_doorbell; 2280 do { 2281 writel(0, ®->host_int_status); /* clear interrupt */ 2282 if (outbound_doorbell & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) { 2283 arcmsr_iop2drv_data_wrote_handle(pACB); 2284 } 2285 if (outbound_doorbell & ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK) { 2286 arcmsr_iop2drv_data_read_handle(pACB); 2287 } 2288 if (outbound_doorbell & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) { 2289 arcmsr_hbaE_message_isr(pACB); 2290 } 2291 tmp = in_doorbell; 2292 in_doorbell = readl(®->iobound_doorbell); 2293 outbound_doorbell = tmp ^ in_doorbell; 2294 } while (outbound_doorbell & (ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK 2295 | ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK 2296 | ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE)); 2297 pACB->in_doorbell = in_doorbell; 2298 } 2299 2300 static void arcmsr_hbaA_postqueue_isr(struct AdapterControlBlock *acb) 2301 { 2302 uint32_t flag_ccb; 2303 struct MessageUnit_A __iomem *reg = acb->pmuA; 2304 struct ARCMSR_CDB *pARCMSR_CDB; 2305 struct CommandControlBlock *pCCB; 2306 bool error; 2307 while ((flag_ccb = readl(®->outbound_queueport)) != 0xFFFFFFFF) { 2308 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));/*frame must be 32 bytes aligned*/ 2309 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb); 2310 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false; 2311 arcmsr_drain_donequeue(acb, pCCB, error); 2312 } 2313 } 2314 static void arcmsr_hbaB_postqueue_isr(struct AdapterControlBlock *acb) 2315 { 2316 uint32_t index; 2317 uint32_t flag_ccb; 2318 struct MessageUnit_B *reg = acb->pmuB; 2319 struct ARCMSR_CDB *pARCMSR_CDB; 2320 struct CommandControlBlock *pCCB; 2321 bool error; 2322 index = reg->doneq_index; 2323 while ((flag_ccb = reg->done_qbuffer[index]) != 0) { 2324 reg->done_qbuffer[index] = 0; 2325 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+(flag_ccb << 5));/*frame must be 32 bytes aligned*/ 2326 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb); 2327 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false; 2328 arcmsr_drain_donequeue(acb, pCCB, error); 2329 index++; 2330 index %= ARCMSR_MAX_HBB_POSTQUEUE; 2331 reg->doneq_index = index; 2332 } 2333 } 2334 2335 static void arcmsr_hbaC_postqueue_isr(struct AdapterControlBlock *acb) 2336 { 2337 struct MessageUnit_C __iomem *phbcmu; 2338 struct ARCMSR_CDB *arcmsr_cdb; 2339 struct CommandControlBlock *ccb; 2340 uint32_t flag_ccb, ccb_cdb_phy, throttling = 0; 2341 int error; 2342 2343 phbcmu = acb->pmuC; 2344 /* areca cdb command done */ 2345 /* Use correct offset and size for syncing */ 2346 2347 while ((flag_ccb = readl(&phbcmu->outbound_queueport_low)) != 2348 0xFFFFFFFF) { 2349 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0); 2350 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset 2351 + ccb_cdb_phy); 2352 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, 2353 arcmsr_cdb); 2354 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) 2355 ? true : false; 2356 /* check if command done with no error */ 2357 arcmsr_drain_donequeue(acb, ccb, error); 2358 throttling++; 2359 if (throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) { 2360 writel(ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING, 2361 &phbcmu->inbound_doorbell); 2362 throttling = 0; 2363 } 2364 } 2365 } 2366 2367 static void arcmsr_hbaD_postqueue_isr(struct AdapterControlBlock *acb) 2368 { 2369 u32 outbound_write_pointer, doneq_index, index_stripped, toggle; 2370 uint32_t addressLow, ccb_cdb_phy; 2371 int error; 2372 struct MessageUnit_D *pmu; 2373 struct ARCMSR_CDB *arcmsr_cdb; 2374 struct CommandControlBlock *ccb; 2375 unsigned long flags; 2376 2377 spin_lock_irqsave(&acb->doneq_lock, flags); 2378 pmu = acb->pmuD; 2379 outbound_write_pointer = pmu->done_qbuffer[0].addressLow + 1; 2380 doneq_index = pmu->doneq_index; 2381 if ((doneq_index & 0xFFF) != (outbound_write_pointer & 0xFFF)) { 2382 do { 2383 toggle = doneq_index & 0x4000; 2384 index_stripped = (doneq_index & 0xFFF) + 1; 2385 index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE; 2386 pmu->doneq_index = index_stripped ? (index_stripped | toggle) : 2387 ((toggle ^ 0x4000) + 1); 2388 doneq_index = pmu->doneq_index; 2389 addressLow = pmu->done_qbuffer[doneq_index & 2390 0xFFF].addressLow; 2391 ccb_cdb_phy = (addressLow & 0xFFFFFFF0); 2392 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset 2393 + ccb_cdb_phy); 2394 ccb = container_of(arcmsr_cdb, 2395 struct CommandControlBlock, arcmsr_cdb); 2396 error = (addressLow & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) 2397 ? true : false; 2398 arcmsr_drain_donequeue(acb, ccb, error); 2399 writel(doneq_index, pmu->outboundlist_read_pointer); 2400 } while ((doneq_index & 0xFFF) != 2401 (outbound_write_pointer & 0xFFF)); 2402 } 2403 writel(ARCMSR_ARC1214_OUTBOUND_LIST_INTERRUPT_CLEAR, 2404 pmu->outboundlist_interrupt_cause); 2405 readl(pmu->outboundlist_interrupt_cause); 2406 spin_unlock_irqrestore(&acb->doneq_lock, flags); 2407 } 2408 2409 static void arcmsr_hbaE_postqueue_isr(struct AdapterControlBlock *acb) 2410 { 2411 uint32_t doneq_index; 2412 uint16_t cmdSMID; 2413 int error; 2414 struct MessageUnit_E __iomem *pmu; 2415 struct CommandControlBlock *ccb; 2416 unsigned long flags; 2417 2418 spin_lock_irqsave(&acb->doneq_lock, flags); 2419 doneq_index = acb->doneq_index; 2420 pmu = acb->pmuE; 2421 while ((readl(&pmu->reply_post_producer_index) & 0xFFFF) != doneq_index) { 2422 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID; 2423 ccb = acb->pccb_pool[cmdSMID]; 2424 error = (acb->pCompletionQ[doneq_index].cmdFlag 2425 & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false; 2426 arcmsr_drain_donequeue(acb, ccb, error); 2427 doneq_index++; 2428 if (doneq_index >= acb->completionQ_entry) 2429 doneq_index = 0; 2430 } 2431 acb->doneq_index = doneq_index; 2432 writel(doneq_index, &pmu->reply_post_consumer_index); 2433 spin_unlock_irqrestore(&acb->doneq_lock, flags); 2434 } 2435 2436 /* 2437 ********************************************************************************** 2438 ** Handle a message interrupt 2439 ** 2440 ** The only message interrupt we expect is in response to a query for the current adapter config. 2441 ** We want this in order to compare the drivemap so that we can detect newly-attached drives. 2442 ********************************************************************************** 2443 */ 2444 static void arcmsr_hbaA_message_isr(struct AdapterControlBlock *acb) 2445 { 2446 struct MessageUnit_A __iomem *reg = acb->pmuA; 2447 /*clear interrupt and message state*/ 2448 writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT, ®->outbound_intstatus); 2449 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG) 2450 schedule_work(&acb->arcmsr_do_message_isr_bh); 2451 } 2452 static void arcmsr_hbaB_message_isr(struct AdapterControlBlock *acb) 2453 { 2454 struct MessageUnit_B *reg = acb->pmuB; 2455 2456 /*clear interrupt and message state*/ 2457 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); 2458 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG) 2459 schedule_work(&acb->arcmsr_do_message_isr_bh); 2460 } 2461 /* 2462 ********************************************************************************** 2463 ** Handle a message interrupt 2464 ** 2465 ** The only message interrupt we expect is in response to a query for the 2466 ** current adapter config. 2467 ** We want this in order to compare the drivemap so that we can detect newly-attached drives. 2468 ********************************************************************************** 2469 */ 2470 static void arcmsr_hbaC_message_isr(struct AdapterControlBlock *acb) 2471 { 2472 struct MessageUnit_C __iomem *reg = acb->pmuC; 2473 /*clear interrupt and message state*/ 2474 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, ®->outbound_doorbell_clear); 2475 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG) 2476 schedule_work(&acb->arcmsr_do_message_isr_bh); 2477 } 2478 2479 static void arcmsr_hbaD_message_isr(struct AdapterControlBlock *acb) 2480 { 2481 struct MessageUnit_D *reg = acb->pmuD; 2482 2483 writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE, reg->outbound_doorbell); 2484 readl(reg->outbound_doorbell); 2485 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG) 2486 schedule_work(&acb->arcmsr_do_message_isr_bh); 2487 } 2488 2489 static void arcmsr_hbaE_message_isr(struct AdapterControlBlock *acb) 2490 { 2491 struct MessageUnit_E __iomem *reg = acb->pmuE; 2492 2493 writel(0, ®->host_int_status); 2494 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG) 2495 schedule_work(&acb->arcmsr_do_message_isr_bh); 2496 } 2497 2498 static int arcmsr_hbaA_handle_isr(struct AdapterControlBlock *acb) 2499 { 2500 uint32_t outbound_intstatus; 2501 struct MessageUnit_A __iomem *reg = acb->pmuA; 2502 outbound_intstatus = readl(®->outbound_intstatus) & 2503 acb->outbound_int_enable; 2504 if (!(outbound_intstatus & ARCMSR_MU_OUTBOUND_HANDLE_INT)) 2505 return IRQ_NONE; 2506 do { 2507 writel(outbound_intstatus, ®->outbound_intstatus); 2508 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) 2509 arcmsr_hbaA_doorbell_isr(acb); 2510 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) 2511 arcmsr_hbaA_postqueue_isr(acb); 2512 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) 2513 arcmsr_hbaA_message_isr(acb); 2514 outbound_intstatus = readl(®->outbound_intstatus) & 2515 acb->outbound_int_enable; 2516 } while (outbound_intstatus & (ARCMSR_MU_OUTBOUND_DOORBELL_INT 2517 | ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 2518 | ARCMSR_MU_OUTBOUND_MESSAGE0_INT)); 2519 return IRQ_HANDLED; 2520 } 2521 2522 static int arcmsr_hbaB_handle_isr(struct AdapterControlBlock *acb) 2523 { 2524 uint32_t outbound_doorbell; 2525 struct MessageUnit_B *reg = acb->pmuB; 2526 outbound_doorbell = readl(reg->iop2drv_doorbell) & 2527 acb->outbound_int_enable; 2528 if (!outbound_doorbell) 2529 return IRQ_NONE; 2530 do { 2531 writel(~outbound_doorbell, reg->iop2drv_doorbell); 2532 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell); 2533 if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) 2534 arcmsr_iop2drv_data_wrote_handle(acb); 2535 if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) 2536 arcmsr_iop2drv_data_read_handle(acb); 2537 if (outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) 2538 arcmsr_hbaB_postqueue_isr(acb); 2539 if (outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) 2540 arcmsr_hbaB_message_isr(acb); 2541 outbound_doorbell = readl(reg->iop2drv_doorbell) & 2542 acb->outbound_int_enable; 2543 } while (outbound_doorbell & (ARCMSR_IOP2DRV_DATA_WRITE_OK 2544 | ARCMSR_IOP2DRV_DATA_READ_OK 2545 | ARCMSR_IOP2DRV_CDB_DONE 2546 | ARCMSR_IOP2DRV_MESSAGE_CMD_DONE)); 2547 return IRQ_HANDLED; 2548 } 2549 2550 static int arcmsr_hbaC_handle_isr(struct AdapterControlBlock *pACB) 2551 { 2552 uint32_t host_interrupt_status; 2553 struct MessageUnit_C __iomem *phbcmu = pACB->pmuC; 2554 /* 2555 ********************************************* 2556 ** check outbound intstatus 2557 ********************************************* 2558 */ 2559 host_interrupt_status = readl(&phbcmu->host_int_status) & 2560 (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | 2561 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR); 2562 if (!host_interrupt_status) 2563 return IRQ_NONE; 2564 do { 2565 if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) 2566 arcmsr_hbaC_doorbell_isr(pACB); 2567 /* MU post queue interrupts*/ 2568 if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) 2569 arcmsr_hbaC_postqueue_isr(pACB); 2570 host_interrupt_status = readl(&phbcmu->host_int_status); 2571 } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | 2572 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR)); 2573 return IRQ_HANDLED; 2574 } 2575 2576 static irqreturn_t arcmsr_hbaD_handle_isr(struct AdapterControlBlock *pACB) 2577 { 2578 u32 host_interrupt_status; 2579 struct MessageUnit_D *pmu = pACB->pmuD; 2580 2581 host_interrupt_status = readl(pmu->host_int_status) & 2582 (ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR | 2583 ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR); 2584 if (!host_interrupt_status) 2585 return IRQ_NONE; 2586 do { 2587 /* MU post queue interrupts*/ 2588 if (host_interrupt_status & 2589 ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR) 2590 arcmsr_hbaD_postqueue_isr(pACB); 2591 if (host_interrupt_status & 2592 ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR) 2593 arcmsr_hbaD_doorbell_isr(pACB); 2594 host_interrupt_status = readl(pmu->host_int_status); 2595 } while (host_interrupt_status & 2596 (ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR | 2597 ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR)); 2598 return IRQ_HANDLED; 2599 } 2600 2601 static irqreturn_t arcmsr_hbaE_handle_isr(struct AdapterControlBlock *pACB) 2602 { 2603 uint32_t host_interrupt_status; 2604 struct MessageUnit_E __iomem *pmu = pACB->pmuE; 2605 2606 host_interrupt_status = readl(&pmu->host_int_status) & 2607 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | 2608 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR); 2609 if (!host_interrupt_status) 2610 return IRQ_NONE; 2611 do { 2612 /* MU ioctl transfer doorbell interrupts*/ 2613 if (host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) { 2614 arcmsr_hbaE_doorbell_isr(pACB); 2615 } 2616 /* MU post queue interrupts*/ 2617 if (host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) { 2618 arcmsr_hbaE_postqueue_isr(pACB); 2619 } 2620 host_interrupt_status = readl(&pmu->host_int_status); 2621 } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | 2622 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR)); 2623 return IRQ_HANDLED; 2624 } 2625 2626 static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb) 2627 { 2628 switch (acb->adapter_type) { 2629 case ACB_ADAPTER_TYPE_A: 2630 return arcmsr_hbaA_handle_isr(acb); 2631 break; 2632 case ACB_ADAPTER_TYPE_B: 2633 return arcmsr_hbaB_handle_isr(acb); 2634 break; 2635 case ACB_ADAPTER_TYPE_C: 2636 return arcmsr_hbaC_handle_isr(acb); 2637 case ACB_ADAPTER_TYPE_D: 2638 return arcmsr_hbaD_handle_isr(acb); 2639 case ACB_ADAPTER_TYPE_E: 2640 return arcmsr_hbaE_handle_isr(acb); 2641 default: 2642 return IRQ_NONE; 2643 } 2644 } 2645 2646 static void arcmsr_iop_parking(struct AdapterControlBlock *acb) 2647 { 2648 if (acb) { 2649 /* stop adapter background rebuild */ 2650 if (acb->acb_flags & ACB_F_MSG_START_BGRB) { 2651 uint32_t intmask_org; 2652 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 2653 intmask_org = arcmsr_disable_outbound_ints(acb); 2654 arcmsr_stop_adapter_bgrb(acb); 2655 arcmsr_flush_adapter_cache(acb); 2656 arcmsr_enable_outbound_ints(acb, intmask_org); 2657 } 2658 } 2659 } 2660 2661 2662 void arcmsr_clear_iop2drv_rqueue_buffer(struct AdapterControlBlock *acb) 2663 { 2664 uint32_t i; 2665 2666 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2667 for (i = 0; i < 15; i++) { 2668 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2669 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2670 acb->rqbuf_getIndex = 0; 2671 acb->rqbuf_putIndex = 0; 2672 arcmsr_iop_message_read(acb); 2673 mdelay(30); 2674 } else if (acb->rqbuf_getIndex != 2675 acb->rqbuf_putIndex) { 2676 acb->rqbuf_getIndex = 0; 2677 acb->rqbuf_putIndex = 0; 2678 mdelay(30); 2679 } else 2680 break; 2681 } 2682 } 2683 } 2684 2685 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, 2686 struct scsi_cmnd *cmd) 2687 { 2688 char *buffer; 2689 unsigned short use_sg; 2690 int retvalue = 0, transfer_len = 0; 2691 unsigned long flags; 2692 struct CMD_MESSAGE_FIELD *pcmdmessagefld; 2693 uint32_t controlcode = (uint32_t)cmd->cmnd[5] << 24 | 2694 (uint32_t)cmd->cmnd[6] << 16 | 2695 (uint32_t)cmd->cmnd[7] << 8 | 2696 (uint32_t)cmd->cmnd[8]; 2697 struct scatterlist *sg; 2698 2699 use_sg = scsi_sg_count(cmd); 2700 sg = scsi_sglist(cmd); 2701 buffer = kmap_atomic(sg_page(sg)) + sg->offset; 2702 if (use_sg > 1) { 2703 retvalue = ARCMSR_MESSAGE_FAIL; 2704 goto message_out; 2705 } 2706 transfer_len += sg->length; 2707 if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) { 2708 retvalue = ARCMSR_MESSAGE_FAIL; 2709 pr_info("%s: ARCMSR_MESSAGE_FAIL!\n", __func__); 2710 goto message_out; 2711 } 2712 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *)buffer; 2713 switch (controlcode) { 2714 case ARCMSR_MESSAGE_READ_RQBUFFER: { 2715 unsigned char *ver_addr; 2716 uint8_t *ptmpQbuffer; 2717 uint32_t allxfer_len = 0; 2718 ver_addr = kmalloc(ARCMSR_API_DATA_BUFLEN, GFP_ATOMIC); 2719 if (!ver_addr) { 2720 retvalue = ARCMSR_MESSAGE_FAIL; 2721 pr_info("%s: memory not enough!\n", __func__); 2722 goto message_out; 2723 } 2724 ptmpQbuffer = ver_addr; 2725 spin_lock_irqsave(&acb->rqbuffer_lock, flags); 2726 if (acb->rqbuf_getIndex != acb->rqbuf_putIndex) { 2727 unsigned int tail = acb->rqbuf_getIndex; 2728 unsigned int head = acb->rqbuf_putIndex; 2729 unsigned int cnt_to_end = CIRC_CNT_TO_END(head, tail, ARCMSR_MAX_QBUFFER); 2730 2731 allxfer_len = CIRC_CNT(head, tail, ARCMSR_MAX_QBUFFER); 2732 if (allxfer_len > ARCMSR_API_DATA_BUFLEN) 2733 allxfer_len = ARCMSR_API_DATA_BUFLEN; 2734 2735 if (allxfer_len <= cnt_to_end) 2736 memcpy(ptmpQbuffer, acb->rqbuffer + tail, allxfer_len); 2737 else { 2738 memcpy(ptmpQbuffer, acb->rqbuffer + tail, cnt_to_end); 2739 memcpy(ptmpQbuffer + cnt_to_end, acb->rqbuffer, allxfer_len - cnt_to_end); 2740 } 2741 acb->rqbuf_getIndex = (acb->rqbuf_getIndex + allxfer_len) % ARCMSR_MAX_QBUFFER; 2742 } 2743 memcpy(pcmdmessagefld->messagedatabuffer, ver_addr, 2744 allxfer_len); 2745 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2746 struct QBUFFER __iomem *prbuffer; 2747 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2748 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2749 if (arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 2750 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2751 } 2752 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags); 2753 kfree(ver_addr); 2754 pcmdmessagefld->cmdmessage.Length = allxfer_len; 2755 if (acb->fw_flag == FW_DEADLOCK) 2756 pcmdmessagefld->cmdmessage.ReturnCode = 2757 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON; 2758 else 2759 pcmdmessagefld->cmdmessage.ReturnCode = 2760 ARCMSR_MESSAGE_RETURNCODE_OK; 2761 break; 2762 } 2763 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 2764 unsigned char *ver_addr; 2765 uint32_t user_len; 2766 int32_t cnt2end; 2767 uint8_t *pQbuffer, *ptmpuserbuffer; 2768 2769 user_len = pcmdmessagefld->cmdmessage.Length; 2770 if (user_len > ARCMSR_API_DATA_BUFLEN) { 2771 retvalue = ARCMSR_MESSAGE_FAIL; 2772 goto message_out; 2773 } 2774 2775 ver_addr = kmalloc(ARCMSR_API_DATA_BUFLEN, GFP_ATOMIC); 2776 if (!ver_addr) { 2777 retvalue = ARCMSR_MESSAGE_FAIL; 2778 goto message_out; 2779 } 2780 ptmpuserbuffer = ver_addr; 2781 2782 memcpy(ptmpuserbuffer, 2783 pcmdmessagefld->messagedatabuffer, user_len); 2784 spin_lock_irqsave(&acb->wqbuffer_lock, flags); 2785 if (acb->wqbuf_putIndex != acb->wqbuf_getIndex) { 2786 struct SENSE_DATA *sensebuffer = 2787 (struct SENSE_DATA *)cmd->sense_buffer; 2788 arcmsr_write_ioctldata2iop(acb); 2789 /* has error report sensedata */ 2790 sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS; 2791 sensebuffer->SenseKey = ILLEGAL_REQUEST; 2792 sensebuffer->AdditionalSenseLength = 0x0A; 2793 sensebuffer->AdditionalSenseCode = 0x20; 2794 sensebuffer->Valid = 1; 2795 retvalue = ARCMSR_MESSAGE_FAIL; 2796 } else { 2797 pQbuffer = &acb->wqbuffer[acb->wqbuf_putIndex]; 2798 cnt2end = ARCMSR_MAX_QBUFFER - acb->wqbuf_putIndex; 2799 if (user_len > cnt2end) { 2800 memcpy(pQbuffer, ptmpuserbuffer, cnt2end); 2801 ptmpuserbuffer += cnt2end; 2802 user_len -= cnt2end; 2803 acb->wqbuf_putIndex = 0; 2804 pQbuffer = acb->wqbuffer; 2805 } 2806 memcpy(pQbuffer, ptmpuserbuffer, user_len); 2807 acb->wqbuf_putIndex += user_len; 2808 acb->wqbuf_putIndex %= ARCMSR_MAX_QBUFFER; 2809 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 2810 acb->acb_flags &= 2811 ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 2812 arcmsr_write_ioctldata2iop(acb); 2813 } 2814 } 2815 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags); 2816 kfree(ver_addr); 2817 if (acb->fw_flag == FW_DEADLOCK) 2818 pcmdmessagefld->cmdmessage.ReturnCode = 2819 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON; 2820 else 2821 pcmdmessagefld->cmdmessage.ReturnCode = 2822 ARCMSR_MESSAGE_RETURNCODE_OK; 2823 break; 2824 } 2825 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 2826 uint8_t *pQbuffer = acb->rqbuffer; 2827 2828 arcmsr_clear_iop2drv_rqueue_buffer(acb); 2829 spin_lock_irqsave(&acb->rqbuffer_lock, flags); 2830 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2831 acb->rqbuf_getIndex = 0; 2832 acb->rqbuf_putIndex = 0; 2833 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2834 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags); 2835 if (acb->fw_flag == FW_DEADLOCK) 2836 pcmdmessagefld->cmdmessage.ReturnCode = 2837 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON; 2838 else 2839 pcmdmessagefld->cmdmessage.ReturnCode = 2840 ARCMSR_MESSAGE_RETURNCODE_OK; 2841 break; 2842 } 2843 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: { 2844 uint8_t *pQbuffer = acb->wqbuffer; 2845 spin_lock_irqsave(&acb->wqbuffer_lock, flags); 2846 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED | 2847 ACB_F_MESSAGE_WQBUFFER_READED); 2848 acb->wqbuf_getIndex = 0; 2849 acb->wqbuf_putIndex = 0; 2850 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2851 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags); 2852 if (acb->fw_flag == FW_DEADLOCK) 2853 pcmdmessagefld->cmdmessage.ReturnCode = 2854 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON; 2855 else 2856 pcmdmessagefld->cmdmessage.ReturnCode = 2857 ARCMSR_MESSAGE_RETURNCODE_OK; 2858 break; 2859 } 2860 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 2861 uint8_t *pQbuffer; 2862 arcmsr_clear_iop2drv_rqueue_buffer(acb); 2863 spin_lock_irqsave(&acb->rqbuffer_lock, flags); 2864 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2865 acb->rqbuf_getIndex = 0; 2866 acb->rqbuf_putIndex = 0; 2867 pQbuffer = acb->rqbuffer; 2868 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2869 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags); 2870 spin_lock_irqsave(&acb->wqbuffer_lock, flags); 2871 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED | 2872 ACB_F_MESSAGE_WQBUFFER_READED); 2873 acb->wqbuf_getIndex = 0; 2874 acb->wqbuf_putIndex = 0; 2875 pQbuffer = acb->wqbuffer; 2876 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2877 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags); 2878 if (acb->fw_flag == FW_DEADLOCK) 2879 pcmdmessagefld->cmdmessage.ReturnCode = 2880 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON; 2881 else 2882 pcmdmessagefld->cmdmessage.ReturnCode = 2883 ARCMSR_MESSAGE_RETURNCODE_OK; 2884 break; 2885 } 2886 case ARCMSR_MESSAGE_RETURN_CODE_3F: { 2887 if (acb->fw_flag == FW_DEADLOCK) 2888 pcmdmessagefld->cmdmessage.ReturnCode = 2889 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON; 2890 else 2891 pcmdmessagefld->cmdmessage.ReturnCode = 2892 ARCMSR_MESSAGE_RETURNCODE_3F; 2893 break; 2894 } 2895 case ARCMSR_MESSAGE_SAY_HELLO: { 2896 int8_t *hello_string = "Hello! I am ARCMSR"; 2897 if (acb->fw_flag == FW_DEADLOCK) 2898 pcmdmessagefld->cmdmessage.ReturnCode = 2899 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON; 2900 else 2901 pcmdmessagefld->cmdmessage.ReturnCode = 2902 ARCMSR_MESSAGE_RETURNCODE_OK; 2903 memcpy(pcmdmessagefld->messagedatabuffer, 2904 hello_string, (int16_t)strlen(hello_string)); 2905 break; 2906 } 2907 case ARCMSR_MESSAGE_SAY_GOODBYE: { 2908 if (acb->fw_flag == FW_DEADLOCK) 2909 pcmdmessagefld->cmdmessage.ReturnCode = 2910 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON; 2911 else 2912 pcmdmessagefld->cmdmessage.ReturnCode = 2913 ARCMSR_MESSAGE_RETURNCODE_OK; 2914 arcmsr_iop_parking(acb); 2915 break; 2916 } 2917 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: { 2918 if (acb->fw_flag == FW_DEADLOCK) 2919 pcmdmessagefld->cmdmessage.ReturnCode = 2920 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON; 2921 else 2922 pcmdmessagefld->cmdmessage.ReturnCode = 2923 ARCMSR_MESSAGE_RETURNCODE_OK; 2924 arcmsr_flush_adapter_cache(acb); 2925 break; 2926 } 2927 default: 2928 retvalue = ARCMSR_MESSAGE_FAIL; 2929 pr_info("%s: unknown controlcode!\n", __func__); 2930 } 2931 message_out: 2932 if (use_sg) { 2933 struct scatterlist *sg = scsi_sglist(cmd); 2934 kunmap_atomic(buffer - sg->offset); 2935 } 2936 return retvalue; 2937 } 2938 2939 static struct CommandControlBlock *arcmsr_get_freeccb(struct AdapterControlBlock *acb) 2940 { 2941 struct list_head *head = &acb->ccb_free_list; 2942 struct CommandControlBlock *ccb = NULL; 2943 unsigned long flags; 2944 spin_lock_irqsave(&acb->ccblist_lock, flags); 2945 if (!list_empty(head)) { 2946 ccb = list_entry(head->next, struct CommandControlBlock, list); 2947 list_del_init(&ccb->list); 2948 }else{ 2949 spin_unlock_irqrestore(&acb->ccblist_lock, flags); 2950 return NULL; 2951 } 2952 spin_unlock_irqrestore(&acb->ccblist_lock, flags); 2953 return ccb; 2954 } 2955 2956 static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb, 2957 struct scsi_cmnd *cmd) 2958 { 2959 switch (cmd->cmnd[0]) { 2960 case INQUIRY: { 2961 unsigned char inqdata[36]; 2962 char *buffer; 2963 struct scatterlist *sg; 2964 2965 if (cmd->device->lun) { 2966 cmd->result = (DID_TIME_OUT << 16); 2967 cmd->scsi_done(cmd); 2968 return; 2969 } 2970 inqdata[0] = TYPE_PROCESSOR; 2971 /* Periph Qualifier & Periph Dev Type */ 2972 inqdata[1] = 0; 2973 /* rem media bit & Dev Type Modifier */ 2974 inqdata[2] = 0; 2975 /* ISO, ECMA, & ANSI versions */ 2976 inqdata[4] = 31; 2977 /* length of additional data */ 2978 strncpy(&inqdata[8], "Areca ", 8); 2979 /* Vendor Identification */ 2980 strncpy(&inqdata[16], "RAID controller ", 16); 2981 /* Product Identification */ 2982 strncpy(&inqdata[32], "R001", 4); /* Product Revision */ 2983 2984 sg = scsi_sglist(cmd); 2985 buffer = kmap_atomic(sg_page(sg)) + sg->offset; 2986 2987 memcpy(buffer, inqdata, sizeof(inqdata)); 2988 sg = scsi_sglist(cmd); 2989 kunmap_atomic(buffer - sg->offset); 2990 2991 cmd->scsi_done(cmd); 2992 } 2993 break; 2994 case WRITE_BUFFER: 2995 case READ_BUFFER: { 2996 if (arcmsr_iop_message_xfer(acb, cmd)) 2997 cmd->result = (DID_ERROR << 16); 2998 cmd->scsi_done(cmd); 2999 } 3000 break; 3001 default: 3002 cmd->scsi_done(cmd); 3003 } 3004 } 3005 3006 static int arcmsr_queue_command_lck(struct scsi_cmnd *cmd, 3007 void (* done)(struct scsi_cmnd *)) 3008 { 3009 struct Scsi_Host *host = cmd->device->host; 3010 struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata; 3011 struct CommandControlBlock *ccb; 3012 int target = cmd->device->id; 3013 3014 if (acb->acb_flags & ACB_F_ADAPTER_REMOVED) { 3015 cmd->result = (DID_NO_CONNECT << 16); 3016 cmd->scsi_done(cmd); 3017 return 0; 3018 } 3019 cmd->scsi_done = done; 3020 cmd->host_scribble = NULL; 3021 cmd->result = 0; 3022 if (target == 16) { 3023 /* virtual device for iop message transfer */ 3024 arcmsr_handle_virtual_command(acb, cmd); 3025 return 0; 3026 } 3027 ccb = arcmsr_get_freeccb(acb); 3028 if (!ccb) 3029 return SCSI_MLQUEUE_HOST_BUSY; 3030 if (arcmsr_build_ccb( acb, ccb, cmd ) == FAILED) { 3031 cmd->result = (DID_ERROR << 16) | (RESERVATION_CONFLICT << 1); 3032 cmd->scsi_done(cmd); 3033 return 0; 3034 } 3035 arcmsr_post_ccb(acb, ccb); 3036 return 0; 3037 } 3038 3039 static DEF_SCSI_QCMD(arcmsr_queue_command) 3040 3041 static void arcmsr_get_adapter_config(struct AdapterControlBlock *pACB, uint32_t *rwbuffer) 3042 { 3043 int count; 3044 uint32_t *acb_firm_model = (uint32_t *)pACB->firm_model; 3045 uint32_t *acb_firm_version = (uint32_t *)pACB->firm_version; 3046 uint32_t *acb_device_map = (uint32_t *)pACB->device_map; 3047 uint32_t *firm_model = &rwbuffer[15]; 3048 uint32_t *firm_version = &rwbuffer[17]; 3049 uint32_t *device_map = &rwbuffer[21]; 3050 3051 count = 2; 3052 while (count) { 3053 *acb_firm_model = readl(firm_model); 3054 acb_firm_model++; 3055 firm_model++; 3056 count--; 3057 } 3058 count = 4; 3059 while (count) { 3060 *acb_firm_version = readl(firm_version); 3061 acb_firm_version++; 3062 firm_version++; 3063 count--; 3064 } 3065 count = 4; 3066 while (count) { 3067 *acb_device_map = readl(device_map); 3068 acb_device_map++; 3069 device_map++; 3070 count--; 3071 } 3072 pACB->signature = readl(&rwbuffer[0]); 3073 pACB->firm_request_len = readl(&rwbuffer[1]); 3074 pACB->firm_numbers_queue = readl(&rwbuffer[2]); 3075 pACB->firm_sdram_size = readl(&rwbuffer[3]); 3076 pACB->firm_hd_channels = readl(&rwbuffer[4]); 3077 pACB->firm_cfg_version = readl(&rwbuffer[25]); 3078 pr_notice("Areca RAID Controller%d: Model %s, F/W %s\n", 3079 pACB->host->host_no, 3080 pACB->firm_model, 3081 pACB->firm_version); 3082 } 3083 3084 static bool arcmsr_hbaA_get_config(struct AdapterControlBlock *acb) 3085 { 3086 struct MessageUnit_A __iomem *reg = acb->pmuA; 3087 3088 arcmsr_wait_firmware_ready(acb); 3089 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0); 3090 if (!arcmsr_hbaA_wait_msgint_ready(acb)) { 3091 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \ 3092 miscellaneous data' timeout \n", acb->host->host_no); 3093 return false; 3094 } 3095 arcmsr_get_adapter_config(acb, reg->message_rwbuffer); 3096 return true; 3097 } 3098 static bool arcmsr_hbaB_get_config(struct AdapterControlBlock *acb) 3099 { 3100 struct MessageUnit_B *reg = acb->pmuB; 3101 3102 arcmsr_wait_firmware_ready(acb); 3103 writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell); 3104 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 3105 printk(KERN_ERR "arcmsr%d: can't set driver mode.\n", acb->host->host_no); 3106 return false; 3107 } 3108 writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell); 3109 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 3110 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \ 3111 miscellaneous data' timeout \n", acb->host->host_no); 3112 return false; 3113 } 3114 arcmsr_get_adapter_config(acb, reg->message_rwbuffer); 3115 return true; 3116 } 3117 3118 static bool arcmsr_hbaC_get_config(struct AdapterControlBlock *pACB) 3119 { 3120 uint32_t intmask_org; 3121 struct MessageUnit_C __iomem *reg = pACB->pmuC; 3122 3123 /* disable all outbound interrupt */ 3124 intmask_org = readl(®->host_int_mask); /* disable outbound message0 int */ 3125 writel(intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE, ®->host_int_mask); 3126 /* wait firmware ready */ 3127 arcmsr_wait_firmware_ready(pACB); 3128 /* post "get config" instruction */ 3129 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0); 3130 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell); 3131 /* wait message ready */ 3132 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) { 3133 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \ 3134 miscellaneous data' timeout \n", pACB->host->host_no); 3135 return false; 3136 } 3137 arcmsr_get_adapter_config(pACB, reg->msgcode_rwbuffer); 3138 return true; 3139 } 3140 3141 static bool arcmsr_hbaD_get_config(struct AdapterControlBlock *acb) 3142 { 3143 struct MessageUnit_D *reg = acb->pmuD; 3144 3145 if (readl(acb->pmuD->outbound_doorbell) & 3146 ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE) { 3147 writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE, 3148 acb->pmuD->outbound_doorbell);/*clear interrupt*/ 3149 } 3150 arcmsr_wait_firmware_ready(acb); 3151 /* post "get config" instruction */ 3152 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, reg->inbound_msgaddr0); 3153 /* wait message ready */ 3154 if (!arcmsr_hbaD_wait_msgint_ready(acb)) { 3155 pr_notice("arcmsr%d: wait get adapter firmware " 3156 "miscellaneous data timeout\n", acb->host->host_no); 3157 return false; 3158 } 3159 arcmsr_get_adapter_config(acb, reg->msgcode_rwbuffer); 3160 return true; 3161 } 3162 3163 static bool arcmsr_hbaE_get_config(struct AdapterControlBlock *pACB) 3164 { 3165 struct MessageUnit_E __iomem *reg = pACB->pmuE; 3166 uint32_t intmask_org; 3167 3168 /* disable all outbound interrupt */ 3169 intmask_org = readl(®->host_int_mask); /* disable outbound message0 int */ 3170 writel(intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE, ®->host_int_mask); 3171 /* wait firmware ready */ 3172 arcmsr_wait_firmware_ready(pACB); 3173 mdelay(20); 3174 /* post "get config" instruction */ 3175 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0); 3176 3177 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 3178 writel(pACB->out_doorbell, ®->iobound_doorbell); 3179 /* wait message ready */ 3180 if (!arcmsr_hbaE_wait_msgint_ready(pACB)) { 3181 pr_notice("arcmsr%d: wait get adapter firmware " 3182 "miscellaneous data timeout\n", pACB->host->host_no); 3183 return false; 3184 } 3185 arcmsr_get_adapter_config(pACB, reg->msgcode_rwbuffer); 3186 return true; 3187 } 3188 3189 static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb) 3190 { 3191 bool rtn = false; 3192 3193 switch (acb->adapter_type) { 3194 case ACB_ADAPTER_TYPE_A: 3195 rtn = arcmsr_hbaA_get_config(acb); 3196 break; 3197 case ACB_ADAPTER_TYPE_B: 3198 rtn = arcmsr_hbaB_get_config(acb); 3199 break; 3200 case ACB_ADAPTER_TYPE_C: 3201 rtn = arcmsr_hbaC_get_config(acb); 3202 break; 3203 case ACB_ADAPTER_TYPE_D: 3204 rtn = arcmsr_hbaD_get_config(acb); 3205 break; 3206 case ACB_ADAPTER_TYPE_E: 3207 rtn = arcmsr_hbaE_get_config(acb); 3208 break; 3209 default: 3210 break; 3211 } 3212 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3213 if (acb->host->can_queue >= acb->firm_numbers_queue) 3214 acb->host->can_queue = acb->maxOutstanding; 3215 else 3216 acb->maxOutstanding = acb->host->can_queue; 3217 acb->maxFreeCCB = acb->host->can_queue; 3218 if (acb->maxFreeCCB < ARCMSR_MAX_FREECCB_NUM) 3219 acb->maxFreeCCB += 64; 3220 return rtn; 3221 } 3222 3223 static int arcmsr_hbaA_polling_ccbdone(struct AdapterControlBlock *acb, 3224 struct CommandControlBlock *poll_ccb) 3225 { 3226 struct MessageUnit_A __iomem *reg = acb->pmuA; 3227 struct CommandControlBlock *ccb; 3228 struct ARCMSR_CDB *arcmsr_cdb; 3229 uint32_t flag_ccb, outbound_intstatus, poll_ccb_done = 0, poll_count = 0; 3230 int rtn; 3231 bool error; 3232 polling_hba_ccb_retry: 3233 poll_count++; 3234 outbound_intstatus = readl(®->outbound_intstatus) & acb->outbound_int_enable; 3235 writel(outbound_intstatus, ®->outbound_intstatus);/*clear interrupt*/ 3236 while (1) { 3237 if ((flag_ccb = readl(®->outbound_queueport)) == 0xFFFFFFFF) { 3238 if (poll_ccb_done){ 3239 rtn = SUCCESS; 3240 break; 3241 }else { 3242 msleep(25); 3243 if (poll_count > 100){ 3244 rtn = FAILED; 3245 break; 3246 } 3247 goto polling_hba_ccb_retry; 3248 } 3249 } 3250 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5)); 3251 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb); 3252 poll_ccb_done |= (ccb == poll_ccb) ? 1 : 0; 3253 if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) { 3254 if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) { 3255 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'" 3256 " poll command abort successfully \n" 3257 , acb->host->host_no 3258 , ccb->pcmd->device->id 3259 , (u32)ccb->pcmd->device->lun 3260 , ccb); 3261 ccb->pcmd->result = DID_ABORT << 16; 3262 arcmsr_ccb_complete(ccb); 3263 continue; 3264 } 3265 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb" 3266 " command done ccb = '0x%p'" 3267 "ccboutstandingcount = %d \n" 3268 , acb->host->host_no 3269 , ccb 3270 , atomic_read(&acb->ccboutstandingcount)); 3271 continue; 3272 } 3273 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false; 3274 arcmsr_report_ccb_state(acb, ccb, error); 3275 } 3276 return rtn; 3277 } 3278 3279 static int arcmsr_hbaB_polling_ccbdone(struct AdapterControlBlock *acb, 3280 struct CommandControlBlock *poll_ccb) 3281 { 3282 struct MessageUnit_B *reg = acb->pmuB; 3283 struct ARCMSR_CDB *arcmsr_cdb; 3284 struct CommandControlBlock *ccb; 3285 uint32_t flag_ccb, poll_ccb_done = 0, poll_count = 0; 3286 int index, rtn; 3287 bool error; 3288 polling_hbb_ccb_retry: 3289 3290 poll_count++; 3291 /* clear doorbell interrupt */ 3292 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); 3293 while(1){ 3294 index = reg->doneq_index; 3295 flag_ccb = reg->done_qbuffer[index]; 3296 if (flag_ccb == 0) { 3297 if (poll_ccb_done){ 3298 rtn = SUCCESS; 3299 break; 3300 }else { 3301 msleep(25); 3302 if (poll_count > 100){ 3303 rtn = FAILED; 3304 break; 3305 } 3306 goto polling_hbb_ccb_retry; 3307 } 3308 } 3309 reg->done_qbuffer[index] = 0; 3310 index++; 3311 /*if last index number set it to 0 */ 3312 index %= ARCMSR_MAX_HBB_POSTQUEUE; 3313 reg->doneq_index = index; 3314 /* check if command done with no error*/ 3315 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5)); 3316 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb); 3317 poll_ccb_done |= (ccb == poll_ccb) ? 1 : 0; 3318 if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) { 3319 if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) { 3320 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'" 3321 " poll command abort successfully \n" 3322 ,acb->host->host_no 3323 ,ccb->pcmd->device->id 3324 ,(u32)ccb->pcmd->device->lun 3325 ,ccb); 3326 ccb->pcmd->result = DID_ABORT << 16; 3327 arcmsr_ccb_complete(ccb); 3328 continue; 3329 } 3330 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb" 3331 " command done ccb = '0x%p'" 3332 "ccboutstandingcount = %d \n" 3333 , acb->host->host_no 3334 , ccb 3335 , atomic_read(&acb->ccboutstandingcount)); 3336 continue; 3337 } 3338 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false; 3339 arcmsr_report_ccb_state(acb, ccb, error); 3340 } 3341 return rtn; 3342 } 3343 3344 static int arcmsr_hbaC_polling_ccbdone(struct AdapterControlBlock *acb, 3345 struct CommandControlBlock *poll_ccb) 3346 { 3347 struct MessageUnit_C __iomem *reg = acb->pmuC; 3348 uint32_t flag_ccb, ccb_cdb_phy; 3349 struct ARCMSR_CDB *arcmsr_cdb; 3350 bool error; 3351 struct CommandControlBlock *pCCB; 3352 uint32_t poll_ccb_done = 0, poll_count = 0; 3353 int rtn; 3354 polling_hbc_ccb_retry: 3355 poll_count++; 3356 while (1) { 3357 if ((readl(®->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) == 0) { 3358 if (poll_ccb_done) { 3359 rtn = SUCCESS; 3360 break; 3361 } else { 3362 msleep(25); 3363 if (poll_count > 100) { 3364 rtn = FAILED; 3365 break; 3366 } 3367 goto polling_hbc_ccb_retry; 3368 } 3369 } 3370 flag_ccb = readl(®->outbound_queueport_low); 3371 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0); 3372 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);/*frame must be 32 bytes aligned*/ 3373 pCCB = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb); 3374 poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0; 3375 /* check ifcommand done with no error*/ 3376 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) { 3377 if (pCCB->startdone == ARCMSR_CCB_ABORTED) { 3378 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'" 3379 " poll command abort successfully \n" 3380 , acb->host->host_no 3381 , pCCB->pcmd->device->id 3382 , (u32)pCCB->pcmd->device->lun 3383 , pCCB); 3384 pCCB->pcmd->result = DID_ABORT << 16; 3385 arcmsr_ccb_complete(pCCB); 3386 continue; 3387 } 3388 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb" 3389 " command done ccb = '0x%p'" 3390 "ccboutstandingcount = %d \n" 3391 , acb->host->host_no 3392 , pCCB 3393 , atomic_read(&acb->ccboutstandingcount)); 3394 continue; 3395 } 3396 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false; 3397 arcmsr_report_ccb_state(acb, pCCB, error); 3398 } 3399 return rtn; 3400 } 3401 3402 static int arcmsr_hbaD_polling_ccbdone(struct AdapterControlBlock *acb, 3403 struct CommandControlBlock *poll_ccb) 3404 { 3405 bool error; 3406 uint32_t poll_ccb_done = 0, poll_count = 0, flag_ccb, ccb_cdb_phy; 3407 int rtn, doneq_index, index_stripped, outbound_write_pointer, toggle; 3408 unsigned long flags; 3409 struct ARCMSR_CDB *arcmsr_cdb; 3410 struct CommandControlBlock *pCCB; 3411 struct MessageUnit_D *pmu = acb->pmuD; 3412 3413 polling_hbaD_ccb_retry: 3414 poll_count++; 3415 while (1) { 3416 spin_lock_irqsave(&acb->doneq_lock, flags); 3417 outbound_write_pointer = pmu->done_qbuffer[0].addressLow + 1; 3418 doneq_index = pmu->doneq_index; 3419 if ((outbound_write_pointer & 0xFFF) == (doneq_index & 0xFFF)) { 3420 spin_unlock_irqrestore(&acb->doneq_lock, flags); 3421 if (poll_ccb_done) { 3422 rtn = SUCCESS; 3423 break; 3424 } else { 3425 msleep(25); 3426 if (poll_count > 40) { 3427 rtn = FAILED; 3428 break; 3429 } 3430 goto polling_hbaD_ccb_retry; 3431 } 3432 } 3433 toggle = doneq_index & 0x4000; 3434 index_stripped = (doneq_index & 0xFFF) + 1; 3435 index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE; 3436 pmu->doneq_index = index_stripped ? (index_stripped | toggle) : 3437 ((toggle ^ 0x4000) + 1); 3438 doneq_index = pmu->doneq_index; 3439 spin_unlock_irqrestore(&acb->doneq_lock, flags); 3440 flag_ccb = pmu->done_qbuffer[doneq_index & 0xFFF].addressLow; 3441 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0); 3442 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + 3443 ccb_cdb_phy); 3444 pCCB = container_of(arcmsr_cdb, struct CommandControlBlock, 3445 arcmsr_cdb); 3446 poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0; 3447 if ((pCCB->acb != acb) || 3448 (pCCB->startdone != ARCMSR_CCB_START)) { 3449 if (pCCB->startdone == ARCMSR_CCB_ABORTED) { 3450 pr_notice("arcmsr%d: scsi id = %d " 3451 "lun = %d ccb = '0x%p' poll command " 3452 "abort successfully\n" 3453 , acb->host->host_no 3454 , pCCB->pcmd->device->id 3455 , (u32)pCCB->pcmd->device->lun 3456 , pCCB); 3457 pCCB->pcmd->result = DID_ABORT << 16; 3458 arcmsr_ccb_complete(pCCB); 3459 continue; 3460 } 3461 pr_notice("arcmsr%d: polling an illegal " 3462 "ccb command done ccb = '0x%p' " 3463 "ccboutstandingcount = %d\n" 3464 , acb->host->host_no 3465 , pCCB 3466 , atomic_read(&acb->ccboutstandingcount)); 3467 continue; 3468 } 3469 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) 3470 ? true : false; 3471 arcmsr_report_ccb_state(acb, pCCB, error); 3472 } 3473 return rtn; 3474 } 3475 3476 static int arcmsr_hbaE_polling_ccbdone(struct AdapterControlBlock *acb, 3477 struct CommandControlBlock *poll_ccb) 3478 { 3479 bool error; 3480 uint32_t poll_ccb_done = 0, poll_count = 0, doneq_index; 3481 uint16_t cmdSMID; 3482 unsigned long flags; 3483 int rtn; 3484 struct CommandControlBlock *pCCB; 3485 struct MessageUnit_E __iomem *reg = acb->pmuE; 3486 3487 polling_hbaC_ccb_retry: 3488 poll_count++; 3489 while (1) { 3490 spin_lock_irqsave(&acb->doneq_lock, flags); 3491 doneq_index = acb->doneq_index; 3492 if ((readl(®->reply_post_producer_index) & 0xFFFF) == 3493 doneq_index) { 3494 spin_unlock_irqrestore(&acb->doneq_lock, flags); 3495 if (poll_ccb_done) { 3496 rtn = SUCCESS; 3497 break; 3498 } else { 3499 msleep(25); 3500 if (poll_count > 40) { 3501 rtn = FAILED; 3502 break; 3503 } 3504 goto polling_hbaC_ccb_retry; 3505 } 3506 } 3507 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID; 3508 doneq_index++; 3509 if (doneq_index >= acb->completionQ_entry) 3510 doneq_index = 0; 3511 acb->doneq_index = doneq_index; 3512 spin_unlock_irqrestore(&acb->doneq_lock, flags); 3513 pCCB = acb->pccb_pool[cmdSMID]; 3514 poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0; 3515 /* check if command done with no error*/ 3516 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) { 3517 if (pCCB->startdone == ARCMSR_CCB_ABORTED) { 3518 pr_notice("arcmsr%d: scsi id = %d " 3519 "lun = %d ccb = '0x%p' poll command " 3520 "abort successfully\n" 3521 , acb->host->host_no 3522 , pCCB->pcmd->device->id 3523 , (u32)pCCB->pcmd->device->lun 3524 , pCCB); 3525 pCCB->pcmd->result = DID_ABORT << 16; 3526 arcmsr_ccb_complete(pCCB); 3527 continue; 3528 } 3529 pr_notice("arcmsr%d: polling an illegal " 3530 "ccb command done ccb = '0x%p' " 3531 "ccboutstandingcount = %d\n" 3532 , acb->host->host_no 3533 , pCCB 3534 , atomic_read(&acb->ccboutstandingcount)); 3535 continue; 3536 } 3537 error = (acb->pCompletionQ[doneq_index].cmdFlag & 3538 ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false; 3539 arcmsr_report_ccb_state(acb, pCCB, error); 3540 } 3541 writel(doneq_index, ®->reply_post_consumer_index); 3542 return rtn; 3543 } 3544 3545 static int arcmsr_polling_ccbdone(struct AdapterControlBlock *acb, 3546 struct CommandControlBlock *poll_ccb) 3547 { 3548 int rtn = 0; 3549 switch (acb->adapter_type) { 3550 3551 case ACB_ADAPTER_TYPE_A: { 3552 rtn = arcmsr_hbaA_polling_ccbdone(acb, poll_ccb); 3553 } 3554 break; 3555 3556 case ACB_ADAPTER_TYPE_B: { 3557 rtn = arcmsr_hbaB_polling_ccbdone(acb, poll_ccb); 3558 } 3559 break; 3560 case ACB_ADAPTER_TYPE_C: { 3561 rtn = arcmsr_hbaC_polling_ccbdone(acb, poll_ccb); 3562 } 3563 break; 3564 case ACB_ADAPTER_TYPE_D: 3565 rtn = arcmsr_hbaD_polling_ccbdone(acb, poll_ccb); 3566 break; 3567 case ACB_ADAPTER_TYPE_E: 3568 rtn = arcmsr_hbaE_polling_ccbdone(acb, poll_ccb); 3569 break; 3570 } 3571 return rtn; 3572 } 3573 3574 static void arcmsr_set_iop_datetime(struct timer_list *t) 3575 { 3576 struct AdapterControlBlock *pacb = from_timer(pacb, t, refresh_timer); 3577 unsigned int next_time; 3578 struct tm tm; 3579 3580 union { 3581 struct { 3582 uint16_t signature; 3583 uint8_t year; 3584 uint8_t month; 3585 uint8_t date; 3586 uint8_t hour; 3587 uint8_t minute; 3588 uint8_t second; 3589 } a; 3590 struct { 3591 uint32_t msg_time[2]; 3592 } b; 3593 } datetime; 3594 3595 time64_to_tm(ktime_get_real_seconds(), -sys_tz.tz_minuteswest * 60, &tm); 3596 3597 datetime.a.signature = 0x55AA; 3598 datetime.a.year = tm.tm_year - 100; /* base 2000 instead of 1900 */ 3599 datetime.a.month = tm.tm_mon; 3600 datetime.a.date = tm.tm_mday; 3601 datetime.a.hour = tm.tm_hour; 3602 datetime.a.minute = tm.tm_min; 3603 datetime.a.second = tm.tm_sec; 3604 3605 switch (pacb->adapter_type) { 3606 case ACB_ADAPTER_TYPE_A: { 3607 struct MessageUnit_A __iomem *reg = pacb->pmuA; 3608 writel(datetime.b.msg_time[0], ®->message_rwbuffer[0]); 3609 writel(datetime.b.msg_time[1], ®->message_rwbuffer[1]); 3610 writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, ®->inbound_msgaddr0); 3611 break; 3612 } 3613 case ACB_ADAPTER_TYPE_B: { 3614 uint32_t __iomem *rwbuffer; 3615 struct MessageUnit_B *reg = pacb->pmuB; 3616 rwbuffer = reg->message_rwbuffer; 3617 writel(datetime.b.msg_time[0], rwbuffer++); 3618 writel(datetime.b.msg_time[1], rwbuffer++); 3619 writel(ARCMSR_MESSAGE_SYNC_TIMER, reg->drv2iop_doorbell); 3620 break; 3621 } 3622 case ACB_ADAPTER_TYPE_C: { 3623 struct MessageUnit_C __iomem *reg = pacb->pmuC; 3624 writel(datetime.b.msg_time[0], ®->msgcode_rwbuffer[0]); 3625 writel(datetime.b.msg_time[1], ®->msgcode_rwbuffer[1]); 3626 writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, ®->inbound_msgaddr0); 3627 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell); 3628 break; 3629 } 3630 case ACB_ADAPTER_TYPE_D: { 3631 uint32_t __iomem *rwbuffer; 3632 struct MessageUnit_D *reg = pacb->pmuD; 3633 rwbuffer = reg->msgcode_rwbuffer; 3634 writel(datetime.b.msg_time[0], rwbuffer++); 3635 writel(datetime.b.msg_time[1], rwbuffer++); 3636 writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, reg->inbound_msgaddr0); 3637 break; 3638 } 3639 case ACB_ADAPTER_TYPE_E: { 3640 struct MessageUnit_E __iomem *reg = pacb->pmuE; 3641 writel(datetime.b.msg_time[0], ®->msgcode_rwbuffer[0]); 3642 writel(datetime.b.msg_time[1], ®->msgcode_rwbuffer[1]); 3643 writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, ®->inbound_msgaddr0); 3644 pacb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 3645 writel(pacb->out_doorbell, ®->iobound_doorbell); 3646 break; 3647 } 3648 } 3649 if (sys_tz.tz_minuteswest) 3650 next_time = ARCMSR_HOURS; 3651 else 3652 next_time = ARCMSR_MINUTES; 3653 mod_timer(&pacb->refresh_timer, jiffies + msecs_to_jiffies(next_time)); 3654 } 3655 3656 static int arcmsr_iop_confirm(struct AdapterControlBlock *acb) 3657 { 3658 uint32_t cdb_phyaddr, cdb_phyaddr_hi32; 3659 dma_addr_t dma_coherent_handle; 3660 3661 /* 3662 ******************************************************************** 3663 ** here we need to tell iop 331 our freeccb.HighPart 3664 ** if freeccb.HighPart is not zero 3665 ******************************************************************** 3666 */ 3667 switch (acb->adapter_type) { 3668 case ACB_ADAPTER_TYPE_B: 3669 case ACB_ADAPTER_TYPE_D: 3670 dma_coherent_handle = acb->dma_coherent_handle2; 3671 break; 3672 case ACB_ADAPTER_TYPE_E: 3673 dma_coherent_handle = acb->dma_coherent_handle + 3674 offsetof(struct CommandControlBlock, arcmsr_cdb); 3675 break; 3676 default: 3677 dma_coherent_handle = acb->dma_coherent_handle; 3678 break; 3679 } 3680 cdb_phyaddr = lower_32_bits(dma_coherent_handle); 3681 cdb_phyaddr_hi32 = upper_32_bits(dma_coherent_handle); 3682 acb->cdb_phyaddr_hi32 = cdb_phyaddr_hi32; 3683 /* 3684 *********************************************************************** 3685 ** if adapter type B, set window of "post command Q" 3686 *********************************************************************** 3687 */ 3688 switch (acb->adapter_type) { 3689 3690 case ACB_ADAPTER_TYPE_A: { 3691 if (cdb_phyaddr_hi32 != 0) { 3692 struct MessageUnit_A __iomem *reg = acb->pmuA; 3693 writel(ARCMSR_SIGNATURE_SET_CONFIG, \ 3694 ®->message_rwbuffer[0]); 3695 writel(cdb_phyaddr_hi32, ®->message_rwbuffer[1]); 3696 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, \ 3697 ®->inbound_msgaddr0); 3698 if (!arcmsr_hbaA_wait_msgint_ready(acb)) { 3699 printk(KERN_NOTICE "arcmsr%d: ""set ccb high \ 3700 part physical address timeout\n", 3701 acb->host->host_no); 3702 return 1; 3703 } 3704 } 3705 } 3706 break; 3707 3708 case ACB_ADAPTER_TYPE_B: { 3709 uint32_t __iomem *rwbuffer; 3710 3711 struct MessageUnit_B *reg = acb->pmuB; 3712 reg->postq_index = 0; 3713 reg->doneq_index = 0; 3714 writel(ARCMSR_MESSAGE_SET_POST_WINDOW, reg->drv2iop_doorbell); 3715 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 3716 printk(KERN_NOTICE "arcmsr%d: cannot set driver mode\n", \ 3717 acb->host->host_no); 3718 return 1; 3719 } 3720 rwbuffer = reg->message_rwbuffer; 3721 /* driver "set config" signature */ 3722 writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++); 3723 /* normal should be zero */ 3724 writel(cdb_phyaddr_hi32, rwbuffer++); 3725 /* postQ size (256 + 8)*4 */ 3726 writel(cdb_phyaddr, rwbuffer++); 3727 /* doneQ size (256 + 8)*4 */ 3728 writel(cdb_phyaddr + 1056, rwbuffer++); 3729 /* ccb maxQ size must be --> [(256 + 8)*4]*/ 3730 writel(1056, rwbuffer); 3731 3732 writel(ARCMSR_MESSAGE_SET_CONFIG, reg->drv2iop_doorbell); 3733 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 3734 printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \ 3735 timeout \n",acb->host->host_no); 3736 return 1; 3737 } 3738 writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell); 3739 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 3740 pr_err("arcmsr%d: can't set driver mode.\n", 3741 acb->host->host_no); 3742 return 1; 3743 } 3744 } 3745 break; 3746 case ACB_ADAPTER_TYPE_C: { 3747 if (cdb_phyaddr_hi32 != 0) { 3748 struct MessageUnit_C __iomem *reg = acb->pmuC; 3749 3750 printk(KERN_NOTICE "arcmsr%d: cdb_phyaddr_hi32=0x%x\n", 3751 acb->adapter_index, cdb_phyaddr_hi32); 3752 writel(ARCMSR_SIGNATURE_SET_CONFIG, ®->msgcode_rwbuffer[0]); 3753 writel(cdb_phyaddr_hi32, ®->msgcode_rwbuffer[1]); 3754 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, ®->inbound_msgaddr0); 3755 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell); 3756 if (!arcmsr_hbaC_wait_msgint_ready(acb)) { 3757 printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \ 3758 timeout \n", acb->host->host_no); 3759 return 1; 3760 } 3761 } 3762 } 3763 break; 3764 case ACB_ADAPTER_TYPE_D: { 3765 uint32_t __iomem *rwbuffer; 3766 struct MessageUnit_D *reg = acb->pmuD; 3767 reg->postq_index = 0; 3768 reg->doneq_index = 0; 3769 rwbuffer = reg->msgcode_rwbuffer; 3770 writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++); 3771 writel(cdb_phyaddr_hi32, rwbuffer++); 3772 writel(cdb_phyaddr, rwbuffer++); 3773 writel(cdb_phyaddr + (ARCMSR_MAX_ARC1214_POSTQUEUE * 3774 sizeof(struct InBound_SRB)), rwbuffer++); 3775 writel(0x100, rwbuffer); 3776 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, reg->inbound_msgaddr0); 3777 if (!arcmsr_hbaD_wait_msgint_ready(acb)) { 3778 pr_notice("arcmsr%d: 'set command Q window' timeout\n", 3779 acb->host->host_no); 3780 return 1; 3781 } 3782 } 3783 break; 3784 case ACB_ADAPTER_TYPE_E: { 3785 struct MessageUnit_E __iomem *reg = acb->pmuE; 3786 writel(ARCMSR_SIGNATURE_SET_CONFIG, ®->msgcode_rwbuffer[0]); 3787 writel(ARCMSR_SIGNATURE_1884, ®->msgcode_rwbuffer[1]); 3788 writel(cdb_phyaddr, ®->msgcode_rwbuffer[2]); 3789 writel(cdb_phyaddr_hi32, ®->msgcode_rwbuffer[3]); 3790 writel(acb->ccbsize, ®->msgcode_rwbuffer[4]); 3791 dma_coherent_handle = acb->dma_coherent_handle2; 3792 cdb_phyaddr = (uint32_t)(dma_coherent_handle & 0xffffffff); 3793 cdb_phyaddr_hi32 = (uint32_t)((dma_coherent_handle >> 16) >> 16); 3794 writel(cdb_phyaddr, ®->msgcode_rwbuffer[5]); 3795 writel(cdb_phyaddr_hi32, ®->msgcode_rwbuffer[6]); 3796 writel(acb->roundup_ccbsize, ®->msgcode_rwbuffer[7]); 3797 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, ®->inbound_msgaddr0); 3798 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 3799 writel(acb->out_doorbell, ®->iobound_doorbell); 3800 if (!arcmsr_hbaE_wait_msgint_ready(acb)) { 3801 pr_notice("arcmsr%d: 'set command Q window' timeout \n", 3802 acb->host->host_no); 3803 return 1; 3804 } 3805 } 3806 break; 3807 } 3808 return 0; 3809 } 3810 3811 static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb) 3812 { 3813 uint32_t firmware_state = 0; 3814 switch (acb->adapter_type) { 3815 3816 case ACB_ADAPTER_TYPE_A: { 3817 struct MessageUnit_A __iomem *reg = acb->pmuA; 3818 do { 3819 if (!(acb->acb_flags & ACB_F_IOP_INITED)) 3820 msleep(20); 3821 firmware_state = readl(®->outbound_msgaddr1); 3822 } while ((firmware_state & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0); 3823 } 3824 break; 3825 3826 case ACB_ADAPTER_TYPE_B: { 3827 struct MessageUnit_B *reg = acb->pmuB; 3828 do { 3829 if (!(acb->acb_flags & ACB_F_IOP_INITED)) 3830 msleep(20); 3831 firmware_state = readl(reg->iop2drv_doorbell); 3832 } while ((firmware_state & ARCMSR_MESSAGE_FIRMWARE_OK) == 0); 3833 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell); 3834 } 3835 break; 3836 case ACB_ADAPTER_TYPE_C: { 3837 struct MessageUnit_C __iomem *reg = acb->pmuC; 3838 do { 3839 if (!(acb->acb_flags & ACB_F_IOP_INITED)) 3840 msleep(20); 3841 firmware_state = readl(®->outbound_msgaddr1); 3842 } while ((firmware_state & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0); 3843 } 3844 break; 3845 case ACB_ADAPTER_TYPE_D: { 3846 struct MessageUnit_D *reg = acb->pmuD; 3847 do { 3848 if (!(acb->acb_flags & ACB_F_IOP_INITED)) 3849 msleep(20); 3850 firmware_state = readl(reg->outbound_msgaddr1); 3851 } while ((firmware_state & 3852 ARCMSR_ARC1214_MESSAGE_FIRMWARE_OK) == 0); 3853 } 3854 break; 3855 case ACB_ADAPTER_TYPE_E: { 3856 struct MessageUnit_E __iomem *reg = acb->pmuE; 3857 do { 3858 if (!(acb->acb_flags & ACB_F_IOP_INITED)) 3859 msleep(20); 3860 firmware_state = readl(®->outbound_msgaddr1); 3861 } while ((firmware_state & ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK) == 0); 3862 } 3863 break; 3864 } 3865 } 3866 3867 static void arcmsr_request_device_map(struct timer_list *t) 3868 { 3869 struct AdapterControlBlock *acb = from_timer(acb, t, eternal_timer); 3870 if (unlikely(atomic_read(&acb->rq_map_token) == 0) || 3871 (acb->acb_flags & ACB_F_BUS_RESET) || 3872 (acb->acb_flags & ACB_F_ABORT)) { 3873 mod_timer(&acb->eternal_timer, 3874 jiffies + msecs_to_jiffies(6 * HZ)); 3875 } else { 3876 acb->fw_flag = FW_NORMAL; 3877 if (atomic_read(&acb->ante_token_value) == 3878 atomic_read(&acb->rq_map_token)) { 3879 atomic_set(&acb->rq_map_token, 16); 3880 } 3881 atomic_set(&acb->ante_token_value, 3882 atomic_read(&acb->rq_map_token)); 3883 if (atomic_dec_and_test(&acb->rq_map_token)) { 3884 mod_timer(&acb->eternal_timer, jiffies + 3885 msecs_to_jiffies(6 * HZ)); 3886 return; 3887 } 3888 switch (acb->adapter_type) { 3889 case ACB_ADAPTER_TYPE_A: { 3890 struct MessageUnit_A __iomem *reg = acb->pmuA; 3891 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0); 3892 break; 3893 } 3894 case ACB_ADAPTER_TYPE_B: { 3895 struct MessageUnit_B *reg = acb->pmuB; 3896 writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell); 3897 break; 3898 } 3899 case ACB_ADAPTER_TYPE_C: { 3900 struct MessageUnit_C __iomem *reg = acb->pmuC; 3901 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0); 3902 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell); 3903 break; 3904 } 3905 case ACB_ADAPTER_TYPE_D: { 3906 struct MessageUnit_D *reg = acb->pmuD; 3907 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, reg->inbound_msgaddr0); 3908 break; 3909 } 3910 case ACB_ADAPTER_TYPE_E: { 3911 struct MessageUnit_E __iomem *reg = acb->pmuE; 3912 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, ®->inbound_msgaddr0); 3913 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 3914 writel(acb->out_doorbell, ®->iobound_doorbell); 3915 break; 3916 } 3917 default: 3918 return; 3919 } 3920 acb->acb_flags |= ACB_F_MSG_GET_CONFIG; 3921 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ)); 3922 } 3923 } 3924 3925 static void arcmsr_hbaA_start_bgrb(struct AdapterControlBlock *acb) 3926 { 3927 struct MessageUnit_A __iomem *reg = acb->pmuA; 3928 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3929 writel(ARCMSR_INBOUND_MESG0_START_BGRB, ®->inbound_msgaddr0); 3930 if (!arcmsr_hbaA_wait_msgint_ready(acb)) { 3931 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \ 3932 rebuild' timeout \n", acb->host->host_no); 3933 } 3934 } 3935 3936 static void arcmsr_hbaB_start_bgrb(struct AdapterControlBlock *acb) 3937 { 3938 struct MessageUnit_B *reg = acb->pmuB; 3939 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3940 writel(ARCMSR_MESSAGE_START_BGRB, reg->drv2iop_doorbell); 3941 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 3942 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \ 3943 rebuild' timeout \n",acb->host->host_no); 3944 } 3945 } 3946 3947 static void arcmsr_hbaC_start_bgrb(struct AdapterControlBlock *pACB) 3948 { 3949 struct MessageUnit_C __iomem *phbcmu = pACB->pmuC; 3950 pACB->acb_flags |= ACB_F_MSG_START_BGRB; 3951 writel(ARCMSR_INBOUND_MESG0_START_BGRB, &phbcmu->inbound_msgaddr0); 3952 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &phbcmu->inbound_doorbell); 3953 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) { 3954 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \ 3955 rebuild' timeout \n", pACB->host->host_no); 3956 } 3957 return; 3958 } 3959 3960 static void arcmsr_hbaD_start_bgrb(struct AdapterControlBlock *pACB) 3961 { 3962 struct MessageUnit_D *pmu = pACB->pmuD; 3963 3964 pACB->acb_flags |= ACB_F_MSG_START_BGRB; 3965 writel(ARCMSR_INBOUND_MESG0_START_BGRB, pmu->inbound_msgaddr0); 3966 if (!arcmsr_hbaD_wait_msgint_ready(pACB)) { 3967 pr_notice("arcmsr%d: wait 'start adapter " 3968 "background rebuild' timeout\n", pACB->host->host_no); 3969 } 3970 } 3971 3972 static void arcmsr_hbaE_start_bgrb(struct AdapterControlBlock *pACB) 3973 { 3974 struct MessageUnit_E __iomem *pmu = pACB->pmuE; 3975 3976 pACB->acb_flags |= ACB_F_MSG_START_BGRB; 3977 writel(ARCMSR_INBOUND_MESG0_START_BGRB, &pmu->inbound_msgaddr0); 3978 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 3979 writel(pACB->out_doorbell, &pmu->iobound_doorbell); 3980 if (!arcmsr_hbaE_wait_msgint_ready(pACB)) { 3981 pr_notice("arcmsr%d: wait 'start adapter " 3982 "background rebuild' timeout \n", pACB->host->host_no); 3983 } 3984 } 3985 3986 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb) 3987 { 3988 switch (acb->adapter_type) { 3989 case ACB_ADAPTER_TYPE_A: 3990 arcmsr_hbaA_start_bgrb(acb); 3991 break; 3992 case ACB_ADAPTER_TYPE_B: 3993 arcmsr_hbaB_start_bgrb(acb); 3994 break; 3995 case ACB_ADAPTER_TYPE_C: 3996 arcmsr_hbaC_start_bgrb(acb); 3997 break; 3998 case ACB_ADAPTER_TYPE_D: 3999 arcmsr_hbaD_start_bgrb(acb); 4000 break; 4001 case ACB_ADAPTER_TYPE_E: 4002 arcmsr_hbaE_start_bgrb(acb); 4003 break; 4004 } 4005 } 4006 4007 static void arcmsr_clear_doorbell_queue_buffer(struct AdapterControlBlock *acb) 4008 { 4009 switch (acb->adapter_type) { 4010 case ACB_ADAPTER_TYPE_A: { 4011 struct MessageUnit_A __iomem *reg = acb->pmuA; 4012 uint32_t outbound_doorbell; 4013 /* empty doorbell Qbuffer if door bell ringed */ 4014 outbound_doorbell = readl(®->outbound_doorbell); 4015 /*clear doorbell interrupt */ 4016 writel(outbound_doorbell, ®->outbound_doorbell); 4017 writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, ®->inbound_doorbell); 4018 } 4019 break; 4020 4021 case ACB_ADAPTER_TYPE_B: { 4022 struct MessageUnit_B *reg = acb->pmuB; 4023 uint32_t outbound_doorbell, i; 4024 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); 4025 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell); 4026 /* let IOP know data has been read */ 4027 for(i=0; i < 200; i++) { 4028 msleep(20); 4029 outbound_doorbell = readl(reg->iop2drv_doorbell); 4030 if( outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) { 4031 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); 4032 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell); 4033 } else 4034 break; 4035 } 4036 } 4037 break; 4038 case ACB_ADAPTER_TYPE_C: { 4039 struct MessageUnit_C __iomem *reg = acb->pmuC; 4040 uint32_t outbound_doorbell, i; 4041 /* empty doorbell Qbuffer if door bell ringed */ 4042 outbound_doorbell = readl(®->outbound_doorbell); 4043 writel(outbound_doorbell, ®->outbound_doorbell_clear); 4044 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, ®->inbound_doorbell); 4045 for (i = 0; i < 200; i++) { 4046 msleep(20); 4047 outbound_doorbell = readl(®->outbound_doorbell); 4048 if (outbound_doorbell & 4049 ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) { 4050 writel(outbound_doorbell, 4051 ®->outbound_doorbell_clear); 4052 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, 4053 ®->inbound_doorbell); 4054 } else 4055 break; 4056 } 4057 } 4058 break; 4059 case ACB_ADAPTER_TYPE_D: { 4060 struct MessageUnit_D *reg = acb->pmuD; 4061 uint32_t outbound_doorbell, i; 4062 /* empty doorbell Qbuffer if door bell ringed */ 4063 outbound_doorbell = readl(reg->outbound_doorbell); 4064 writel(outbound_doorbell, reg->outbound_doorbell); 4065 writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ, 4066 reg->inbound_doorbell); 4067 for (i = 0; i < 200; i++) { 4068 msleep(20); 4069 outbound_doorbell = readl(reg->outbound_doorbell); 4070 if (outbound_doorbell & 4071 ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK) { 4072 writel(outbound_doorbell, 4073 reg->outbound_doorbell); 4074 writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ, 4075 reg->inbound_doorbell); 4076 } else 4077 break; 4078 } 4079 } 4080 break; 4081 case ACB_ADAPTER_TYPE_E: { 4082 struct MessageUnit_E __iomem *reg = acb->pmuE; 4083 uint32_t i, tmp; 4084 4085 acb->in_doorbell = readl(®->iobound_doorbell); 4086 writel(0, ®->host_int_status); /*clear interrupt*/ 4087 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK; 4088 writel(acb->out_doorbell, ®->iobound_doorbell); 4089 for(i=0; i < 200; i++) { 4090 msleep(20); 4091 tmp = acb->in_doorbell; 4092 acb->in_doorbell = readl(®->iobound_doorbell); 4093 if((tmp ^ acb->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) { 4094 writel(0, ®->host_int_status); /*clear interrupt*/ 4095 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK; 4096 writel(acb->out_doorbell, ®->iobound_doorbell); 4097 } else 4098 break; 4099 } 4100 } 4101 break; 4102 } 4103 } 4104 4105 static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb) 4106 { 4107 switch (acb->adapter_type) { 4108 case ACB_ADAPTER_TYPE_A: 4109 return; 4110 case ACB_ADAPTER_TYPE_B: 4111 { 4112 struct MessageUnit_B *reg = acb->pmuB; 4113 writel(ARCMSR_MESSAGE_ACTIVE_EOI_MODE, reg->drv2iop_doorbell); 4114 if (!arcmsr_hbaB_wait_msgint_ready(acb)) { 4115 printk(KERN_NOTICE "ARCMSR IOP enables EOI_MODE TIMEOUT"); 4116 return; 4117 } 4118 } 4119 break; 4120 case ACB_ADAPTER_TYPE_C: 4121 return; 4122 } 4123 return; 4124 } 4125 4126 static void arcmsr_hardware_reset(struct AdapterControlBlock *acb) 4127 { 4128 uint8_t value[64]; 4129 int i, count = 0; 4130 struct MessageUnit_A __iomem *pmuA = acb->pmuA; 4131 struct MessageUnit_C __iomem *pmuC = acb->pmuC; 4132 struct MessageUnit_D *pmuD = acb->pmuD; 4133 4134 /* backup pci config data */ 4135 printk(KERN_NOTICE "arcmsr%d: executing hw bus reset .....\n", acb->host->host_no); 4136 for (i = 0; i < 64; i++) { 4137 pci_read_config_byte(acb->pdev, i, &value[i]); 4138 } 4139 /* hardware reset signal */ 4140 if (acb->dev_id == 0x1680) { 4141 writel(ARCMSR_ARC1680_BUS_RESET, &pmuA->reserved1[0]); 4142 } else if (acb->dev_id == 0x1880) { 4143 do { 4144 count++; 4145 writel(0xF, &pmuC->write_sequence); 4146 writel(0x4, &pmuC->write_sequence); 4147 writel(0xB, &pmuC->write_sequence); 4148 writel(0x2, &pmuC->write_sequence); 4149 writel(0x7, &pmuC->write_sequence); 4150 writel(0xD, &pmuC->write_sequence); 4151 } while (((readl(&pmuC->host_diagnostic) & ARCMSR_ARC1880_DiagWrite_ENABLE) == 0) && (count < 5)); 4152 writel(ARCMSR_ARC1880_RESET_ADAPTER, &pmuC->host_diagnostic); 4153 } else if (acb->dev_id == 0x1884) { 4154 struct MessageUnit_E __iomem *pmuE = acb->pmuE; 4155 do { 4156 count++; 4157 writel(0x4, &pmuE->write_sequence_3xxx); 4158 writel(0xB, &pmuE->write_sequence_3xxx); 4159 writel(0x2, &pmuE->write_sequence_3xxx); 4160 writel(0x7, &pmuE->write_sequence_3xxx); 4161 writel(0xD, &pmuE->write_sequence_3xxx); 4162 mdelay(10); 4163 } while (((readl(&pmuE->host_diagnostic_3xxx) & 4164 ARCMSR_ARC1884_DiagWrite_ENABLE) == 0) && (count < 5)); 4165 writel(ARCMSR_ARC188X_RESET_ADAPTER, &pmuE->host_diagnostic_3xxx); 4166 } else if (acb->dev_id == 0x1214) { 4167 writel(0x20, pmuD->reset_request); 4168 } else { 4169 pci_write_config_byte(acb->pdev, 0x84, 0x20); 4170 } 4171 msleep(2000); 4172 /* write back pci config data */ 4173 for (i = 0; i < 64; i++) { 4174 pci_write_config_byte(acb->pdev, i, value[i]); 4175 } 4176 msleep(1000); 4177 return; 4178 } 4179 4180 static bool arcmsr_reset_in_progress(struct AdapterControlBlock *acb) 4181 { 4182 bool rtn = true; 4183 4184 switch(acb->adapter_type) { 4185 case ACB_ADAPTER_TYPE_A:{ 4186 struct MessageUnit_A __iomem *reg = acb->pmuA; 4187 rtn = ((readl(®->outbound_msgaddr1) & 4188 ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) ? true : false; 4189 } 4190 break; 4191 case ACB_ADAPTER_TYPE_B:{ 4192 struct MessageUnit_B *reg = acb->pmuB; 4193 rtn = ((readl(reg->iop2drv_doorbell) & 4194 ARCMSR_MESSAGE_FIRMWARE_OK) == 0) ? true : false; 4195 } 4196 break; 4197 case ACB_ADAPTER_TYPE_C:{ 4198 struct MessageUnit_C __iomem *reg = acb->pmuC; 4199 rtn = (readl(®->host_diagnostic) & 0x04) ? true : false; 4200 } 4201 break; 4202 case ACB_ADAPTER_TYPE_D:{ 4203 struct MessageUnit_D *reg = acb->pmuD; 4204 rtn = ((readl(reg->sample_at_reset) & 0x80) == 0) ? 4205 true : false; 4206 } 4207 break; 4208 case ACB_ADAPTER_TYPE_E:{ 4209 struct MessageUnit_E __iomem *reg = acb->pmuE; 4210 rtn = (readl(®->host_diagnostic_3xxx) & 4211 ARCMSR_ARC188X_RESET_ADAPTER) ? true : false; 4212 } 4213 break; 4214 } 4215 return rtn; 4216 } 4217 4218 static void arcmsr_iop_init(struct AdapterControlBlock *acb) 4219 { 4220 uint32_t intmask_org; 4221 /* disable all outbound interrupt */ 4222 intmask_org = arcmsr_disable_outbound_ints(acb); 4223 arcmsr_wait_firmware_ready(acb); 4224 arcmsr_iop_confirm(acb); 4225 /*start background rebuild*/ 4226 arcmsr_start_adapter_bgrb(acb); 4227 /* empty doorbell Qbuffer if door bell ringed */ 4228 arcmsr_clear_doorbell_queue_buffer(acb); 4229 arcmsr_enable_eoi_mode(acb); 4230 /* enable outbound Post Queue,outbound doorbell Interrupt */ 4231 arcmsr_enable_outbound_ints(acb, intmask_org); 4232 acb->acb_flags |= ACB_F_IOP_INITED; 4233 } 4234 4235 static uint8_t arcmsr_iop_reset(struct AdapterControlBlock *acb) 4236 { 4237 struct CommandControlBlock *ccb; 4238 uint32_t intmask_org; 4239 uint8_t rtnval = 0x00; 4240 int i = 0; 4241 unsigned long flags; 4242 4243 if (atomic_read(&acb->ccboutstandingcount) != 0) { 4244 /* disable all outbound interrupt */ 4245 intmask_org = arcmsr_disable_outbound_ints(acb); 4246 /* talk to iop 331 outstanding command aborted */ 4247 rtnval = arcmsr_abort_allcmd(acb); 4248 /* clear all outbound posted Q */ 4249 arcmsr_done4abort_postqueue(acb); 4250 for (i = 0; i < acb->maxFreeCCB; i++) { 4251 ccb = acb->pccb_pool[i]; 4252 if (ccb->startdone == ARCMSR_CCB_START) { 4253 scsi_dma_unmap(ccb->pcmd); 4254 ccb->startdone = ARCMSR_CCB_DONE; 4255 ccb->ccb_flags = 0; 4256 spin_lock_irqsave(&acb->ccblist_lock, flags); 4257 list_add_tail(&ccb->list, &acb->ccb_free_list); 4258 spin_unlock_irqrestore(&acb->ccblist_lock, flags); 4259 } 4260 } 4261 atomic_set(&acb->ccboutstandingcount, 0); 4262 /* enable all outbound interrupt */ 4263 arcmsr_enable_outbound_ints(acb, intmask_org); 4264 return rtnval; 4265 } 4266 return rtnval; 4267 } 4268 4269 static int arcmsr_bus_reset(struct scsi_cmnd *cmd) 4270 { 4271 struct AdapterControlBlock *acb; 4272 int retry_count = 0; 4273 int rtn = FAILED; 4274 acb = (struct AdapterControlBlock *) cmd->device->host->hostdata; 4275 if (acb->acb_flags & ACB_F_ADAPTER_REMOVED) 4276 return SUCCESS; 4277 pr_notice("arcmsr: executing bus reset eh.....num_resets = %d," 4278 " num_aborts = %d \n", acb->num_resets, acb->num_aborts); 4279 acb->num_resets++; 4280 4281 if (acb->acb_flags & ACB_F_BUS_RESET) { 4282 long timeout; 4283 pr_notice("arcmsr: there is a bus reset eh proceeding...\n"); 4284 timeout = wait_event_timeout(wait_q, (acb->acb_flags 4285 & ACB_F_BUS_RESET) == 0, 220 * HZ); 4286 if (timeout) 4287 return SUCCESS; 4288 } 4289 acb->acb_flags |= ACB_F_BUS_RESET; 4290 if (!arcmsr_iop_reset(acb)) { 4291 arcmsr_hardware_reset(acb); 4292 acb->acb_flags &= ~ACB_F_IOP_INITED; 4293 wait_reset_done: 4294 ssleep(ARCMSR_SLEEPTIME); 4295 if (arcmsr_reset_in_progress(acb)) { 4296 if (retry_count > ARCMSR_RETRYCOUNT) { 4297 acb->fw_flag = FW_DEADLOCK; 4298 pr_notice("arcmsr%d: waiting for hw bus reset" 4299 " return, RETRY TERMINATED!!\n", 4300 acb->host->host_no); 4301 return FAILED; 4302 } 4303 retry_count++; 4304 goto wait_reset_done; 4305 } 4306 arcmsr_iop_init(acb); 4307 atomic_set(&acb->rq_map_token, 16); 4308 atomic_set(&acb->ante_token_value, 16); 4309 acb->fw_flag = FW_NORMAL; 4310 mod_timer(&acb->eternal_timer, jiffies + 4311 msecs_to_jiffies(6 * HZ)); 4312 acb->acb_flags &= ~ACB_F_BUS_RESET; 4313 rtn = SUCCESS; 4314 pr_notice("arcmsr: scsi bus reset eh returns with success\n"); 4315 } else { 4316 acb->acb_flags &= ~ACB_F_BUS_RESET; 4317 atomic_set(&acb->rq_map_token, 16); 4318 atomic_set(&acb->ante_token_value, 16); 4319 acb->fw_flag = FW_NORMAL; 4320 mod_timer(&acb->eternal_timer, jiffies + 4321 msecs_to_jiffies(6 * HZ)); 4322 rtn = SUCCESS; 4323 } 4324 return rtn; 4325 } 4326 4327 static int arcmsr_abort_one_cmd(struct AdapterControlBlock *acb, 4328 struct CommandControlBlock *ccb) 4329 { 4330 int rtn; 4331 rtn = arcmsr_polling_ccbdone(acb, ccb); 4332 return rtn; 4333 } 4334 4335 static int arcmsr_abort(struct scsi_cmnd *cmd) 4336 { 4337 struct AdapterControlBlock *acb = 4338 (struct AdapterControlBlock *)cmd->device->host->hostdata; 4339 int i = 0; 4340 int rtn = FAILED; 4341 uint32_t intmask_org; 4342 4343 if (acb->acb_flags & ACB_F_ADAPTER_REMOVED) 4344 return SUCCESS; 4345 printk(KERN_NOTICE 4346 "arcmsr%d: abort device command of scsi id = %d lun = %d\n", 4347 acb->host->host_no, cmd->device->id, (u32)cmd->device->lun); 4348 acb->acb_flags |= ACB_F_ABORT; 4349 acb->num_aborts++; 4350 /* 4351 ************************************************ 4352 ** the all interrupt service routine is locked 4353 ** we need to handle it as soon as possible and exit 4354 ************************************************ 4355 */ 4356 if (!atomic_read(&acb->ccboutstandingcount)) { 4357 acb->acb_flags &= ~ACB_F_ABORT; 4358 return rtn; 4359 } 4360 4361 intmask_org = arcmsr_disable_outbound_ints(acb); 4362 for (i = 0; i < acb->maxFreeCCB; i++) { 4363 struct CommandControlBlock *ccb = acb->pccb_pool[i]; 4364 if (ccb->startdone == ARCMSR_CCB_START && ccb->pcmd == cmd) { 4365 ccb->startdone = ARCMSR_CCB_ABORTED; 4366 rtn = arcmsr_abort_one_cmd(acb, ccb); 4367 break; 4368 } 4369 } 4370 acb->acb_flags &= ~ACB_F_ABORT; 4371 arcmsr_enable_outbound_ints(acb, intmask_org); 4372 return rtn; 4373 } 4374 4375 static const char *arcmsr_info(struct Scsi_Host *host) 4376 { 4377 struct AdapterControlBlock *acb = 4378 (struct AdapterControlBlock *) host->hostdata; 4379 static char buf[256]; 4380 char *type; 4381 int raid6 = 1; 4382 switch (acb->pdev->device) { 4383 case PCI_DEVICE_ID_ARECA_1110: 4384 case PCI_DEVICE_ID_ARECA_1200: 4385 case PCI_DEVICE_ID_ARECA_1202: 4386 case PCI_DEVICE_ID_ARECA_1210: 4387 raid6 = 0; 4388 /*FALLTHRU*/ 4389 case PCI_DEVICE_ID_ARECA_1120: 4390 case PCI_DEVICE_ID_ARECA_1130: 4391 case PCI_DEVICE_ID_ARECA_1160: 4392 case PCI_DEVICE_ID_ARECA_1170: 4393 case PCI_DEVICE_ID_ARECA_1201: 4394 case PCI_DEVICE_ID_ARECA_1203: 4395 case PCI_DEVICE_ID_ARECA_1220: 4396 case PCI_DEVICE_ID_ARECA_1230: 4397 case PCI_DEVICE_ID_ARECA_1260: 4398 case PCI_DEVICE_ID_ARECA_1270: 4399 case PCI_DEVICE_ID_ARECA_1280: 4400 type = "SATA"; 4401 break; 4402 case PCI_DEVICE_ID_ARECA_1214: 4403 case PCI_DEVICE_ID_ARECA_1380: 4404 case PCI_DEVICE_ID_ARECA_1381: 4405 case PCI_DEVICE_ID_ARECA_1680: 4406 case PCI_DEVICE_ID_ARECA_1681: 4407 case PCI_DEVICE_ID_ARECA_1880: 4408 case PCI_DEVICE_ID_ARECA_1884: 4409 type = "SAS/SATA"; 4410 break; 4411 default: 4412 type = "unknown"; 4413 raid6 = 0; 4414 break; 4415 } 4416 sprintf(buf, "Areca %s RAID Controller %s\narcmsr version %s\n", 4417 type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION); 4418 return buf; 4419 } 4420