1 /* 2 ******************************************************************************* 3 ** O.S : Linux 4 ** FILE NAME : arcmsr.h 5 ** BY : Erich Chen 6 ** Description: SCSI RAID Device Driver for 7 ** ARECA RAID Host adapter 8 ******************************************************************************* 9 ** Copyright (C) 2002 - 2005, Areca Technology Corporation All rights reserved. 10 ** 11 ** Web site: www.areca.com.tw 12 ** E-mail: erich@areca.com.tw 13 ** 14 ** This program is free software; you can redistribute it and/or modify 15 ** it under the terms of the GNU General Public License version 2 as 16 ** published by the Free Software Foundation. 17 ** This program is distributed in the hope that it will be useful, 18 ** but WITHOUT ANY WARRANTY; without even the implied warranty of 19 ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 ** GNU General Public License for more details. 21 ******************************************************************************* 22 ** Redistribution and use in source and binary forms, with or without 23 ** modification, are permitted provided that the following conditions 24 ** are met: 25 ** 1. Redistributions of source code must retain the above copyright 26 ** notice, this list of conditions and the following disclaimer. 27 ** 2. Redistributions in binary form must reproduce the above copyright 28 ** notice, this list of conditions and the following disclaimer in the 29 ** documentation and/or other materials provided with the distribution. 30 ** 3. The name of the author may not be used to endorse or promote products 31 ** derived from this software without specific prior written permission. 32 ** 33 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 34 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 35 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 36 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 37 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT 38 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 39 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 40 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 41 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 42 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 43 ******************************************************************************* 44 */ 45 #include <linux/interrupt.h> 46 47 struct class_device_attribute; 48 49 #define ARCMSR_MAX_OUTSTANDING_CMD 256 50 #define ARCMSR_MAX_FREECCB_NUM 288 51 #define ARCMSR_DRIVER_VERSION "Driver Version 1.20.00.14" 52 #define ARCMSR_SCSI_INITIATOR_ID 255 53 #define ARCMSR_MAX_XFER_SECTORS 512 54 #define ARCMSR_MAX_XFER_SECTORS_B 4096 55 #define ARCMSR_MAX_TARGETID 17 56 #define ARCMSR_MAX_TARGETLUN 8 57 #define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD 58 #define ARCMSR_MAX_QBUFFER 4096 59 #define ARCMSR_MAX_SG_ENTRIES 38 60 61 /* 62 ******************************************************************************* 63 ** split 64bits dma addressing 64 ******************************************************************************* 65 */ 66 #define dma_addr_hi32(addr) (uint32_t) ((addr>>16)>>16) 67 #define dma_addr_lo32(addr) (uint32_t) (addr & 0xffffffff) 68 /* 69 ******************************************************************************* 70 ** MESSAGE CONTROL CODE 71 ******************************************************************************* 72 */ 73 struct CMD_MESSAGE 74 { 75 uint32_t HeaderLength; 76 uint8_t Signature[8]; 77 uint32_t Timeout; 78 uint32_t ControlCode; 79 uint32_t ReturnCode; 80 uint32_t Length; 81 }; 82 /* 83 ******************************************************************************* 84 ** IOP Message Transfer Data for user space 85 ******************************************************************************* 86 */ 87 struct CMD_MESSAGE_FIELD 88 { 89 struct CMD_MESSAGE cmdmessage; 90 uint8_t messagedatabuffer[1032]; 91 }; 92 /* IOP message transfer */ 93 #define ARCMSR_MESSAGE_FAIL 0x0001 94 /* DeviceType */ 95 #define ARECA_SATA_RAID 0x90000000 96 /* FunctionCode */ 97 #define FUNCTION_READ_RQBUFFER 0x0801 98 #define FUNCTION_WRITE_WQBUFFER 0x0802 99 #define FUNCTION_CLEAR_RQBUFFER 0x0803 100 #define FUNCTION_CLEAR_WQBUFFER 0x0804 101 #define FUNCTION_CLEAR_ALLQBUFFER 0x0805 102 #define FUNCTION_RETURN_CODE_3F 0x0806 103 #define FUNCTION_SAY_HELLO 0x0807 104 #define FUNCTION_SAY_GOODBYE 0x0808 105 #define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809 106 /* ARECA IO CONTROL CODE*/ 107 #define ARCMSR_MESSAGE_READ_RQBUFFER \ 108 ARECA_SATA_RAID | FUNCTION_READ_RQBUFFER 109 #define ARCMSR_MESSAGE_WRITE_WQBUFFER \ 110 ARECA_SATA_RAID | FUNCTION_WRITE_WQBUFFER 111 #define ARCMSR_MESSAGE_CLEAR_RQBUFFER \ 112 ARECA_SATA_RAID | FUNCTION_CLEAR_RQBUFFER 113 #define ARCMSR_MESSAGE_CLEAR_WQBUFFER \ 114 ARECA_SATA_RAID | FUNCTION_CLEAR_WQBUFFER 115 #define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER \ 116 ARECA_SATA_RAID | FUNCTION_CLEAR_ALLQBUFFER 117 #define ARCMSR_MESSAGE_RETURN_CODE_3F \ 118 ARECA_SATA_RAID | FUNCTION_RETURN_CODE_3F 119 #define ARCMSR_MESSAGE_SAY_HELLO \ 120 ARECA_SATA_RAID | FUNCTION_SAY_HELLO 121 #define ARCMSR_MESSAGE_SAY_GOODBYE \ 122 ARECA_SATA_RAID | FUNCTION_SAY_GOODBYE 123 #define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE \ 124 ARECA_SATA_RAID | FUNCTION_FLUSH_ADAPTER_CACHE 125 /* ARECA IOCTL ReturnCode */ 126 #define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001 127 #define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006 128 #define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F 129 /* 130 ************************************************************* 131 ** structure for holding DMA address data 132 ************************************************************* 133 */ 134 #define IS_SG64_ADDR 0x01000000 /* bit24 */ 135 struct SG32ENTRY 136 { 137 uint32_t length; 138 uint32_t address; 139 }; 140 struct SG64ENTRY 141 { 142 uint32_t length; 143 uint32_t address; 144 uint32_t addresshigh; 145 }; 146 struct SGENTRY_UNION 147 { 148 union 149 { 150 struct SG32ENTRY sg32entry; 151 struct SG64ENTRY sg64entry; 152 }u; 153 }; 154 /* 155 ******************************************************************** 156 ** Q Buffer of IOP Message Transfer 157 ******************************************************************** 158 */ 159 struct QBUFFER 160 { 161 uint32_t data_len; 162 uint8_t data[124]; 163 }; 164 /* 165 ******************************************************************************* 166 ** FIRMWARE INFO 167 ******************************************************************************* 168 */ 169 struct FIRMWARE_INFO 170 { 171 uint32_t signature; /*0, 00-03*/ 172 uint32_t request_len; /*1, 04-07*/ 173 uint32_t numbers_queue; /*2, 08-11*/ 174 uint32_t sdram_size; /*3, 12-15*/ 175 uint32_t ide_channels; /*4, 16-19*/ 176 char vendor[40]; /*5, 20-59*/ 177 char model[8]; /*15, 60-67*/ 178 char firmware_ver[16]; /*17, 68-83*/ 179 char device_map[16]; /*21, 84-99*/ 180 }; 181 /* signature of set and get firmware config */ 182 #define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060 183 #define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063 184 /* message code of inbound message register */ 185 #define ARCMSR_INBOUND_MESG0_NOP 0x00000000 186 #define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001 187 #define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002 188 #define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003 189 #define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004 190 #define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005 191 #define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006 192 #define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007 193 #define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008 194 /* doorbell interrupt generator */ 195 #define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001 196 #define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002 197 #define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001 198 #define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002 199 /* ccb areca cdb flag */ 200 #define ARCMSR_CCBPOST_FLAG_SGL_BSIZE 0x80000000 201 #define ARCMSR_CCBPOST_FLAG_IAM_BIOS 0x40000000 202 #define ARCMSR_CCBREPLY_FLAG_IAM_BIOS 0x40000000 203 #define ARCMSR_CCBREPLY_FLAG_ERROR 0x10000000 204 /* outbound firmware ok */ 205 #define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000 206 /* 207 ******************************************************************************* 208 ** ARECA SCSI COMMAND DESCRIPTOR BLOCK size 0x1F8 (504) 209 ******************************************************************************* 210 */ 211 struct ARCMSR_CDB 212 { 213 uint8_t Bus; 214 uint8_t TargetID; 215 uint8_t LUN; 216 uint8_t Function; 217 218 uint8_t CdbLength; 219 uint8_t sgcount; 220 uint8_t Flags; 221 #define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01 222 #define ARCMSR_CDB_FLAG_BIOS 0x02 223 #define ARCMSR_CDB_FLAG_WRITE 0x04 224 #define ARCMSR_CDB_FLAG_SIMPLEQ 0x00 225 #define ARCMSR_CDB_FLAG_HEADQ 0x08 226 #define ARCMSR_CDB_FLAG_ORDEREDQ 0x10 227 uint8_t Reserved1; 228 229 uint32_t Context; 230 uint32_t DataLength; 231 232 uint8_t Cdb[16]; 233 234 uint8_t DeviceStatus; 235 #define ARCMSR_DEV_CHECK_CONDITION 0x02 236 #define ARCMSR_DEV_SELECT_TIMEOUT 0xF0 237 #define ARCMSR_DEV_ABORTED 0xF1 238 #define ARCMSR_DEV_INIT_FAIL 0xF2 239 uint8_t SenseData[15]; 240 241 union 242 { 243 struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES]; 244 struct SG64ENTRY sg64entry[ARCMSR_MAX_SG_ENTRIES]; 245 } u; 246 }; 247 /* 248 ******************************************************************************* 249 ** Messaging Unit (MU) of the Intel R 80331 I/O processor (80331) 250 ******************************************************************************* 251 */ 252 struct MessageUnit 253 { 254 uint32_t resrved0[4]; /*0000 000F*/ 255 uint32_t inbound_msgaddr0; /*0010 0013*/ 256 uint32_t inbound_msgaddr1; /*0014 0017*/ 257 uint32_t outbound_msgaddr0; /*0018 001B*/ 258 uint32_t outbound_msgaddr1; /*001C 001F*/ 259 uint32_t inbound_doorbell; /*0020 0023*/ 260 uint32_t inbound_intstatus; /*0024 0027*/ 261 uint32_t inbound_intmask; /*0028 002B*/ 262 uint32_t outbound_doorbell; /*002C 002F*/ 263 uint32_t outbound_intstatus; /*0030 0033*/ 264 uint32_t outbound_intmask; /*0034 0037*/ 265 uint32_t reserved1[2]; /*0038 003F*/ 266 uint32_t inbound_queueport; /*0040 0043*/ 267 uint32_t outbound_queueport; /*0044 0047*/ 268 uint32_t reserved2[2]; /*0048 004F*/ 269 uint32_t reserved3[492]; /*0050 07FF 492*/ 270 uint32_t reserved4[128]; /*0800 09FF 128*/ 271 uint32_t message_rwbuffer[256]; /*0a00 0DFF 256*/ 272 uint32_t message_wbuffer[32]; /*0E00 0E7F 32*/ 273 uint32_t reserved5[32]; /*0E80 0EFF 32*/ 274 uint32_t message_rbuffer[32]; /*0F00 0F7F 32*/ 275 uint32_t reserved6[32]; /*0F80 0FFF 32*/ 276 }; 277 /* 278 ******************************************************************************* 279 ** Adapter Control Block 280 ******************************************************************************* 281 */ 282 struct AdapterControlBlock 283 { 284 struct pci_dev * pdev; 285 struct Scsi_Host * host; 286 unsigned long vir2phy_offset; 287 /* Offset is used in making arc cdb physical to virtual calculations */ 288 uint32_t outbound_int_enable; 289 290 struct MessageUnit __iomem * pmu; 291 /* message unit ATU inbound base address0 */ 292 293 uint32_t acb_flags; 294 #define ACB_F_SCSISTOPADAPTER 0x0001 295 #define ACB_F_MSG_STOP_BGRB 0x0002 296 /* stop RAID background rebuild */ 297 #define ACB_F_MSG_START_BGRB 0x0004 298 /* stop RAID background rebuild */ 299 #define ACB_F_IOPDATA_OVERFLOW 0x0008 300 /* iop message data rqbuffer overflow */ 301 #define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 302 /* message clear wqbuffer */ 303 #define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 304 /* message clear rqbuffer */ 305 #define ACB_F_MESSAGE_WQBUFFER_READED 0x0040 306 #define ACB_F_BUS_RESET 0x0080 307 #define ACB_F_IOP_INITED 0x0100 308 /* iop init */ 309 310 struct CommandControlBlock * pccb_pool[ARCMSR_MAX_FREECCB_NUM]; 311 /* used for memory free */ 312 struct list_head ccb_free_list; 313 /* head of free ccb list */ 314 atomic_t ccboutstandingcount; 315 316 void * dma_coherent; 317 /* dma_coherent used for memory free */ 318 dma_addr_t dma_coherent_handle; 319 /* dma_coherent_handle used for memory free */ 320 321 uint8_t rqbuffer[ARCMSR_MAX_QBUFFER]; 322 /* data collection buffer for read from 80331 */ 323 int32_t rqbuf_firstindex; 324 /* first of read buffer */ 325 int32_t rqbuf_lastindex; 326 /* last of read buffer */ 327 uint8_t wqbuffer[ARCMSR_MAX_QBUFFER]; 328 /* data collection buffer for write to 80331 */ 329 int32_t wqbuf_firstindex; 330 /* first of write buffer */ 331 int32_t wqbuf_lastindex; 332 /* last of write buffer */ 333 uint8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; 334 /* id0 ..... id15, lun0...lun7 */ 335 #define ARECA_RAID_GONE 0x55 336 #define ARECA_RAID_GOOD 0xaa 337 uint32_t num_resets; 338 uint32_t num_aborts; 339 uint32_t firm_request_len; 340 uint32_t firm_numbers_queue; 341 uint32_t firm_sdram_size; 342 uint32_t firm_hd_channels; 343 char firm_model[12]; 344 char firm_version[20]; 345 };/* HW_DEVICE_EXTENSION */ 346 /* 347 ******************************************************************************* 348 ** Command Control Block 349 ** this CCB length must be 32 bytes boundary 350 ******************************************************************************* 351 */ 352 struct CommandControlBlock 353 { 354 struct ARCMSR_CDB arcmsr_cdb; 355 /* 356 ** 0-503 (size of CDB=504): 357 ** arcmsr messenger scsi command descriptor size 504 bytes 358 */ 359 uint32_t cdb_shifted_phyaddr; 360 /* 504-507 */ 361 uint32_t reserved1; 362 /* 508-511 */ 363 #if BITS_PER_LONG == 64 364 /* ======================512+64 bytes======================== */ 365 struct list_head list; 366 /* 512-527 16 bytes next/prev ptrs for ccb lists */ 367 struct scsi_cmnd * pcmd; 368 /* 528-535 8 bytes pointer of linux scsi command */ 369 struct AdapterControlBlock * acb; 370 /* 536-543 8 bytes pointer of acb */ 371 372 uint16_t ccb_flags; 373 /* 544-545 */ 374 #define CCB_FLAG_READ 0x0000 375 #define CCB_FLAG_WRITE 0x0001 376 #define CCB_FLAG_ERROR 0x0002 377 #define CCB_FLAG_FLUSHCACHE 0x0004 378 #define CCB_FLAG_MASTER_ABORTED 0x0008 379 uint16_t startdone; 380 /* 546-547 */ 381 #define ARCMSR_CCB_DONE 0x0000 382 #define ARCMSR_CCB_START 0x55AA 383 #define ARCMSR_CCB_ABORTED 0xAA55 384 #define ARCMSR_CCB_ILLEGAL 0xFFFF 385 uint32_t reserved2[7]; 386 /* 548-551 552-555 556-559 560-563 564-567 568-571 572-575 */ 387 #else 388 /* ======================512+32 bytes======================== */ 389 struct list_head list; 390 /* 512-519 8 bytes next/prev ptrs for ccb lists */ 391 struct scsi_cmnd * pcmd; 392 /* 520-523 4 bytes pointer of linux scsi command */ 393 struct AdapterControlBlock * acb; 394 /* 524-527 4 bytes pointer of acb */ 395 396 uint16_t ccb_flags; 397 /* 528-529 */ 398 #define CCB_FLAG_READ 0x0000 399 #define CCB_FLAG_WRITE 0x0001 400 #define CCB_FLAG_ERROR 0x0002 401 #define CCB_FLAG_FLUSHCACHE 0x0004 402 #define CCB_FLAG_MASTER_ABORTED 0x0008 403 uint16_t startdone; 404 /* 530-531 */ 405 #define ARCMSR_CCB_DONE 0x0000 406 #define ARCMSR_CCB_START 0x55AA 407 #define ARCMSR_CCB_ABORTED 0xAA55 408 #define ARCMSR_CCB_ILLEGAL 0xFFFF 409 uint32_t reserved2[3]; 410 /* 532-535 536-539 540-543 */ 411 #endif 412 /* ========================================================== */ 413 }; 414 /* 415 ******************************************************************************* 416 ** ARECA SCSI sense data 417 ******************************************************************************* 418 */ 419 struct SENSE_DATA 420 { 421 uint8_t ErrorCode:7; 422 #define SCSI_SENSE_CURRENT_ERRORS 0x70 423 #define SCSI_SENSE_DEFERRED_ERRORS 0x71 424 uint8_t Valid:1; 425 uint8_t SegmentNumber; 426 uint8_t SenseKey:4; 427 uint8_t Reserved:1; 428 uint8_t IncorrectLength:1; 429 uint8_t EndOfMedia:1; 430 uint8_t FileMark:1; 431 uint8_t Information[4]; 432 uint8_t AdditionalSenseLength; 433 uint8_t CommandSpecificInformation[4]; 434 uint8_t AdditionalSenseCode; 435 uint8_t AdditionalSenseCodeQualifier; 436 uint8_t FieldReplaceableUnitCode; 437 uint8_t SenseKeySpecific[3]; 438 }; 439 /* 440 ******************************************************************************* 441 ** Outbound Interrupt Status Register - OISR 442 ******************************************************************************* 443 */ 444 #define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30 445 #define ARCMSR_MU_OUTBOUND_PCI_INT 0x10 446 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08 447 #define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04 448 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02 449 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01 450 #define ARCMSR_MU_OUTBOUND_HANDLE_INT \ 451 (ARCMSR_MU_OUTBOUND_MESSAGE0_INT \ 452 |ARCMSR_MU_OUTBOUND_MESSAGE1_INT \ 453 |ARCMSR_MU_OUTBOUND_DOORBELL_INT \ 454 |ARCMSR_MU_OUTBOUND_POSTQUEUE_INT \ 455 |ARCMSR_MU_OUTBOUND_PCI_INT) 456 /* 457 ******************************************************************************* 458 ** Outbound Interrupt Mask Register - OIMR 459 ******************************************************************************* 460 */ 461 #define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34 462 #define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10 463 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08 464 #define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04 465 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02 466 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01 467 #define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F 468 469 extern void arcmsr_post_Qbuffer(struct AdapterControlBlock *acb); 470 extern struct class_device_attribute *arcmsr_host_attrs[]; 471 extern int arcmsr_alloc_sysfs_attr(struct AdapterControlBlock *acb); 472 void arcmsr_free_sysfs_attr(struct AdapterControlBlock *acb); 473