1 /* 2 ******************************************************************************* 3 ** O.S : Linux 4 ** FILE NAME : arcmsr.h 5 ** BY : Nick Cheng 6 ** Description: SCSI RAID Device Driver for 7 ** ARECA RAID Host adapter 8 ******************************************************************************* 9 ** Copyright (C) 2002 - 2005, Areca Technology Corporation All rights reserved. 10 ** 11 ** Web site: www.areca.com.tw 12 ** E-mail: support@areca.com.tw 13 ** 14 ** This program is free software; you can redistribute it and/or modify 15 ** it under the terms of the GNU General Public License version 2 as 16 ** published by the Free Software Foundation. 17 ** This program is distributed in the hope that it will be useful, 18 ** but WITHOUT ANY WARRANTY; without even the implied warranty of 19 ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 ** GNU General Public License for more details. 21 ******************************************************************************* 22 ** Redistribution and use in source and binary forms, with or without 23 ** modification, are permitted provided that the following conditions 24 ** are met: 25 ** 1. Redistributions of source code must retain the above copyright 26 ** notice, this list of conditions and the following disclaimer. 27 ** 2. Redistributions in binary form must reproduce the above copyright 28 ** notice, this list of conditions and the following disclaimer in the 29 ** documentation and/or other materials provided with the distribution. 30 ** 3. The name of the author may not be used to endorse or promote products 31 ** derived from this software without specific prior written permission. 32 ** 33 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 34 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 35 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 36 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 37 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT 38 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 39 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 40 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 41 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 42 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 43 ******************************************************************************* 44 */ 45 #include <linux/interrupt.h> 46 struct device_attribute; 47 /*The limit of outstanding scsi command that firmware can handle*/ 48 #define ARCMSR_NAME "arcmsr" 49 #define ARCMSR_MAX_FREECCB_NUM 1024 50 #define ARCMSR_MAX_OUTSTANDING_CMD 1024 51 #define ARCMSR_DEFAULT_OUTSTANDING_CMD 128 52 #define ARCMSR_MIN_OUTSTANDING_CMD 32 53 #define ARCMSR_DRIVER_VERSION "v1.50.00.13-20230206" 54 #define ARCMSR_SCSI_INITIATOR_ID 255 55 #define ARCMSR_MAX_XFER_SECTORS 512 56 #define ARCMSR_MAX_XFER_SECTORS_B 4096 57 #define ARCMSR_MAX_XFER_SECTORS_C 304 58 #define ARCMSR_MAX_TARGETID 17 59 #define ARCMSR_MAX_TARGETLUN 8 60 #define ARCMSR_MAX_CMD_PERLUN 128 61 #define ARCMSR_DEFAULT_CMD_PERLUN 32 62 #define ARCMSR_MIN_CMD_PERLUN 1 63 #define ARCMSR_MAX_QBUFFER 4096 64 #define ARCMSR_DEFAULT_SG_ENTRIES 38 65 #define ARCMSR_MAX_HBB_POSTQUEUE 264 66 #define ARCMSR_MAX_ARC1214_POSTQUEUE 256 67 #define ARCMSR_MAX_ARC1214_DONEQUEUE 257 68 #define ARCMSR_MAX_HBE_DONEQUEUE 512 69 #define ARCMSR_MAX_XFER_LEN 0x26000 /* 152K */ 70 #define ARCMSR_CDB_SG_PAGE_LENGTH 256 71 #define ARCMST_NUM_MSIX_VECTORS 4 72 #ifndef PCI_DEVICE_ID_ARECA_1880 73 #define PCI_DEVICE_ID_ARECA_1880 0x1880 74 #endif 75 #ifndef PCI_DEVICE_ID_ARECA_1214 76 #define PCI_DEVICE_ID_ARECA_1214 0x1214 77 #endif 78 #ifndef PCI_DEVICE_ID_ARECA_1203 79 #define PCI_DEVICE_ID_ARECA_1203 0x1203 80 #endif 81 #ifndef PCI_DEVICE_ID_ARECA_1883 82 #define PCI_DEVICE_ID_ARECA_1883 0x1883 83 #endif 84 #ifndef PCI_DEVICE_ID_ARECA_1884 85 #define PCI_DEVICE_ID_ARECA_1884 0x1884 86 #endif 87 #define PCI_DEVICE_ID_ARECA_1886_0 0x1886 88 #define PCI_DEVICE_ID_ARECA_1886 0x188A 89 #define ARCMSR_HOURS (1000 * 60 * 60 * 4) 90 #define ARCMSR_MINUTES (1000 * 60 * 60) 91 #define ARCMSR_DEFAULT_TIMEOUT 90 92 /* 93 ********************************************************************************** 94 ** 95 ********************************************************************************** 96 */ 97 #define ARC_SUCCESS 0 98 #define ARC_FAILURE 1 99 /* 100 ******************************************************************************* 101 ** split 64bits dma addressing 102 ******************************************************************************* 103 */ 104 #define dma_addr_hi32(addr) (uint32_t) ((addr>>16)>>16) 105 #define dma_addr_lo32(addr) (uint32_t) (addr & 0xffffffff) 106 /* 107 ******************************************************************************* 108 ** MESSAGE CONTROL CODE 109 ******************************************************************************* 110 */ 111 struct CMD_MESSAGE 112 { 113 uint32_t HeaderLength; 114 uint8_t Signature[8]; 115 uint32_t Timeout; 116 uint32_t ControlCode; 117 uint32_t ReturnCode; 118 uint32_t Length; 119 }; 120 /* 121 ******************************************************************************* 122 ** IOP Message Transfer Data for user space 123 ******************************************************************************* 124 */ 125 #define ARCMSR_API_DATA_BUFLEN 1032 126 struct CMD_MESSAGE_FIELD 127 { 128 struct CMD_MESSAGE cmdmessage; 129 uint8_t messagedatabuffer[ARCMSR_API_DATA_BUFLEN]; 130 }; 131 /* IOP message transfer */ 132 #define ARCMSR_MESSAGE_FAIL 0x0001 133 /* DeviceType */ 134 #define ARECA_SATA_RAID 0x90000000 135 /* FunctionCode */ 136 #define FUNCTION_READ_RQBUFFER 0x0801 137 #define FUNCTION_WRITE_WQBUFFER 0x0802 138 #define FUNCTION_CLEAR_RQBUFFER 0x0803 139 #define FUNCTION_CLEAR_WQBUFFER 0x0804 140 #define FUNCTION_CLEAR_ALLQBUFFER 0x0805 141 #define FUNCTION_RETURN_CODE_3F 0x0806 142 #define FUNCTION_SAY_HELLO 0x0807 143 #define FUNCTION_SAY_GOODBYE 0x0808 144 #define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809 145 #define FUNCTION_GET_FIRMWARE_STATUS 0x080A 146 #define FUNCTION_HARDWARE_RESET 0x080B 147 /* ARECA IO CONTROL CODE*/ 148 #define ARCMSR_MESSAGE_READ_RQBUFFER \ 149 ARECA_SATA_RAID | FUNCTION_READ_RQBUFFER 150 #define ARCMSR_MESSAGE_WRITE_WQBUFFER \ 151 ARECA_SATA_RAID | FUNCTION_WRITE_WQBUFFER 152 #define ARCMSR_MESSAGE_CLEAR_RQBUFFER \ 153 ARECA_SATA_RAID | FUNCTION_CLEAR_RQBUFFER 154 #define ARCMSR_MESSAGE_CLEAR_WQBUFFER \ 155 ARECA_SATA_RAID | FUNCTION_CLEAR_WQBUFFER 156 #define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER \ 157 ARECA_SATA_RAID | FUNCTION_CLEAR_ALLQBUFFER 158 #define ARCMSR_MESSAGE_RETURN_CODE_3F \ 159 ARECA_SATA_RAID | FUNCTION_RETURN_CODE_3F 160 #define ARCMSR_MESSAGE_SAY_HELLO \ 161 ARECA_SATA_RAID | FUNCTION_SAY_HELLO 162 #define ARCMSR_MESSAGE_SAY_GOODBYE \ 163 ARECA_SATA_RAID | FUNCTION_SAY_GOODBYE 164 #define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE \ 165 ARECA_SATA_RAID | FUNCTION_FLUSH_ADAPTER_CACHE 166 /* ARECA IOCTL ReturnCode */ 167 #define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001 168 #define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006 169 #define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F 170 #define ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON 0x00000088 171 /* 172 ************************************************************* 173 ** structure for holding DMA address data 174 ************************************************************* 175 */ 176 #define IS_DMA64 (sizeof(dma_addr_t) == 8) 177 #define IS_SG64_ADDR 0x01000000 /* bit24 */ 178 struct SG32ENTRY 179 { 180 __le32 length; 181 __le32 address; 182 }__attribute__ ((packed)); 183 struct SG64ENTRY 184 { 185 __le32 length; 186 __le32 address; 187 __le32 addresshigh; 188 }__attribute__ ((packed)); 189 /* 190 ******************************************************************** 191 ** Q Buffer of IOP Message Transfer 192 ******************************************************************** 193 */ 194 struct QBUFFER 195 { 196 uint32_t data_len; 197 uint8_t data[124]; 198 }; 199 /* 200 ******************************************************************************* 201 ** FIRMWARE INFO for Intel IOP R 80331 processor (Type A) 202 ******************************************************************************* 203 */ 204 struct FIRMWARE_INFO 205 { 206 uint32_t signature; /*0, 00-03*/ 207 uint32_t request_len; /*1, 04-07*/ 208 uint32_t numbers_queue; /*2, 08-11*/ 209 uint32_t sdram_size; /*3, 12-15*/ 210 uint32_t ide_channels; /*4, 16-19*/ 211 char vendor[40]; /*5, 20-59*/ 212 char model[8]; /*15, 60-67*/ 213 char firmware_ver[16]; /*17, 68-83*/ 214 char device_map[16]; /*21, 84-99*/ 215 uint32_t cfgVersion; /*25,100-103 Added for checking of new firmware capability*/ 216 uint8_t cfgSerial[16]; /*26,104-119*/ 217 uint32_t cfgPicStatus; /*30,120-123*/ 218 }; 219 /* signature of set and get firmware config */ 220 #define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060 221 #define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063 222 /* message code of inbound message register */ 223 #define ARCMSR_INBOUND_MESG0_NOP 0x00000000 224 #define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001 225 #define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002 226 #define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003 227 #define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004 228 #define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005 229 #define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006 230 #define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007 231 #define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008 232 /* doorbell interrupt generator */ 233 #define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001 234 #define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002 235 #define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001 236 #define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002 237 /* ccb areca cdb flag */ 238 #define ARCMSR_CCBPOST_FLAG_SGL_BSIZE 0x80000000 239 #define ARCMSR_CCBPOST_FLAG_IAM_BIOS 0x40000000 240 #define ARCMSR_CCBREPLY_FLAG_IAM_BIOS 0x40000000 241 #define ARCMSR_CCBREPLY_FLAG_ERROR_MODE0 0x10000000 242 #define ARCMSR_CCBREPLY_FLAG_ERROR_MODE1 0x00000001 243 /* outbound firmware ok */ 244 #define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000 245 /* ARC-1680 Bus Reset*/ 246 #define ARCMSR_ARC1680_BUS_RESET 0x00000003 247 /* ARC-1880 Bus Reset*/ 248 #define ARCMSR_ARC1880_RESET_ADAPTER 0x00000024 249 #define ARCMSR_ARC1880_DiagWrite_ENABLE 0x00000080 250 251 /* 252 ************************************************************************ 253 ** SPEC. for Areca Type B adapter 254 ************************************************************************ 255 */ 256 /* ARECA HBB COMMAND for its FIRMWARE */ 257 /* window of "instruction flags" from driver to iop */ 258 #define ARCMSR_DRV2IOP_DOORBELL 0x00020400 259 #define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404 260 /* window of "instruction flags" from iop to driver */ 261 #define ARCMSR_IOP2DRV_DOORBELL 0x00020408 262 #define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C 263 /* window of "instruction flags" from iop to driver */ 264 #define ARCMSR_IOP2DRV_DOORBELL_1203 0x00021870 265 #define ARCMSR_IOP2DRV_DOORBELL_MASK_1203 0x00021874 266 /* window of "instruction flags" from driver to iop */ 267 #define ARCMSR_DRV2IOP_DOORBELL_1203 0x00021878 268 #define ARCMSR_DRV2IOP_DOORBELL_MASK_1203 0x0002187C 269 /* ARECA FLAG LANGUAGE */ 270 /* ioctl transfer */ 271 #define ARCMSR_IOP2DRV_DATA_WRITE_OK 0x00000001 272 /* ioctl transfer */ 273 #define ARCMSR_IOP2DRV_DATA_READ_OK 0x00000002 274 #define ARCMSR_IOP2DRV_CDB_DONE 0x00000004 275 #define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 276 277 #define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F 278 #define ARCMSR_DOORBELL_INT_CLEAR_PATTERN 0xFF00FFF0 279 #define ARCMSR_MESSAGE_INT_CLEAR_PATTERN 0xFF00FFF7 280 /* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 281 #define ARCMSR_MESSAGE_GET_CONFIG 0x00010008 282 /* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 283 #define ARCMSR_MESSAGE_SET_CONFIG 0x00020008 284 /* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 285 #define ARCMSR_MESSAGE_ABORT_CMD 0x00030008 286 /* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 287 #define ARCMSR_MESSAGE_STOP_BGRB 0x00040008 288 /* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 289 #define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008 290 /* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 291 #define ARCMSR_MESSAGE_START_BGRB 0x00060008 292 #define ARCMSR_MESSAGE_SYNC_TIMER 0x00080008 293 #define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008 294 #define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008 295 #define ARCMSR_MESSAGE_ACTIVE_EOI_MODE 0x00100008 296 /* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */ 297 #define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000 298 /* ioctl transfer */ 299 #define ARCMSR_DRV2IOP_DATA_WRITE_OK 0x00000001 300 /* ioctl transfer */ 301 #define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002 302 #define ARCMSR_DRV2IOP_CDB_POSTED 0x00000004 303 #define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED 0x00000008 304 #define ARCMSR_DRV2IOP_END_OF_INTERRUPT 0x00000010 305 306 /* data tunnel buffer between user space program and its firmware */ 307 /* user space data to iop 128bytes */ 308 #define ARCMSR_MESSAGE_WBUFFER 0x0000fe00 309 /* iop data to user space 128bytes */ 310 #define ARCMSR_MESSAGE_RBUFFER 0x0000ff00 311 /* iop message_rwbuffer for message command */ 312 #define ARCMSR_MESSAGE_RWBUFFER 0x0000fa00 313 314 #define MEM_BASE0(x) (u32 __iomem *)((unsigned long)acb->mem_base0 + x) 315 #define MEM_BASE1(x) (u32 __iomem *)((unsigned long)acb->mem_base1 + x) 316 /* 317 ************************************************************************ 318 ** SPEC. for Areca HBC adapter 319 ************************************************************************ 320 */ 321 #define ARCMSR_HBC_ISR_THROTTLING_LEVEL 12 322 #define ARCMSR_HBC_ISR_MAX_DONE_QUEUE 20 323 /* Host Interrupt Mask */ 324 #define ARCMSR_HBCMU_UTILITY_A_ISR_MASK 0x00000001 /* When clear, the Utility_A interrupt routes to the host.*/ 325 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK 0x00000004 /* When clear, the General Outbound Doorbell interrupt routes to the host.*/ 326 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK 0x00000008 /* When clear, the Outbound Post List FIFO Not Empty interrupt routes to the host.*/ 327 #define ARCMSR_HBCMU_ALL_INTMASKENABLE 0x0000000D /* disable all ISR */ 328 /* Host Interrupt Status */ 329 #define ARCMSR_HBCMU_UTILITY_A_ISR 0x00000001 330 /* 331 ** Set when the Utility_A Interrupt bit is set in the Outbound Doorbell Register. 332 ** It clears by writing a 1 to the Utility_A bit in the Outbound Doorbell Clear Register or through automatic clearing (if enabled). 333 */ 334 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR 0x00000004 335 /* 336 ** Set if Outbound Doorbell register bits 30:1 have a non-zero 337 ** value. This bit clears only when Outbound Doorbell bits 338 ** 30:1 are ALL clear. Only a write to the Outbound Doorbell 339 ** Clear register clears bits in the Outbound Doorbell register. 340 */ 341 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR 0x00000008 342 /* 343 ** Set whenever the Outbound Post List Producer/Consumer 344 ** Register (FIFO) is not empty. It clears when the Outbound 345 ** Post List FIFO is empty. 346 */ 347 #define ARCMSR_HBCMU_SAS_ALL_INT 0x00000010 348 /* 349 ** This bit indicates a SAS interrupt from a source external to 350 ** the PCIe core. This bit is not maskable. 351 */ 352 /* DoorBell*/ 353 #define ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK 0x00000002 354 #define ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK 0x00000004 355 /*inbound message 0 ready*/ 356 #define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008 357 /*more than 12 request completed in a time*/ 358 #define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING 0x00000010 359 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 0x00000002 360 /*outbound DATA WRITE isr door bell clear*/ 361 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002 362 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 0x00000004 363 /*outbound DATA READ isr door bell clear*/ 364 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004 365 /*outbound message 0 ready*/ 366 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 367 /*outbound message cmd isr door bell clear*/ 368 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008 369 /*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/ 370 #define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000 371 /* 372 ******************************************************************************* 373 ** SPEC. for Areca Type D adapter 374 ******************************************************************************* 375 */ 376 #define ARCMSR_ARC1214_CHIP_ID 0x00004 377 #define ARCMSR_ARC1214_CPU_MEMORY_CONFIGURATION 0x00008 378 #define ARCMSR_ARC1214_I2_HOST_INTERRUPT_MASK 0x00034 379 #define ARCMSR_ARC1214_SAMPLE_RESET 0x00100 380 #define ARCMSR_ARC1214_RESET_REQUEST 0x00108 381 #define ARCMSR_ARC1214_MAIN_INTERRUPT_STATUS 0x00200 382 #define ARCMSR_ARC1214_PCIE_F0_INTERRUPT_ENABLE 0x0020C 383 #define ARCMSR_ARC1214_INBOUND_MESSAGE0 0x00400 384 #define ARCMSR_ARC1214_INBOUND_MESSAGE1 0x00404 385 #define ARCMSR_ARC1214_OUTBOUND_MESSAGE0 0x00420 386 #define ARCMSR_ARC1214_OUTBOUND_MESSAGE1 0x00424 387 #define ARCMSR_ARC1214_INBOUND_DOORBELL 0x00460 388 #define ARCMSR_ARC1214_OUTBOUND_DOORBELL 0x00480 389 #define ARCMSR_ARC1214_OUTBOUND_DOORBELL_ENABLE 0x00484 390 #define ARCMSR_ARC1214_INBOUND_LIST_BASE_LOW 0x01000 391 #define ARCMSR_ARC1214_INBOUND_LIST_BASE_HIGH 0x01004 392 #define ARCMSR_ARC1214_INBOUND_LIST_WRITE_POINTER 0x01018 393 #define ARCMSR_ARC1214_OUTBOUND_LIST_BASE_LOW 0x01060 394 #define ARCMSR_ARC1214_OUTBOUND_LIST_BASE_HIGH 0x01064 395 #define ARCMSR_ARC1214_OUTBOUND_LIST_COPY_POINTER 0x0106C 396 #define ARCMSR_ARC1214_OUTBOUND_LIST_READ_POINTER 0x01070 397 #define ARCMSR_ARC1214_OUTBOUND_INTERRUPT_CAUSE 0x01088 398 #define ARCMSR_ARC1214_OUTBOUND_INTERRUPT_ENABLE 0x0108C 399 #define ARCMSR_ARC1214_MESSAGE_WBUFFER 0x02000 400 #define ARCMSR_ARC1214_MESSAGE_RBUFFER 0x02100 401 #define ARCMSR_ARC1214_MESSAGE_RWBUFFER 0x02200 402 /* Host Interrupt Mask */ 403 #define ARCMSR_ARC1214_ALL_INT_ENABLE 0x00001010 404 #define ARCMSR_ARC1214_ALL_INT_DISABLE 0x00000000 405 /* Host Interrupt Status */ 406 #define ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR 0x00001000 407 #define ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR 0x00000010 408 /* DoorBell*/ 409 #define ARCMSR_ARC1214_DRV2IOP_DATA_IN_READY 0x00000001 410 #define ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ 0x00000002 411 /*inbound message 0 ready*/ 412 #define ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK 0x00000001 413 /*outbound DATA WRITE isr door bell clear*/ 414 #define ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK 0x00000002 415 /*outbound message 0 ready*/ 416 #define ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE 0x02000000 417 /*outbound message cmd isr door bell clear*/ 418 /*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/ 419 #define ARCMSR_ARC1214_MESSAGE_FIRMWARE_OK 0x80000000 420 #define ARCMSR_ARC1214_OUTBOUND_LIST_INTERRUPT_CLEAR 0x00000001 421 /* 422 ******************************************************************************* 423 ** SPEC. for Areca Type E adapter 424 ******************************************************************************* 425 */ 426 #define ARCMSR_SIGNATURE_1884 0x188417D3 427 428 #define ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK 0x00000002 429 #define ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK 0x00000004 430 #define ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008 431 432 #define ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK 0x00000002 433 #define ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK 0x00000004 434 #define ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 435 436 #define ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK 0x80000000 437 438 #define ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR 0x00000001 439 #define ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR 0x00000008 440 #define ARCMSR_HBEMU_ALL_INTMASKENABLE 0x00000009 441 442 /* ARC-1884 doorbell sync */ 443 #define ARCMSR_HBEMU_DOORBELL_SYNC 0x100 444 #define ARCMSR_ARC188X_RESET_ADAPTER 0x00000004 445 #define ARCMSR_ARC1884_DiagWrite_ENABLE 0x00000080 446 447 /* 448 ******************************************************************************* 449 ** SPEC. for Areca Type F adapter 450 ******************************************************************************* 451 */ 452 #define ARCMSR_SIGNATURE_1886 0x188617D3 453 // Doorbell and interrupt definition are same as Type E adapter 454 /* ARC-1886 doorbell sync */ 455 #define ARCMSR_HBFMU_DOORBELL_SYNC 0x100 456 //set host rw buffer physical address at inbound message 0, 1 (low,high) 457 #define ARCMSR_HBFMU_DOORBELL_SYNC1 0x300 458 #define ARCMSR_HBFMU_MESSAGE_FIRMWARE_OK 0x80000000 459 #define ARCMSR_HBFMU_MESSAGE_NO_VOLUME_CHANGE 0x20000000 460 461 /* 462 ******************************************************************************* 463 ** ARECA SCSI COMMAND DESCRIPTOR BLOCK size 0x1F8 (504) 464 ******************************************************************************* 465 */ 466 struct ARCMSR_CDB 467 { 468 uint8_t Bus; 469 uint8_t TargetID; 470 uint8_t LUN; 471 uint8_t Function; 472 uint8_t CdbLength; 473 uint8_t sgcount; 474 uint8_t Flags; 475 #define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01 476 #define ARCMSR_CDB_FLAG_BIOS 0x02 477 #define ARCMSR_CDB_FLAG_WRITE 0x04 478 #define ARCMSR_CDB_FLAG_SIMPLEQ 0x00 479 #define ARCMSR_CDB_FLAG_HEADQ 0x08 480 #define ARCMSR_CDB_FLAG_ORDEREDQ 0x10 481 482 uint8_t msgPages; 483 uint32_t msgContext; 484 uint32_t DataLength; 485 uint8_t Cdb[16]; 486 uint8_t DeviceStatus; 487 #define ARCMSR_DEV_CHECK_CONDITION 0x02 488 #define ARCMSR_DEV_SELECT_TIMEOUT 0xF0 489 #define ARCMSR_DEV_ABORTED 0xF1 490 #define ARCMSR_DEV_INIT_FAIL 0xF2 491 492 uint8_t SenseData[15]; 493 union 494 { 495 struct SG32ENTRY sg32entry[1]; 496 struct SG64ENTRY sg64entry[1]; 497 } u; 498 }; 499 /* 500 ******************************************************************************* 501 ** Messaging Unit (MU) of the Intel R 80331 I/O processor(Type A) and Type B processor 502 ******************************************************************************* 503 */ 504 struct MessageUnit_A 505 { 506 uint32_t resrved0[4]; /*0000 000F*/ 507 uint32_t inbound_msgaddr0; /*0010 0013*/ 508 uint32_t inbound_msgaddr1; /*0014 0017*/ 509 uint32_t outbound_msgaddr0; /*0018 001B*/ 510 uint32_t outbound_msgaddr1; /*001C 001F*/ 511 uint32_t inbound_doorbell; /*0020 0023*/ 512 uint32_t inbound_intstatus; /*0024 0027*/ 513 uint32_t inbound_intmask; /*0028 002B*/ 514 uint32_t outbound_doorbell; /*002C 002F*/ 515 uint32_t outbound_intstatus; /*0030 0033*/ 516 uint32_t outbound_intmask; /*0034 0037*/ 517 uint32_t reserved1[2]; /*0038 003F*/ 518 uint32_t inbound_queueport; /*0040 0043*/ 519 uint32_t outbound_queueport; /*0044 0047*/ 520 uint32_t reserved2[2]; /*0048 004F*/ 521 uint32_t reserved3[492]; /*0050 07FF 492*/ 522 uint32_t reserved4[128]; /*0800 09FF 128*/ 523 uint32_t message_rwbuffer[256]; /*0a00 0DFF 256*/ 524 uint32_t message_wbuffer[32]; /*0E00 0E7F 32*/ 525 uint32_t reserved5[32]; /*0E80 0EFF 32*/ 526 uint32_t message_rbuffer[32]; /*0F00 0F7F 32*/ 527 uint32_t reserved6[32]; /*0F80 0FFF 32*/ 528 }; 529 530 struct MessageUnit_B 531 { 532 uint32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; 533 uint32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; 534 uint32_t postq_index; 535 uint32_t doneq_index; 536 uint32_t __iomem *drv2iop_doorbell; 537 uint32_t __iomem *drv2iop_doorbell_mask; 538 uint32_t __iomem *iop2drv_doorbell; 539 uint32_t __iomem *iop2drv_doorbell_mask; 540 uint32_t __iomem *message_rwbuffer; 541 uint32_t __iomem *message_wbuffer; 542 uint32_t __iomem *message_rbuffer; 543 }; 544 /* 545 ********************************************************************* 546 ** LSI 547 ********************************************************************* 548 */ 549 struct MessageUnit_C{ 550 uint32_t message_unit_status; /*0000 0003*/ 551 uint32_t slave_error_attribute; /*0004 0007*/ 552 uint32_t slave_error_address; /*0008 000B*/ 553 uint32_t posted_outbound_doorbell; /*000C 000F*/ 554 uint32_t master_error_attribute; /*0010 0013*/ 555 uint32_t master_error_address_low; /*0014 0017*/ 556 uint32_t master_error_address_high; /*0018 001B*/ 557 uint32_t hcb_size; /*001C 001F*/ 558 uint32_t inbound_doorbell; /*0020 0023*/ 559 uint32_t diagnostic_rw_data; /*0024 0027*/ 560 uint32_t diagnostic_rw_address_low; /*0028 002B*/ 561 uint32_t diagnostic_rw_address_high; /*002C 002F*/ 562 uint32_t host_int_status; /*0030 0033*/ 563 uint32_t host_int_mask; /*0034 0037*/ 564 uint32_t dcr_data; /*0038 003B*/ 565 uint32_t dcr_address; /*003C 003F*/ 566 uint32_t inbound_queueport; /*0040 0043*/ 567 uint32_t outbound_queueport; /*0044 0047*/ 568 uint32_t hcb_pci_address_low; /*0048 004B*/ 569 uint32_t hcb_pci_address_high; /*004C 004F*/ 570 uint32_t iop_int_status; /*0050 0053*/ 571 uint32_t iop_int_mask; /*0054 0057*/ 572 uint32_t iop_inbound_queue_port; /*0058 005B*/ 573 uint32_t iop_outbound_queue_port; /*005C 005F*/ 574 uint32_t inbound_free_list_index; /*0060 0063*/ 575 uint32_t inbound_post_list_index; /*0064 0067*/ 576 uint32_t outbound_free_list_index; /*0068 006B*/ 577 uint32_t outbound_post_list_index; /*006C 006F*/ 578 uint32_t inbound_doorbell_clear; /*0070 0073*/ 579 uint32_t i2o_message_unit_control; /*0074 0077*/ 580 uint32_t last_used_message_source_address_low; /*0078 007B*/ 581 uint32_t last_used_message_source_address_high; /*007C 007F*/ 582 uint32_t pull_mode_data_byte_count[4]; /*0080 008F*/ 583 uint32_t message_dest_address_index; /*0090 0093*/ 584 uint32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/ 585 uint32_t utility_A_int_counter_timer; /*0098 009B*/ 586 uint32_t outbound_doorbell; /*009C 009F*/ 587 uint32_t outbound_doorbell_clear; /*00A0 00A3*/ 588 uint32_t message_source_address_index; /*00A4 00A7*/ 589 uint32_t message_done_queue_index; /*00A8 00AB*/ 590 uint32_t reserved0; /*00AC 00AF*/ 591 uint32_t inbound_msgaddr0; /*00B0 00B3*/ 592 uint32_t inbound_msgaddr1; /*00B4 00B7*/ 593 uint32_t outbound_msgaddr0; /*00B8 00BB*/ 594 uint32_t outbound_msgaddr1; /*00BC 00BF*/ 595 uint32_t inbound_queueport_low; /*00C0 00C3*/ 596 uint32_t inbound_queueport_high; /*00C4 00C7*/ 597 uint32_t outbound_queueport_low; /*00C8 00CB*/ 598 uint32_t outbound_queueport_high; /*00CC 00CF*/ 599 uint32_t iop_inbound_queue_port_low; /*00D0 00D3*/ 600 uint32_t iop_inbound_queue_port_high; /*00D4 00D7*/ 601 uint32_t iop_outbound_queue_port_low; /*00D8 00DB*/ 602 uint32_t iop_outbound_queue_port_high; /*00DC 00DF*/ 603 uint32_t message_dest_queue_port_low; /*00E0 00E3*/ 604 uint32_t message_dest_queue_port_high; /*00E4 00E7*/ 605 uint32_t last_used_message_dest_address_low; /*00E8 00EB*/ 606 uint32_t last_used_message_dest_address_high; /*00EC 00EF*/ 607 uint32_t message_done_queue_base_address_low; /*00F0 00F3*/ 608 uint32_t message_done_queue_base_address_high; /*00F4 00F7*/ 609 uint32_t host_diagnostic; /*00F8 00FB*/ 610 uint32_t write_sequence; /*00FC 00FF*/ 611 uint32_t reserved1[34]; /*0100 0187*/ 612 uint32_t reserved2[1950]; /*0188 1FFF*/ 613 uint32_t message_wbuffer[32]; /*2000 207F*/ 614 uint32_t reserved3[32]; /*2080 20FF*/ 615 uint32_t message_rbuffer[32]; /*2100 217F*/ 616 uint32_t reserved4[32]; /*2180 21FF*/ 617 uint32_t msgcode_rwbuffer[256]; /*2200 23FF*/ 618 }; 619 /* 620 ********************************************************************* 621 ** Messaging Unit (MU) of Type D processor 622 ********************************************************************* 623 */ 624 struct InBound_SRB { 625 uint32_t addressLow; /* pointer to SRB block */ 626 uint32_t addressHigh; 627 uint32_t length; /* in DWORDs */ 628 uint32_t reserved0; 629 }; 630 631 struct OutBound_SRB { 632 uint32_t addressLow; /* pointer to SRB block */ 633 uint32_t addressHigh; 634 }; 635 636 struct MessageUnit_D { 637 struct InBound_SRB post_qbuffer[ARCMSR_MAX_ARC1214_POSTQUEUE]; 638 volatile struct OutBound_SRB 639 done_qbuffer[ARCMSR_MAX_ARC1214_DONEQUEUE]; 640 u16 postq_index; 641 volatile u16 doneq_index; 642 u32 __iomem *chip_id; /* 0x00004 */ 643 u32 __iomem *cpu_mem_config; /* 0x00008 */ 644 u32 __iomem *i2o_host_interrupt_mask; /* 0x00034 */ 645 u32 __iomem *sample_at_reset; /* 0x00100 */ 646 u32 __iomem *reset_request; /* 0x00108 */ 647 u32 __iomem *host_int_status; /* 0x00200 */ 648 u32 __iomem *pcief0_int_enable; /* 0x0020C */ 649 u32 __iomem *inbound_msgaddr0; /* 0x00400 */ 650 u32 __iomem *inbound_msgaddr1; /* 0x00404 */ 651 u32 __iomem *outbound_msgaddr0; /* 0x00420 */ 652 u32 __iomem *outbound_msgaddr1; /* 0x00424 */ 653 u32 __iomem *inbound_doorbell; /* 0x00460 */ 654 u32 __iomem *outbound_doorbell; /* 0x00480 */ 655 u32 __iomem *outbound_doorbell_enable; /* 0x00484 */ 656 u32 __iomem *inboundlist_base_low; /* 0x01000 */ 657 u32 __iomem *inboundlist_base_high; /* 0x01004 */ 658 u32 __iomem *inboundlist_write_pointer; /* 0x01018 */ 659 u32 __iomem *outboundlist_base_low; /* 0x01060 */ 660 u32 __iomem *outboundlist_base_high; /* 0x01064 */ 661 u32 __iomem *outboundlist_copy_pointer; /* 0x0106C */ 662 u32 __iomem *outboundlist_read_pointer; /* 0x01070 0x01072 */ 663 u32 __iomem *outboundlist_interrupt_cause; /* 0x1088 */ 664 u32 __iomem *outboundlist_interrupt_enable; /* 0x108C */ 665 u32 __iomem *message_wbuffer; /* 0x2000 */ 666 u32 __iomem *message_rbuffer; /* 0x2100 */ 667 u32 __iomem *msgcode_rwbuffer; /* 0x2200 */ 668 }; 669 /* 670 ********************************************************************* 671 ** Messaging Unit (MU) of Type E processor(LSI) 672 ********************************************************************* 673 */ 674 struct MessageUnit_E{ 675 uint32_t iobound_doorbell; /*0000 0003*/ 676 uint32_t write_sequence_3xxx; /*0004 0007*/ 677 uint32_t host_diagnostic_3xxx; /*0008 000B*/ 678 uint32_t posted_outbound_doorbell; /*000C 000F*/ 679 uint32_t master_error_attribute; /*0010 0013*/ 680 uint32_t master_error_address_low; /*0014 0017*/ 681 uint32_t master_error_address_high; /*0018 001B*/ 682 uint32_t hcb_size; /*001C 001F*/ 683 uint32_t inbound_doorbell; /*0020 0023*/ 684 uint32_t diagnostic_rw_data; /*0024 0027*/ 685 uint32_t diagnostic_rw_address_low; /*0028 002B*/ 686 uint32_t diagnostic_rw_address_high; /*002C 002F*/ 687 uint32_t host_int_status; /*0030 0033*/ 688 uint32_t host_int_mask; /*0034 0037*/ 689 uint32_t dcr_data; /*0038 003B*/ 690 uint32_t dcr_address; /*003C 003F*/ 691 uint32_t inbound_queueport; /*0040 0043*/ 692 uint32_t outbound_queueport; /*0044 0047*/ 693 uint32_t hcb_pci_address_low; /*0048 004B*/ 694 uint32_t hcb_pci_address_high; /*004C 004F*/ 695 uint32_t iop_int_status; /*0050 0053*/ 696 uint32_t iop_int_mask; /*0054 0057*/ 697 uint32_t iop_inbound_queue_port; /*0058 005B*/ 698 uint32_t iop_outbound_queue_port; /*005C 005F*/ 699 uint32_t inbound_free_list_index; /*0060 0063*/ 700 uint32_t inbound_post_list_index; /*0064 0067*/ 701 uint32_t reply_post_producer_index; /*0068 006B*/ 702 uint32_t reply_post_consumer_index; /*006C 006F*/ 703 uint32_t inbound_doorbell_clear; /*0070 0073*/ 704 uint32_t i2o_message_unit_control; /*0074 0077*/ 705 uint32_t last_used_message_source_address_low; /*0078 007B*/ 706 uint32_t last_used_message_source_address_high; /*007C 007F*/ 707 uint32_t pull_mode_data_byte_count[4]; /*0080 008F*/ 708 uint32_t message_dest_address_index; /*0090 0093*/ 709 uint32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/ 710 uint32_t utility_A_int_counter_timer; /*0098 009B*/ 711 uint32_t outbound_doorbell; /*009C 009F*/ 712 uint32_t outbound_doorbell_clear; /*00A0 00A3*/ 713 uint32_t message_source_address_index; /*00A4 00A7*/ 714 uint32_t message_done_queue_index; /*00A8 00AB*/ 715 uint32_t reserved0; /*00AC 00AF*/ 716 uint32_t inbound_msgaddr0; /*00B0 00B3*/ 717 uint32_t inbound_msgaddr1; /*00B4 00B7*/ 718 uint32_t outbound_msgaddr0; /*00B8 00BB*/ 719 uint32_t outbound_msgaddr1; /*00BC 00BF*/ 720 uint32_t inbound_queueport_low; /*00C0 00C3*/ 721 uint32_t inbound_queueport_high; /*00C4 00C7*/ 722 uint32_t outbound_queueport_low; /*00C8 00CB*/ 723 uint32_t outbound_queueport_high; /*00CC 00CF*/ 724 uint32_t iop_inbound_queue_port_low; /*00D0 00D3*/ 725 uint32_t iop_inbound_queue_port_high; /*00D4 00D7*/ 726 uint32_t iop_outbound_queue_port_low; /*00D8 00DB*/ 727 uint32_t iop_outbound_queue_port_high; /*00DC 00DF*/ 728 uint32_t message_dest_queue_port_low; /*00E0 00E3*/ 729 uint32_t message_dest_queue_port_high; /*00E4 00E7*/ 730 uint32_t last_used_message_dest_address_low; /*00E8 00EB*/ 731 uint32_t last_used_message_dest_address_high; /*00EC 00EF*/ 732 uint32_t message_done_queue_base_address_low; /*00F0 00F3*/ 733 uint32_t message_done_queue_base_address_high; /*00F4 00F7*/ 734 uint32_t host_diagnostic; /*00F8 00FB*/ 735 uint32_t write_sequence; /*00FC 00FF*/ 736 uint32_t reserved1[34]; /*0100 0187*/ 737 uint32_t reserved2[1950]; /*0188 1FFF*/ 738 uint32_t message_wbuffer[32]; /*2000 207F*/ 739 uint32_t reserved3[32]; /*2080 20FF*/ 740 uint32_t message_rbuffer[32]; /*2100 217F*/ 741 uint32_t reserved4[32]; /*2180 21FF*/ 742 uint32_t msgcode_rwbuffer[256]; /*2200 23FF*/ 743 }; 744 745 /* 746 ********************************************************************* 747 ** Messaging Unit (MU) of Type F processor(LSI) 748 ********************************************************************* 749 */ 750 struct MessageUnit_F { 751 uint32_t iobound_doorbell; /*0000 0003*/ 752 uint32_t write_sequence_3xxx; /*0004 0007*/ 753 uint32_t host_diagnostic_3xxx; /*0008 000B*/ 754 uint32_t posted_outbound_doorbell; /*000C 000F*/ 755 uint32_t master_error_attribute; /*0010 0013*/ 756 uint32_t master_error_address_low; /*0014 0017*/ 757 uint32_t master_error_address_high; /*0018 001B*/ 758 uint32_t hcb_size; /*001C 001F*/ 759 uint32_t inbound_doorbell; /*0020 0023*/ 760 uint32_t diagnostic_rw_data; /*0024 0027*/ 761 uint32_t diagnostic_rw_address_low; /*0028 002B*/ 762 uint32_t diagnostic_rw_address_high; /*002C 002F*/ 763 uint32_t host_int_status; /*0030 0033*/ 764 uint32_t host_int_mask; /*0034 0037*/ 765 uint32_t dcr_data; /*0038 003B*/ 766 uint32_t dcr_address; /*003C 003F*/ 767 uint32_t inbound_queueport; /*0040 0043*/ 768 uint32_t outbound_queueport; /*0044 0047*/ 769 uint32_t hcb_pci_address_low; /*0048 004B*/ 770 uint32_t hcb_pci_address_high; /*004C 004F*/ 771 uint32_t iop_int_status; /*0050 0053*/ 772 uint32_t iop_int_mask; /*0054 0057*/ 773 uint32_t iop_inbound_queue_port; /*0058 005B*/ 774 uint32_t iop_outbound_queue_port; /*005C 005F*/ 775 uint32_t inbound_free_list_index; /*0060 0063*/ 776 uint32_t inbound_post_list_index; /*0064 0067*/ 777 uint32_t reply_post_producer_index; /*0068 006B*/ 778 uint32_t reply_post_consumer_index; /*006C 006F*/ 779 uint32_t inbound_doorbell_clear; /*0070 0073*/ 780 uint32_t i2o_message_unit_control; /*0074 0077*/ 781 uint32_t last_used_message_source_address_low; /*0078 007B*/ 782 uint32_t last_used_message_source_address_high; /*007C 007F*/ 783 uint32_t pull_mode_data_byte_count[4]; /*0080 008F*/ 784 uint32_t message_dest_address_index; /*0090 0093*/ 785 uint32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/ 786 uint32_t utility_A_int_counter_timer; /*0098 009B*/ 787 uint32_t outbound_doorbell; /*009C 009F*/ 788 uint32_t outbound_doorbell_clear; /*00A0 00A3*/ 789 uint32_t message_source_address_index; /*00A4 00A7*/ 790 uint32_t message_done_queue_index; /*00A8 00AB*/ 791 uint32_t reserved0; /*00AC 00AF*/ 792 uint32_t inbound_msgaddr0; /*00B0 00B3*/ 793 uint32_t inbound_msgaddr1; /*00B4 00B7*/ 794 uint32_t outbound_msgaddr0; /*00B8 00BB*/ 795 uint32_t outbound_msgaddr1; /*00BC 00BF*/ 796 uint32_t inbound_queueport_low; /*00C0 00C3*/ 797 uint32_t inbound_queueport_high; /*00C4 00C7*/ 798 uint32_t outbound_queueport_low; /*00C8 00CB*/ 799 uint32_t outbound_queueport_high; /*00CC 00CF*/ 800 uint32_t iop_inbound_queue_port_low; /*00D0 00D3*/ 801 uint32_t iop_inbound_queue_port_high; /*00D4 00D7*/ 802 uint32_t iop_outbound_queue_port_low; /*00D8 00DB*/ 803 uint32_t iop_outbound_queue_port_high; /*00DC 00DF*/ 804 uint32_t message_dest_queue_port_low; /*00E0 00E3*/ 805 uint32_t message_dest_queue_port_high; /*00E4 00E7*/ 806 uint32_t last_used_message_dest_address_low; /*00E8 00EB*/ 807 uint32_t last_used_message_dest_address_high; /*00EC 00EF*/ 808 uint32_t message_done_queue_base_address_low; /*00F0 00F3*/ 809 uint32_t message_done_queue_base_address_high; /*00F4 00F7*/ 810 uint32_t host_diagnostic; /*00F8 00FB*/ 811 uint32_t write_sequence; /*00FC 00FF*/ 812 uint32_t reserved1[46]; /*0100 01B7*/ 813 uint32_t reply_post_producer_index1; /*01B8 01BB*/ 814 uint32_t reply_post_consumer_index1; /*01BC 01BF*/ 815 }; 816 817 #define MESG_RW_BUFFER_SIZE (256 * 3) 818 819 typedef struct deliver_completeQ { 820 uint16_t cmdFlag; 821 uint16_t cmdSMID; 822 uint16_t cmdLMID; // reserved (0) 823 uint16_t cmdFlag2; // reserved (0) 824 } DeliverQ, CompletionQ, *pDeliver_Q, *pCompletion_Q; 825 /* 826 ******************************************************************************* 827 ** Adapter Control Block 828 ******************************************************************************* 829 */ 830 struct AdapterControlBlock 831 { 832 uint32_t adapter_type; /* adapter A,B..... */ 833 #define ACB_ADAPTER_TYPE_A 0x00000000 /* hba I IOP */ 834 #define ACB_ADAPTER_TYPE_B 0x00000001 /* hbb M IOP */ 835 #define ACB_ADAPTER_TYPE_C 0x00000002 /* hbc L IOP */ 836 #define ACB_ADAPTER_TYPE_D 0x00000003 /* hbd M IOP */ 837 #define ACB_ADAPTER_TYPE_E 0x00000004 /* hba L IOP */ 838 #define ACB_ADAPTER_TYPE_F 0x00000005 /* hba L IOP */ 839 u32 ioqueue_size; 840 struct pci_dev * pdev; 841 struct Scsi_Host * host; 842 unsigned long vir2phy_offset; 843 /* Offset is used in making arc cdb physical to virtual calculations */ 844 uint32_t outbound_int_enable; 845 uint32_t cdb_phyaddr_hi32; 846 uint32_t reg_mu_acc_handle0; 847 uint64_t cdb_phyadd_hipart; 848 spinlock_t eh_lock; 849 spinlock_t ccblist_lock; 850 spinlock_t postq_lock; 851 spinlock_t doneq_lock; 852 spinlock_t rqbuffer_lock; 853 spinlock_t wqbuffer_lock; 854 union { 855 struct MessageUnit_A __iomem *pmuA; 856 struct MessageUnit_B *pmuB; 857 struct MessageUnit_C __iomem *pmuC; 858 struct MessageUnit_D *pmuD; 859 struct MessageUnit_E __iomem *pmuE; 860 struct MessageUnit_F __iomem *pmuF; 861 }; 862 /* message unit ATU inbound base address0 */ 863 void __iomem *mem_base0; 864 void __iomem *mem_base1; 865 //0x000 - COMPORT_IN (Host sent to ROC) 866 uint32_t *message_wbuffer; 867 //0x100 - COMPORT_OUT (ROC sent to Host) 868 uint32_t *message_rbuffer; 869 uint32_t *msgcode_rwbuffer; //0x200 - BIOS_AREA 870 uint32_t acb_flags; 871 u16 dev_id; 872 uint8_t adapter_index; 873 #define ACB_F_SCSISTOPADAPTER 0x0001 874 #define ACB_F_MSG_STOP_BGRB 0x0002 875 /* stop RAID background rebuild */ 876 #define ACB_F_MSG_START_BGRB 0x0004 877 /* stop RAID background rebuild */ 878 #define ACB_F_IOPDATA_OVERFLOW 0x0008 879 /* iop message data rqbuffer overflow */ 880 #define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 881 /* message clear wqbuffer */ 882 #define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 883 /* message clear rqbuffer */ 884 #define ACB_F_MESSAGE_WQBUFFER_READED 0x0040 885 #define ACB_F_BUS_RESET 0x0080 886 887 #define ACB_F_IOP_INITED 0x0100 888 /* iop init */ 889 #define ACB_F_ABORT 0x0200 890 #define ACB_F_FIRMWARE_TRAP 0x0400 891 #define ACB_F_ADAPTER_REMOVED 0x0800 892 #define ACB_F_MSG_GET_CONFIG 0x1000 893 struct CommandControlBlock * pccb_pool[ARCMSR_MAX_FREECCB_NUM]; 894 /* used for memory free */ 895 struct list_head ccb_free_list; 896 /* head of free ccb list */ 897 898 atomic_t ccboutstandingcount; 899 /*The present outstanding command number that in the IOP that 900 waiting for being handled by FW*/ 901 902 void * dma_coherent; 903 /* dma_coherent used for memory free */ 904 dma_addr_t dma_coherent_handle; 905 /* dma_coherent_handle used for memory free */ 906 dma_addr_t dma_coherent_handle2; 907 void *dma_coherent2; 908 unsigned int uncache_size; 909 uint8_t rqbuffer[ARCMSR_MAX_QBUFFER]; 910 /* data collection buffer for read from 80331 */ 911 int32_t rqbuf_getIndex; 912 /* first of read buffer */ 913 int32_t rqbuf_putIndex; 914 /* last of read buffer */ 915 uint8_t wqbuffer[ARCMSR_MAX_QBUFFER]; 916 /* data collection buffer for write to 80331 */ 917 int32_t wqbuf_getIndex; 918 /* first of write buffer */ 919 int32_t wqbuf_putIndex; 920 /* last of write buffer */ 921 uint8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; 922 /* id0 ..... id15, lun0...lun7 */ 923 #define ARECA_RAID_GONE 0x55 924 #define ARECA_RAID_GOOD 0xaa 925 uint32_t num_resets; 926 uint32_t num_aborts; 927 uint32_t signature; 928 uint32_t firm_request_len; 929 uint32_t firm_numbers_queue; 930 uint32_t firm_sdram_size; 931 uint32_t firm_hd_channels; 932 uint32_t firm_cfg_version; 933 char firm_model[12]; 934 char firm_version[20]; 935 char device_map[20]; /*21,84-99*/ 936 struct work_struct arcmsr_do_message_isr_bh; 937 struct timer_list eternal_timer; 938 unsigned short fw_flag; 939 #define FW_NORMAL 0x0000 940 #define FW_BOG 0x0001 941 #define FW_DEADLOCK 0x0010 942 uint32_t maxOutstanding; 943 int vector_count; 944 uint32_t maxFreeCCB; 945 struct timer_list refresh_timer; 946 uint32_t doneq_index; 947 uint32_t ccbsize; 948 uint32_t in_doorbell; 949 uint32_t out_doorbell; 950 uint32_t completionQ_entry; 951 pCompletion_Q pCompletionQ; 952 uint32_t completeQ_size; 953 };/* HW_DEVICE_EXTENSION */ 954 /* 955 ******************************************************************************* 956 ** Command Control Block 957 ** this CCB length must be 32 bytes boundary 958 ******************************************************************************* 959 */ 960 struct CommandControlBlock{ 961 /*x32:sizeof struct_CCB=(64+60)byte, x64:sizeof struct_CCB=(64+60)byte*/ 962 struct list_head list; /*x32: 8byte, x64: 16byte*/ 963 struct scsi_cmnd *pcmd; /*8 bytes pointer of linux scsi command */ 964 struct AdapterControlBlock *acb; /*x32: 4byte, x64: 8byte*/ 965 unsigned long cdb_phyaddr; /*x32: 4byte, x64: 8byte*/ 966 uint32_t arc_cdb_size; /*x32:4byte,x64:4byte*/ 967 uint16_t ccb_flags; /*x32: 2byte, x64: 2byte*/ 968 #define CCB_FLAG_READ 0x0000 969 #define CCB_FLAG_WRITE 0x0001 970 #define CCB_FLAG_ERROR 0x0002 971 #define CCB_FLAG_FLUSHCACHE 0x0004 972 #define CCB_FLAG_MASTER_ABORTED 0x0008 973 uint16_t startdone; /*x32:2byte,x32:2byte*/ 974 #define ARCMSR_CCB_DONE 0x0000 975 #define ARCMSR_CCB_START 0x55AA 976 #define ARCMSR_CCB_ABORTED 0xAA55 977 #define ARCMSR_CCB_ILLEGAL 0xFFFF 978 uint32_t smid; 979 #if BITS_PER_LONG == 64 980 /* ======================512+64 bytes======================== */ 981 uint32_t reserved[3]; /*12 byte*/ 982 #else 983 /* ======================512+32 bytes======================== */ 984 uint32_t reserved[8]; /*32 byte*/ 985 #endif 986 /* ======================================================= */ 987 struct ARCMSR_CDB arcmsr_cdb; 988 }; 989 /* 990 ******************************************************************************* 991 ** ARECA SCSI sense data 992 ******************************************************************************* 993 */ 994 struct SENSE_DATA 995 { 996 uint8_t ErrorCode:7; 997 #define SCSI_SENSE_CURRENT_ERRORS 0x70 998 #define SCSI_SENSE_DEFERRED_ERRORS 0x71 999 uint8_t Valid:1; 1000 uint8_t SegmentNumber; 1001 uint8_t SenseKey:4; 1002 uint8_t Reserved:1; 1003 uint8_t IncorrectLength:1; 1004 uint8_t EndOfMedia:1; 1005 uint8_t FileMark:1; 1006 uint8_t Information[4]; 1007 uint8_t AdditionalSenseLength; 1008 uint8_t CommandSpecificInformation[4]; 1009 uint8_t AdditionalSenseCode; 1010 uint8_t AdditionalSenseCodeQualifier; 1011 uint8_t FieldReplaceableUnitCode; 1012 uint8_t SenseKeySpecific[3]; 1013 }; 1014 /* 1015 ******************************************************************************* 1016 ** Outbound Interrupt Status Register - OISR 1017 ******************************************************************************* 1018 */ 1019 #define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30 1020 #define ARCMSR_MU_OUTBOUND_PCI_INT 0x10 1021 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08 1022 #define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04 1023 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02 1024 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01 1025 #define ARCMSR_MU_OUTBOUND_HANDLE_INT \ 1026 (ARCMSR_MU_OUTBOUND_MESSAGE0_INT \ 1027 |ARCMSR_MU_OUTBOUND_MESSAGE1_INT \ 1028 |ARCMSR_MU_OUTBOUND_DOORBELL_INT \ 1029 |ARCMSR_MU_OUTBOUND_POSTQUEUE_INT \ 1030 |ARCMSR_MU_OUTBOUND_PCI_INT) 1031 /* 1032 ******************************************************************************* 1033 ** Outbound Interrupt Mask Register - OIMR 1034 ******************************************************************************* 1035 */ 1036 #define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34 1037 #define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10 1038 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08 1039 #define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04 1040 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02 1041 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01 1042 #define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F 1043 1044 extern void arcmsr_write_ioctldata2iop(struct AdapterControlBlock *); 1045 extern uint32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *, 1046 struct QBUFFER __iomem *); 1047 extern void arcmsr_clear_iop2drv_rqueue_buffer(struct AdapterControlBlock *); 1048 extern struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *); 1049 extern const struct attribute_group *arcmsr_host_groups[]; 1050 extern int arcmsr_alloc_sysfs_attr(struct AdapterControlBlock *); 1051 void arcmsr_free_sysfs_attr(struct AdapterControlBlock *acb); 1052