1 /* 2 ******************************************************************************* 3 ** O.S : Linux 4 ** FILE NAME : arcmsr.h 5 ** BY : Erich Chen 6 ** Description: SCSI RAID Device Driver for 7 ** ARECA RAID Host adapter 8 ******************************************************************************* 9 ** Copyright (C) 2002 - 2005, Areca Technology Corporation All rights reserved. 10 ** 11 ** Web site: www.areca.com.tw 12 ** E-mail: support@areca.com.tw 13 ** 14 ** This program is free software; you can redistribute it and/or modify 15 ** it under the terms of the GNU General Public License version 2 as 16 ** published by the Free Software Foundation. 17 ** This program is distributed in the hope that it will be useful, 18 ** but WITHOUT ANY WARRANTY; without even the implied warranty of 19 ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 ** GNU General Public License for more details. 21 ******************************************************************************* 22 ** Redistribution and use in source and binary forms, with or without 23 ** modification, are permitted provided that the following conditions 24 ** are met: 25 ** 1. Redistributions of source code must retain the above copyright 26 ** notice, this list of conditions and the following disclaimer. 27 ** 2. Redistributions in binary form must reproduce the above copyright 28 ** notice, this list of conditions and the following disclaimer in the 29 ** documentation and/or other materials provided with the distribution. 30 ** 3. The name of the author may not be used to endorse or promote products 31 ** derived from this software without specific prior written permission. 32 ** 33 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 34 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 35 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 36 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 37 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT 38 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 39 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 40 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 41 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 42 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 43 ******************************************************************************* 44 */ 45 #include <linux/interrupt.h> 46 47 struct class_device_attribute; 48 /*The limit of outstanding scsi command that firmware can handle*/ 49 #define ARCMSR_MAX_OUTSTANDING_CMD 256 50 #define ARCMSR_MAX_FREECCB_NUM 320 51 #define ARCMSR_DRIVER_VERSION "Driver Version 1.20.00.15 2007/08/30" 52 #define ARCMSR_SCSI_INITIATOR_ID 255 53 #define ARCMSR_MAX_XFER_SECTORS 512 54 #define ARCMSR_MAX_XFER_SECTORS_B 4096 55 #define ARCMSR_MAX_TARGETID 17 56 #define ARCMSR_MAX_TARGETLUN 8 57 #define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD 58 #define ARCMSR_MAX_QBUFFER 4096 59 #define ARCMSR_MAX_SG_ENTRIES 38 60 #define ARCMSR_MAX_HBB_POSTQUEUE 264 61 /* 62 ********************************************************************************** 63 ** 64 ********************************************************************************** 65 */ 66 #define ARC_SUCCESS 0 67 #define ARC_FAILURE 1 68 /* 69 ******************************************************************************* 70 ** split 64bits dma addressing 71 ******************************************************************************* 72 */ 73 #define dma_addr_hi32(addr) (uint32_t) ((addr>>16)>>16) 74 #define dma_addr_lo32(addr) (uint32_t) (addr & 0xffffffff) 75 /* 76 ******************************************************************************* 77 ** MESSAGE CONTROL CODE 78 ******************************************************************************* 79 */ 80 struct CMD_MESSAGE 81 { 82 uint32_t HeaderLength; 83 uint8_t Signature[8]; 84 uint32_t Timeout; 85 uint32_t ControlCode; 86 uint32_t ReturnCode; 87 uint32_t Length; 88 }; 89 /* 90 ******************************************************************************* 91 ** IOP Message Transfer Data for user space 92 ******************************************************************************* 93 */ 94 struct CMD_MESSAGE_FIELD 95 { 96 struct CMD_MESSAGE cmdmessage; 97 uint8_t messagedatabuffer[1032]; 98 }; 99 /* IOP message transfer */ 100 #define ARCMSR_MESSAGE_FAIL 0x0001 101 /* DeviceType */ 102 #define ARECA_SATA_RAID 0x90000000 103 /* FunctionCode */ 104 #define FUNCTION_READ_RQBUFFER 0x0801 105 #define FUNCTION_WRITE_WQBUFFER 0x0802 106 #define FUNCTION_CLEAR_RQBUFFER 0x0803 107 #define FUNCTION_CLEAR_WQBUFFER 0x0804 108 #define FUNCTION_CLEAR_ALLQBUFFER 0x0805 109 #define FUNCTION_RETURN_CODE_3F 0x0806 110 #define FUNCTION_SAY_HELLO 0x0807 111 #define FUNCTION_SAY_GOODBYE 0x0808 112 #define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809 113 /* ARECA IO CONTROL CODE*/ 114 #define ARCMSR_MESSAGE_READ_RQBUFFER \ 115 ARECA_SATA_RAID | FUNCTION_READ_RQBUFFER 116 #define ARCMSR_MESSAGE_WRITE_WQBUFFER \ 117 ARECA_SATA_RAID | FUNCTION_WRITE_WQBUFFER 118 #define ARCMSR_MESSAGE_CLEAR_RQBUFFER \ 119 ARECA_SATA_RAID | FUNCTION_CLEAR_RQBUFFER 120 #define ARCMSR_MESSAGE_CLEAR_WQBUFFER \ 121 ARECA_SATA_RAID | FUNCTION_CLEAR_WQBUFFER 122 #define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER \ 123 ARECA_SATA_RAID | FUNCTION_CLEAR_ALLQBUFFER 124 #define ARCMSR_MESSAGE_RETURN_CODE_3F \ 125 ARECA_SATA_RAID | FUNCTION_RETURN_CODE_3F 126 #define ARCMSR_MESSAGE_SAY_HELLO \ 127 ARECA_SATA_RAID | FUNCTION_SAY_HELLO 128 #define ARCMSR_MESSAGE_SAY_GOODBYE \ 129 ARECA_SATA_RAID | FUNCTION_SAY_GOODBYE 130 #define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE \ 131 ARECA_SATA_RAID | FUNCTION_FLUSH_ADAPTER_CACHE 132 /* ARECA IOCTL ReturnCode */ 133 #define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001 134 #define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006 135 #define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F 136 /* 137 ************************************************************* 138 ** structure for holding DMA address data 139 ************************************************************* 140 */ 141 #define IS_SG64_ADDR 0x01000000 /* bit24 */ 142 struct SG32ENTRY 143 { 144 __le32 length; 145 __le32 address; 146 }; 147 struct SG64ENTRY 148 { 149 __le32 length; 150 __le32 address; 151 __le32 addresshigh; 152 }; 153 struct SGENTRY_UNION 154 { 155 union 156 { 157 struct SG32ENTRY sg32entry; 158 struct SG64ENTRY sg64entry; 159 }u; 160 }; 161 /* 162 ******************************************************************** 163 ** Q Buffer of IOP Message Transfer 164 ******************************************************************** 165 */ 166 struct QBUFFER 167 { 168 uint32_t data_len; 169 uint8_t data[124]; 170 }; 171 /* 172 ******************************************************************************* 173 ** FIRMWARE INFO for Intel IOP R 80331 processor (Type A) 174 ******************************************************************************* 175 */ 176 struct FIRMWARE_INFO 177 { 178 uint32_t signature; /*0, 00-03*/ 179 uint32_t request_len; /*1, 04-07*/ 180 uint32_t numbers_queue; /*2, 08-11*/ 181 uint32_t sdram_size; /*3, 12-15*/ 182 uint32_t ide_channels; /*4, 16-19*/ 183 char vendor[40]; /*5, 20-59*/ 184 char model[8]; /*15, 60-67*/ 185 char firmware_ver[16]; /*17, 68-83*/ 186 char device_map[16]; /*21, 84-99*/ 187 }; 188 /* signature of set and get firmware config */ 189 #define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060 190 #define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063 191 /* message code of inbound message register */ 192 #define ARCMSR_INBOUND_MESG0_NOP 0x00000000 193 #define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001 194 #define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002 195 #define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003 196 #define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004 197 #define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005 198 #define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006 199 #define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007 200 #define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008 201 /* doorbell interrupt generator */ 202 #define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001 203 #define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002 204 #define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001 205 #define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002 206 /* ccb areca cdb flag */ 207 #define ARCMSR_CCBPOST_FLAG_SGL_BSIZE 0x80000000 208 #define ARCMSR_CCBPOST_FLAG_IAM_BIOS 0x40000000 209 #define ARCMSR_CCBREPLY_FLAG_IAM_BIOS 0x40000000 210 #define ARCMSR_CCBREPLY_FLAG_ERROR 0x10000000 211 /* outbound firmware ok */ 212 #define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000 213 214 /* 215 ************************************************************************ 216 ** SPEC. for Areca Type B adapter 217 ************************************************************************ 218 */ 219 /* ARECA HBB COMMAND for its FIRMWARE */ 220 /* window of "instruction flags" from driver to iop */ 221 #define ARCMSR_DRV2IOP_DOORBELL 0x00020400 222 #define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404 223 /* window of "instruction flags" from iop to driver */ 224 #define ARCMSR_IOP2DRV_DOORBELL 0x00020408 225 #define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C 226 /* ARECA FLAG LANGUAGE */ 227 /* ioctl transfer */ 228 #define ARCMSR_IOP2DRV_DATA_WRITE_OK 0x00000001 229 /* ioctl transfer */ 230 #define ARCMSR_IOP2DRV_DATA_READ_OK 0x00000002 231 #define ARCMSR_IOP2DRV_CDB_DONE 0x00000004 232 #define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 233 234 #define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F 235 #define ARCMSR_DOORBELL_INT_CLEAR_PATTERN 0xFF00FFF0 236 #define ARCMSR_MESSAGE_INT_CLEAR_PATTERN 0xFF00FFF7 237 /* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 238 #define ARCMSR_MESSAGE_GET_CONFIG 0x00010008 239 /* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 240 #define ARCMSR_MESSAGE_SET_CONFIG 0x00020008 241 /* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 242 #define ARCMSR_MESSAGE_ABORT_CMD 0x00030008 243 /* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 244 #define ARCMSR_MESSAGE_STOP_BGRB 0x00040008 245 /* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 246 #define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008 247 /* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 248 #define ARCMSR_MESSAGE_START_BGRB 0x00060008 249 #define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008 250 #define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008 251 /* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */ 252 #define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000 253 /* ioctl transfer */ 254 #define ARCMSR_DRV2IOP_DATA_WRITE_OK 0x00000001 255 /* ioctl transfer */ 256 #define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002 257 #define ARCMSR_DRV2IOP_CDB_POSTED 0x00000004 258 #define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED 0x00000008 259 260 /* data tunnel buffer between user space program and its firmware */ 261 /* user space data to iop 128bytes */ 262 #define ARCMSR_IOCTL_WBUFFER 0x0000fe00 263 /* iop data to user space 128bytes */ 264 #define ARCMSR_IOCTL_RBUFFER 0x0000ff00 265 /* iop message_rwbuffer for message command */ 266 #define ARCMSR_MSGCODE_RWBUFFER 0x0000fa00 267 /* 268 ******************************************************************************* 269 ** ARECA SCSI COMMAND DESCRIPTOR BLOCK size 0x1F8 (504) 270 ******************************************************************************* 271 */ 272 struct ARCMSR_CDB 273 { 274 uint8_t Bus; 275 uint8_t TargetID; 276 uint8_t LUN; 277 uint8_t Function; 278 uint8_t CdbLength; 279 uint8_t sgcount; 280 uint8_t Flags; 281 #define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01 282 #define ARCMSR_CDB_FLAG_BIOS 0x02 283 #define ARCMSR_CDB_FLAG_WRITE 0x04 284 #define ARCMSR_CDB_FLAG_SIMPLEQ 0x00 285 #define ARCMSR_CDB_FLAG_HEADQ 0x08 286 #define ARCMSR_CDB_FLAG_ORDEREDQ 0x10 287 288 uint8_t Reserved1; 289 uint32_t Context; 290 uint32_t DataLength; 291 uint8_t Cdb[16]; 292 uint8_t DeviceStatus; 293 #define ARCMSR_DEV_CHECK_CONDITION 0x02 294 #define ARCMSR_DEV_SELECT_TIMEOUT 0xF0 295 #define ARCMSR_DEV_ABORTED 0xF1 296 #define ARCMSR_DEV_INIT_FAIL 0xF2 297 298 uint8_t SenseData[15]; 299 union 300 { 301 struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES]; 302 struct SG64ENTRY sg64entry[ARCMSR_MAX_SG_ENTRIES]; 303 } u; 304 }; 305 /* 306 ******************************************************************************* 307 ** Messaging Unit (MU) of the Intel R 80331 I/O processor(Type A) and Type B processor 308 ******************************************************************************* 309 */ 310 struct MessageUnit_A 311 { 312 uint32_t resrved0[4]; /*0000 000F*/ 313 uint32_t inbound_msgaddr0; /*0010 0013*/ 314 uint32_t inbound_msgaddr1; /*0014 0017*/ 315 uint32_t outbound_msgaddr0; /*0018 001B*/ 316 uint32_t outbound_msgaddr1; /*001C 001F*/ 317 uint32_t inbound_doorbell; /*0020 0023*/ 318 uint32_t inbound_intstatus; /*0024 0027*/ 319 uint32_t inbound_intmask; /*0028 002B*/ 320 uint32_t outbound_doorbell; /*002C 002F*/ 321 uint32_t outbound_intstatus; /*0030 0033*/ 322 uint32_t outbound_intmask; /*0034 0037*/ 323 uint32_t reserved1[2]; /*0038 003F*/ 324 uint32_t inbound_queueport; /*0040 0043*/ 325 uint32_t outbound_queueport; /*0044 0047*/ 326 uint32_t reserved2[2]; /*0048 004F*/ 327 uint32_t reserved3[492]; /*0050 07FF 492*/ 328 uint32_t reserved4[128]; /*0800 09FF 128*/ 329 uint32_t message_rwbuffer[256]; /*0a00 0DFF 256*/ 330 uint32_t message_wbuffer[32]; /*0E00 0E7F 32*/ 331 uint32_t reserved5[32]; /*0E80 0EFF 32*/ 332 uint32_t message_rbuffer[32]; /*0F00 0F7F 32*/ 333 uint32_t reserved6[32]; /*0F80 0FFF 32*/ 334 }; 335 336 struct MessageUnit_B 337 { 338 uint32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; 339 uint32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; 340 uint32_t postq_index; 341 uint32_t doneq_index; 342 uint32_t __iomem *drv2iop_doorbell_reg; 343 uint32_t __iomem *drv2iop_doorbell_mask_reg; 344 uint32_t __iomem *iop2drv_doorbell_reg; 345 uint32_t __iomem *iop2drv_doorbell_mask_reg; 346 uint32_t __iomem *msgcode_rwbuffer_reg; 347 uint32_t __iomem *ioctl_wbuffer_reg; 348 uint32_t __iomem *ioctl_rbuffer_reg; 349 }; 350 351 /* 352 ******************************************************************************* 353 ** Adapter Control Block 354 ******************************************************************************* 355 */ 356 struct AdapterControlBlock 357 { 358 uint32_t adapter_type; /* adapter A,B..... */ 359 #define ACB_ADAPTER_TYPE_A 0x00000001 /* hba I IOP */ 360 #define ACB_ADAPTER_TYPE_B 0x00000002 /* hbb M IOP */ 361 #define ACB_ADAPTER_TYPE_C 0x00000004 /* hbc P IOP */ 362 #define ACB_ADAPTER_TYPE_D 0x00000008 /* hbd A IOP */ 363 struct pci_dev * pdev; 364 struct Scsi_Host * host; 365 unsigned long vir2phy_offset; 366 /* Offset is used in making arc cdb physical to virtual calculations */ 367 uint32_t outbound_int_enable; 368 369 union { 370 struct MessageUnit_A __iomem * pmuA; 371 struct MessageUnit_B * pmuB; 372 }; 373 /* message unit ATU inbound base address0 */ 374 375 uint32_t acb_flags; 376 #define ACB_F_SCSISTOPADAPTER 0x0001 377 #define ACB_F_MSG_STOP_BGRB 0x0002 378 /* stop RAID background rebuild */ 379 #define ACB_F_MSG_START_BGRB 0x0004 380 /* stop RAID background rebuild */ 381 #define ACB_F_IOPDATA_OVERFLOW 0x0008 382 /* iop message data rqbuffer overflow */ 383 #define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 384 /* message clear wqbuffer */ 385 #define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 386 /* message clear rqbuffer */ 387 #define ACB_F_MESSAGE_WQBUFFER_READED 0x0040 388 #define ACB_F_BUS_RESET 0x0080 389 #define ACB_F_IOP_INITED 0x0100 390 /* iop init */ 391 392 struct CommandControlBlock * pccb_pool[ARCMSR_MAX_FREECCB_NUM]; 393 /* used for memory free */ 394 struct list_head ccb_free_list; 395 /* head of free ccb list */ 396 397 atomic_t ccboutstandingcount; 398 /*The present outstanding command number that in the IOP that 399 waiting for being handled by FW*/ 400 401 void * dma_coherent; 402 /* dma_coherent used for memory free */ 403 dma_addr_t dma_coherent_handle; 404 /* dma_coherent_handle used for memory free */ 405 406 uint8_t rqbuffer[ARCMSR_MAX_QBUFFER]; 407 /* data collection buffer for read from 80331 */ 408 int32_t rqbuf_firstindex; 409 /* first of read buffer */ 410 int32_t rqbuf_lastindex; 411 /* last of read buffer */ 412 uint8_t wqbuffer[ARCMSR_MAX_QBUFFER]; 413 /* data collection buffer for write to 80331 */ 414 int32_t wqbuf_firstindex; 415 /* first of write buffer */ 416 int32_t wqbuf_lastindex; 417 /* last of write buffer */ 418 uint8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; 419 /* id0 ..... id15, lun0...lun7 */ 420 #define ARECA_RAID_GONE 0x55 421 #define ARECA_RAID_GOOD 0xaa 422 uint32_t num_resets; 423 uint32_t num_aborts; 424 uint32_t firm_request_len; 425 uint32_t firm_numbers_queue; 426 uint32_t firm_sdram_size; 427 uint32_t firm_hd_channels; 428 char firm_model[12]; 429 char firm_version[20]; 430 };/* HW_DEVICE_EXTENSION */ 431 /* 432 ******************************************************************************* 433 ** Command Control Block 434 ** this CCB length must be 32 bytes boundary 435 ******************************************************************************* 436 */ 437 struct CommandControlBlock 438 { 439 struct ARCMSR_CDB arcmsr_cdb; 440 /* 441 ** 0-503 (size of CDB = 504): 442 ** arcmsr messenger scsi command descriptor size 504 bytes 443 */ 444 uint32_t cdb_shifted_phyaddr; 445 /* 504-507 */ 446 uint32_t reserved1; 447 /* 508-511 */ 448 #if BITS_PER_LONG == 64 449 /* ======================512+64 bytes======================== */ 450 struct list_head list; 451 /* 512-527 16 bytes next/prev ptrs for ccb lists */ 452 struct scsi_cmnd * pcmd; 453 /* 528-535 8 bytes pointer of linux scsi command */ 454 struct AdapterControlBlock * acb; 455 /* 536-543 8 bytes pointer of acb */ 456 457 uint16_t ccb_flags; 458 /* 544-545 */ 459 #define CCB_FLAG_READ 0x0000 460 #define CCB_FLAG_WRITE 0x0001 461 #define CCB_FLAG_ERROR 0x0002 462 #define CCB_FLAG_FLUSHCACHE 0x0004 463 #define CCB_FLAG_MASTER_ABORTED 0x0008 464 uint16_t startdone; 465 /* 546-547 */ 466 #define ARCMSR_CCB_DONE 0x0000 467 #define ARCMSR_CCB_START 0x55AA 468 #define ARCMSR_CCB_ABORTED 0xAA55 469 #define ARCMSR_CCB_ILLEGAL 0xFFFF 470 uint32_t reserved2[7]; 471 /* 548-551 552-555 556-559 560-563 564-567 568-571 572-575 */ 472 #else 473 /* ======================512+32 bytes======================== */ 474 struct list_head list; 475 /* 512-519 8 bytes next/prev ptrs for ccb lists */ 476 struct scsi_cmnd * pcmd; 477 /* 520-523 4 bytes pointer of linux scsi command */ 478 struct AdapterControlBlock * acb; 479 /* 524-527 4 bytes pointer of acb */ 480 481 uint16_t ccb_flags; 482 /* 528-529 */ 483 #define CCB_FLAG_READ 0x0000 484 #define CCB_FLAG_WRITE 0x0001 485 #define CCB_FLAG_ERROR 0x0002 486 #define CCB_FLAG_FLUSHCACHE 0x0004 487 #define CCB_FLAG_MASTER_ABORTED 0x0008 488 uint16_t startdone; 489 /* 530-531 */ 490 #define ARCMSR_CCB_DONE 0x0000 491 #define ARCMSR_CCB_START 0x55AA 492 #define ARCMSR_CCB_ABORTED 0xAA55 493 #define ARCMSR_CCB_ILLEGAL 0xFFFF 494 uint32_t reserved2[3]; 495 /* 532-535 536-539 540-543 */ 496 #endif 497 /* ========================================================== */ 498 }; 499 /* 500 ******************************************************************************* 501 ** ARECA SCSI sense data 502 ******************************************************************************* 503 */ 504 struct SENSE_DATA 505 { 506 uint8_t ErrorCode:7; 507 #define SCSI_SENSE_CURRENT_ERRORS 0x70 508 #define SCSI_SENSE_DEFERRED_ERRORS 0x71 509 uint8_t Valid:1; 510 uint8_t SegmentNumber; 511 uint8_t SenseKey:4; 512 uint8_t Reserved:1; 513 uint8_t IncorrectLength:1; 514 uint8_t EndOfMedia:1; 515 uint8_t FileMark:1; 516 uint8_t Information[4]; 517 uint8_t AdditionalSenseLength; 518 uint8_t CommandSpecificInformation[4]; 519 uint8_t AdditionalSenseCode; 520 uint8_t AdditionalSenseCodeQualifier; 521 uint8_t FieldReplaceableUnitCode; 522 uint8_t SenseKeySpecific[3]; 523 }; 524 /* 525 ******************************************************************************* 526 ** Outbound Interrupt Status Register - OISR 527 ******************************************************************************* 528 */ 529 #define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30 530 #define ARCMSR_MU_OUTBOUND_PCI_INT 0x10 531 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08 532 #define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04 533 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02 534 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01 535 #define ARCMSR_MU_OUTBOUND_HANDLE_INT \ 536 (ARCMSR_MU_OUTBOUND_MESSAGE0_INT \ 537 |ARCMSR_MU_OUTBOUND_MESSAGE1_INT \ 538 |ARCMSR_MU_OUTBOUND_DOORBELL_INT \ 539 |ARCMSR_MU_OUTBOUND_POSTQUEUE_INT \ 540 |ARCMSR_MU_OUTBOUND_PCI_INT) 541 /* 542 ******************************************************************************* 543 ** Outbound Interrupt Mask Register - OIMR 544 ******************************************************************************* 545 */ 546 #define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34 547 #define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10 548 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08 549 #define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04 550 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02 551 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01 552 #define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F 553 554 extern void arcmsr_post_ioctldata2iop(struct AdapterControlBlock *); 555 extern void arcmsr_iop_message_read(struct AdapterControlBlock *); 556 extern struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *); 557 extern struct class_device_attribute *arcmsr_host_attrs[]; 558 extern int arcmsr_alloc_sysfs_attr(struct AdapterControlBlock *); 559 void arcmsr_free_sysfs_attr(struct AdapterControlBlock *acb); 560