1 /* 2 ******************************************************************************* 3 ** O.S : Linux 4 ** FILE NAME : arcmsr.h 5 ** BY : Nick Cheng 6 ** Description: SCSI RAID Device Driver for 7 ** ARECA RAID Host adapter 8 ******************************************************************************* 9 ** Copyright (C) 2002 - 2005, Areca Technology Corporation All rights reserved. 10 ** 11 ** Web site: www.areca.com.tw 12 ** E-mail: support@areca.com.tw 13 ** 14 ** This program is free software; you can redistribute it and/or modify 15 ** it under the terms of the GNU General Public License version 2 as 16 ** published by the Free Software Foundation. 17 ** This program is distributed in the hope that it will be useful, 18 ** but WITHOUT ANY WARRANTY; without even the implied warranty of 19 ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 ** GNU General Public License for more details. 21 ******************************************************************************* 22 ** Redistribution and use in source and binary forms, with or without 23 ** modification, are permitted provided that the following conditions 24 ** are met: 25 ** 1. Redistributions of source code must retain the above copyright 26 ** notice, this list of conditions and the following disclaimer. 27 ** 2. Redistributions in binary form must reproduce the above copyright 28 ** notice, this list of conditions and the following disclaimer in the 29 ** documentation and/or other materials provided with the distribution. 30 ** 3. The name of the author may not be used to endorse or promote products 31 ** derived from this software without specific prior written permission. 32 ** 33 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 34 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 35 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 36 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 37 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT 38 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 39 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 40 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 41 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 42 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 43 ******************************************************************************* 44 */ 45 #include <linux/interrupt.h> 46 struct device_attribute; 47 /*The limit of outstanding scsi command that firmware can handle*/ 48 #ifdef CONFIG_XEN 49 #define ARCMSR_MAX_FREECCB_NUM 160 50 #define ARCMSR_MAX_OUTSTANDING_CMD 155 51 #else 52 #define ARCMSR_MAX_FREECCB_NUM 320 53 #define ARCMSR_MAX_OUTSTANDING_CMD 255 54 #endif 55 #define ARCMSR_DRIVER_VERSION "v1.30.00.22-20151126" 56 #define ARCMSR_SCSI_INITIATOR_ID 255 57 #define ARCMSR_MAX_XFER_SECTORS 512 58 #define ARCMSR_MAX_XFER_SECTORS_B 4096 59 #define ARCMSR_MAX_XFER_SECTORS_C 304 60 #define ARCMSR_MAX_TARGETID 17 61 #define ARCMSR_MAX_TARGETLUN 8 62 #define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD 63 #define ARCMSR_MAX_QBUFFER 4096 64 #define ARCMSR_DEFAULT_SG_ENTRIES 38 65 #define ARCMSR_MAX_HBB_POSTQUEUE 264 66 #define ARCMSR_MAX_ARC1214_POSTQUEUE 256 67 #define ARCMSR_MAX_ARC1214_DONEQUEUE 257 68 #define ARCMSR_MAX_XFER_LEN 0x26000 /* 152K */ 69 #define ARCMSR_CDB_SG_PAGE_LENGTH 256 70 #define ARCMST_NUM_MSIX_VECTORS 4 71 #ifndef PCI_DEVICE_ID_ARECA_1880 72 #define PCI_DEVICE_ID_ARECA_1880 0x1880 73 #endif 74 #ifndef PCI_DEVICE_ID_ARECA_1214 75 #define PCI_DEVICE_ID_ARECA_1214 0x1214 76 #endif 77 #ifndef PCI_DEVICE_ID_ARECA_1203 78 #define PCI_DEVICE_ID_ARECA_1203 0x1203 79 #endif 80 /* 81 ********************************************************************************** 82 ** 83 ********************************************************************************** 84 */ 85 #define ARC_SUCCESS 0 86 #define ARC_FAILURE 1 87 /* 88 ******************************************************************************* 89 ** split 64bits dma addressing 90 ******************************************************************************* 91 */ 92 #define dma_addr_hi32(addr) (uint32_t) ((addr>>16)>>16) 93 #define dma_addr_lo32(addr) (uint32_t) (addr & 0xffffffff) 94 /* 95 ******************************************************************************* 96 ** MESSAGE CONTROL CODE 97 ******************************************************************************* 98 */ 99 struct CMD_MESSAGE 100 { 101 uint32_t HeaderLength; 102 uint8_t Signature[8]; 103 uint32_t Timeout; 104 uint32_t ControlCode; 105 uint32_t ReturnCode; 106 uint32_t Length; 107 }; 108 /* 109 ******************************************************************************* 110 ** IOP Message Transfer Data for user space 111 ******************************************************************************* 112 */ 113 #define ARCMSR_API_DATA_BUFLEN 1032 114 struct CMD_MESSAGE_FIELD 115 { 116 struct CMD_MESSAGE cmdmessage; 117 uint8_t messagedatabuffer[ARCMSR_API_DATA_BUFLEN]; 118 }; 119 /* IOP message transfer */ 120 #define ARCMSR_MESSAGE_FAIL 0x0001 121 /* DeviceType */ 122 #define ARECA_SATA_RAID 0x90000000 123 /* FunctionCode */ 124 #define FUNCTION_READ_RQBUFFER 0x0801 125 #define FUNCTION_WRITE_WQBUFFER 0x0802 126 #define FUNCTION_CLEAR_RQBUFFER 0x0803 127 #define FUNCTION_CLEAR_WQBUFFER 0x0804 128 #define FUNCTION_CLEAR_ALLQBUFFER 0x0805 129 #define FUNCTION_RETURN_CODE_3F 0x0806 130 #define FUNCTION_SAY_HELLO 0x0807 131 #define FUNCTION_SAY_GOODBYE 0x0808 132 #define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809 133 #define FUNCTION_GET_FIRMWARE_STATUS 0x080A 134 #define FUNCTION_HARDWARE_RESET 0x080B 135 /* ARECA IO CONTROL CODE*/ 136 #define ARCMSR_MESSAGE_READ_RQBUFFER \ 137 ARECA_SATA_RAID | FUNCTION_READ_RQBUFFER 138 #define ARCMSR_MESSAGE_WRITE_WQBUFFER \ 139 ARECA_SATA_RAID | FUNCTION_WRITE_WQBUFFER 140 #define ARCMSR_MESSAGE_CLEAR_RQBUFFER \ 141 ARECA_SATA_RAID | FUNCTION_CLEAR_RQBUFFER 142 #define ARCMSR_MESSAGE_CLEAR_WQBUFFER \ 143 ARECA_SATA_RAID | FUNCTION_CLEAR_WQBUFFER 144 #define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER \ 145 ARECA_SATA_RAID | FUNCTION_CLEAR_ALLQBUFFER 146 #define ARCMSR_MESSAGE_RETURN_CODE_3F \ 147 ARECA_SATA_RAID | FUNCTION_RETURN_CODE_3F 148 #define ARCMSR_MESSAGE_SAY_HELLO \ 149 ARECA_SATA_RAID | FUNCTION_SAY_HELLO 150 #define ARCMSR_MESSAGE_SAY_GOODBYE \ 151 ARECA_SATA_RAID | FUNCTION_SAY_GOODBYE 152 #define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE \ 153 ARECA_SATA_RAID | FUNCTION_FLUSH_ADAPTER_CACHE 154 /* ARECA IOCTL ReturnCode */ 155 #define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001 156 #define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006 157 #define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F 158 #define ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON 0x00000088 159 /* 160 ************************************************************* 161 ** structure for holding DMA address data 162 ************************************************************* 163 */ 164 #define IS_DMA64 (sizeof(dma_addr_t) == 8) 165 #define IS_SG64_ADDR 0x01000000 /* bit24 */ 166 struct SG32ENTRY 167 { 168 __le32 length; 169 __le32 address; 170 }__attribute__ ((packed)); 171 struct SG64ENTRY 172 { 173 __le32 length; 174 __le32 address; 175 __le32 addresshigh; 176 }__attribute__ ((packed)); 177 /* 178 ******************************************************************** 179 ** Q Buffer of IOP Message Transfer 180 ******************************************************************** 181 */ 182 struct QBUFFER 183 { 184 uint32_t data_len; 185 uint8_t data[124]; 186 }; 187 /* 188 ******************************************************************************* 189 ** FIRMWARE INFO for Intel IOP R 80331 processor (Type A) 190 ******************************************************************************* 191 */ 192 struct FIRMWARE_INFO 193 { 194 uint32_t signature; /*0, 00-03*/ 195 uint32_t request_len; /*1, 04-07*/ 196 uint32_t numbers_queue; /*2, 08-11*/ 197 uint32_t sdram_size; /*3, 12-15*/ 198 uint32_t ide_channels; /*4, 16-19*/ 199 char vendor[40]; /*5, 20-59*/ 200 char model[8]; /*15, 60-67*/ 201 char firmware_ver[16]; /*17, 68-83*/ 202 char device_map[16]; /*21, 84-99*/ 203 uint32_t cfgVersion; /*25,100-103 Added for checking of new firmware capability*/ 204 uint8_t cfgSerial[16]; /*26,104-119*/ 205 uint32_t cfgPicStatus; /*30,120-123*/ 206 }; 207 /* signature of set and get firmware config */ 208 #define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060 209 #define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063 210 /* message code of inbound message register */ 211 #define ARCMSR_INBOUND_MESG0_NOP 0x00000000 212 #define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001 213 #define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002 214 #define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003 215 #define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004 216 #define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005 217 #define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006 218 #define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007 219 #define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008 220 /* doorbell interrupt generator */ 221 #define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001 222 #define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002 223 #define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001 224 #define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002 225 /* ccb areca cdb flag */ 226 #define ARCMSR_CCBPOST_FLAG_SGL_BSIZE 0x80000000 227 #define ARCMSR_CCBPOST_FLAG_IAM_BIOS 0x40000000 228 #define ARCMSR_CCBREPLY_FLAG_IAM_BIOS 0x40000000 229 #define ARCMSR_CCBREPLY_FLAG_ERROR_MODE0 0x10000000 230 #define ARCMSR_CCBREPLY_FLAG_ERROR_MODE1 0x00000001 231 /* outbound firmware ok */ 232 #define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000 233 /* ARC-1680 Bus Reset*/ 234 #define ARCMSR_ARC1680_BUS_RESET 0x00000003 235 /* ARC-1880 Bus Reset*/ 236 #define ARCMSR_ARC1880_RESET_ADAPTER 0x00000024 237 #define ARCMSR_ARC1880_DiagWrite_ENABLE 0x00000080 238 239 /* 240 ************************************************************************ 241 ** SPEC. for Areca Type B adapter 242 ************************************************************************ 243 */ 244 /* ARECA HBB COMMAND for its FIRMWARE */ 245 /* window of "instruction flags" from driver to iop */ 246 #define ARCMSR_DRV2IOP_DOORBELL 0x00020400 247 #define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404 248 /* window of "instruction flags" from iop to driver */ 249 #define ARCMSR_IOP2DRV_DOORBELL 0x00020408 250 #define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C 251 /* window of "instruction flags" from iop to driver */ 252 #define ARCMSR_IOP2DRV_DOORBELL_1203 0x00021870 253 #define ARCMSR_IOP2DRV_DOORBELL_MASK_1203 0x00021874 254 /* window of "instruction flags" from driver to iop */ 255 #define ARCMSR_DRV2IOP_DOORBELL_1203 0x00021878 256 #define ARCMSR_DRV2IOP_DOORBELL_MASK_1203 0x0002187C 257 /* ARECA FLAG LANGUAGE */ 258 /* ioctl transfer */ 259 #define ARCMSR_IOP2DRV_DATA_WRITE_OK 0x00000001 260 /* ioctl transfer */ 261 #define ARCMSR_IOP2DRV_DATA_READ_OK 0x00000002 262 #define ARCMSR_IOP2DRV_CDB_DONE 0x00000004 263 #define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 264 265 #define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F 266 #define ARCMSR_DOORBELL_INT_CLEAR_PATTERN 0xFF00FFF0 267 #define ARCMSR_MESSAGE_INT_CLEAR_PATTERN 0xFF00FFF7 268 /* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 269 #define ARCMSR_MESSAGE_GET_CONFIG 0x00010008 270 /* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 271 #define ARCMSR_MESSAGE_SET_CONFIG 0x00020008 272 /* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 273 #define ARCMSR_MESSAGE_ABORT_CMD 0x00030008 274 /* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 275 #define ARCMSR_MESSAGE_STOP_BGRB 0x00040008 276 /* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 277 #define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008 278 /* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 279 #define ARCMSR_MESSAGE_START_BGRB 0x00060008 280 #define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008 281 #define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008 282 #define ARCMSR_MESSAGE_ACTIVE_EOI_MODE 0x00100008 283 /* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */ 284 #define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000 285 /* ioctl transfer */ 286 #define ARCMSR_DRV2IOP_DATA_WRITE_OK 0x00000001 287 /* ioctl transfer */ 288 #define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002 289 #define ARCMSR_DRV2IOP_CDB_POSTED 0x00000004 290 #define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED 0x00000008 291 #define ARCMSR_DRV2IOP_END_OF_INTERRUPT 0x00000010 292 293 /* data tunnel buffer between user space program and its firmware */ 294 /* user space data to iop 128bytes */ 295 #define ARCMSR_MESSAGE_WBUFFER 0x0000fe00 296 /* iop data to user space 128bytes */ 297 #define ARCMSR_MESSAGE_RBUFFER 0x0000ff00 298 /* iop message_rwbuffer for message command */ 299 #define ARCMSR_MESSAGE_RWBUFFER 0x0000fa00 300 301 #define MEM_BASE0(x) (u32 __iomem *)((unsigned long)acb->mem_base0 + x) 302 #define MEM_BASE1(x) (u32 __iomem *)((unsigned long)acb->mem_base1 + x) 303 /* 304 ************************************************************************ 305 ** SPEC. for Areca HBC adapter 306 ************************************************************************ 307 */ 308 #define ARCMSR_HBC_ISR_THROTTLING_LEVEL 12 309 #define ARCMSR_HBC_ISR_MAX_DONE_QUEUE 20 310 /* Host Interrupt Mask */ 311 #define ARCMSR_HBCMU_UTILITY_A_ISR_MASK 0x00000001 /* When clear, the Utility_A interrupt routes to the host.*/ 312 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK 0x00000004 /* When clear, the General Outbound Doorbell interrupt routes to the host.*/ 313 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK 0x00000008 /* When clear, the Outbound Post List FIFO Not Empty interrupt routes to the host.*/ 314 #define ARCMSR_HBCMU_ALL_INTMASKENABLE 0x0000000D /* disable all ISR */ 315 /* Host Interrupt Status */ 316 #define ARCMSR_HBCMU_UTILITY_A_ISR 0x00000001 317 /* 318 ** Set when the Utility_A Interrupt bit is set in the Outbound Doorbell Register. 319 ** It clears by writing a 1 to the Utility_A bit in the Outbound Doorbell Clear Register or through automatic clearing (if enabled). 320 */ 321 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR 0x00000004 322 /* 323 ** Set if Outbound Doorbell register bits 30:1 have a non-zero 324 ** value. This bit clears only when Outbound Doorbell bits 325 ** 30:1 are ALL clear. Only a write to the Outbound Doorbell 326 ** Clear register clears bits in the Outbound Doorbell register. 327 */ 328 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR 0x00000008 329 /* 330 ** Set whenever the Outbound Post List Producer/Consumer 331 ** Register (FIFO) is not empty. It clears when the Outbound 332 ** Post List FIFO is empty. 333 */ 334 #define ARCMSR_HBCMU_SAS_ALL_INT 0x00000010 335 /* 336 ** This bit indicates a SAS interrupt from a source external to 337 ** the PCIe core. This bit is not maskable. 338 */ 339 /* DoorBell*/ 340 #define ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK 0x00000002 341 #define ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK 0x00000004 342 /*inbound message 0 ready*/ 343 #define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008 344 /*more than 12 request completed in a time*/ 345 #define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING 0x00000010 346 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 0x00000002 347 /*outbound DATA WRITE isr door bell clear*/ 348 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002 349 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 0x00000004 350 /*outbound DATA READ isr door bell clear*/ 351 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004 352 /*outbound message 0 ready*/ 353 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 354 /*outbound message cmd isr door bell clear*/ 355 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008 356 /*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/ 357 #define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000 358 /* 359 ******************************************************************************* 360 ** SPEC. for Areca Type D adapter 361 ******************************************************************************* 362 */ 363 #define ARCMSR_ARC1214_CHIP_ID 0x00004 364 #define ARCMSR_ARC1214_CPU_MEMORY_CONFIGURATION 0x00008 365 #define ARCMSR_ARC1214_I2_HOST_INTERRUPT_MASK 0x00034 366 #define ARCMSR_ARC1214_SAMPLE_RESET 0x00100 367 #define ARCMSR_ARC1214_RESET_REQUEST 0x00108 368 #define ARCMSR_ARC1214_MAIN_INTERRUPT_STATUS 0x00200 369 #define ARCMSR_ARC1214_PCIE_F0_INTERRUPT_ENABLE 0x0020C 370 #define ARCMSR_ARC1214_INBOUND_MESSAGE0 0x00400 371 #define ARCMSR_ARC1214_INBOUND_MESSAGE1 0x00404 372 #define ARCMSR_ARC1214_OUTBOUND_MESSAGE0 0x00420 373 #define ARCMSR_ARC1214_OUTBOUND_MESSAGE1 0x00424 374 #define ARCMSR_ARC1214_INBOUND_DOORBELL 0x00460 375 #define ARCMSR_ARC1214_OUTBOUND_DOORBELL 0x00480 376 #define ARCMSR_ARC1214_OUTBOUND_DOORBELL_ENABLE 0x00484 377 #define ARCMSR_ARC1214_INBOUND_LIST_BASE_LOW 0x01000 378 #define ARCMSR_ARC1214_INBOUND_LIST_BASE_HIGH 0x01004 379 #define ARCMSR_ARC1214_INBOUND_LIST_WRITE_POINTER 0x01018 380 #define ARCMSR_ARC1214_OUTBOUND_LIST_BASE_LOW 0x01060 381 #define ARCMSR_ARC1214_OUTBOUND_LIST_BASE_HIGH 0x01064 382 #define ARCMSR_ARC1214_OUTBOUND_LIST_COPY_POINTER 0x0106C 383 #define ARCMSR_ARC1214_OUTBOUND_LIST_READ_POINTER 0x01070 384 #define ARCMSR_ARC1214_OUTBOUND_INTERRUPT_CAUSE 0x01088 385 #define ARCMSR_ARC1214_OUTBOUND_INTERRUPT_ENABLE 0x0108C 386 #define ARCMSR_ARC1214_MESSAGE_WBUFFER 0x02000 387 #define ARCMSR_ARC1214_MESSAGE_RBUFFER 0x02100 388 #define ARCMSR_ARC1214_MESSAGE_RWBUFFER 0x02200 389 /* Host Interrupt Mask */ 390 #define ARCMSR_ARC1214_ALL_INT_ENABLE 0x00001010 391 #define ARCMSR_ARC1214_ALL_INT_DISABLE 0x00000000 392 /* Host Interrupt Status */ 393 #define ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR 0x00001000 394 #define ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR 0x00000010 395 /* DoorBell*/ 396 #define ARCMSR_ARC1214_DRV2IOP_DATA_IN_READY 0x00000001 397 #define ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ 0x00000002 398 /*inbound message 0 ready*/ 399 #define ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK 0x00000001 400 /*outbound DATA WRITE isr door bell clear*/ 401 #define ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK 0x00000002 402 /*outbound message 0 ready*/ 403 #define ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE 0x02000000 404 /*outbound message cmd isr door bell clear*/ 405 /*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/ 406 #define ARCMSR_ARC1214_MESSAGE_FIRMWARE_OK 0x80000000 407 #define ARCMSR_ARC1214_OUTBOUND_LIST_INTERRUPT_CLEAR 0x00000001 408 /* 409 ******************************************************************************* 410 ** ARECA SCSI COMMAND DESCRIPTOR BLOCK size 0x1F8 (504) 411 ******************************************************************************* 412 */ 413 struct ARCMSR_CDB 414 { 415 uint8_t Bus; 416 uint8_t TargetID; 417 uint8_t LUN; 418 uint8_t Function; 419 uint8_t CdbLength; 420 uint8_t sgcount; 421 uint8_t Flags; 422 #define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01 423 #define ARCMSR_CDB_FLAG_BIOS 0x02 424 #define ARCMSR_CDB_FLAG_WRITE 0x04 425 #define ARCMSR_CDB_FLAG_SIMPLEQ 0x00 426 #define ARCMSR_CDB_FLAG_HEADQ 0x08 427 #define ARCMSR_CDB_FLAG_ORDEREDQ 0x10 428 429 uint8_t msgPages; 430 uint32_t msgContext; 431 uint32_t DataLength; 432 uint8_t Cdb[16]; 433 uint8_t DeviceStatus; 434 #define ARCMSR_DEV_CHECK_CONDITION 0x02 435 #define ARCMSR_DEV_SELECT_TIMEOUT 0xF0 436 #define ARCMSR_DEV_ABORTED 0xF1 437 #define ARCMSR_DEV_INIT_FAIL 0xF2 438 439 uint8_t SenseData[15]; 440 union 441 { 442 struct SG32ENTRY sg32entry[1]; 443 struct SG64ENTRY sg64entry[1]; 444 } u; 445 }; 446 /* 447 ******************************************************************************* 448 ** Messaging Unit (MU) of the Intel R 80331 I/O processor(Type A) and Type B processor 449 ******************************************************************************* 450 */ 451 struct MessageUnit_A 452 { 453 uint32_t resrved0[4]; /*0000 000F*/ 454 uint32_t inbound_msgaddr0; /*0010 0013*/ 455 uint32_t inbound_msgaddr1; /*0014 0017*/ 456 uint32_t outbound_msgaddr0; /*0018 001B*/ 457 uint32_t outbound_msgaddr1; /*001C 001F*/ 458 uint32_t inbound_doorbell; /*0020 0023*/ 459 uint32_t inbound_intstatus; /*0024 0027*/ 460 uint32_t inbound_intmask; /*0028 002B*/ 461 uint32_t outbound_doorbell; /*002C 002F*/ 462 uint32_t outbound_intstatus; /*0030 0033*/ 463 uint32_t outbound_intmask; /*0034 0037*/ 464 uint32_t reserved1[2]; /*0038 003F*/ 465 uint32_t inbound_queueport; /*0040 0043*/ 466 uint32_t outbound_queueport; /*0044 0047*/ 467 uint32_t reserved2[2]; /*0048 004F*/ 468 uint32_t reserved3[492]; /*0050 07FF 492*/ 469 uint32_t reserved4[128]; /*0800 09FF 128*/ 470 uint32_t message_rwbuffer[256]; /*0a00 0DFF 256*/ 471 uint32_t message_wbuffer[32]; /*0E00 0E7F 32*/ 472 uint32_t reserved5[32]; /*0E80 0EFF 32*/ 473 uint32_t message_rbuffer[32]; /*0F00 0F7F 32*/ 474 uint32_t reserved6[32]; /*0F80 0FFF 32*/ 475 }; 476 477 struct MessageUnit_B 478 { 479 uint32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; 480 uint32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; 481 uint32_t postq_index; 482 uint32_t doneq_index; 483 uint32_t __iomem *drv2iop_doorbell; 484 uint32_t __iomem *drv2iop_doorbell_mask; 485 uint32_t __iomem *iop2drv_doorbell; 486 uint32_t __iomem *iop2drv_doorbell_mask; 487 uint32_t __iomem *message_rwbuffer; 488 uint32_t __iomem *message_wbuffer; 489 uint32_t __iomem *message_rbuffer; 490 }; 491 /* 492 ********************************************************************* 493 ** LSI 494 ********************************************************************* 495 */ 496 struct MessageUnit_C{ 497 uint32_t message_unit_status; /*0000 0003*/ 498 uint32_t slave_error_attribute; /*0004 0007*/ 499 uint32_t slave_error_address; /*0008 000B*/ 500 uint32_t posted_outbound_doorbell; /*000C 000F*/ 501 uint32_t master_error_attribute; /*0010 0013*/ 502 uint32_t master_error_address_low; /*0014 0017*/ 503 uint32_t master_error_address_high; /*0018 001B*/ 504 uint32_t hcb_size; /*001C 001F*/ 505 uint32_t inbound_doorbell; /*0020 0023*/ 506 uint32_t diagnostic_rw_data; /*0024 0027*/ 507 uint32_t diagnostic_rw_address_low; /*0028 002B*/ 508 uint32_t diagnostic_rw_address_high; /*002C 002F*/ 509 uint32_t host_int_status; /*0030 0033*/ 510 uint32_t host_int_mask; /*0034 0037*/ 511 uint32_t dcr_data; /*0038 003B*/ 512 uint32_t dcr_address; /*003C 003F*/ 513 uint32_t inbound_queueport; /*0040 0043*/ 514 uint32_t outbound_queueport; /*0044 0047*/ 515 uint32_t hcb_pci_address_low; /*0048 004B*/ 516 uint32_t hcb_pci_address_high; /*004C 004F*/ 517 uint32_t iop_int_status; /*0050 0053*/ 518 uint32_t iop_int_mask; /*0054 0057*/ 519 uint32_t iop_inbound_queue_port; /*0058 005B*/ 520 uint32_t iop_outbound_queue_port; /*005C 005F*/ 521 uint32_t inbound_free_list_index; /*0060 0063*/ 522 uint32_t inbound_post_list_index; /*0064 0067*/ 523 uint32_t outbound_free_list_index; /*0068 006B*/ 524 uint32_t outbound_post_list_index; /*006C 006F*/ 525 uint32_t inbound_doorbell_clear; /*0070 0073*/ 526 uint32_t i2o_message_unit_control; /*0074 0077*/ 527 uint32_t last_used_message_source_address_low; /*0078 007B*/ 528 uint32_t last_used_message_source_address_high; /*007C 007F*/ 529 uint32_t pull_mode_data_byte_count[4]; /*0080 008F*/ 530 uint32_t message_dest_address_index; /*0090 0093*/ 531 uint32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/ 532 uint32_t utility_A_int_counter_timer; /*0098 009B*/ 533 uint32_t outbound_doorbell; /*009C 009F*/ 534 uint32_t outbound_doorbell_clear; /*00A0 00A3*/ 535 uint32_t message_source_address_index; /*00A4 00A7*/ 536 uint32_t message_done_queue_index; /*00A8 00AB*/ 537 uint32_t reserved0; /*00AC 00AF*/ 538 uint32_t inbound_msgaddr0; /*00B0 00B3*/ 539 uint32_t inbound_msgaddr1; /*00B4 00B7*/ 540 uint32_t outbound_msgaddr0; /*00B8 00BB*/ 541 uint32_t outbound_msgaddr1; /*00BC 00BF*/ 542 uint32_t inbound_queueport_low; /*00C0 00C3*/ 543 uint32_t inbound_queueport_high; /*00C4 00C7*/ 544 uint32_t outbound_queueport_low; /*00C8 00CB*/ 545 uint32_t outbound_queueport_high; /*00CC 00CF*/ 546 uint32_t iop_inbound_queue_port_low; /*00D0 00D3*/ 547 uint32_t iop_inbound_queue_port_high; /*00D4 00D7*/ 548 uint32_t iop_outbound_queue_port_low; /*00D8 00DB*/ 549 uint32_t iop_outbound_queue_port_high; /*00DC 00DF*/ 550 uint32_t message_dest_queue_port_low; /*00E0 00E3*/ 551 uint32_t message_dest_queue_port_high; /*00E4 00E7*/ 552 uint32_t last_used_message_dest_address_low; /*00E8 00EB*/ 553 uint32_t last_used_message_dest_address_high; /*00EC 00EF*/ 554 uint32_t message_done_queue_base_address_low; /*00F0 00F3*/ 555 uint32_t message_done_queue_base_address_high; /*00F4 00F7*/ 556 uint32_t host_diagnostic; /*00F8 00FB*/ 557 uint32_t write_sequence; /*00FC 00FF*/ 558 uint32_t reserved1[34]; /*0100 0187*/ 559 uint32_t reserved2[1950]; /*0188 1FFF*/ 560 uint32_t message_wbuffer[32]; /*2000 207F*/ 561 uint32_t reserved3[32]; /*2080 20FF*/ 562 uint32_t message_rbuffer[32]; /*2100 217F*/ 563 uint32_t reserved4[32]; /*2180 21FF*/ 564 uint32_t msgcode_rwbuffer[256]; /*2200 23FF*/ 565 }; 566 /* 567 ********************************************************************* 568 ** Messaging Unit (MU) of Type D processor 569 ********************************************************************* 570 */ 571 struct InBound_SRB { 572 uint32_t addressLow; /* pointer to SRB block */ 573 uint32_t addressHigh; 574 uint32_t length; /* in DWORDs */ 575 uint32_t reserved0; 576 }; 577 578 struct OutBound_SRB { 579 uint32_t addressLow; /* pointer to SRB block */ 580 uint32_t addressHigh; 581 }; 582 583 struct MessageUnit_D { 584 struct InBound_SRB post_qbuffer[ARCMSR_MAX_ARC1214_POSTQUEUE]; 585 volatile struct OutBound_SRB 586 done_qbuffer[ARCMSR_MAX_ARC1214_DONEQUEUE]; 587 u16 postq_index; 588 volatile u16 doneq_index; 589 u32 __iomem *chip_id; /* 0x00004 */ 590 u32 __iomem *cpu_mem_config; /* 0x00008 */ 591 u32 __iomem *i2o_host_interrupt_mask; /* 0x00034 */ 592 u32 __iomem *sample_at_reset; /* 0x00100 */ 593 u32 __iomem *reset_request; /* 0x00108 */ 594 u32 __iomem *host_int_status; /* 0x00200 */ 595 u32 __iomem *pcief0_int_enable; /* 0x0020C */ 596 u32 __iomem *inbound_msgaddr0; /* 0x00400 */ 597 u32 __iomem *inbound_msgaddr1; /* 0x00404 */ 598 u32 __iomem *outbound_msgaddr0; /* 0x00420 */ 599 u32 __iomem *outbound_msgaddr1; /* 0x00424 */ 600 u32 __iomem *inbound_doorbell; /* 0x00460 */ 601 u32 __iomem *outbound_doorbell; /* 0x00480 */ 602 u32 __iomem *outbound_doorbell_enable; /* 0x00484 */ 603 u32 __iomem *inboundlist_base_low; /* 0x01000 */ 604 u32 __iomem *inboundlist_base_high; /* 0x01004 */ 605 u32 __iomem *inboundlist_write_pointer; /* 0x01018 */ 606 u32 __iomem *outboundlist_base_low; /* 0x01060 */ 607 u32 __iomem *outboundlist_base_high; /* 0x01064 */ 608 u32 __iomem *outboundlist_copy_pointer; /* 0x0106C */ 609 u32 __iomem *outboundlist_read_pointer; /* 0x01070 0x01072 */ 610 u32 __iomem *outboundlist_interrupt_cause; /* 0x1088 */ 611 u32 __iomem *outboundlist_interrupt_enable; /* 0x108C */ 612 u32 __iomem *message_wbuffer; /* 0x2000 */ 613 u32 __iomem *message_rbuffer; /* 0x2100 */ 614 u32 __iomem *msgcode_rwbuffer; /* 0x2200 */ 615 }; 616 /* 617 ******************************************************************************* 618 ** Adapter Control Block 619 ******************************************************************************* 620 */ 621 struct AdapterControlBlock 622 { 623 uint32_t adapter_type; /* adapter A,B..... */ 624 #define ACB_ADAPTER_TYPE_A 0x00000001 /* hba I IOP */ 625 #define ACB_ADAPTER_TYPE_B 0x00000002 /* hbb M IOP */ 626 #define ACB_ADAPTER_TYPE_C 0x00000004 /* hbc P IOP */ 627 #define ACB_ADAPTER_TYPE_D 0x00000008 /* hbd A IOP */ 628 u32 roundup_ccbsize; 629 struct pci_dev * pdev; 630 struct Scsi_Host * host; 631 unsigned long vir2phy_offset; 632 struct msix_entry entries[ARCMST_NUM_MSIX_VECTORS]; 633 /* Offset is used in making arc cdb physical to virtual calculations */ 634 uint32_t outbound_int_enable; 635 uint32_t cdb_phyaddr_hi32; 636 uint32_t reg_mu_acc_handle0; 637 spinlock_t eh_lock; 638 spinlock_t ccblist_lock; 639 spinlock_t postq_lock; 640 spinlock_t doneq_lock; 641 spinlock_t rqbuffer_lock; 642 spinlock_t wqbuffer_lock; 643 union { 644 struct MessageUnit_A __iomem *pmuA; 645 struct MessageUnit_B *pmuB; 646 struct MessageUnit_C __iomem *pmuC; 647 struct MessageUnit_D *pmuD; 648 }; 649 /* message unit ATU inbound base address0 */ 650 void __iomem *mem_base0; 651 void __iomem *mem_base1; 652 uint32_t acb_flags; 653 u16 dev_id; 654 uint8_t adapter_index; 655 #define ACB_F_SCSISTOPADAPTER 0x0001 656 #define ACB_F_MSG_STOP_BGRB 0x0002 657 /* stop RAID background rebuild */ 658 #define ACB_F_MSG_START_BGRB 0x0004 659 /* stop RAID background rebuild */ 660 #define ACB_F_IOPDATA_OVERFLOW 0x0008 661 /* iop message data rqbuffer overflow */ 662 #define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 663 /* message clear wqbuffer */ 664 #define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 665 /* message clear rqbuffer */ 666 #define ACB_F_MESSAGE_WQBUFFER_READED 0x0040 667 #define ACB_F_BUS_RESET 0x0080 668 #define ACB_F_BUS_HANG_ON 0x0800/* need hardware reset bus */ 669 670 #define ACB_F_IOP_INITED 0x0100 671 /* iop init */ 672 #define ACB_F_ABORT 0x0200 673 #define ACB_F_FIRMWARE_TRAP 0x0400 674 #define ACB_F_MSI_ENABLED 0x1000 675 #define ACB_F_MSIX_ENABLED 0x2000 676 struct CommandControlBlock * pccb_pool[ARCMSR_MAX_FREECCB_NUM]; 677 /* used for memory free */ 678 struct list_head ccb_free_list; 679 /* head of free ccb list */ 680 681 atomic_t ccboutstandingcount; 682 /*The present outstanding command number that in the IOP that 683 waiting for being handled by FW*/ 684 685 void * dma_coherent; 686 /* dma_coherent used for memory free */ 687 dma_addr_t dma_coherent_handle; 688 /* dma_coherent_handle used for memory free */ 689 dma_addr_t dma_coherent_handle2; 690 void *dma_coherent2; 691 unsigned int uncache_size; 692 uint8_t rqbuffer[ARCMSR_MAX_QBUFFER]; 693 /* data collection buffer for read from 80331 */ 694 int32_t rqbuf_getIndex; 695 /* first of read buffer */ 696 int32_t rqbuf_putIndex; 697 /* last of read buffer */ 698 uint8_t wqbuffer[ARCMSR_MAX_QBUFFER]; 699 /* data collection buffer for write to 80331 */ 700 int32_t wqbuf_getIndex; 701 /* first of write buffer */ 702 int32_t wqbuf_putIndex; 703 /* last of write buffer */ 704 uint8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; 705 /* id0 ..... id15, lun0...lun7 */ 706 #define ARECA_RAID_GONE 0x55 707 #define ARECA_RAID_GOOD 0xaa 708 uint32_t num_resets; 709 uint32_t num_aborts; 710 uint32_t signature; 711 uint32_t firm_request_len; 712 uint32_t firm_numbers_queue; 713 uint32_t firm_sdram_size; 714 uint32_t firm_hd_channels; 715 uint32_t firm_cfg_version; 716 char firm_model[12]; 717 char firm_version[20]; 718 char device_map[20]; /*21,84-99*/ 719 struct work_struct arcmsr_do_message_isr_bh; 720 struct timer_list eternal_timer; 721 unsigned short fw_flag; 722 #define FW_NORMAL 0x0000 723 #define FW_BOG 0x0001 724 #define FW_DEADLOCK 0x0010 725 atomic_t rq_map_token; 726 atomic_t ante_token_value; 727 uint32_t maxOutstanding; 728 int msix_vector_count; 729 };/* HW_DEVICE_EXTENSION */ 730 /* 731 ******************************************************************************* 732 ** Command Control Block 733 ** this CCB length must be 32 bytes boundary 734 ******************************************************************************* 735 */ 736 struct CommandControlBlock{ 737 /*x32:sizeof struct_CCB=(32+60)byte, x64:sizeof struct_CCB=(64+60)byte*/ 738 struct list_head list; /*x32: 8byte, x64: 16byte*/ 739 struct scsi_cmnd *pcmd; /*8 bytes pointer of linux scsi command */ 740 struct AdapterControlBlock *acb; /*x32: 4byte, x64: 8byte*/ 741 uint32_t cdb_phyaddr; /*x32: 4byte, x64: 4byte*/ 742 uint32_t arc_cdb_size; /*x32:4byte,x64:4byte*/ 743 uint16_t ccb_flags; /*x32: 2byte, x64: 2byte*/ 744 #define CCB_FLAG_READ 0x0000 745 #define CCB_FLAG_WRITE 0x0001 746 #define CCB_FLAG_ERROR 0x0002 747 #define CCB_FLAG_FLUSHCACHE 0x0004 748 #define CCB_FLAG_MASTER_ABORTED 0x0008 749 uint16_t startdone; /*x32:2byte,x32:2byte*/ 750 #define ARCMSR_CCB_DONE 0x0000 751 #define ARCMSR_CCB_START 0x55AA 752 #define ARCMSR_CCB_ABORTED 0xAA55 753 #define ARCMSR_CCB_ILLEGAL 0xFFFF 754 #if BITS_PER_LONG == 64 755 /* ======================512+64 bytes======================== */ 756 uint32_t reserved[5]; /*24 byte*/ 757 #else 758 /* ======================512+32 bytes======================== */ 759 uint32_t reserved; /*8 byte*/ 760 #endif 761 /* ======================================================= */ 762 struct ARCMSR_CDB arcmsr_cdb; 763 }; 764 /* 765 ******************************************************************************* 766 ** ARECA SCSI sense data 767 ******************************************************************************* 768 */ 769 struct SENSE_DATA 770 { 771 uint8_t ErrorCode:7; 772 #define SCSI_SENSE_CURRENT_ERRORS 0x70 773 #define SCSI_SENSE_DEFERRED_ERRORS 0x71 774 uint8_t Valid:1; 775 uint8_t SegmentNumber; 776 uint8_t SenseKey:4; 777 uint8_t Reserved:1; 778 uint8_t IncorrectLength:1; 779 uint8_t EndOfMedia:1; 780 uint8_t FileMark:1; 781 uint8_t Information[4]; 782 uint8_t AdditionalSenseLength; 783 uint8_t CommandSpecificInformation[4]; 784 uint8_t AdditionalSenseCode; 785 uint8_t AdditionalSenseCodeQualifier; 786 uint8_t FieldReplaceableUnitCode; 787 uint8_t SenseKeySpecific[3]; 788 }; 789 /* 790 ******************************************************************************* 791 ** Outbound Interrupt Status Register - OISR 792 ******************************************************************************* 793 */ 794 #define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30 795 #define ARCMSR_MU_OUTBOUND_PCI_INT 0x10 796 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08 797 #define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04 798 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02 799 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01 800 #define ARCMSR_MU_OUTBOUND_HANDLE_INT \ 801 (ARCMSR_MU_OUTBOUND_MESSAGE0_INT \ 802 |ARCMSR_MU_OUTBOUND_MESSAGE1_INT \ 803 |ARCMSR_MU_OUTBOUND_DOORBELL_INT \ 804 |ARCMSR_MU_OUTBOUND_POSTQUEUE_INT \ 805 |ARCMSR_MU_OUTBOUND_PCI_INT) 806 /* 807 ******************************************************************************* 808 ** Outbound Interrupt Mask Register - OIMR 809 ******************************************************************************* 810 */ 811 #define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34 812 #define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10 813 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08 814 #define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04 815 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02 816 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01 817 #define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F 818 819 extern void arcmsr_write_ioctldata2iop(struct AdapterControlBlock *); 820 extern uint32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *, 821 struct QBUFFER __iomem *); 822 extern void arcmsr_clear_iop2drv_rqueue_buffer(struct AdapterControlBlock *); 823 extern struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *); 824 extern struct device_attribute *arcmsr_host_attrs[]; 825 extern int arcmsr_alloc_sysfs_attr(struct AdapterControlBlock *); 826 void arcmsr_free_sysfs_attr(struct AdapterControlBlock *acb); 827