1 /* 2 ******************************************************************************* 3 ** O.S : Linux 4 ** FILE NAME : arcmsr.h 5 ** BY : Nick Cheng 6 ** Description: SCSI RAID Device Driver for 7 ** ARECA RAID Host adapter 8 ******************************************************************************* 9 ** Copyright (C) 2002 - 2005, Areca Technology Corporation All rights reserved. 10 ** 11 ** Web site: www.areca.com.tw 12 ** E-mail: support@areca.com.tw 13 ** 14 ** This program is free software; you can redistribute it and/or modify 15 ** it under the terms of the GNU General Public License version 2 as 16 ** published by the Free Software Foundation. 17 ** This program is distributed in the hope that it will be useful, 18 ** but WITHOUT ANY WARRANTY; without even the implied warranty of 19 ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 ** GNU General Public License for more details. 21 ******************************************************************************* 22 ** Redistribution and use in source and binary forms, with or without 23 ** modification, are permitted provided that the following conditions 24 ** are met: 25 ** 1. Redistributions of source code must retain the above copyright 26 ** notice, this list of conditions and the following disclaimer. 27 ** 2. Redistributions in binary form must reproduce the above copyright 28 ** notice, this list of conditions and the following disclaimer in the 29 ** documentation and/or other materials provided with the distribution. 30 ** 3. The name of the author may not be used to endorse or promote products 31 ** derived from this software without specific prior written permission. 32 ** 33 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 34 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 35 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 36 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 37 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT 38 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 39 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 40 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 41 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 42 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 43 ******************************************************************************* 44 */ 45 #include <linux/interrupt.h> 46 struct device_attribute; 47 /*The limit of outstanding scsi command that firmware can handle*/ 48 #define ARCMSR_MAX_OUTSTANDING_CMD 256 49 #ifdef CONFIG_XEN 50 #define ARCMSR_MAX_FREECCB_NUM 160 51 #else 52 #define ARCMSR_MAX_FREECCB_NUM 320 53 #endif 54 #define ARCMSR_DRIVER_VERSION "Driver Version 1.20.00.15 2010/08/05" 55 #define ARCMSR_SCSI_INITIATOR_ID 255 56 #define ARCMSR_MAX_XFER_SECTORS 512 57 #define ARCMSR_MAX_XFER_SECTORS_B 4096 58 #define ARCMSR_MAX_XFER_SECTORS_C 304 59 #define ARCMSR_MAX_TARGETID 17 60 #define ARCMSR_MAX_TARGETLUN 8 61 #define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD 62 #define ARCMSR_MAX_QBUFFER 4096 63 #define ARCMSR_DEFAULT_SG_ENTRIES 38 64 #define ARCMSR_MAX_HBB_POSTQUEUE 264 65 #define ARCMSR_MAX_XFER_LEN 0x26000 /* 152K */ 66 #define ARCMSR_CDB_SG_PAGE_LENGTH 256 67 #ifndef PCI_DEVICE_ID_ARECA_1880 68 #define PCI_DEVICE_ID_ARECA_1880 0x1880 69 #endif 70 /* 71 ********************************************************************************** 72 ** 73 ********************************************************************************** 74 */ 75 #define ARC_SUCCESS 0 76 #define ARC_FAILURE 1 77 /* 78 ******************************************************************************* 79 ** split 64bits dma addressing 80 ******************************************************************************* 81 */ 82 #define dma_addr_hi32(addr) (uint32_t) ((addr>>16)>>16) 83 #define dma_addr_lo32(addr) (uint32_t) (addr & 0xffffffff) 84 /* 85 ******************************************************************************* 86 ** MESSAGE CONTROL CODE 87 ******************************************************************************* 88 */ 89 struct CMD_MESSAGE 90 { 91 uint32_t HeaderLength; 92 uint8_t Signature[8]; 93 uint32_t Timeout; 94 uint32_t ControlCode; 95 uint32_t ReturnCode; 96 uint32_t Length; 97 }; 98 /* 99 ******************************************************************************* 100 ** IOP Message Transfer Data for user space 101 ******************************************************************************* 102 */ 103 struct CMD_MESSAGE_FIELD 104 { 105 struct CMD_MESSAGE cmdmessage; 106 uint8_t messagedatabuffer[1032]; 107 }; 108 /* IOP message transfer */ 109 #define ARCMSR_MESSAGE_FAIL 0x0001 110 /* DeviceType */ 111 #define ARECA_SATA_RAID 0x90000000 112 /* FunctionCode */ 113 #define FUNCTION_READ_RQBUFFER 0x0801 114 #define FUNCTION_WRITE_WQBUFFER 0x0802 115 #define FUNCTION_CLEAR_RQBUFFER 0x0803 116 #define FUNCTION_CLEAR_WQBUFFER 0x0804 117 #define FUNCTION_CLEAR_ALLQBUFFER 0x0805 118 #define FUNCTION_RETURN_CODE_3F 0x0806 119 #define FUNCTION_SAY_HELLO 0x0807 120 #define FUNCTION_SAY_GOODBYE 0x0808 121 #define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809 122 #define FUNCTION_GET_FIRMWARE_STATUS 0x080A 123 #define FUNCTION_HARDWARE_RESET 0x080B 124 /* ARECA IO CONTROL CODE*/ 125 #define ARCMSR_MESSAGE_READ_RQBUFFER \ 126 ARECA_SATA_RAID | FUNCTION_READ_RQBUFFER 127 #define ARCMSR_MESSAGE_WRITE_WQBUFFER \ 128 ARECA_SATA_RAID | FUNCTION_WRITE_WQBUFFER 129 #define ARCMSR_MESSAGE_CLEAR_RQBUFFER \ 130 ARECA_SATA_RAID | FUNCTION_CLEAR_RQBUFFER 131 #define ARCMSR_MESSAGE_CLEAR_WQBUFFER \ 132 ARECA_SATA_RAID | FUNCTION_CLEAR_WQBUFFER 133 #define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER \ 134 ARECA_SATA_RAID | FUNCTION_CLEAR_ALLQBUFFER 135 #define ARCMSR_MESSAGE_RETURN_CODE_3F \ 136 ARECA_SATA_RAID | FUNCTION_RETURN_CODE_3F 137 #define ARCMSR_MESSAGE_SAY_HELLO \ 138 ARECA_SATA_RAID | FUNCTION_SAY_HELLO 139 #define ARCMSR_MESSAGE_SAY_GOODBYE \ 140 ARECA_SATA_RAID | FUNCTION_SAY_GOODBYE 141 #define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE \ 142 ARECA_SATA_RAID | FUNCTION_FLUSH_ADAPTER_CACHE 143 /* ARECA IOCTL ReturnCode */ 144 #define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001 145 #define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006 146 #define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F 147 #define ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON 0x00000088 148 /* 149 ************************************************************* 150 ** structure for holding DMA address data 151 ************************************************************* 152 */ 153 #define IS_DMA64 (sizeof(dma_addr_t) == 8) 154 #define IS_SG64_ADDR 0x01000000 /* bit24 */ 155 struct SG32ENTRY 156 { 157 __le32 length; 158 __le32 address; 159 }__attribute__ ((packed)); 160 struct SG64ENTRY 161 { 162 __le32 length; 163 __le32 address; 164 __le32 addresshigh; 165 }__attribute__ ((packed)); 166 /* 167 ******************************************************************** 168 ** Q Buffer of IOP Message Transfer 169 ******************************************************************** 170 */ 171 struct QBUFFER 172 { 173 uint32_t data_len; 174 uint8_t data[124]; 175 }; 176 /* 177 ******************************************************************************* 178 ** FIRMWARE INFO for Intel IOP R 80331 processor (Type A) 179 ******************************************************************************* 180 */ 181 struct FIRMWARE_INFO 182 { 183 uint32_t signature; /*0, 00-03*/ 184 uint32_t request_len; /*1, 04-07*/ 185 uint32_t numbers_queue; /*2, 08-11*/ 186 uint32_t sdram_size; /*3, 12-15*/ 187 uint32_t ide_channels; /*4, 16-19*/ 188 char vendor[40]; /*5, 20-59*/ 189 char model[8]; /*15, 60-67*/ 190 char firmware_ver[16]; /*17, 68-83*/ 191 char device_map[16]; /*21, 84-99*/ 192 uint32_t cfgVersion; /*25,100-103 Added for checking of new firmware capability*/ 193 uint8_t cfgSerial[16]; /*26,104-119*/ 194 uint32_t cfgPicStatus; /*30,120-123*/ 195 }; 196 /* signature of set and get firmware config */ 197 #define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060 198 #define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063 199 /* message code of inbound message register */ 200 #define ARCMSR_INBOUND_MESG0_NOP 0x00000000 201 #define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001 202 #define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002 203 #define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003 204 #define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004 205 #define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005 206 #define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006 207 #define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007 208 #define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008 209 /* doorbell interrupt generator */ 210 #define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001 211 #define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002 212 #define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001 213 #define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002 214 /* ccb areca cdb flag */ 215 #define ARCMSR_CCBPOST_FLAG_SGL_BSIZE 0x80000000 216 #define ARCMSR_CCBPOST_FLAG_IAM_BIOS 0x40000000 217 #define ARCMSR_CCBREPLY_FLAG_IAM_BIOS 0x40000000 218 #define ARCMSR_CCBREPLY_FLAG_ERROR_MODE0 0x10000000 219 #define ARCMSR_CCBREPLY_FLAG_ERROR_MODE1 0x00000001 220 /* outbound firmware ok */ 221 #define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000 222 /* ARC-1680 Bus Reset*/ 223 #define ARCMSR_ARC1680_BUS_RESET 0x00000003 224 /* ARC-1880 Bus Reset*/ 225 #define ARCMSR_ARC1880_RESET_ADAPTER 0x00000024 226 #define ARCMSR_ARC1880_DiagWrite_ENABLE 0x00000080 227 228 /* 229 ************************************************************************ 230 ** SPEC. for Areca Type B adapter 231 ************************************************************************ 232 */ 233 /* ARECA HBB COMMAND for its FIRMWARE */ 234 /* window of "instruction flags" from driver to iop */ 235 #define ARCMSR_DRV2IOP_DOORBELL 0x00020400 236 #define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404 237 /* window of "instruction flags" from iop to driver */ 238 #define ARCMSR_IOP2DRV_DOORBELL 0x00020408 239 #define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C 240 /* ARECA FLAG LANGUAGE */ 241 /* ioctl transfer */ 242 #define ARCMSR_IOP2DRV_DATA_WRITE_OK 0x00000001 243 /* ioctl transfer */ 244 #define ARCMSR_IOP2DRV_DATA_READ_OK 0x00000002 245 #define ARCMSR_IOP2DRV_CDB_DONE 0x00000004 246 #define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 247 248 #define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F 249 #define ARCMSR_DOORBELL_INT_CLEAR_PATTERN 0xFF00FFF0 250 #define ARCMSR_MESSAGE_INT_CLEAR_PATTERN 0xFF00FFF7 251 /* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 252 #define ARCMSR_MESSAGE_GET_CONFIG 0x00010008 253 /* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 254 #define ARCMSR_MESSAGE_SET_CONFIG 0x00020008 255 /* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 256 #define ARCMSR_MESSAGE_ABORT_CMD 0x00030008 257 /* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 258 #define ARCMSR_MESSAGE_STOP_BGRB 0x00040008 259 /* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 260 #define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008 261 /* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 262 #define ARCMSR_MESSAGE_START_BGRB 0x00060008 263 #define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008 264 #define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008 265 #define ARCMSR_MESSAGE_ACTIVE_EOI_MODE 0x00100008 266 /* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */ 267 #define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000 268 /* ioctl transfer */ 269 #define ARCMSR_DRV2IOP_DATA_WRITE_OK 0x00000001 270 /* ioctl transfer */ 271 #define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002 272 #define ARCMSR_DRV2IOP_CDB_POSTED 0x00000004 273 #define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED 0x00000008 274 #define ARCMSR_DRV2IOP_END_OF_INTERRUPT 0x00000010 275 276 /* data tunnel buffer between user space program and its firmware */ 277 /* user space data to iop 128bytes */ 278 #define ARCMSR_MESSAGE_WBUFFER 0x0000fe00 279 /* iop data to user space 128bytes */ 280 #define ARCMSR_MESSAGE_RBUFFER 0x0000ff00 281 /* iop message_rwbuffer for message command */ 282 #define ARCMSR_MESSAGE_RWBUFFER 0x0000fa00 283 /* 284 ************************************************************************ 285 ** SPEC. for Areca HBC adapter 286 ************************************************************************ 287 */ 288 #define ARCMSR_HBC_ISR_THROTTLING_LEVEL 12 289 #define ARCMSR_HBC_ISR_MAX_DONE_QUEUE 20 290 /* Host Interrupt Mask */ 291 #define ARCMSR_HBCMU_UTILITY_A_ISR_MASK 0x00000001 /* When clear, the Utility_A interrupt routes to the host.*/ 292 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK 0x00000004 /* When clear, the General Outbound Doorbell interrupt routes to the host.*/ 293 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK 0x00000008 /* When clear, the Outbound Post List FIFO Not Empty interrupt routes to the host.*/ 294 #define ARCMSR_HBCMU_ALL_INTMASKENABLE 0x0000000D /* disable all ISR */ 295 /* Host Interrupt Status */ 296 #define ARCMSR_HBCMU_UTILITY_A_ISR 0x00000001 297 /* 298 ** Set when the Utility_A Interrupt bit is set in the Outbound Doorbell Register. 299 ** It clears by writing a 1 to the Utility_A bit in the Outbound Doorbell Clear Register or through automatic clearing (if enabled). 300 */ 301 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR 0x00000004 302 /* 303 ** Set if Outbound Doorbell register bits 30:1 have a non-zero 304 ** value. This bit clears only when Outbound Doorbell bits 305 ** 30:1 are ALL clear. Only a write to the Outbound Doorbell 306 ** Clear register clears bits in the Outbound Doorbell register. 307 */ 308 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR 0x00000008 309 /* 310 ** Set whenever the Outbound Post List Producer/Consumer 311 ** Register (FIFO) is not empty. It clears when the Outbound 312 ** Post List FIFO is empty. 313 */ 314 #define ARCMSR_HBCMU_SAS_ALL_INT 0x00000010 315 /* 316 ** This bit indicates a SAS interrupt from a source external to 317 ** the PCIe core. This bit is not maskable. 318 */ 319 /* DoorBell*/ 320 #define ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK 0x00000002 321 #define ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK 0x00000004 322 /*inbound message 0 ready*/ 323 #define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008 324 /*more than 12 request completed in a time*/ 325 #define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING 0x00000010 326 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 0x00000002 327 /*outbound DATA WRITE isr door bell clear*/ 328 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002 329 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 0x00000004 330 /*outbound DATA READ isr door bell clear*/ 331 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004 332 /*outbound message 0 ready*/ 333 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 334 /*outbound message cmd isr door bell clear*/ 335 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008 336 /*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/ 337 #define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000 338 /* 339 ******************************************************************************* 340 ** ARECA SCSI COMMAND DESCRIPTOR BLOCK size 0x1F8 (504) 341 ******************************************************************************* 342 */ 343 struct ARCMSR_CDB 344 { 345 uint8_t Bus; 346 uint8_t TargetID; 347 uint8_t LUN; 348 uint8_t Function; 349 uint8_t CdbLength; 350 uint8_t sgcount; 351 uint8_t Flags; 352 #define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01 353 #define ARCMSR_CDB_FLAG_BIOS 0x02 354 #define ARCMSR_CDB_FLAG_WRITE 0x04 355 #define ARCMSR_CDB_FLAG_SIMPLEQ 0x00 356 #define ARCMSR_CDB_FLAG_HEADQ 0x08 357 #define ARCMSR_CDB_FLAG_ORDEREDQ 0x10 358 359 uint8_t msgPages; 360 uint32_t Context; 361 uint32_t DataLength; 362 uint8_t Cdb[16]; 363 uint8_t DeviceStatus; 364 #define ARCMSR_DEV_CHECK_CONDITION 0x02 365 #define ARCMSR_DEV_SELECT_TIMEOUT 0xF0 366 #define ARCMSR_DEV_ABORTED 0xF1 367 #define ARCMSR_DEV_INIT_FAIL 0xF2 368 369 uint8_t SenseData[15]; 370 union 371 { 372 struct SG32ENTRY sg32entry[1]; 373 struct SG64ENTRY sg64entry[1]; 374 } u; 375 }; 376 /* 377 ******************************************************************************* 378 ** Messaging Unit (MU) of the Intel R 80331 I/O processor(Type A) and Type B processor 379 ******************************************************************************* 380 */ 381 struct MessageUnit_A 382 { 383 uint32_t resrved0[4]; /*0000 000F*/ 384 uint32_t inbound_msgaddr0; /*0010 0013*/ 385 uint32_t inbound_msgaddr1; /*0014 0017*/ 386 uint32_t outbound_msgaddr0; /*0018 001B*/ 387 uint32_t outbound_msgaddr1; /*001C 001F*/ 388 uint32_t inbound_doorbell; /*0020 0023*/ 389 uint32_t inbound_intstatus; /*0024 0027*/ 390 uint32_t inbound_intmask; /*0028 002B*/ 391 uint32_t outbound_doorbell; /*002C 002F*/ 392 uint32_t outbound_intstatus; /*0030 0033*/ 393 uint32_t outbound_intmask; /*0034 0037*/ 394 uint32_t reserved1[2]; /*0038 003F*/ 395 uint32_t inbound_queueport; /*0040 0043*/ 396 uint32_t outbound_queueport; /*0044 0047*/ 397 uint32_t reserved2[2]; /*0048 004F*/ 398 uint32_t reserved3[492]; /*0050 07FF 492*/ 399 uint32_t reserved4[128]; /*0800 09FF 128*/ 400 uint32_t message_rwbuffer[256]; /*0a00 0DFF 256*/ 401 uint32_t message_wbuffer[32]; /*0E00 0E7F 32*/ 402 uint32_t reserved5[32]; /*0E80 0EFF 32*/ 403 uint32_t message_rbuffer[32]; /*0F00 0F7F 32*/ 404 uint32_t reserved6[32]; /*0F80 0FFF 32*/ 405 }; 406 407 struct MessageUnit_B 408 { 409 uint32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; 410 uint32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; 411 uint32_t postq_index; 412 uint32_t doneq_index; 413 uint32_t __iomem *drv2iop_doorbell; 414 uint32_t __iomem *drv2iop_doorbell_mask; 415 uint32_t __iomem *iop2drv_doorbell; 416 uint32_t __iomem *iop2drv_doorbell_mask; 417 uint32_t __iomem *message_rwbuffer; 418 uint32_t __iomem *message_wbuffer; 419 uint32_t __iomem *message_rbuffer; 420 }; 421 /* 422 ********************************************************************* 423 ** LSI 424 ********************************************************************* 425 */ 426 struct MessageUnit_C{ 427 uint32_t message_unit_status; /*0000 0003*/ 428 uint32_t slave_error_attribute; /*0004 0007*/ 429 uint32_t slave_error_address; /*0008 000B*/ 430 uint32_t posted_outbound_doorbell; /*000C 000F*/ 431 uint32_t master_error_attribute; /*0010 0013*/ 432 uint32_t master_error_address_low; /*0014 0017*/ 433 uint32_t master_error_address_high; /*0018 001B*/ 434 uint32_t hcb_size; /*001C 001F*/ 435 uint32_t inbound_doorbell; /*0020 0023*/ 436 uint32_t diagnostic_rw_data; /*0024 0027*/ 437 uint32_t diagnostic_rw_address_low; /*0028 002B*/ 438 uint32_t diagnostic_rw_address_high; /*002C 002F*/ 439 uint32_t host_int_status; /*0030 0033*/ 440 uint32_t host_int_mask; /*0034 0037*/ 441 uint32_t dcr_data; /*0038 003B*/ 442 uint32_t dcr_address; /*003C 003F*/ 443 uint32_t inbound_queueport; /*0040 0043*/ 444 uint32_t outbound_queueport; /*0044 0047*/ 445 uint32_t hcb_pci_address_low; /*0048 004B*/ 446 uint32_t hcb_pci_address_high; /*004C 004F*/ 447 uint32_t iop_int_status; /*0050 0053*/ 448 uint32_t iop_int_mask; /*0054 0057*/ 449 uint32_t iop_inbound_queue_port; /*0058 005B*/ 450 uint32_t iop_outbound_queue_port; /*005C 005F*/ 451 uint32_t inbound_free_list_index; /*0060 0063*/ 452 uint32_t inbound_post_list_index; /*0064 0067*/ 453 uint32_t outbound_free_list_index; /*0068 006B*/ 454 uint32_t outbound_post_list_index; /*006C 006F*/ 455 uint32_t inbound_doorbell_clear; /*0070 0073*/ 456 uint32_t i2o_message_unit_control; /*0074 0077*/ 457 uint32_t last_used_message_source_address_low; /*0078 007B*/ 458 uint32_t last_used_message_source_address_high; /*007C 007F*/ 459 uint32_t pull_mode_data_byte_count[4]; /*0080 008F*/ 460 uint32_t message_dest_address_index; /*0090 0093*/ 461 uint32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/ 462 uint32_t utility_A_int_counter_timer; /*0098 009B*/ 463 uint32_t outbound_doorbell; /*009C 009F*/ 464 uint32_t outbound_doorbell_clear; /*00A0 00A3*/ 465 uint32_t message_source_address_index; /*00A4 00A7*/ 466 uint32_t message_done_queue_index; /*00A8 00AB*/ 467 uint32_t reserved0; /*00AC 00AF*/ 468 uint32_t inbound_msgaddr0; /*00B0 00B3*/ 469 uint32_t inbound_msgaddr1; /*00B4 00B7*/ 470 uint32_t outbound_msgaddr0; /*00B8 00BB*/ 471 uint32_t outbound_msgaddr1; /*00BC 00BF*/ 472 uint32_t inbound_queueport_low; /*00C0 00C3*/ 473 uint32_t inbound_queueport_high; /*00C4 00C7*/ 474 uint32_t outbound_queueport_low; /*00C8 00CB*/ 475 uint32_t outbound_queueport_high; /*00CC 00CF*/ 476 uint32_t iop_inbound_queue_port_low; /*00D0 00D3*/ 477 uint32_t iop_inbound_queue_port_high; /*00D4 00D7*/ 478 uint32_t iop_outbound_queue_port_low; /*00D8 00DB*/ 479 uint32_t iop_outbound_queue_port_high; /*00DC 00DF*/ 480 uint32_t message_dest_queue_port_low; /*00E0 00E3*/ 481 uint32_t message_dest_queue_port_high; /*00E4 00E7*/ 482 uint32_t last_used_message_dest_address_low; /*00E8 00EB*/ 483 uint32_t last_used_message_dest_address_high; /*00EC 00EF*/ 484 uint32_t message_done_queue_base_address_low; /*00F0 00F3*/ 485 uint32_t message_done_queue_base_address_high; /*00F4 00F7*/ 486 uint32_t host_diagnostic; /*00F8 00FB*/ 487 uint32_t write_sequence; /*00FC 00FF*/ 488 uint32_t reserved1[34]; /*0100 0187*/ 489 uint32_t reserved2[1950]; /*0188 1FFF*/ 490 uint32_t message_wbuffer[32]; /*2000 207F*/ 491 uint32_t reserved3[32]; /*2080 20FF*/ 492 uint32_t message_rbuffer[32]; /*2100 217F*/ 493 uint32_t reserved4[32]; /*2180 21FF*/ 494 uint32_t msgcode_rwbuffer[256]; /*2200 23FF*/ 495 }; 496 /* 497 ******************************************************************************* 498 ** Adapter Control Block 499 ******************************************************************************* 500 */ 501 struct AdapterControlBlock 502 { 503 uint32_t adapter_type; /* adapter A,B..... */ 504 #define ACB_ADAPTER_TYPE_A 0x00000001 /* hba I IOP */ 505 #define ACB_ADAPTER_TYPE_B 0x00000002 /* hbb M IOP */ 506 #define ACB_ADAPTER_TYPE_C 0x00000004 /* hbc P IOP */ 507 #define ACB_ADAPTER_TYPE_D 0x00000008 /* hbd A IOP */ 508 struct pci_dev * pdev; 509 struct Scsi_Host * host; 510 unsigned long vir2phy_offset; 511 /* Offset is used in making arc cdb physical to virtual calculations */ 512 uint32_t outbound_int_enable; 513 uint32_t cdb_phyaddr_hi32; 514 uint32_t reg_mu_acc_handle0; 515 spinlock_t eh_lock; 516 spinlock_t ccblist_lock; 517 union { 518 struct MessageUnit_A __iomem *pmuA; 519 struct MessageUnit_B *pmuB; 520 struct MessageUnit_C __iomem *pmuC; 521 }; 522 /* message unit ATU inbound base address0 */ 523 void __iomem *mem_base0; 524 void __iomem *mem_base1; 525 uint32_t acb_flags; 526 u16 dev_id; 527 uint8_t adapter_index; 528 #define ACB_F_SCSISTOPADAPTER 0x0001 529 #define ACB_F_MSG_STOP_BGRB 0x0002 530 /* stop RAID background rebuild */ 531 #define ACB_F_MSG_START_BGRB 0x0004 532 /* stop RAID background rebuild */ 533 #define ACB_F_IOPDATA_OVERFLOW 0x0008 534 /* iop message data rqbuffer overflow */ 535 #define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 536 /* message clear wqbuffer */ 537 #define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 538 /* message clear rqbuffer */ 539 #define ACB_F_MESSAGE_WQBUFFER_READED 0x0040 540 #define ACB_F_BUS_RESET 0x0080 541 #define ACB_F_BUS_HANG_ON 0x0800/* need hardware reset bus */ 542 543 #define ACB_F_IOP_INITED 0x0100 544 /* iop init */ 545 #define ACB_F_ABORT 0x0200 546 #define ACB_F_FIRMWARE_TRAP 0x0400 547 struct CommandControlBlock * pccb_pool[ARCMSR_MAX_FREECCB_NUM]; 548 /* used for memory free */ 549 struct list_head ccb_free_list; 550 /* head of free ccb list */ 551 552 atomic_t ccboutstandingcount; 553 /*The present outstanding command number that in the IOP that 554 waiting for being handled by FW*/ 555 556 void * dma_coherent; 557 /* dma_coherent used for memory free */ 558 dma_addr_t dma_coherent_handle; 559 /* dma_coherent_handle used for memory free */ 560 dma_addr_t dma_coherent_handle_hbb_mu; 561 unsigned int uncache_size; 562 uint8_t rqbuffer[ARCMSR_MAX_QBUFFER]; 563 /* data collection buffer for read from 80331 */ 564 int32_t rqbuf_firstindex; 565 /* first of read buffer */ 566 int32_t rqbuf_lastindex; 567 /* last of read buffer */ 568 uint8_t wqbuffer[ARCMSR_MAX_QBUFFER]; 569 /* data collection buffer for write to 80331 */ 570 int32_t wqbuf_firstindex; 571 /* first of write buffer */ 572 int32_t wqbuf_lastindex; 573 /* last of write buffer */ 574 uint8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; 575 /* id0 ..... id15, lun0...lun7 */ 576 #define ARECA_RAID_GONE 0x55 577 #define ARECA_RAID_GOOD 0xaa 578 uint32_t num_resets; 579 uint32_t num_aborts; 580 uint32_t signature; 581 uint32_t firm_request_len; 582 uint32_t firm_numbers_queue; 583 uint32_t firm_sdram_size; 584 uint32_t firm_hd_channels; 585 uint32_t firm_cfg_version; 586 char firm_model[12]; 587 char firm_version[20]; 588 char device_map[20]; /*21,84-99*/ 589 struct work_struct arcmsr_do_message_isr_bh; 590 struct timer_list eternal_timer; 591 unsigned short fw_flag; 592 #define FW_NORMAL 0x0000 593 #define FW_BOG 0x0001 594 #define FW_DEADLOCK 0x0010 595 atomic_t rq_map_token; 596 atomic_t ante_token_value; 597 };/* HW_DEVICE_EXTENSION */ 598 /* 599 ******************************************************************************* 600 ** Command Control Block 601 ** this CCB length must be 32 bytes boundary 602 ******************************************************************************* 603 */ 604 struct CommandControlBlock{ 605 /*x32:sizeof struct_CCB=(32+60)byte, x64:sizeof struct_CCB=(64+60)byte*/ 606 struct list_head list; /*x32: 8byte, x64: 16byte*/ 607 struct scsi_cmnd *pcmd; /*8 bytes pointer of linux scsi command */ 608 struct AdapterControlBlock *acb; /*x32: 4byte, x64: 8byte*/ 609 uint32_t cdb_phyaddr_pattern; /*x32: 4byte, x64: 4byte*/ 610 uint32_t arc_cdb_size; /*x32:4byte,x64:4byte*/ 611 uint16_t ccb_flags; /*x32: 2byte, x64: 2byte*/ 612 #define CCB_FLAG_READ 0x0000 613 #define CCB_FLAG_WRITE 0x0001 614 #define CCB_FLAG_ERROR 0x0002 615 #define CCB_FLAG_FLUSHCACHE 0x0004 616 #define CCB_FLAG_MASTER_ABORTED 0x0008 617 uint16_t startdone; /*x32:2byte,x32:2byte*/ 618 #define ARCMSR_CCB_DONE 0x0000 619 #define ARCMSR_CCB_START 0x55AA 620 #define ARCMSR_CCB_ABORTED 0xAA55 621 #define ARCMSR_CCB_ILLEGAL 0xFFFF 622 #if BITS_PER_LONG == 64 623 /* ======================512+64 bytes======================== */ 624 uint32_t reserved[5]; /*24 byte*/ 625 #else 626 /* ======================512+32 bytes======================== */ 627 uint32_t reserved; /*8 byte*/ 628 #endif 629 /* ======================================================= */ 630 struct ARCMSR_CDB arcmsr_cdb; 631 }; 632 /* 633 ******************************************************************************* 634 ** ARECA SCSI sense data 635 ******************************************************************************* 636 */ 637 struct SENSE_DATA 638 { 639 uint8_t ErrorCode:7; 640 #define SCSI_SENSE_CURRENT_ERRORS 0x70 641 #define SCSI_SENSE_DEFERRED_ERRORS 0x71 642 uint8_t Valid:1; 643 uint8_t SegmentNumber; 644 uint8_t SenseKey:4; 645 uint8_t Reserved:1; 646 uint8_t IncorrectLength:1; 647 uint8_t EndOfMedia:1; 648 uint8_t FileMark:1; 649 uint8_t Information[4]; 650 uint8_t AdditionalSenseLength; 651 uint8_t CommandSpecificInformation[4]; 652 uint8_t AdditionalSenseCode; 653 uint8_t AdditionalSenseCodeQualifier; 654 uint8_t FieldReplaceableUnitCode; 655 uint8_t SenseKeySpecific[3]; 656 }; 657 /* 658 ******************************************************************************* 659 ** Outbound Interrupt Status Register - OISR 660 ******************************************************************************* 661 */ 662 #define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30 663 #define ARCMSR_MU_OUTBOUND_PCI_INT 0x10 664 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08 665 #define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04 666 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02 667 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01 668 #define ARCMSR_MU_OUTBOUND_HANDLE_INT \ 669 (ARCMSR_MU_OUTBOUND_MESSAGE0_INT \ 670 |ARCMSR_MU_OUTBOUND_MESSAGE1_INT \ 671 |ARCMSR_MU_OUTBOUND_DOORBELL_INT \ 672 |ARCMSR_MU_OUTBOUND_POSTQUEUE_INT \ 673 |ARCMSR_MU_OUTBOUND_PCI_INT) 674 /* 675 ******************************************************************************* 676 ** Outbound Interrupt Mask Register - OIMR 677 ******************************************************************************* 678 */ 679 #define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34 680 #define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10 681 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08 682 #define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04 683 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02 684 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01 685 #define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F 686 687 extern void arcmsr_post_ioctldata2iop(struct AdapterControlBlock *); 688 extern void arcmsr_iop_message_read(struct AdapterControlBlock *); 689 extern struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *); 690 extern struct device_attribute *arcmsr_host_attrs[]; 691 extern int arcmsr_alloc_sysfs_attr(struct AdapterControlBlock *); 692 void arcmsr_free_sysfs_attr(struct AdapterControlBlock *acb); 693