1 /*
2  * Aic94xx SAS/SATA driver hardware interface.
3  *
4  * Copyright (C) 2005 Adaptec, Inc.  All rights reserved.
5  * Copyright (C) 2005 Luben Tuikov <luben_tuikov@adaptec.com>
6  *
7  * This file is licensed under GPLv2.
8  *
9  * This file is part of the aic94xx driver.
10  *
11  * The aic94xx driver is free software; you can redistribute it and/or
12  * modify it under the terms of the GNU General Public License as
13  * published by the Free Software Foundation; version 2 of the
14  * License.
15  *
16  * The aic94xx driver is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
19  * General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with the aic94xx driver; if not, write to the Free Software
23  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
24  *
25  */
26 
27 #include <linux/pci.h>
28 #include <linux/slab.h>
29 #include <linux/delay.h>
30 #include <linux/module.h>
31 #include <linux/firmware.h>
32 
33 #include "aic94xx.h"
34 #include "aic94xx_reg.h"
35 #include "aic94xx_hwi.h"
36 #include "aic94xx_seq.h"
37 #include "aic94xx_dump.h"
38 
39 u32 MBAR0_SWB_SIZE;
40 
41 /* ---------- Initialization ---------- */
42 
43 static int asd_get_user_sas_addr(struct asd_ha_struct *asd_ha)
44 {
45 	/* adapter came with a sas address */
46 	if (asd_ha->hw_prof.sas_addr[0])
47 		return 0;
48 
49 	return sas_request_addr(asd_ha->sas_ha.core.shost,
50 				asd_ha->hw_prof.sas_addr);
51 }
52 
53 static void asd_propagate_sas_addr(struct asd_ha_struct *asd_ha)
54 {
55 	int i;
56 
57 	for (i = 0; i < ASD_MAX_PHYS; i++) {
58 		if (asd_ha->hw_prof.phy_desc[i].sas_addr[0] == 0)
59 			continue;
60 		/* Set a phy's address only if it has none.
61 		 */
62 		ASD_DPRINTK("setting phy%d addr to %llx\n", i,
63 			    SAS_ADDR(asd_ha->hw_prof.sas_addr));
64 		memcpy(asd_ha->hw_prof.phy_desc[i].sas_addr,
65 		       asd_ha->hw_prof.sas_addr, SAS_ADDR_SIZE);
66 	}
67 }
68 
69 /* ---------- PHY initialization ---------- */
70 
71 static void asd_init_phy_identify(struct asd_phy *phy)
72 {
73 	phy->identify_frame = phy->id_frm_tok->vaddr;
74 
75 	memset(phy->identify_frame, 0, sizeof(*phy->identify_frame));
76 
77 	phy->identify_frame->dev_type = SAS_END_DEVICE;
78 	if (phy->sas_phy.role & PHY_ROLE_INITIATOR)
79 		phy->identify_frame->initiator_bits = phy->sas_phy.iproto;
80 	if (phy->sas_phy.role & PHY_ROLE_TARGET)
81 		phy->identify_frame->target_bits = phy->sas_phy.tproto;
82 	memcpy(phy->identify_frame->sas_addr, phy->phy_desc->sas_addr,
83 	       SAS_ADDR_SIZE);
84 	phy->identify_frame->phy_id = phy->sas_phy.id;
85 }
86 
87 static int asd_init_phy(struct asd_phy *phy)
88 {
89 	struct asd_ha_struct *asd_ha = phy->sas_phy.ha->lldd_ha;
90 	struct asd_sas_phy *sas_phy = &phy->sas_phy;
91 
92 	sas_phy->enabled = 1;
93 	sas_phy->class = SAS;
94 	sas_phy->iproto = SAS_PROTOCOL_ALL;
95 	sas_phy->tproto = 0;
96 	sas_phy->type = PHY_TYPE_PHYSICAL;
97 	sas_phy->role = PHY_ROLE_INITIATOR;
98 	sas_phy->oob_mode = OOB_NOT_CONNECTED;
99 	sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
100 
101 	phy->id_frm_tok = asd_alloc_coherent(asd_ha,
102 					     sizeof(*phy->identify_frame),
103 					     GFP_KERNEL);
104 	if (!phy->id_frm_tok) {
105 		asd_printk("no mem for IDENTIFY for phy%d\n", sas_phy->id);
106 		return -ENOMEM;
107 	} else
108 		asd_init_phy_identify(phy);
109 
110 	memset(phy->frame_rcvd, 0, sizeof(phy->frame_rcvd));
111 
112 	return 0;
113 }
114 
115 static void asd_init_ports(struct asd_ha_struct *asd_ha)
116 {
117 	int i;
118 
119 	spin_lock_init(&asd_ha->asd_ports_lock);
120 	for (i = 0; i < ASD_MAX_PHYS; i++) {
121 		struct asd_port *asd_port = &asd_ha->asd_ports[i];
122 
123 		memset(asd_port->sas_addr, 0, SAS_ADDR_SIZE);
124 		memset(asd_port->attached_sas_addr, 0, SAS_ADDR_SIZE);
125 		asd_port->phy_mask = 0;
126 		asd_port->num_phys = 0;
127 	}
128 }
129 
130 static int asd_init_phys(struct asd_ha_struct *asd_ha)
131 {
132 	u8 i;
133 	u8 phy_mask = asd_ha->hw_prof.enabled_phys;
134 
135 	for (i = 0; i < ASD_MAX_PHYS; i++) {
136 		struct asd_phy *phy = &asd_ha->phys[i];
137 
138 		phy->phy_desc = &asd_ha->hw_prof.phy_desc[i];
139 		phy->asd_port = NULL;
140 
141 		phy->sas_phy.enabled = 0;
142 		phy->sas_phy.id = i;
143 		phy->sas_phy.sas_addr = &phy->phy_desc->sas_addr[0];
144 		phy->sas_phy.frame_rcvd = &phy->frame_rcvd[0];
145 		phy->sas_phy.ha = &asd_ha->sas_ha;
146 		phy->sas_phy.lldd_phy = phy;
147 	}
148 
149 	/* Now enable and initialize only the enabled phys. */
150 	for_each_phy(phy_mask, phy_mask, i) {
151 		int err = asd_init_phy(&asd_ha->phys[i]);
152 		if (err)
153 			return err;
154 	}
155 
156 	return 0;
157 }
158 
159 /* ---------- Sliding windows ---------- */
160 
161 static int asd_init_sw(struct asd_ha_struct *asd_ha)
162 {
163 	struct pci_dev *pcidev = asd_ha->pcidev;
164 	int err;
165 	u32 v;
166 
167 	/* Unlock MBARs */
168 	err = pci_read_config_dword(pcidev, PCI_CONF_MBAR_KEY, &v);
169 	if (err) {
170 		asd_printk("couldn't access conf. space of %s\n",
171 			   pci_name(pcidev));
172 		goto Err;
173 	}
174 	if (v)
175 		err = pci_write_config_dword(pcidev, PCI_CONF_MBAR_KEY, v);
176 	if (err) {
177 		asd_printk("couldn't write to MBAR_KEY of %s\n",
178 			   pci_name(pcidev));
179 		goto Err;
180 	}
181 
182 	/* Set sliding windows A, B and C to point to proper internal
183 	 * memory regions.
184 	 */
185 	pci_write_config_dword(pcidev, PCI_CONF_MBAR0_SWA, REG_BASE_ADDR);
186 	pci_write_config_dword(pcidev, PCI_CONF_MBAR0_SWB,
187 			       REG_BASE_ADDR_CSEQCIO);
188 	pci_write_config_dword(pcidev, PCI_CONF_MBAR0_SWC, REG_BASE_ADDR_EXSI);
189 	asd_ha->io_handle[0].swa_base = REG_BASE_ADDR;
190 	asd_ha->io_handle[0].swb_base = REG_BASE_ADDR_CSEQCIO;
191 	asd_ha->io_handle[0].swc_base = REG_BASE_ADDR_EXSI;
192 	MBAR0_SWB_SIZE = asd_ha->io_handle[0].len - 0x80;
193 	if (!asd_ha->iospace) {
194 		/* MBAR1 will point to OCM (On Chip Memory) */
195 		pci_write_config_dword(pcidev, PCI_CONF_MBAR1, OCM_BASE_ADDR);
196 		asd_ha->io_handle[1].swa_base = OCM_BASE_ADDR;
197 	}
198 	spin_lock_init(&asd_ha->iolock);
199 Err:
200 	return err;
201 }
202 
203 /* ---------- SCB initialization ---------- */
204 
205 /**
206  * asd_init_scbs - manually allocate the first SCB.
207  * @asd_ha: pointer to host adapter structure
208  *
209  * This allocates the very first SCB which would be sent to the
210  * sequencer for execution.  Its bus address is written to
211  * CSEQ_Q_NEW_POINTER, mode page 2, mode 8.  Since the bus address of
212  * the _next_ scb to be DMA-ed to the host adapter is read from the last
213  * SCB DMA-ed to the host adapter, we have to always stay one step
214  * ahead of the sequencer and keep one SCB already allocated.
215  */
216 static int asd_init_scbs(struct asd_ha_struct *asd_ha)
217 {
218 	struct asd_seq_data *seq = &asd_ha->seq;
219 	int bitmap_bytes;
220 
221 	/* allocate the index array and bitmap */
222 	asd_ha->seq.tc_index_bitmap_bits = asd_ha->hw_prof.max_scbs;
223 	asd_ha->seq.tc_index_array = kcalloc(asd_ha->seq.tc_index_bitmap_bits,
224 					     sizeof(void *),
225 					     GFP_KERNEL);
226 	if (!asd_ha->seq.tc_index_array)
227 		return -ENOMEM;
228 
229 	bitmap_bytes = (asd_ha->seq.tc_index_bitmap_bits+7)/8;
230 	bitmap_bytes = BITS_TO_LONGS(bitmap_bytes*8)*sizeof(unsigned long);
231 	asd_ha->seq.tc_index_bitmap = kzalloc(bitmap_bytes, GFP_KERNEL);
232 	if (!asd_ha->seq.tc_index_bitmap) {
233 		kfree(asd_ha->seq.tc_index_array);
234 		asd_ha->seq.tc_index_array = NULL;
235 		return -ENOMEM;
236 	}
237 
238 	spin_lock_init(&seq->tc_index_lock);
239 
240 	seq->next_scb.size = sizeof(struct scb);
241 	seq->next_scb.vaddr = dma_pool_alloc(asd_ha->scb_pool, GFP_KERNEL,
242 					     &seq->next_scb.dma_handle);
243 	if (!seq->next_scb.vaddr) {
244 		kfree(asd_ha->seq.tc_index_bitmap);
245 		kfree(asd_ha->seq.tc_index_array);
246 		asd_ha->seq.tc_index_bitmap = NULL;
247 		asd_ha->seq.tc_index_array = NULL;
248 		return -ENOMEM;
249 	}
250 
251 	seq->pending = 0;
252 	spin_lock_init(&seq->pend_q_lock);
253 	INIT_LIST_HEAD(&seq->pend_q);
254 
255 	return 0;
256 }
257 
258 static void asd_get_max_scb_ddb(struct asd_ha_struct *asd_ha)
259 {
260 	asd_ha->hw_prof.max_scbs = asd_get_cmdctx_size(asd_ha)/ASD_SCB_SIZE;
261 	asd_ha->hw_prof.max_ddbs = asd_get_devctx_size(asd_ha)/ASD_DDB_SIZE;
262 	ASD_DPRINTK("max_scbs:%d, max_ddbs:%d\n",
263 		    asd_ha->hw_prof.max_scbs,
264 		    asd_ha->hw_prof.max_ddbs);
265 }
266 
267 /* ---------- Done List initialization ---------- */
268 
269 static void asd_dl_tasklet_handler(unsigned long);
270 
271 static int asd_init_dl(struct asd_ha_struct *asd_ha)
272 {
273 	asd_ha->seq.actual_dl
274 		= asd_alloc_coherent(asd_ha,
275 			     ASD_DL_SIZE * sizeof(struct done_list_struct),
276 				     GFP_KERNEL);
277 	if (!asd_ha->seq.actual_dl)
278 		return -ENOMEM;
279 	asd_ha->seq.dl = asd_ha->seq.actual_dl->vaddr;
280 	asd_ha->seq.dl_toggle = ASD_DEF_DL_TOGGLE;
281 	asd_ha->seq.dl_next = 0;
282 	tasklet_init(&asd_ha->seq.dl_tasklet, asd_dl_tasklet_handler,
283 		     (unsigned long) asd_ha);
284 
285 	return 0;
286 }
287 
288 /* ---------- EDB and ESCB init ---------- */
289 
290 static int asd_alloc_edbs(struct asd_ha_struct *asd_ha, gfp_t gfp_flags)
291 {
292 	struct asd_seq_data *seq = &asd_ha->seq;
293 	int i;
294 
295 	seq->edb_arr = kmalloc_array(seq->num_edbs, sizeof(*seq->edb_arr),
296 				     gfp_flags);
297 	if (!seq->edb_arr)
298 		return -ENOMEM;
299 
300 	for (i = 0; i < seq->num_edbs; i++) {
301 		seq->edb_arr[i] = asd_alloc_coherent(asd_ha, ASD_EDB_SIZE,
302 						     gfp_flags);
303 		if (!seq->edb_arr[i])
304 			goto Err_unroll;
305 		memset(seq->edb_arr[i]->vaddr, 0, ASD_EDB_SIZE);
306 	}
307 
308 	ASD_DPRINTK("num_edbs:%d\n", seq->num_edbs);
309 
310 	return 0;
311 
312 Err_unroll:
313 	for (i-- ; i >= 0; i--)
314 		asd_free_coherent(asd_ha, seq->edb_arr[i]);
315 	kfree(seq->edb_arr);
316 	seq->edb_arr = NULL;
317 
318 	return -ENOMEM;
319 }
320 
321 static int asd_alloc_escbs(struct asd_ha_struct *asd_ha,
322 			   gfp_t gfp_flags)
323 {
324 	struct asd_seq_data *seq = &asd_ha->seq;
325 	struct asd_ascb *escb;
326 	int i, escbs;
327 
328 	seq->escb_arr = kmalloc_array(seq->num_escbs, sizeof(*seq->escb_arr),
329 				      gfp_flags);
330 	if (!seq->escb_arr)
331 		return -ENOMEM;
332 
333 	escbs = seq->num_escbs;
334 	escb = asd_ascb_alloc_list(asd_ha, &escbs, gfp_flags);
335 	if (!escb) {
336 		asd_printk("couldn't allocate list of escbs\n");
337 		goto Err;
338 	}
339 	seq->num_escbs -= escbs;  /* subtract what was not allocated */
340 	ASD_DPRINTK("num_escbs:%d\n", seq->num_escbs);
341 
342 	for (i = 0; i < seq->num_escbs; i++, escb = list_entry(escb->list.next,
343 							       struct asd_ascb,
344 							       list)) {
345 		seq->escb_arr[i] = escb;
346 		escb->scb->header.opcode = EMPTY_SCB;
347 	}
348 
349 	return 0;
350 Err:
351 	kfree(seq->escb_arr);
352 	seq->escb_arr = NULL;
353 	return -ENOMEM;
354 
355 }
356 
357 static void asd_assign_edbs2escbs(struct asd_ha_struct *asd_ha)
358 {
359 	struct asd_seq_data *seq = &asd_ha->seq;
360 	int i, k, z = 0;
361 
362 	for (i = 0; i < seq->num_escbs; i++) {
363 		struct asd_ascb *ascb = seq->escb_arr[i];
364 		struct empty_scb *escb = &ascb->scb->escb;
365 
366 		ascb->edb_index = z;
367 
368 		escb->num_valid = ASD_EDBS_PER_SCB;
369 
370 		for (k = 0; k < ASD_EDBS_PER_SCB; k++) {
371 			struct sg_el *eb = &escb->eb[k];
372 			struct asd_dma_tok *edb = seq->edb_arr[z++];
373 
374 			memset(eb, 0, sizeof(*eb));
375 			eb->bus_addr = cpu_to_le64(((u64) edb->dma_handle));
376 			eb->size = cpu_to_le32(((u32) edb->size));
377 		}
378 	}
379 }
380 
381 /**
382  * asd_init_escbs -- allocate and initialize empty scbs
383  * @asd_ha: pointer to host adapter structure
384  *
385  * An empty SCB has sg_elements of ASD_EDBS_PER_SCB (7) buffers.
386  * They transport sense data, etc.
387  */
388 static int asd_init_escbs(struct asd_ha_struct *asd_ha)
389 {
390 	struct asd_seq_data *seq = &asd_ha->seq;
391 	int err = 0;
392 
393 	/* Allocate two empty data buffers (edb) per sequencer. */
394 	int edbs = 2*(1+asd_ha->hw_prof.num_phys);
395 
396 	seq->num_escbs = (edbs+ASD_EDBS_PER_SCB-1)/ASD_EDBS_PER_SCB;
397 	seq->num_edbs = seq->num_escbs * ASD_EDBS_PER_SCB;
398 
399 	err = asd_alloc_edbs(asd_ha, GFP_KERNEL);
400 	if (err) {
401 		asd_printk("couldn't allocate edbs\n");
402 		return err;
403 	}
404 
405 	err = asd_alloc_escbs(asd_ha, GFP_KERNEL);
406 	if (err) {
407 		asd_printk("couldn't allocate escbs\n");
408 		return err;
409 	}
410 
411 	asd_assign_edbs2escbs(asd_ha);
412 	/* In order to insure that normal SCBs do not overfill sequencer
413 	 * memory and leave no space for escbs (halting condition),
414 	 * we increment pending here by the number of escbs.  However,
415 	 * escbs are never pending.
416 	 */
417 	seq->pending   = seq->num_escbs;
418 	seq->can_queue = 1 + (asd_ha->hw_prof.max_scbs - seq->pending)/2;
419 
420 	return 0;
421 }
422 
423 /* ---------- HW initialization ---------- */
424 
425 /**
426  * asd_chip_hardrst -- hard reset the chip
427  * @asd_ha: pointer to host adapter structure
428  *
429  * This takes 16 cycles and is synchronous to CFCLK, which runs
430  * at 200 MHz, so this should take at most 80 nanoseconds.
431  */
432 int asd_chip_hardrst(struct asd_ha_struct *asd_ha)
433 {
434 	int i;
435 	int count = 100;
436 	u32 reg;
437 
438 	for (i = 0 ; i < 4 ; i++) {
439 		asd_write_reg_dword(asd_ha, COMBIST, HARDRST);
440 	}
441 
442 	do {
443 		udelay(1);
444 		reg = asd_read_reg_dword(asd_ha, CHIMINT);
445 		if (reg & HARDRSTDET) {
446 			asd_write_reg_dword(asd_ha, CHIMINT,
447 					    HARDRSTDET|PORRSTDET);
448 			return 0;
449 		}
450 	} while (--count > 0);
451 
452 	return -ENODEV;
453 }
454 
455 /**
456  * asd_init_chip -- initialize the chip
457  * @asd_ha: pointer to host adapter structure
458  *
459  * Hard resets the chip, disables HA interrupts, downloads the sequnecer
460  * microcode and starts the sequencers.  The caller has to explicitly
461  * enable HA interrupts with asd_enable_ints(asd_ha).
462  */
463 static int asd_init_chip(struct asd_ha_struct *asd_ha)
464 {
465 	int err;
466 
467 	err = asd_chip_hardrst(asd_ha);
468 	if (err) {
469 		asd_printk("couldn't hard reset %s\n",
470 			    pci_name(asd_ha->pcidev));
471 		goto out;
472 	}
473 
474 	asd_disable_ints(asd_ha);
475 
476 	err = asd_init_seqs(asd_ha);
477 	if (err) {
478 		asd_printk("couldn't init seqs for %s\n",
479 			   pci_name(asd_ha->pcidev));
480 		goto out;
481 	}
482 
483 	err = asd_start_seqs(asd_ha);
484 	if (err) {
485 		asd_printk("couldn't start seqs for %s\n",
486 			   pci_name(asd_ha->pcidev));
487 		goto out;
488 	}
489 out:
490 	return err;
491 }
492 
493 #define MAX_DEVS ((OCM_MAX_SIZE) / (ASD_DDB_SIZE))
494 
495 static int max_devs = 0;
496 module_param_named(max_devs, max_devs, int, S_IRUGO);
497 MODULE_PARM_DESC(max_devs, "\n"
498 	"\tMaximum number of SAS devices to support (not LUs).\n"
499 	"\tDefault: 2176, Maximum: 65663.\n");
500 
501 static int max_cmnds = 0;
502 module_param_named(max_cmnds, max_cmnds, int, S_IRUGO);
503 MODULE_PARM_DESC(max_cmnds, "\n"
504 	"\tMaximum number of commands queuable.\n"
505 	"\tDefault: 512, Maximum: 66047.\n");
506 
507 static void asd_extend_devctx_ocm(struct asd_ha_struct *asd_ha)
508 {
509 	unsigned long dma_addr = OCM_BASE_ADDR;
510 	u32 d;
511 
512 	dma_addr -= asd_ha->hw_prof.max_ddbs * ASD_DDB_SIZE;
513 	asd_write_reg_addr(asd_ha, DEVCTXBASE, (dma_addr_t) dma_addr);
514 	d = asd_read_reg_dword(asd_ha, CTXDOMAIN);
515 	d |= 4;
516 	asd_write_reg_dword(asd_ha, CTXDOMAIN, d);
517 	asd_ha->hw_prof.max_ddbs += MAX_DEVS;
518 }
519 
520 static int asd_extend_devctx(struct asd_ha_struct *asd_ha)
521 {
522 	dma_addr_t dma_handle;
523 	unsigned long dma_addr;
524 	u32 d;
525 	int size;
526 
527 	asd_extend_devctx_ocm(asd_ha);
528 
529 	asd_ha->hw_prof.ddb_ext = NULL;
530 	if (max_devs <= asd_ha->hw_prof.max_ddbs || max_devs > 0xFFFF) {
531 		max_devs = asd_ha->hw_prof.max_ddbs;
532 		return 0;
533 	}
534 
535 	size = (max_devs - asd_ha->hw_prof.max_ddbs + 1) * ASD_DDB_SIZE;
536 
537 	asd_ha->hw_prof.ddb_ext = asd_alloc_coherent(asd_ha, size, GFP_KERNEL);
538 	if (!asd_ha->hw_prof.ddb_ext) {
539 		asd_printk("couldn't allocate memory for %d devices\n",
540 			   max_devs);
541 		max_devs = asd_ha->hw_prof.max_ddbs;
542 		return -ENOMEM;
543 	}
544 	dma_handle = asd_ha->hw_prof.ddb_ext->dma_handle;
545 	dma_addr = ALIGN((unsigned long) dma_handle, ASD_DDB_SIZE);
546 	dma_addr -= asd_ha->hw_prof.max_ddbs * ASD_DDB_SIZE;
547 	dma_handle = (dma_addr_t) dma_addr;
548 	asd_write_reg_addr(asd_ha, DEVCTXBASE, dma_handle);
549 	d = asd_read_reg_dword(asd_ha, CTXDOMAIN);
550 	d &= ~4;
551 	asd_write_reg_dword(asd_ha, CTXDOMAIN, d);
552 
553 	asd_ha->hw_prof.max_ddbs = max_devs;
554 
555 	return 0;
556 }
557 
558 static int asd_extend_cmdctx(struct asd_ha_struct *asd_ha)
559 {
560 	dma_addr_t dma_handle;
561 	unsigned long dma_addr;
562 	u32 d;
563 	int size;
564 
565 	asd_ha->hw_prof.scb_ext = NULL;
566 	if (max_cmnds <= asd_ha->hw_prof.max_scbs || max_cmnds > 0xFFFF) {
567 		max_cmnds = asd_ha->hw_prof.max_scbs;
568 		return 0;
569 	}
570 
571 	size = (max_cmnds - asd_ha->hw_prof.max_scbs + 1) * ASD_SCB_SIZE;
572 
573 	asd_ha->hw_prof.scb_ext = asd_alloc_coherent(asd_ha, size, GFP_KERNEL);
574 	if (!asd_ha->hw_prof.scb_ext) {
575 		asd_printk("couldn't allocate memory for %d commands\n",
576 			   max_cmnds);
577 		max_cmnds = asd_ha->hw_prof.max_scbs;
578 		return -ENOMEM;
579 	}
580 	dma_handle = asd_ha->hw_prof.scb_ext->dma_handle;
581 	dma_addr = ALIGN((unsigned long) dma_handle, ASD_SCB_SIZE);
582 	dma_addr -= asd_ha->hw_prof.max_scbs * ASD_SCB_SIZE;
583 	dma_handle = (dma_addr_t) dma_addr;
584 	asd_write_reg_addr(asd_ha, CMDCTXBASE, dma_handle);
585 	d = asd_read_reg_dword(asd_ha, CTXDOMAIN);
586 	d &= ~1;
587 	asd_write_reg_dword(asd_ha, CTXDOMAIN, d);
588 
589 	asd_ha->hw_prof.max_scbs = max_cmnds;
590 
591 	return 0;
592 }
593 
594 /**
595  * asd_init_ctxmem -- initialize context memory
596  * asd_ha: pointer to host adapter structure
597  *
598  * This function sets the maximum number of SCBs and
599  * DDBs which can be used by the sequencer.  This is normally
600  * 512 and 128 respectively.  If support for more SCBs or more DDBs
601  * is required then CMDCTXBASE, DEVCTXBASE and CTXDOMAIN are
602  * initialized here to extend context memory to point to host memory,
603  * thus allowing unlimited support for SCBs and DDBs -- only limited
604  * by host memory.
605  */
606 static int asd_init_ctxmem(struct asd_ha_struct *asd_ha)
607 {
608 	int bitmap_bytes;
609 
610 	asd_get_max_scb_ddb(asd_ha);
611 	asd_extend_devctx(asd_ha);
612 	asd_extend_cmdctx(asd_ha);
613 
614 	/* The kernel wants bitmaps to be unsigned long sized. */
615 	bitmap_bytes = (asd_ha->hw_prof.max_ddbs+7)/8;
616 	bitmap_bytes = BITS_TO_LONGS(bitmap_bytes*8)*sizeof(unsigned long);
617 	asd_ha->hw_prof.ddb_bitmap = kzalloc(bitmap_bytes, GFP_KERNEL);
618 	if (!asd_ha->hw_prof.ddb_bitmap)
619 		return -ENOMEM;
620 	spin_lock_init(&asd_ha->hw_prof.ddb_lock);
621 
622 	return 0;
623 }
624 
625 int asd_init_hw(struct asd_ha_struct *asd_ha)
626 {
627 	int err;
628 	u32 v;
629 
630 	err = asd_init_sw(asd_ha);
631 	if (err)
632 		return err;
633 
634 	err = pci_read_config_dword(asd_ha->pcidev, PCIC_HSTPCIX_CNTRL, &v);
635 	if (err) {
636 		asd_printk("couldn't read PCIC_HSTPCIX_CNTRL of %s\n",
637 			   pci_name(asd_ha->pcidev));
638 		return err;
639 	}
640 	err = pci_write_config_dword(asd_ha->pcidev, PCIC_HSTPCIX_CNTRL,
641 					v | SC_TMR_DIS);
642 	if (err) {
643 		asd_printk("couldn't disable split completion timer of %s\n",
644 			   pci_name(asd_ha->pcidev));
645 		return err;
646 	}
647 
648 	err = asd_read_ocm(asd_ha);
649 	if (err) {
650 		asd_printk("couldn't read ocm(%d)\n", err);
651 		/* While suspicios, it is not an error that we
652 		 * couldn't read the OCM. */
653 	}
654 
655 	err = asd_read_flash(asd_ha);
656 	if (err) {
657 		asd_printk("couldn't read flash(%d)\n", err);
658 		/* While suspicios, it is not an error that we
659 		 * couldn't read FLASH memory.
660 		 */
661 	}
662 
663 	asd_init_ctxmem(asd_ha);
664 
665 	if (asd_get_user_sas_addr(asd_ha)) {
666 		asd_printk("No SAS Address provided for %s\n",
667 			   pci_name(asd_ha->pcidev));
668 		err = -ENODEV;
669 		goto Out;
670 	}
671 
672 	asd_propagate_sas_addr(asd_ha);
673 
674 	err = asd_init_phys(asd_ha);
675 	if (err) {
676 		asd_printk("couldn't initialize phys for %s\n",
677 			    pci_name(asd_ha->pcidev));
678 		goto Out;
679 	}
680 
681 	asd_init_ports(asd_ha);
682 
683 	err = asd_init_scbs(asd_ha);
684 	if (err) {
685 		asd_printk("couldn't initialize scbs for %s\n",
686 			    pci_name(asd_ha->pcidev));
687 		goto Out;
688 	}
689 
690 	err = asd_init_dl(asd_ha);
691 	if (err) {
692 		asd_printk("couldn't initialize the done list:%d\n",
693 			    err);
694 		goto Out;
695 	}
696 
697 	err = asd_init_escbs(asd_ha);
698 	if (err) {
699 		asd_printk("couldn't initialize escbs\n");
700 		goto Out;
701 	}
702 
703 	err = asd_init_chip(asd_ha);
704 	if (err) {
705 		asd_printk("couldn't init the chip\n");
706 		goto Out;
707 	}
708 Out:
709 	return err;
710 }
711 
712 /* ---------- Chip reset ---------- */
713 
714 /**
715  * asd_chip_reset -- reset the host adapter, etc
716  * @asd_ha: pointer to host adapter structure of interest
717  *
718  * Called from the ISR.  Hard reset the chip.  Let everything
719  * timeout.  This should be no different than hot-unplugging the
720  * host adapter.  Once everything times out we'll init the chip with
721  * a call to asd_init_chip() and enable interrupts with asd_enable_ints().
722  * XXX finish.
723  */
724 static void asd_chip_reset(struct asd_ha_struct *asd_ha)
725 {
726 	ASD_DPRINTK("chip reset for %s\n", pci_name(asd_ha->pcidev));
727 	asd_chip_hardrst(asd_ha);
728 }
729 
730 /* ---------- Done List Routines ---------- */
731 
732 static void asd_dl_tasklet_handler(unsigned long data)
733 {
734 	struct asd_ha_struct *asd_ha = (struct asd_ha_struct *) data;
735 	struct asd_seq_data *seq = &asd_ha->seq;
736 	unsigned long flags;
737 
738 	while (1) {
739 		struct done_list_struct *dl = &seq->dl[seq->dl_next];
740 		struct asd_ascb *ascb;
741 
742 		if ((dl->toggle & DL_TOGGLE_MASK) != seq->dl_toggle)
743 			break;
744 
745 		/* find the aSCB */
746 		spin_lock_irqsave(&seq->tc_index_lock, flags);
747 		ascb = asd_tc_index_find(seq, (int)le16_to_cpu(dl->index));
748 		spin_unlock_irqrestore(&seq->tc_index_lock, flags);
749 		if (unlikely(!ascb)) {
750 			ASD_DPRINTK("BUG:sequencer:dl:no ascb?!\n");
751 			goto next_1;
752 		} else if (ascb->scb->header.opcode == EMPTY_SCB) {
753 			goto out;
754 		} else if (!ascb->uldd_timer && !del_timer(&ascb->timer)) {
755 			goto next_1;
756 		}
757 		spin_lock_irqsave(&seq->pend_q_lock, flags);
758 		list_del_init(&ascb->list);
759 		seq->pending--;
760 		spin_unlock_irqrestore(&seq->pend_q_lock, flags);
761 	out:
762 		ascb->tasklet_complete(ascb, dl);
763 
764 	next_1:
765 		seq->dl_next = (seq->dl_next + 1) & (ASD_DL_SIZE-1);
766 		if (!seq->dl_next)
767 			seq->dl_toggle ^= DL_TOGGLE_MASK;
768 	}
769 }
770 
771 /* ---------- Interrupt Service Routines ---------- */
772 
773 /**
774  * asd_process_donelist_isr -- schedule processing of done list entries
775  * @asd_ha: pointer to host adapter structure
776  */
777 static void asd_process_donelist_isr(struct asd_ha_struct *asd_ha)
778 {
779 	tasklet_schedule(&asd_ha->seq.dl_tasklet);
780 }
781 
782 /**
783  * asd_com_sas_isr -- process device communication interrupt (COMINT)
784  * @asd_ha: pointer to host adapter structure
785  */
786 static void asd_com_sas_isr(struct asd_ha_struct *asd_ha)
787 {
788 	u32 comstat = asd_read_reg_dword(asd_ha, COMSTAT);
789 
790 	/* clear COMSTAT int */
791 	asd_write_reg_dword(asd_ha, COMSTAT, 0xFFFFFFFF);
792 
793 	if (comstat & CSBUFPERR) {
794 		asd_printk("%s: command/status buffer dma parity error\n",
795 			   pci_name(asd_ha->pcidev));
796 	} else if (comstat & CSERR) {
797 		int i;
798 		u32 dmaerr = asd_read_reg_dword(asd_ha, DMAERR);
799 		dmaerr &= 0xFF;
800 		asd_printk("%s: command/status dma error, DMAERR: 0x%02x, "
801 			   "CSDMAADR: 0x%04x, CSDMAADR+4: 0x%04x\n",
802 			   pci_name(asd_ha->pcidev),
803 			   dmaerr,
804 			   asd_read_reg_dword(asd_ha, CSDMAADR),
805 			   asd_read_reg_dword(asd_ha, CSDMAADR+4));
806 		asd_printk("CSBUFFER:\n");
807 		for (i = 0; i < 8; i++) {
808 			asd_printk("%08x %08x %08x %08x\n",
809 				   asd_read_reg_dword(asd_ha, CSBUFFER),
810 				   asd_read_reg_dword(asd_ha, CSBUFFER+4),
811 				   asd_read_reg_dword(asd_ha, CSBUFFER+8),
812 				   asd_read_reg_dword(asd_ha, CSBUFFER+12));
813 		}
814 		asd_dump_seq_state(asd_ha, 0);
815 	} else if (comstat & OVLYERR) {
816 		u32 dmaerr = asd_read_reg_dword(asd_ha, DMAERR);
817 		dmaerr = (dmaerr >> 8) & 0xFF;
818 		asd_printk("%s: overlay dma error:0x%x\n",
819 			   pci_name(asd_ha->pcidev),
820 			   dmaerr);
821 	}
822 	asd_chip_reset(asd_ha);
823 }
824 
825 static void asd_arp2_err(struct asd_ha_struct *asd_ha, u32 dchstatus)
826 {
827 	static const char *halt_code[256] = {
828 		"UNEXPECTED_INTERRUPT0",
829 		"UNEXPECTED_INTERRUPT1",
830 		"UNEXPECTED_INTERRUPT2",
831 		"UNEXPECTED_INTERRUPT3",
832 		"UNEXPECTED_INTERRUPT4",
833 		"UNEXPECTED_INTERRUPT5",
834 		"UNEXPECTED_INTERRUPT6",
835 		"UNEXPECTED_INTERRUPT7",
836 		"UNEXPECTED_INTERRUPT8",
837 		"UNEXPECTED_INTERRUPT9",
838 		"UNEXPECTED_INTERRUPT10",
839 		[11 ... 19] = "unknown[11,19]",
840 		"NO_FREE_SCB_AVAILABLE",
841 		"INVALID_SCB_OPCODE",
842 		"INVALID_MBX_OPCODE",
843 		"INVALID_ATA_STATE",
844 		"ATA_QUEUE_FULL",
845 		"ATA_TAG_TABLE_FAULT",
846 		"ATA_TAG_MASK_FAULT",
847 		"BAD_LINK_QUEUE_STATE",
848 		"DMA2CHIM_QUEUE_ERROR",
849 		"EMPTY_SCB_LIST_FULL",
850 		"unknown[30]",
851 		"IN_USE_SCB_ON_FREE_LIST",
852 		"BAD_OPEN_WAIT_STATE",
853 		"INVALID_STP_AFFILIATION",
854 		"unknown[34]",
855 		"EXEC_QUEUE_ERROR",
856 		"TOO_MANY_EMPTIES_NEEDED",
857 		"EMPTY_REQ_QUEUE_ERROR",
858 		"Q_MONIRTT_MGMT_ERROR",
859 		"TARGET_MODE_FLOW_ERROR",
860 		"DEVICE_QUEUE_NOT_FOUND",
861 		"START_IRTT_TIMER_ERROR",
862 		"ABORT_TASK_ILLEGAL_REQ",
863 		[43 ... 255] = "unknown[43,255]"
864 	};
865 
866 	if (dchstatus & CSEQINT) {
867 		u32 arp2int = asd_read_reg_dword(asd_ha, CARP2INT);
868 
869 		if (arp2int & (ARP2WAITTO|ARP2ILLOPC|ARP2PERR|ARP2CIOPERR)) {
870 			asd_printk("%s: CSEQ arp2int:0x%x\n",
871 				   pci_name(asd_ha->pcidev),
872 				   arp2int);
873 		} else if (arp2int & ARP2HALTC)
874 			asd_printk("%s: CSEQ halted: %s\n",
875 				   pci_name(asd_ha->pcidev),
876 				   halt_code[(arp2int>>16)&0xFF]);
877 		else
878 			asd_printk("%s: CARP2INT:0x%x\n",
879 				   pci_name(asd_ha->pcidev),
880 				   arp2int);
881 	}
882 	if (dchstatus & LSEQINT_MASK) {
883 		int lseq;
884 		u8  lseq_mask = dchstatus & LSEQINT_MASK;
885 
886 		for_each_sequencer(lseq_mask, lseq_mask, lseq) {
887 			u32 arp2int = asd_read_reg_dword(asd_ha,
888 							 LmARP2INT(lseq));
889 			if (arp2int & (ARP2WAITTO | ARP2ILLOPC | ARP2PERR
890 				       | ARP2CIOPERR)) {
891 				asd_printk("%s: LSEQ%d arp2int:0x%x\n",
892 					   pci_name(asd_ha->pcidev),
893 					   lseq, arp2int);
894 				/* XXX we should only do lseq reset */
895 			} else if (arp2int & ARP2HALTC)
896 				asd_printk("%s: LSEQ%d halted: %s\n",
897 					   pci_name(asd_ha->pcidev),
898 					   lseq,halt_code[(arp2int>>16)&0xFF]);
899 			else
900 				asd_printk("%s: LSEQ%d ARP2INT:0x%x\n",
901 					   pci_name(asd_ha->pcidev), lseq,
902 					   arp2int);
903 		}
904 	}
905 	asd_chip_reset(asd_ha);
906 }
907 
908 /**
909  * asd_dch_sas_isr -- process device channel interrupt (DEVINT)
910  * @asd_ha: pointer to host adapter structure
911  */
912 static void asd_dch_sas_isr(struct asd_ha_struct *asd_ha)
913 {
914 	u32 dchstatus = asd_read_reg_dword(asd_ha, DCHSTATUS);
915 
916 	if (dchstatus & CFIFTOERR) {
917 		asd_printk("%s: CFIFTOERR\n", pci_name(asd_ha->pcidev));
918 		asd_chip_reset(asd_ha);
919 	} else
920 		asd_arp2_err(asd_ha, dchstatus);
921 }
922 
923 /**
924  * ads_rbi_exsi_isr -- process external system interface interrupt (INITERR)
925  * @asd_ha: pointer to host adapter structure
926  */
927 static void asd_rbi_exsi_isr(struct asd_ha_struct *asd_ha)
928 {
929 	u32 stat0r = asd_read_reg_dword(asd_ha, ASISTAT0R);
930 
931 	if (!(stat0r & ASIERR)) {
932 		asd_printk("hmm, EXSI interrupted but no error?\n");
933 		return;
934 	}
935 
936 	if (stat0r & ASIFMTERR) {
937 		asd_printk("ASI SEEPROM format error for %s\n",
938 			   pci_name(asd_ha->pcidev));
939 	} else if (stat0r & ASISEECHKERR) {
940 		u32 stat1r = asd_read_reg_dword(asd_ha, ASISTAT1R);
941 		asd_printk("ASI SEEPROM checksum 0x%x error for %s\n",
942 			   stat1r & CHECKSUM_MASK,
943 			   pci_name(asd_ha->pcidev));
944 	} else {
945 		u32 statr = asd_read_reg_dword(asd_ha, ASIERRSTATR);
946 
947 		if (!(statr & CPI2ASIMSTERR_MASK)) {
948 			ASD_DPRINTK("hmm, ASIERR?\n");
949 			return;
950 		} else {
951 			u32 addr = asd_read_reg_dword(asd_ha, ASIERRADDR);
952 			u32 data = asd_read_reg_dword(asd_ha, ASIERRDATAR);
953 
954 			asd_printk("%s: CPI2 xfer err: addr: 0x%x, wdata: 0x%x, "
955 				   "count: 0x%x, byteen: 0x%x, targerr: 0x%x "
956 				   "master id: 0x%x, master err: 0x%x\n",
957 				   pci_name(asd_ha->pcidev),
958 				   addr, data,
959 				   (statr & CPI2ASIBYTECNT_MASK) >> 16,
960 				   (statr & CPI2ASIBYTEEN_MASK) >> 12,
961 				   (statr & CPI2ASITARGERR_MASK) >> 8,
962 				   (statr & CPI2ASITARGMID_MASK) >> 4,
963 				   (statr & CPI2ASIMSTERR_MASK));
964 		}
965 	}
966 	asd_chip_reset(asd_ha);
967 }
968 
969 /**
970  * asd_hst_pcix_isr -- process host interface interrupts
971  * @asd_ha: pointer to host adapter structure
972  *
973  * Asserted on PCIX errors: target abort, etc.
974  */
975 static void asd_hst_pcix_isr(struct asd_ha_struct *asd_ha)
976 {
977 	u16 status;
978 	u32 pcix_status;
979 	u32 ecc_status;
980 
981 	pci_read_config_word(asd_ha->pcidev, PCI_STATUS, &status);
982 	pci_read_config_dword(asd_ha->pcidev, PCIX_STATUS, &pcix_status);
983 	pci_read_config_dword(asd_ha->pcidev, ECC_CTRL_STAT, &ecc_status);
984 
985 	if (status & PCI_STATUS_DETECTED_PARITY)
986 		asd_printk("parity error for %s\n", pci_name(asd_ha->pcidev));
987 	else if (status & PCI_STATUS_REC_MASTER_ABORT)
988 		asd_printk("master abort for %s\n", pci_name(asd_ha->pcidev));
989 	else if (status & PCI_STATUS_REC_TARGET_ABORT)
990 		asd_printk("target abort for %s\n", pci_name(asd_ha->pcidev));
991 	else if (status & PCI_STATUS_PARITY)
992 		asd_printk("data parity for %s\n", pci_name(asd_ha->pcidev));
993 	else if (pcix_status & RCV_SCE) {
994 		asd_printk("received split completion error for %s\n",
995 			   pci_name(asd_ha->pcidev));
996 		pci_write_config_dword(asd_ha->pcidev,PCIX_STATUS,pcix_status);
997 		/* XXX: Abort task? */
998 		return;
999 	} else if (pcix_status & UNEXP_SC) {
1000 		asd_printk("unexpected split completion for %s\n",
1001 			   pci_name(asd_ha->pcidev));
1002 		pci_write_config_dword(asd_ha->pcidev,PCIX_STATUS,pcix_status);
1003 		/* ignore */
1004 		return;
1005 	} else if (pcix_status & SC_DISCARD)
1006 		asd_printk("split completion discarded for %s\n",
1007 			   pci_name(asd_ha->pcidev));
1008 	else if (ecc_status & UNCOR_ECCERR)
1009 		asd_printk("uncorrectable ECC error for %s\n",
1010 			   pci_name(asd_ha->pcidev));
1011 	asd_chip_reset(asd_ha);
1012 }
1013 
1014 /**
1015  * asd_hw_isr -- host adapter interrupt service routine
1016  * @irq: ignored
1017  * @dev_id: pointer to host adapter structure
1018  *
1019  * The ISR processes done list entries and level 3 error handling.
1020  */
1021 irqreturn_t asd_hw_isr(int irq, void *dev_id)
1022 {
1023 	struct asd_ha_struct *asd_ha = dev_id;
1024 	u32 chimint = asd_read_reg_dword(asd_ha, CHIMINT);
1025 
1026 	if (!chimint)
1027 		return IRQ_NONE;
1028 
1029 	asd_write_reg_dword(asd_ha, CHIMINT, chimint);
1030 	(void) asd_read_reg_dword(asd_ha, CHIMINT);
1031 
1032 	if (chimint & DLAVAIL)
1033 		asd_process_donelist_isr(asd_ha);
1034 	if (chimint & COMINT)
1035 		asd_com_sas_isr(asd_ha);
1036 	if (chimint & DEVINT)
1037 		asd_dch_sas_isr(asd_ha);
1038 	if (chimint & INITERR)
1039 		asd_rbi_exsi_isr(asd_ha);
1040 	if (chimint & HOSTERR)
1041 		asd_hst_pcix_isr(asd_ha);
1042 
1043 	return IRQ_HANDLED;
1044 }
1045 
1046 /* ---------- SCB handling ---------- */
1047 
1048 static struct asd_ascb *asd_ascb_alloc(struct asd_ha_struct *asd_ha,
1049 				       gfp_t gfp_flags)
1050 {
1051 	extern struct kmem_cache *asd_ascb_cache;
1052 	struct asd_seq_data *seq = &asd_ha->seq;
1053 	struct asd_ascb *ascb;
1054 	unsigned long flags;
1055 
1056 	ascb = kmem_cache_zalloc(asd_ascb_cache, gfp_flags);
1057 
1058 	if (ascb) {
1059 		ascb->dma_scb.size = sizeof(struct scb);
1060 		ascb->dma_scb.vaddr = dma_pool_zalloc(asd_ha->scb_pool,
1061 						     gfp_flags,
1062 						    &ascb->dma_scb.dma_handle);
1063 		if (!ascb->dma_scb.vaddr) {
1064 			kmem_cache_free(asd_ascb_cache, ascb);
1065 			return NULL;
1066 		}
1067 		asd_init_ascb(asd_ha, ascb);
1068 
1069 		spin_lock_irqsave(&seq->tc_index_lock, flags);
1070 		ascb->tc_index = asd_tc_index_get(seq, ascb);
1071 		spin_unlock_irqrestore(&seq->tc_index_lock, flags);
1072 		if (ascb->tc_index == -1)
1073 			goto undo;
1074 
1075 		ascb->scb->header.index = cpu_to_le16((u16)ascb->tc_index);
1076 	}
1077 
1078 	return ascb;
1079 undo:
1080 	dma_pool_free(asd_ha->scb_pool, ascb->dma_scb.vaddr,
1081 		      ascb->dma_scb.dma_handle);
1082 	kmem_cache_free(asd_ascb_cache, ascb);
1083 	ASD_DPRINTK("no index for ascb\n");
1084 	return NULL;
1085 }
1086 
1087 /**
1088  * asd_ascb_alloc_list -- allocate a list of aSCBs
1089  * @asd_ha: pointer to host adapter structure
1090  * @num: pointer to integer number of aSCBs
1091  * @gfp_flags: GFP_ flags.
1092  *
1093  * This is the only function which is used to allocate aSCBs.
1094  * It can allocate one or many. If more than one, then they form
1095  * a linked list in two ways: by their list field of the ascb struct
1096  * and by the next_scb field of the scb_header.
1097  *
1098  * Returns NULL if no memory was available, else pointer to a list
1099  * of ascbs.  When this function returns, @num would be the number
1100  * of SCBs which were not able to be allocated, 0 if all requested
1101  * were able to be allocated.
1102  */
1103 struct asd_ascb *asd_ascb_alloc_list(struct asd_ha_struct
1104 				     *asd_ha, int *num,
1105 				     gfp_t gfp_flags)
1106 {
1107 	struct asd_ascb *first = NULL;
1108 
1109 	for ( ; *num > 0; --*num) {
1110 		struct asd_ascb *ascb = asd_ascb_alloc(asd_ha, gfp_flags);
1111 
1112 		if (!ascb)
1113 			break;
1114 		else if (!first)
1115 			first = ascb;
1116 		else {
1117 			struct asd_ascb *last = list_entry(first->list.prev,
1118 							   struct asd_ascb,
1119 							   list);
1120 			list_add_tail(&ascb->list, &first->list);
1121 			last->scb->header.next_scb =
1122 				cpu_to_le64(((u64)ascb->dma_scb.dma_handle));
1123 		}
1124 	}
1125 
1126 	return first;
1127 }
1128 
1129 /**
1130  * asd_swap_head_scb -- swap the head scb
1131  * @asd_ha: pointer to host adapter structure
1132  * @ascb: pointer to the head of an ascb list
1133  *
1134  * The sequencer knows the DMA address of the next SCB to be DMAed to
1135  * the host adapter, from initialization or from the last list DMAed.
1136  * seq->next_scb keeps the address of this SCB.  The sequencer will
1137  * DMA to the host adapter this list of SCBs.  But the head (first
1138  * element) of this list is not known to the sequencer.  Here we swap
1139  * the head of the list with the known SCB (memcpy()).
1140  * Only one memcpy() is required per list so it is in our interest
1141  * to keep the list of SCB as long as possible so that the ratio
1142  * of number of memcpy calls to the number of SCB DMA-ed is as small
1143  * as possible.
1144  *
1145  * LOCKING: called with the pending list lock held.
1146  */
1147 static void asd_swap_head_scb(struct asd_ha_struct *asd_ha,
1148 			      struct asd_ascb *ascb)
1149 {
1150 	struct asd_seq_data *seq = &asd_ha->seq;
1151 	struct asd_ascb *last = list_entry(ascb->list.prev,
1152 					   struct asd_ascb,
1153 					   list);
1154 	struct asd_dma_tok t = ascb->dma_scb;
1155 
1156 	memcpy(seq->next_scb.vaddr, ascb->scb, sizeof(*ascb->scb));
1157 	ascb->dma_scb = seq->next_scb;
1158 	ascb->scb = ascb->dma_scb.vaddr;
1159 	seq->next_scb = t;
1160 	last->scb->header.next_scb =
1161 		cpu_to_le64(((u64)seq->next_scb.dma_handle));
1162 }
1163 
1164 /**
1165  * asd_start_timers -- (add and) start timers of SCBs
1166  * @list: pointer to struct list_head of the scbs
1167  * @to: timeout in jiffies
1168  *
1169  * If an SCB in the @list has no timer function, assign the default
1170  * one,  then start the timer of the SCB.  This function is
1171  * intended to be called from asd_post_ascb_list(), just prior to
1172  * posting the SCBs to the sequencer.
1173  */
1174 static void asd_start_scb_timers(struct list_head *list)
1175 {
1176 	struct asd_ascb *ascb;
1177 	list_for_each_entry(ascb, list, list) {
1178 		if (!ascb->uldd_timer) {
1179 			ascb->timer.function = asd_ascb_timedout;
1180 			ascb->timer.expires = jiffies + AIC94XX_SCB_TIMEOUT;
1181 			add_timer(&ascb->timer);
1182 		}
1183 	}
1184 }
1185 
1186 /**
1187  * asd_post_ascb_list -- post a list of 1 or more aSCBs to the host adapter
1188  * @asd_ha: pointer to a host adapter structure
1189  * @ascb: pointer to the first aSCB in the list
1190  * @num: number of aSCBs in the list (to be posted)
1191  *
1192  * See queueing comment in asd_post_escb_list().
1193  *
1194  * Additional note on queuing: In order to minimize the ratio of memcpy()
1195  * to the number of ascbs sent, we try to batch-send as many ascbs as possible
1196  * in one go.
1197  * Two cases are possible:
1198  *    A) can_queue >= num,
1199  *    B) can_queue < num.
1200  * Case A: we can send the whole batch at once.  Increment "pending"
1201  * in the beginning of this function, when it is checked, in order to
1202  * eliminate races when this function is called by multiple processes.
1203  * Case B: should never happen.
1204  */
1205 int asd_post_ascb_list(struct asd_ha_struct *asd_ha, struct asd_ascb *ascb,
1206 		       int num)
1207 {
1208 	unsigned long flags;
1209 	LIST_HEAD(list);
1210 	int can_queue;
1211 
1212 	spin_lock_irqsave(&asd_ha->seq.pend_q_lock, flags);
1213 	can_queue = asd_ha->hw_prof.max_scbs - asd_ha->seq.pending;
1214 	if (can_queue >= num)
1215 		asd_ha->seq.pending += num;
1216 	else
1217 		can_queue = 0;
1218 
1219 	if (!can_queue) {
1220 		spin_unlock_irqrestore(&asd_ha->seq.pend_q_lock, flags);
1221 		asd_printk("%s: scb queue full\n", pci_name(asd_ha->pcidev));
1222 		return -SAS_QUEUE_FULL;
1223 	}
1224 
1225 	asd_swap_head_scb(asd_ha, ascb);
1226 
1227 	__list_add(&list, ascb->list.prev, &ascb->list);
1228 
1229 	asd_start_scb_timers(&list);
1230 
1231 	asd_ha->seq.scbpro += num;
1232 	list_splice_init(&list, asd_ha->seq.pend_q.prev);
1233 	asd_write_reg_dword(asd_ha, SCBPRO, (u32)asd_ha->seq.scbpro);
1234 	spin_unlock_irqrestore(&asd_ha->seq.pend_q_lock, flags);
1235 
1236 	return 0;
1237 }
1238 
1239 /**
1240  * asd_post_escb_list -- post a list of 1 or more empty scb
1241  * @asd_ha: pointer to a host adapter structure
1242  * @ascb: pointer to the first empty SCB in the list
1243  * @num: number of aSCBs in the list (to be posted)
1244  *
1245  * This is essentially the same as asd_post_ascb_list, but we do not
1246  * increment pending, add those to the pending list or get indexes.
1247  * See asd_init_escbs() and asd_init_post_escbs().
1248  *
1249  * Since sending a list of ascbs is a superset of sending a single
1250  * ascb, this function exists to generalize this.  More specifically,
1251  * when sending a list of those, we want to do only a _single_
1252  * memcpy() at swap head, as opposed to for each ascb sent (in the
1253  * case of sending them one by one).  That is, we want to minimize the
1254  * ratio of memcpy() operations to the number of ascbs sent.  The same
1255  * logic applies to asd_post_ascb_list().
1256  */
1257 int asd_post_escb_list(struct asd_ha_struct *asd_ha, struct asd_ascb *ascb,
1258 		       int num)
1259 {
1260 	unsigned long flags;
1261 
1262 	spin_lock_irqsave(&asd_ha->seq.pend_q_lock, flags);
1263 	asd_swap_head_scb(asd_ha, ascb);
1264 	asd_ha->seq.scbpro += num;
1265 	asd_write_reg_dword(asd_ha, SCBPRO, (u32)asd_ha->seq.scbpro);
1266 	spin_unlock_irqrestore(&asd_ha->seq.pend_q_lock, flags);
1267 
1268 	return 0;
1269 }
1270 
1271 /* ---------- LED ---------- */
1272 
1273 /**
1274  * asd_turn_led -- turn on/off an LED
1275  * @asd_ha: pointer to host adapter structure
1276  * @phy_id: the PHY id whose LED we want to manupulate
1277  * @op: 1 to turn on, 0 to turn off
1278  */
1279 void asd_turn_led(struct asd_ha_struct *asd_ha, int phy_id, int op)
1280 {
1281 	if (phy_id < ASD_MAX_PHYS) {
1282 		u32 v = asd_read_reg_dword(asd_ha, LmCONTROL(phy_id));
1283 		if (op)
1284 			v |= LEDPOL;
1285 		else
1286 			v &= ~LEDPOL;
1287 		asd_write_reg_dword(asd_ha, LmCONTROL(phy_id), v);
1288 	}
1289 }
1290 
1291 /**
1292  * asd_control_led -- enable/disable an LED on the board
1293  * @asd_ha: pointer to host adapter structure
1294  * @phy_id: integer, the phy id
1295  * @op: integer, 1 to enable, 0 to disable the LED
1296  *
1297  * First we output enable the LED, then we set the source
1298  * to be an external module.
1299  */
1300 void asd_control_led(struct asd_ha_struct *asd_ha, int phy_id, int op)
1301 {
1302 	if (phy_id < ASD_MAX_PHYS) {
1303 		u32 v;
1304 
1305 		v = asd_read_reg_dword(asd_ha, GPIOOER);
1306 		if (op)
1307 			v |= (1 << phy_id);
1308 		else
1309 			v &= ~(1 << phy_id);
1310 		asd_write_reg_dword(asd_ha, GPIOOER, v);
1311 
1312 		v = asd_read_reg_dword(asd_ha, GPIOCNFGR);
1313 		if (op)
1314 			v |= (1 << phy_id);
1315 		else
1316 			v &= ~(1 << phy_id);
1317 		asd_write_reg_dword(asd_ha, GPIOCNFGR, v);
1318 	}
1319 }
1320 
1321 /* ---------- PHY enable ---------- */
1322 
1323 static int asd_enable_phy(struct asd_ha_struct *asd_ha, int phy_id)
1324 {
1325 	struct asd_phy *phy = &asd_ha->phys[phy_id];
1326 
1327 	asd_write_reg_byte(asd_ha, LmSEQ_OOB_REG(phy_id, INT_ENABLE_2), 0);
1328 	asd_write_reg_byte(asd_ha, LmSEQ_OOB_REG(phy_id, HOT_PLUG_DELAY),
1329 			   HOTPLUG_DELAY_TIMEOUT);
1330 
1331 	/* Get defaults from manuf. sector */
1332 	/* XXX we need defaults for those in case MS is broken. */
1333 	asd_write_reg_byte(asd_ha, LmSEQ_OOB_REG(phy_id, PHY_CONTROL_0),
1334 			   phy->phy_desc->phy_control_0);
1335 	asd_write_reg_byte(asd_ha, LmSEQ_OOB_REG(phy_id, PHY_CONTROL_1),
1336 			   phy->phy_desc->phy_control_1);
1337 	asd_write_reg_byte(asd_ha, LmSEQ_OOB_REG(phy_id, PHY_CONTROL_2),
1338 			   phy->phy_desc->phy_control_2);
1339 	asd_write_reg_byte(asd_ha, LmSEQ_OOB_REG(phy_id, PHY_CONTROL_3),
1340 			   phy->phy_desc->phy_control_3);
1341 
1342 	asd_write_reg_dword(asd_ha, LmSEQ_TEN_MS_COMINIT_TIMEOUT(phy_id),
1343 			    ASD_COMINIT_TIMEOUT);
1344 
1345 	asd_write_reg_addr(asd_ha, LmSEQ_TX_ID_ADDR_FRAME(phy_id),
1346 			   phy->id_frm_tok->dma_handle);
1347 
1348 	asd_control_led(asd_ha, phy_id, 1);
1349 
1350 	return 0;
1351 }
1352 
1353 int asd_enable_phys(struct asd_ha_struct *asd_ha, const u8 phy_mask)
1354 {
1355 	u8  phy_m;
1356 	u8  i;
1357 	int num = 0, k;
1358 	struct asd_ascb *ascb;
1359 	struct asd_ascb *ascb_list;
1360 
1361 	if (!phy_mask) {
1362 		asd_printk("%s called with phy_mask of 0!?\n", __func__);
1363 		return 0;
1364 	}
1365 
1366 	for_each_phy(phy_mask, phy_m, i) {
1367 		num++;
1368 		asd_enable_phy(asd_ha, i);
1369 	}
1370 
1371 	k = num;
1372 	ascb_list = asd_ascb_alloc_list(asd_ha, &k, GFP_KERNEL);
1373 	if (!ascb_list) {
1374 		asd_printk("no memory for control phy ascb list\n");
1375 		return -ENOMEM;
1376 	}
1377 	num -= k;
1378 
1379 	ascb = ascb_list;
1380 	for_each_phy(phy_mask, phy_m, i) {
1381 		asd_build_control_phy(ascb, i, ENABLE_PHY);
1382 		ascb = list_entry(ascb->list.next, struct asd_ascb, list);
1383 	}
1384 	ASD_DPRINTK("posting %d control phy scbs\n", num);
1385 	k = asd_post_ascb_list(asd_ha, ascb_list, num);
1386 	if (k)
1387 		asd_ascb_free_list(ascb_list);
1388 
1389 	return k;
1390 }
1391