1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Aic94xx SAS/SATA driver hardware interface. 4 * 5 * Copyright (C) 2005 Adaptec, Inc. All rights reserved. 6 * Copyright (C) 2005 Luben Tuikov <luben_tuikov@adaptec.com> 7 */ 8 9 #include <linux/pci.h> 10 #include <linux/slab.h> 11 #include <linux/delay.h> 12 #include <linux/module.h> 13 #include <linux/firmware.h> 14 15 #include "aic94xx.h" 16 #include "aic94xx_reg.h" 17 #include "aic94xx_hwi.h" 18 #include "aic94xx_seq.h" 19 #include "aic94xx_dump.h" 20 21 u32 MBAR0_SWB_SIZE; 22 23 /* ---------- Initialization ---------- */ 24 25 static int asd_get_user_sas_addr(struct asd_ha_struct *asd_ha) 26 { 27 /* adapter came with a sas address */ 28 if (asd_ha->hw_prof.sas_addr[0]) 29 return 0; 30 31 return sas_request_addr(asd_ha->sas_ha.core.shost, 32 asd_ha->hw_prof.sas_addr); 33 } 34 35 static void asd_propagate_sas_addr(struct asd_ha_struct *asd_ha) 36 { 37 int i; 38 39 for (i = 0; i < ASD_MAX_PHYS; i++) { 40 if (asd_ha->hw_prof.phy_desc[i].sas_addr[0] == 0) 41 continue; 42 /* Set a phy's address only if it has none. 43 */ 44 ASD_DPRINTK("setting phy%d addr to %llx\n", i, 45 SAS_ADDR(asd_ha->hw_prof.sas_addr)); 46 memcpy(asd_ha->hw_prof.phy_desc[i].sas_addr, 47 asd_ha->hw_prof.sas_addr, SAS_ADDR_SIZE); 48 } 49 } 50 51 /* ---------- PHY initialization ---------- */ 52 53 static void asd_init_phy_identify(struct asd_phy *phy) 54 { 55 phy->identify_frame = phy->id_frm_tok->vaddr; 56 57 memset(phy->identify_frame, 0, sizeof(*phy->identify_frame)); 58 59 phy->identify_frame->dev_type = SAS_END_DEVICE; 60 if (phy->sas_phy.role & PHY_ROLE_INITIATOR) 61 phy->identify_frame->initiator_bits = phy->sas_phy.iproto; 62 if (phy->sas_phy.role & PHY_ROLE_TARGET) 63 phy->identify_frame->target_bits = phy->sas_phy.tproto; 64 memcpy(phy->identify_frame->sas_addr, phy->phy_desc->sas_addr, 65 SAS_ADDR_SIZE); 66 phy->identify_frame->phy_id = phy->sas_phy.id; 67 } 68 69 static int asd_init_phy(struct asd_phy *phy) 70 { 71 struct asd_ha_struct *asd_ha = phy->sas_phy.ha->lldd_ha; 72 struct asd_sas_phy *sas_phy = &phy->sas_phy; 73 74 sas_phy->enabled = 1; 75 sas_phy->class = SAS; 76 sas_phy->iproto = SAS_PROTOCOL_ALL; 77 sas_phy->tproto = 0; 78 sas_phy->type = PHY_TYPE_PHYSICAL; 79 sas_phy->role = PHY_ROLE_INITIATOR; 80 sas_phy->oob_mode = OOB_NOT_CONNECTED; 81 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN; 82 83 phy->id_frm_tok = asd_alloc_coherent(asd_ha, 84 sizeof(*phy->identify_frame), 85 GFP_KERNEL); 86 if (!phy->id_frm_tok) { 87 asd_printk("no mem for IDENTIFY for phy%d\n", sas_phy->id); 88 return -ENOMEM; 89 } else 90 asd_init_phy_identify(phy); 91 92 memset(phy->frame_rcvd, 0, sizeof(phy->frame_rcvd)); 93 94 return 0; 95 } 96 97 static void asd_init_ports(struct asd_ha_struct *asd_ha) 98 { 99 int i; 100 101 spin_lock_init(&asd_ha->asd_ports_lock); 102 for (i = 0; i < ASD_MAX_PHYS; i++) { 103 struct asd_port *asd_port = &asd_ha->asd_ports[i]; 104 105 memset(asd_port->sas_addr, 0, SAS_ADDR_SIZE); 106 memset(asd_port->attached_sas_addr, 0, SAS_ADDR_SIZE); 107 asd_port->phy_mask = 0; 108 asd_port->num_phys = 0; 109 } 110 } 111 112 static int asd_init_phys(struct asd_ha_struct *asd_ha) 113 { 114 u8 i; 115 u8 phy_mask = asd_ha->hw_prof.enabled_phys; 116 117 for (i = 0; i < ASD_MAX_PHYS; i++) { 118 struct asd_phy *phy = &asd_ha->phys[i]; 119 120 phy->phy_desc = &asd_ha->hw_prof.phy_desc[i]; 121 phy->asd_port = NULL; 122 123 phy->sas_phy.enabled = 0; 124 phy->sas_phy.id = i; 125 phy->sas_phy.sas_addr = &phy->phy_desc->sas_addr[0]; 126 phy->sas_phy.frame_rcvd = &phy->frame_rcvd[0]; 127 phy->sas_phy.ha = &asd_ha->sas_ha; 128 phy->sas_phy.lldd_phy = phy; 129 } 130 131 /* Now enable and initialize only the enabled phys. */ 132 for_each_phy(phy_mask, phy_mask, i) { 133 int err = asd_init_phy(&asd_ha->phys[i]); 134 if (err) 135 return err; 136 } 137 138 return 0; 139 } 140 141 /* ---------- Sliding windows ---------- */ 142 143 static int asd_init_sw(struct asd_ha_struct *asd_ha) 144 { 145 struct pci_dev *pcidev = asd_ha->pcidev; 146 int err; 147 u32 v; 148 149 /* Unlock MBARs */ 150 err = pci_read_config_dword(pcidev, PCI_CONF_MBAR_KEY, &v); 151 if (err) { 152 asd_printk("couldn't access conf. space of %s\n", 153 pci_name(pcidev)); 154 goto Err; 155 } 156 if (v) 157 err = pci_write_config_dword(pcidev, PCI_CONF_MBAR_KEY, v); 158 if (err) { 159 asd_printk("couldn't write to MBAR_KEY of %s\n", 160 pci_name(pcidev)); 161 goto Err; 162 } 163 164 /* Set sliding windows A, B and C to point to proper internal 165 * memory regions. 166 */ 167 pci_write_config_dword(pcidev, PCI_CONF_MBAR0_SWA, REG_BASE_ADDR); 168 pci_write_config_dword(pcidev, PCI_CONF_MBAR0_SWB, 169 REG_BASE_ADDR_CSEQCIO); 170 pci_write_config_dword(pcidev, PCI_CONF_MBAR0_SWC, REG_BASE_ADDR_EXSI); 171 asd_ha->io_handle[0].swa_base = REG_BASE_ADDR; 172 asd_ha->io_handle[0].swb_base = REG_BASE_ADDR_CSEQCIO; 173 asd_ha->io_handle[0].swc_base = REG_BASE_ADDR_EXSI; 174 MBAR0_SWB_SIZE = asd_ha->io_handle[0].len - 0x80; 175 if (!asd_ha->iospace) { 176 /* MBAR1 will point to OCM (On Chip Memory) */ 177 pci_write_config_dword(pcidev, PCI_CONF_MBAR1, OCM_BASE_ADDR); 178 asd_ha->io_handle[1].swa_base = OCM_BASE_ADDR; 179 } 180 spin_lock_init(&asd_ha->iolock); 181 Err: 182 return err; 183 } 184 185 /* ---------- SCB initialization ---------- */ 186 187 /** 188 * asd_init_scbs - manually allocate the first SCB. 189 * @asd_ha: pointer to host adapter structure 190 * 191 * This allocates the very first SCB which would be sent to the 192 * sequencer for execution. Its bus address is written to 193 * CSEQ_Q_NEW_POINTER, mode page 2, mode 8. Since the bus address of 194 * the _next_ scb to be DMA-ed to the host adapter is read from the last 195 * SCB DMA-ed to the host adapter, we have to always stay one step 196 * ahead of the sequencer and keep one SCB already allocated. 197 */ 198 static int asd_init_scbs(struct asd_ha_struct *asd_ha) 199 { 200 struct asd_seq_data *seq = &asd_ha->seq; 201 int bitmap_bytes; 202 203 /* allocate the index array and bitmap */ 204 asd_ha->seq.tc_index_bitmap_bits = asd_ha->hw_prof.max_scbs; 205 asd_ha->seq.tc_index_array = kcalloc(asd_ha->seq.tc_index_bitmap_bits, 206 sizeof(void *), 207 GFP_KERNEL); 208 if (!asd_ha->seq.tc_index_array) 209 return -ENOMEM; 210 211 bitmap_bytes = (asd_ha->seq.tc_index_bitmap_bits+7)/8; 212 bitmap_bytes = BITS_TO_LONGS(bitmap_bytes*8)*sizeof(unsigned long); 213 asd_ha->seq.tc_index_bitmap = kzalloc(bitmap_bytes, GFP_KERNEL); 214 if (!asd_ha->seq.tc_index_bitmap) { 215 kfree(asd_ha->seq.tc_index_array); 216 asd_ha->seq.tc_index_array = NULL; 217 return -ENOMEM; 218 } 219 220 spin_lock_init(&seq->tc_index_lock); 221 222 seq->next_scb.size = sizeof(struct scb); 223 seq->next_scb.vaddr = dma_pool_alloc(asd_ha->scb_pool, GFP_KERNEL, 224 &seq->next_scb.dma_handle); 225 if (!seq->next_scb.vaddr) { 226 kfree(asd_ha->seq.tc_index_bitmap); 227 kfree(asd_ha->seq.tc_index_array); 228 asd_ha->seq.tc_index_bitmap = NULL; 229 asd_ha->seq.tc_index_array = NULL; 230 return -ENOMEM; 231 } 232 233 seq->pending = 0; 234 spin_lock_init(&seq->pend_q_lock); 235 INIT_LIST_HEAD(&seq->pend_q); 236 237 return 0; 238 } 239 240 static void asd_get_max_scb_ddb(struct asd_ha_struct *asd_ha) 241 { 242 asd_ha->hw_prof.max_scbs = asd_get_cmdctx_size(asd_ha)/ASD_SCB_SIZE; 243 asd_ha->hw_prof.max_ddbs = asd_get_devctx_size(asd_ha)/ASD_DDB_SIZE; 244 ASD_DPRINTK("max_scbs:%d, max_ddbs:%d\n", 245 asd_ha->hw_prof.max_scbs, 246 asd_ha->hw_prof.max_ddbs); 247 } 248 249 /* ---------- Done List initialization ---------- */ 250 251 static void asd_dl_tasklet_handler(unsigned long); 252 253 static int asd_init_dl(struct asd_ha_struct *asd_ha) 254 { 255 asd_ha->seq.actual_dl 256 = asd_alloc_coherent(asd_ha, 257 ASD_DL_SIZE * sizeof(struct done_list_struct), 258 GFP_KERNEL); 259 if (!asd_ha->seq.actual_dl) 260 return -ENOMEM; 261 asd_ha->seq.dl = asd_ha->seq.actual_dl->vaddr; 262 asd_ha->seq.dl_toggle = ASD_DEF_DL_TOGGLE; 263 asd_ha->seq.dl_next = 0; 264 tasklet_init(&asd_ha->seq.dl_tasklet, asd_dl_tasklet_handler, 265 (unsigned long) asd_ha); 266 267 return 0; 268 } 269 270 /* ---------- EDB and ESCB init ---------- */ 271 272 static int asd_alloc_edbs(struct asd_ha_struct *asd_ha, gfp_t gfp_flags) 273 { 274 struct asd_seq_data *seq = &asd_ha->seq; 275 int i; 276 277 seq->edb_arr = kmalloc_array(seq->num_edbs, sizeof(*seq->edb_arr), 278 gfp_flags); 279 if (!seq->edb_arr) 280 return -ENOMEM; 281 282 for (i = 0; i < seq->num_edbs; i++) { 283 seq->edb_arr[i] = asd_alloc_coherent(asd_ha, ASD_EDB_SIZE, 284 gfp_flags); 285 if (!seq->edb_arr[i]) 286 goto Err_unroll; 287 memset(seq->edb_arr[i]->vaddr, 0, ASD_EDB_SIZE); 288 } 289 290 ASD_DPRINTK("num_edbs:%d\n", seq->num_edbs); 291 292 return 0; 293 294 Err_unroll: 295 for (i-- ; i >= 0; i--) 296 asd_free_coherent(asd_ha, seq->edb_arr[i]); 297 kfree(seq->edb_arr); 298 seq->edb_arr = NULL; 299 300 return -ENOMEM; 301 } 302 303 static int asd_alloc_escbs(struct asd_ha_struct *asd_ha, 304 gfp_t gfp_flags) 305 { 306 struct asd_seq_data *seq = &asd_ha->seq; 307 struct asd_ascb *escb; 308 int i, escbs; 309 310 seq->escb_arr = kmalloc_array(seq->num_escbs, sizeof(*seq->escb_arr), 311 gfp_flags); 312 if (!seq->escb_arr) 313 return -ENOMEM; 314 315 escbs = seq->num_escbs; 316 escb = asd_ascb_alloc_list(asd_ha, &escbs, gfp_flags); 317 if (!escb) { 318 asd_printk("couldn't allocate list of escbs\n"); 319 goto Err; 320 } 321 seq->num_escbs -= escbs; /* subtract what was not allocated */ 322 ASD_DPRINTK("num_escbs:%d\n", seq->num_escbs); 323 324 for (i = 0; i < seq->num_escbs; i++, escb = list_entry(escb->list.next, 325 struct asd_ascb, 326 list)) { 327 seq->escb_arr[i] = escb; 328 escb->scb->header.opcode = EMPTY_SCB; 329 } 330 331 return 0; 332 Err: 333 kfree(seq->escb_arr); 334 seq->escb_arr = NULL; 335 return -ENOMEM; 336 337 } 338 339 static void asd_assign_edbs2escbs(struct asd_ha_struct *asd_ha) 340 { 341 struct asd_seq_data *seq = &asd_ha->seq; 342 int i, k, z = 0; 343 344 for (i = 0; i < seq->num_escbs; i++) { 345 struct asd_ascb *ascb = seq->escb_arr[i]; 346 struct empty_scb *escb = &ascb->scb->escb; 347 348 ascb->edb_index = z; 349 350 escb->num_valid = ASD_EDBS_PER_SCB; 351 352 for (k = 0; k < ASD_EDBS_PER_SCB; k++) { 353 struct sg_el *eb = &escb->eb[k]; 354 struct asd_dma_tok *edb = seq->edb_arr[z++]; 355 356 memset(eb, 0, sizeof(*eb)); 357 eb->bus_addr = cpu_to_le64(((u64) edb->dma_handle)); 358 eb->size = cpu_to_le32(((u32) edb->size)); 359 } 360 } 361 } 362 363 /** 364 * asd_init_escbs -- allocate and initialize empty scbs 365 * @asd_ha: pointer to host adapter structure 366 * 367 * An empty SCB has sg_elements of ASD_EDBS_PER_SCB (7) buffers. 368 * They transport sense data, etc. 369 */ 370 static int asd_init_escbs(struct asd_ha_struct *asd_ha) 371 { 372 struct asd_seq_data *seq = &asd_ha->seq; 373 int err = 0; 374 375 /* Allocate two empty data buffers (edb) per sequencer. */ 376 int edbs = 2*(1+asd_ha->hw_prof.num_phys); 377 378 seq->num_escbs = (edbs+ASD_EDBS_PER_SCB-1)/ASD_EDBS_PER_SCB; 379 seq->num_edbs = seq->num_escbs * ASD_EDBS_PER_SCB; 380 381 err = asd_alloc_edbs(asd_ha, GFP_KERNEL); 382 if (err) { 383 asd_printk("couldn't allocate edbs\n"); 384 return err; 385 } 386 387 err = asd_alloc_escbs(asd_ha, GFP_KERNEL); 388 if (err) { 389 asd_printk("couldn't allocate escbs\n"); 390 return err; 391 } 392 393 asd_assign_edbs2escbs(asd_ha); 394 /* In order to insure that normal SCBs do not overfill sequencer 395 * memory and leave no space for escbs (halting condition), 396 * we increment pending here by the number of escbs. However, 397 * escbs are never pending. 398 */ 399 seq->pending = seq->num_escbs; 400 seq->can_queue = 1 + (asd_ha->hw_prof.max_scbs - seq->pending)/2; 401 402 return 0; 403 } 404 405 /* ---------- HW initialization ---------- */ 406 407 /** 408 * asd_chip_hardrst -- hard reset the chip 409 * @asd_ha: pointer to host adapter structure 410 * 411 * This takes 16 cycles and is synchronous to CFCLK, which runs 412 * at 200 MHz, so this should take at most 80 nanoseconds. 413 */ 414 int asd_chip_hardrst(struct asd_ha_struct *asd_ha) 415 { 416 int i; 417 int count = 100; 418 u32 reg; 419 420 for (i = 0 ; i < 4 ; i++) { 421 asd_write_reg_dword(asd_ha, COMBIST, HARDRST); 422 } 423 424 do { 425 udelay(1); 426 reg = asd_read_reg_dword(asd_ha, CHIMINT); 427 if (reg & HARDRSTDET) { 428 asd_write_reg_dword(asd_ha, CHIMINT, 429 HARDRSTDET|PORRSTDET); 430 return 0; 431 } 432 } while (--count > 0); 433 434 return -ENODEV; 435 } 436 437 /** 438 * asd_init_chip -- initialize the chip 439 * @asd_ha: pointer to host adapter structure 440 * 441 * Hard resets the chip, disables HA interrupts, downloads the sequnecer 442 * microcode and starts the sequencers. The caller has to explicitly 443 * enable HA interrupts with asd_enable_ints(asd_ha). 444 */ 445 static int asd_init_chip(struct asd_ha_struct *asd_ha) 446 { 447 int err; 448 449 err = asd_chip_hardrst(asd_ha); 450 if (err) { 451 asd_printk("couldn't hard reset %s\n", 452 pci_name(asd_ha->pcidev)); 453 goto out; 454 } 455 456 asd_disable_ints(asd_ha); 457 458 err = asd_init_seqs(asd_ha); 459 if (err) { 460 asd_printk("couldn't init seqs for %s\n", 461 pci_name(asd_ha->pcidev)); 462 goto out; 463 } 464 465 err = asd_start_seqs(asd_ha); 466 if (err) { 467 asd_printk("couldn't start seqs for %s\n", 468 pci_name(asd_ha->pcidev)); 469 goto out; 470 } 471 out: 472 return err; 473 } 474 475 #define MAX_DEVS ((OCM_MAX_SIZE) / (ASD_DDB_SIZE)) 476 477 static int max_devs = 0; 478 module_param_named(max_devs, max_devs, int, S_IRUGO); 479 MODULE_PARM_DESC(max_devs, "\n" 480 "\tMaximum number of SAS devices to support (not LUs).\n" 481 "\tDefault: 2176, Maximum: 65663.\n"); 482 483 static int max_cmnds = 0; 484 module_param_named(max_cmnds, max_cmnds, int, S_IRUGO); 485 MODULE_PARM_DESC(max_cmnds, "\n" 486 "\tMaximum number of commands queuable.\n" 487 "\tDefault: 512, Maximum: 66047.\n"); 488 489 static void asd_extend_devctx_ocm(struct asd_ha_struct *asd_ha) 490 { 491 unsigned long dma_addr = OCM_BASE_ADDR; 492 u32 d; 493 494 dma_addr -= asd_ha->hw_prof.max_ddbs * ASD_DDB_SIZE; 495 asd_write_reg_addr(asd_ha, DEVCTXBASE, (dma_addr_t) dma_addr); 496 d = asd_read_reg_dword(asd_ha, CTXDOMAIN); 497 d |= 4; 498 asd_write_reg_dword(asd_ha, CTXDOMAIN, d); 499 asd_ha->hw_prof.max_ddbs += MAX_DEVS; 500 } 501 502 static int asd_extend_devctx(struct asd_ha_struct *asd_ha) 503 { 504 dma_addr_t dma_handle; 505 unsigned long dma_addr; 506 u32 d; 507 int size; 508 509 asd_extend_devctx_ocm(asd_ha); 510 511 asd_ha->hw_prof.ddb_ext = NULL; 512 if (max_devs <= asd_ha->hw_prof.max_ddbs || max_devs > 0xFFFF) { 513 max_devs = asd_ha->hw_prof.max_ddbs; 514 return 0; 515 } 516 517 size = (max_devs - asd_ha->hw_prof.max_ddbs + 1) * ASD_DDB_SIZE; 518 519 asd_ha->hw_prof.ddb_ext = asd_alloc_coherent(asd_ha, size, GFP_KERNEL); 520 if (!asd_ha->hw_prof.ddb_ext) { 521 asd_printk("couldn't allocate memory for %d devices\n", 522 max_devs); 523 max_devs = asd_ha->hw_prof.max_ddbs; 524 return -ENOMEM; 525 } 526 dma_handle = asd_ha->hw_prof.ddb_ext->dma_handle; 527 dma_addr = ALIGN((unsigned long) dma_handle, ASD_DDB_SIZE); 528 dma_addr -= asd_ha->hw_prof.max_ddbs * ASD_DDB_SIZE; 529 dma_handle = (dma_addr_t) dma_addr; 530 asd_write_reg_addr(asd_ha, DEVCTXBASE, dma_handle); 531 d = asd_read_reg_dword(asd_ha, CTXDOMAIN); 532 d &= ~4; 533 asd_write_reg_dword(asd_ha, CTXDOMAIN, d); 534 535 asd_ha->hw_prof.max_ddbs = max_devs; 536 537 return 0; 538 } 539 540 static int asd_extend_cmdctx(struct asd_ha_struct *asd_ha) 541 { 542 dma_addr_t dma_handle; 543 unsigned long dma_addr; 544 u32 d; 545 int size; 546 547 asd_ha->hw_prof.scb_ext = NULL; 548 if (max_cmnds <= asd_ha->hw_prof.max_scbs || max_cmnds > 0xFFFF) { 549 max_cmnds = asd_ha->hw_prof.max_scbs; 550 return 0; 551 } 552 553 size = (max_cmnds - asd_ha->hw_prof.max_scbs + 1) * ASD_SCB_SIZE; 554 555 asd_ha->hw_prof.scb_ext = asd_alloc_coherent(asd_ha, size, GFP_KERNEL); 556 if (!asd_ha->hw_prof.scb_ext) { 557 asd_printk("couldn't allocate memory for %d commands\n", 558 max_cmnds); 559 max_cmnds = asd_ha->hw_prof.max_scbs; 560 return -ENOMEM; 561 } 562 dma_handle = asd_ha->hw_prof.scb_ext->dma_handle; 563 dma_addr = ALIGN((unsigned long) dma_handle, ASD_SCB_SIZE); 564 dma_addr -= asd_ha->hw_prof.max_scbs * ASD_SCB_SIZE; 565 dma_handle = (dma_addr_t) dma_addr; 566 asd_write_reg_addr(asd_ha, CMDCTXBASE, dma_handle); 567 d = asd_read_reg_dword(asd_ha, CTXDOMAIN); 568 d &= ~1; 569 asd_write_reg_dword(asd_ha, CTXDOMAIN, d); 570 571 asd_ha->hw_prof.max_scbs = max_cmnds; 572 573 return 0; 574 } 575 576 /** 577 * asd_init_ctxmem -- initialize context memory 578 * asd_ha: pointer to host adapter structure 579 * 580 * This function sets the maximum number of SCBs and 581 * DDBs which can be used by the sequencer. This is normally 582 * 512 and 128 respectively. If support for more SCBs or more DDBs 583 * is required then CMDCTXBASE, DEVCTXBASE and CTXDOMAIN are 584 * initialized here to extend context memory to point to host memory, 585 * thus allowing unlimited support for SCBs and DDBs -- only limited 586 * by host memory. 587 */ 588 static int asd_init_ctxmem(struct asd_ha_struct *asd_ha) 589 { 590 int bitmap_bytes; 591 592 asd_get_max_scb_ddb(asd_ha); 593 asd_extend_devctx(asd_ha); 594 asd_extend_cmdctx(asd_ha); 595 596 /* The kernel wants bitmaps to be unsigned long sized. */ 597 bitmap_bytes = (asd_ha->hw_prof.max_ddbs+7)/8; 598 bitmap_bytes = BITS_TO_LONGS(bitmap_bytes*8)*sizeof(unsigned long); 599 asd_ha->hw_prof.ddb_bitmap = kzalloc(bitmap_bytes, GFP_KERNEL); 600 if (!asd_ha->hw_prof.ddb_bitmap) 601 return -ENOMEM; 602 spin_lock_init(&asd_ha->hw_prof.ddb_lock); 603 604 return 0; 605 } 606 607 int asd_init_hw(struct asd_ha_struct *asd_ha) 608 { 609 int err; 610 u32 v; 611 612 err = asd_init_sw(asd_ha); 613 if (err) 614 return err; 615 616 err = pci_read_config_dword(asd_ha->pcidev, PCIC_HSTPCIX_CNTRL, &v); 617 if (err) { 618 asd_printk("couldn't read PCIC_HSTPCIX_CNTRL of %s\n", 619 pci_name(asd_ha->pcidev)); 620 return err; 621 } 622 err = pci_write_config_dword(asd_ha->pcidev, PCIC_HSTPCIX_CNTRL, 623 v | SC_TMR_DIS); 624 if (err) { 625 asd_printk("couldn't disable split completion timer of %s\n", 626 pci_name(asd_ha->pcidev)); 627 return err; 628 } 629 630 err = asd_read_ocm(asd_ha); 631 if (err) { 632 asd_printk("couldn't read ocm(%d)\n", err); 633 /* While suspicios, it is not an error that we 634 * couldn't read the OCM. */ 635 } 636 637 err = asd_read_flash(asd_ha); 638 if (err) { 639 asd_printk("couldn't read flash(%d)\n", err); 640 /* While suspicios, it is not an error that we 641 * couldn't read FLASH memory. 642 */ 643 } 644 645 asd_init_ctxmem(asd_ha); 646 647 if (asd_get_user_sas_addr(asd_ha)) { 648 asd_printk("No SAS Address provided for %s\n", 649 pci_name(asd_ha->pcidev)); 650 err = -ENODEV; 651 goto Out; 652 } 653 654 asd_propagate_sas_addr(asd_ha); 655 656 err = asd_init_phys(asd_ha); 657 if (err) { 658 asd_printk("couldn't initialize phys for %s\n", 659 pci_name(asd_ha->pcidev)); 660 goto Out; 661 } 662 663 asd_init_ports(asd_ha); 664 665 err = asd_init_scbs(asd_ha); 666 if (err) { 667 asd_printk("couldn't initialize scbs for %s\n", 668 pci_name(asd_ha->pcidev)); 669 goto Out; 670 } 671 672 err = asd_init_dl(asd_ha); 673 if (err) { 674 asd_printk("couldn't initialize the done list:%d\n", 675 err); 676 goto Out; 677 } 678 679 err = asd_init_escbs(asd_ha); 680 if (err) { 681 asd_printk("couldn't initialize escbs\n"); 682 goto Out; 683 } 684 685 err = asd_init_chip(asd_ha); 686 if (err) { 687 asd_printk("couldn't init the chip\n"); 688 goto Out; 689 } 690 Out: 691 return err; 692 } 693 694 /* ---------- Chip reset ---------- */ 695 696 /** 697 * asd_chip_reset -- reset the host adapter, etc 698 * @asd_ha: pointer to host adapter structure of interest 699 * 700 * Called from the ISR. Hard reset the chip. Let everything 701 * timeout. This should be no different than hot-unplugging the 702 * host adapter. Once everything times out we'll init the chip with 703 * a call to asd_init_chip() and enable interrupts with asd_enable_ints(). 704 * XXX finish. 705 */ 706 static void asd_chip_reset(struct asd_ha_struct *asd_ha) 707 { 708 ASD_DPRINTK("chip reset for %s\n", pci_name(asd_ha->pcidev)); 709 asd_chip_hardrst(asd_ha); 710 } 711 712 /* ---------- Done List Routines ---------- */ 713 714 static void asd_dl_tasklet_handler(unsigned long data) 715 { 716 struct asd_ha_struct *asd_ha = (struct asd_ha_struct *) data; 717 struct asd_seq_data *seq = &asd_ha->seq; 718 unsigned long flags; 719 720 while (1) { 721 struct done_list_struct *dl = &seq->dl[seq->dl_next]; 722 struct asd_ascb *ascb; 723 724 if ((dl->toggle & DL_TOGGLE_MASK) != seq->dl_toggle) 725 break; 726 727 /* find the aSCB */ 728 spin_lock_irqsave(&seq->tc_index_lock, flags); 729 ascb = asd_tc_index_find(seq, (int)le16_to_cpu(dl->index)); 730 spin_unlock_irqrestore(&seq->tc_index_lock, flags); 731 if (unlikely(!ascb)) { 732 ASD_DPRINTK("BUG:sequencer:dl:no ascb?!\n"); 733 goto next_1; 734 } else if (ascb->scb->header.opcode == EMPTY_SCB) { 735 goto out; 736 } else if (!ascb->uldd_timer && !del_timer(&ascb->timer)) { 737 goto next_1; 738 } 739 spin_lock_irqsave(&seq->pend_q_lock, flags); 740 list_del_init(&ascb->list); 741 seq->pending--; 742 spin_unlock_irqrestore(&seq->pend_q_lock, flags); 743 out: 744 ascb->tasklet_complete(ascb, dl); 745 746 next_1: 747 seq->dl_next = (seq->dl_next + 1) & (ASD_DL_SIZE-1); 748 if (!seq->dl_next) 749 seq->dl_toggle ^= DL_TOGGLE_MASK; 750 } 751 } 752 753 /* ---------- Interrupt Service Routines ---------- */ 754 755 /** 756 * asd_process_donelist_isr -- schedule processing of done list entries 757 * @asd_ha: pointer to host adapter structure 758 */ 759 static void asd_process_donelist_isr(struct asd_ha_struct *asd_ha) 760 { 761 tasklet_schedule(&asd_ha->seq.dl_tasklet); 762 } 763 764 /** 765 * asd_com_sas_isr -- process device communication interrupt (COMINT) 766 * @asd_ha: pointer to host adapter structure 767 */ 768 static void asd_com_sas_isr(struct asd_ha_struct *asd_ha) 769 { 770 u32 comstat = asd_read_reg_dword(asd_ha, COMSTAT); 771 772 /* clear COMSTAT int */ 773 asd_write_reg_dword(asd_ha, COMSTAT, 0xFFFFFFFF); 774 775 if (comstat & CSBUFPERR) { 776 asd_printk("%s: command/status buffer dma parity error\n", 777 pci_name(asd_ha->pcidev)); 778 } else if (comstat & CSERR) { 779 int i; 780 u32 dmaerr = asd_read_reg_dword(asd_ha, DMAERR); 781 dmaerr &= 0xFF; 782 asd_printk("%s: command/status dma error, DMAERR: 0x%02x, " 783 "CSDMAADR: 0x%04x, CSDMAADR+4: 0x%04x\n", 784 pci_name(asd_ha->pcidev), 785 dmaerr, 786 asd_read_reg_dword(asd_ha, CSDMAADR), 787 asd_read_reg_dword(asd_ha, CSDMAADR+4)); 788 asd_printk("CSBUFFER:\n"); 789 for (i = 0; i < 8; i++) { 790 asd_printk("%08x %08x %08x %08x\n", 791 asd_read_reg_dword(asd_ha, CSBUFFER), 792 asd_read_reg_dword(asd_ha, CSBUFFER+4), 793 asd_read_reg_dword(asd_ha, CSBUFFER+8), 794 asd_read_reg_dword(asd_ha, CSBUFFER+12)); 795 } 796 asd_dump_seq_state(asd_ha, 0); 797 } else if (comstat & OVLYERR) { 798 u32 dmaerr = asd_read_reg_dword(asd_ha, DMAERR); 799 dmaerr = (dmaerr >> 8) & 0xFF; 800 asd_printk("%s: overlay dma error:0x%x\n", 801 pci_name(asd_ha->pcidev), 802 dmaerr); 803 } 804 asd_chip_reset(asd_ha); 805 } 806 807 static void asd_arp2_err(struct asd_ha_struct *asd_ha, u32 dchstatus) 808 { 809 static const char *halt_code[256] = { 810 "UNEXPECTED_INTERRUPT0", 811 "UNEXPECTED_INTERRUPT1", 812 "UNEXPECTED_INTERRUPT2", 813 "UNEXPECTED_INTERRUPT3", 814 "UNEXPECTED_INTERRUPT4", 815 "UNEXPECTED_INTERRUPT5", 816 "UNEXPECTED_INTERRUPT6", 817 "UNEXPECTED_INTERRUPT7", 818 "UNEXPECTED_INTERRUPT8", 819 "UNEXPECTED_INTERRUPT9", 820 "UNEXPECTED_INTERRUPT10", 821 [11 ... 19] = "unknown[11,19]", 822 "NO_FREE_SCB_AVAILABLE", 823 "INVALID_SCB_OPCODE", 824 "INVALID_MBX_OPCODE", 825 "INVALID_ATA_STATE", 826 "ATA_QUEUE_FULL", 827 "ATA_TAG_TABLE_FAULT", 828 "ATA_TAG_MASK_FAULT", 829 "BAD_LINK_QUEUE_STATE", 830 "DMA2CHIM_QUEUE_ERROR", 831 "EMPTY_SCB_LIST_FULL", 832 "unknown[30]", 833 "IN_USE_SCB_ON_FREE_LIST", 834 "BAD_OPEN_WAIT_STATE", 835 "INVALID_STP_AFFILIATION", 836 "unknown[34]", 837 "EXEC_QUEUE_ERROR", 838 "TOO_MANY_EMPTIES_NEEDED", 839 "EMPTY_REQ_QUEUE_ERROR", 840 "Q_MONIRTT_MGMT_ERROR", 841 "TARGET_MODE_FLOW_ERROR", 842 "DEVICE_QUEUE_NOT_FOUND", 843 "START_IRTT_TIMER_ERROR", 844 "ABORT_TASK_ILLEGAL_REQ", 845 [43 ... 255] = "unknown[43,255]" 846 }; 847 848 if (dchstatus & CSEQINT) { 849 u32 arp2int = asd_read_reg_dword(asd_ha, CARP2INT); 850 851 if (arp2int & (ARP2WAITTO|ARP2ILLOPC|ARP2PERR|ARP2CIOPERR)) { 852 asd_printk("%s: CSEQ arp2int:0x%x\n", 853 pci_name(asd_ha->pcidev), 854 arp2int); 855 } else if (arp2int & ARP2HALTC) 856 asd_printk("%s: CSEQ halted: %s\n", 857 pci_name(asd_ha->pcidev), 858 halt_code[(arp2int>>16)&0xFF]); 859 else 860 asd_printk("%s: CARP2INT:0x%x\n", 861 pci_name(asd_ha->pcidev), 862 arp2int); 863 } 864 if (dchstatus & LSEQINT_MASK) { 865 int lseq; 866 u8 lseq_mask = dchstatus & LSEQINT_MASK; 867 868 for_each_sequencer(lseq_mask, lseq_mask, lseq) { 869 u32 arp2int = asd_read_reg_dword(asd_ha, 870 LmARP2INT(lseq)); 871 if (arp2int & (ARP2WAITTO | ARP2ILLOPC | ARP2PERR 872 | ARP2CIOPERR)) { 873 asd_printk("%s: LSEQ%d arp2int:0x%x\n", 874 pci_name(asd_ha->pcidev), 875 lseq, arp2int); 876 /* XXX we should only do lseq reset */ 877 } else if (arp2int & ARP2HALTC) 878 asd_printk("%s: LSEQ%d halted: %s\n", 879 pci_name(asd_ha->pcidev), 880 lseq,halt_code[(arp2int>>16)&0xFF]); 881 else 882 asd_printk("%s: LSEQ%d ARP2INT:0x%x\n", 883 pci_name(asd_ha->pcidev), lseq, 884 arp2int); 885 } 886 } 887 asd_chip_reset(asd_ha); 888 } 889 890 /** 891 * asd_dch_sas_isr -- process device channel interrupt (DEVINT) 892 * @asd_ha: pointer to host adapter structure 893 */ 894 static void asd_dch_sas_isr(struct asd_ha_struct *asd_ha) 895 { 896 u32 dchstatus = asd_read_reg_dword(asd_ha, DCHSTATUS); 897 898 if (dchstatus & CFIFTOERR) { 899 asd_printk("%s: CFIFTOERR\n", pci_name(asd_ha->pcidev)); 900 asd_chip_reset(asd_ha); 901 } else 902 asd_arp2_err(asd_ha, dchstatus); 903 } 904 905 /** 906 * ads_rbi_exsi_isr -- process external system interface interrupt (INITERR) 907 * @asd_ha: pointer to host adapter structure 908 */ 909 static void asd_rbi_exsi_isr(struct asd_ha_struct *asd_ha) 910 { 911 u32 stat0r = asd_read_reg_dword(asd_ha, ASISTAT0R); 912 913 if (!(stat0r & ASIERR)) { 914 asd_printk("hmm, EXSI interrupted but no error?\n"); 915 return; 916 } 917 918 if (stat0r & ASIFMTERR) { 919 asd_printk("ASI SEEPROM format error for %s\n", 920 pci_name(asd_ha->pcidev)); 921 } else if (stat0r & ASISEECHKERR) { 922 u32 stat1r = asd_read_reg_dword(asd_ha, ASISTAT1R); 923 asd_printk("ASI SEEPROM checksum 0x%x error for %s\n", 924 stat1r & CHECKSUM_MASK, 925 pci_name(asd_ha->pcidev)); 926 } else { 927 u32 statr = asd_read_reg_dword(asd_ha, ASIERRSTATR); 928 929 if (!(statr & CPI2ASIMSTERR_MASK)) { 930 ASD_DPRINTK("hmm, ASIERR?\n"); 931 return; 932 } else { 933 u32 addr = asd_read_reg_dword(asd_ha, ASIERRADDR); 934 u32 data = asd_read_reg_dword(asd_ha, ASIERRDATAR); 935 936 asd_printk("%s: CPI2 xfer err: addr: 0x%x, wdata: 0x%x, " 937 "count: 0x%x, byteen: 0x%x, targerr: 0x%x " 938 "master id: 0x%x, master err: 0x%x\n", 939 pci_name(asd_ha->pcidev), 940 addr, data, 941 (statr & CPI2ASIBYTECNT_MASK) >> 16, 942 (statr & CPI2ASIBYTEEN_MASK) >> 12, 943 (statr & CPI2ASITARGERR_MASK) >> 8, 944 (statr & CPI2ASITARGMID_MASK) >> 4, 945 (statr & CPI2ASIMSTERR_MASK)); 946 } 947 } 948 asd_chip_reset(asd_ha); 949 } 950 951 /** 952 * asd_hst_pcix_isr -- process host interface interrupts 953 * @asd_ha: pointer to host adapter structure 954 * 955 * Asserted on PCIX errors: target abort, etc. 956 */ 957 static void asd_hst_pcix_isr(struct asd_ha_struct *asd_ha) 958 { 959 u16 status; 960 u32 pcix_status; 961 u32 ecc_status; 962 963 pci_read_config_word(asd_ha->pcidev, PCI_STATUS, &status); 964 pci_read_config_dword(asd_ha->pcidev, PCIX_STATUS, &pcix_status); 965 pci_read_config_dword(asd_ha->pcidev, ECC_CTRL_STAT, &ecc_status); 966 967 if (status & PCI_STATUS_DETECTED_PARITY) 968 asd_printk("parity error for %s\n", pci_name(asd_ha->pcidev)); 969 else if (status & PCI_STATUS_REC_MASTER_ABORT) 970 asd_printk("master abort for %s\n", pci_name(asd_ha->pcidev)); 971 else if (status & PCI_STATUS_REC_TARGET_ABORT) 972 asd_printk("target abort for %s\n", pci_name(asd_ha->pcidev)); 973 else if (status & PCI_STATUS_PARITY) 974 asd_printk("data parity for %s\n", pci_name(asd_ha->pcidev)); 975 else if (pcix_status & RCV_SCE) { 976 asd_printk("received split completion error for %s\n", 977 pci_name(asd_ha->pcidev)); 978 pci_write_config_dword(asd_ha->pcidev,PCIX_STATUS,pcix_status); 979 /* XXX: Abort task? */ 980 return; 981 } else if (pcix_status & UNEXP_SC) { 982 asd_printk("unexpected split completion for %s\n", 983 pci_name(asd_ha->pcidev)); 984 pci_write_config_dword(asd_ha->pcidev,PCIX_STATUS,pcix_status); 985 /* ignore */ 986 return; 987 } else if (pcix_status & SC_DISCARD) 988 asd_printk("split completion discarded for %s\n", 989 pci_name(asd_ha->pcidev)); 990 else if (ecc_status & UNCOR_ECCERR) 991 asd_printk("uncorrectable ECC error for %s\n", 992 pci_name(asd_ha->pcidev)); 993 asd_chip_reset(asd_ha); 994 } 995 996 /** 997 * asd_hw_isr -- host adapter interrupt service routine 998 * @irq: ignored 999 * @dev_id: pointer to host adapter structure 1000 * 1001 * The ISR processes done list entries and level 3 error handling. 1002 */ 1003 irqreturn_t asd_hw_isr(int irq, void *dev_id) 1004 { 1005 struct asd_ha_struct *asd_ha = dev_id; 1006 u32 chimint = asd_read_reg_dword(asd_ha, CHIMINT); 1007 1008 if (!chimint) 1009 return IRQ_NONE; 1010 1011 asd_write_reg_dword(asd_ha, CHIMINT, chimint); 1012 (void) asd_read_reg_dword(asd_ha, CHIMINT); 1013 1014 if (chimint & DLAVAIL) 1015 asd_process_donelist_isr(asd_ha); 1016 if (chimint & COMINT) 1017 asd_com_sas_isr(asd_ha); 1018 if (chimint & DEVINT) 1019 asd_dch_sas_isr(asd_ha); 1020 if (chimint & INITERR) 1021 asd_rbi_exsi_isr(asd_ha); 1022 if (chimint & HOSTERR) 1023 asd_hst_pcix_isr(asd_ha); 1024 1025 return IRQ_HANDLED; 1026 } 1027 1028 /* ---------- SCB handling ---------- */ 1029 1030 static struct asd_ascb *asd_ascb_alloc(struct asd_ha_struct *asd_ha, 1031 gfp_t gfp_flags) 1032 { 1033 extern struct kmem_cache *asd_ascb_cache; 1034 struct asd_seq_data *seq = &asd_ha->seq; 1035 struct asd_ascb *ascb; 1036 unsigned long flags; 1037 1038 ascb = kmem_cache_zalloc(asd_ascb_cache, gfp_flags); 1039 1040 if (ascb) { 1041 ascb->dma_scb.size = sizeof(struct scb); 1042 ascb->dma_scb.vaddr = dma_pool_zalloc(asd_ha->scb_pool, 1043 gfp_flags, 1044 &ascb->dma_scb.dma_handle); 1045 if (!ascb->dma_scb.vaddr) { 1046 kmem_cache_free(asd_ascb_cache, ascb); 1047 return NULL; 1048 } 1049 asd_init_ascb(asd_ha, ascb); 1050 1051 spin_lock_irqsave(&seq->tc_index_lock, flags); 1052 ascb->tc_index = asd_tc_index_get(seq, ascb); 1053 spin_unlock_irqrestore(&seq->tc_index_lock, flags); 1054 if (ascb->tc_index == -1) 1055 goto undo; 1056 1057 ascb->scb->header.index = cpu_to_le16((u16)ascb->tc_index); 1058 } 1059 1060 return ascb; 1061 undo: 1062 dma_pool_free(asd_ha->scb_pool, ascb->dma_scb.vaddr, 1063 ascb->dma_scb.dma_handle); 1064 kmem_cache_free(asd_ascb_cache, ascb); 1065 ASD_DPRINTK("no index for ascb\n"); 1066 return NULL; 1067 } 1068 1069 /** 1070 * asd_ascb_alloc_list -- allocate a list of aSCBs 1071 * @asd_ha: pointer to host adapter structure 1072 * @num: pointer to integer number of aSCBs 1073 * @gfp_flags: GFP_ flags. 1074 * 1075 * This is the only function which is used to allocate aSCBs. 1076 * It can allocate one or many. If more than one, then they form 1077 * a linked list in two ways: by their list field of the ascb struct 1078 * and by the next_scb field of the scb_header. 1079 * 1080 * Returns NULL if no memory was available, else pointer to a list 1081 * of ascbs. When this function returns, @num would be the number 1082 * of SCBs which were not able to be allocated, 0 if all requested 1083 * were able to be allocated. 1084 */ 1085 struct asd_ascb *asd_ascb_alloc_list(struct asd_ha_struct 1086 *asd_ha, int *num, 1087 gfp_t gfp_flags) 1088 { 1089 struct asd_ascb *first = NULL; 1090 1091 for ( ; *num > 0; --*num) { 1092 struct asd_ascb *ascb = asd_ascb_alloc(asd_ha, gfp_flags); 1093 1094 if (!ascb) 1095 break; 1096 else if (!first) 1097 first = ascb; 1098 else { 1099 struct asd_ascb *last = list_entry(first->list.prev, 1100 struct asd_ascb, 1101 list); 1102 list_add_tail(&ascb->list, &first->list); 1103 last->scb->header.next_scb = 1104 cpu_to_le64(((u64)ascb->dma_scb.dma_handle)); 1105 } 1106 } 1107 1108 return first; 1109 } 1110 1111 /** 1112 * asd_swap_head_scb -- swap the head scb 1113 * @asd_ha: pointer to host adapter structure 1114 * @ascb: pointer to the head of an ascb list 1115 * 1116 * The sequencer knows the DMA address of the next SCB to be DMAed to 1117 * the host adapter, from initialization or from the last list DMAed. 1118 * seq->next_scb keeps the address of this SCB. The sequencer will 1119 * DMA to the host adapter this list of SCBs. But the head (first 1120 * element) of this list is not known to the sequencer. Here we swap 1121 * the head of the list with the known SCB (memcpy()). 1122 * Only one memcpy() is required per list so it is in our interest 1123 * to keep the list of SCB as long as possible so that the ratio 1124 * of number of memcpy calls to the number of SCB DMA-ed is as small 1125 * as possible. 1126 * 1127 * LOCKING: called with the pending list lock held. 1128 */ 1129 static void asd_swap_head_scb(struct asd_ha_struct *asd_ha, 1130 struct asd_ascb *ascb) 1131 { 1132 struct asd_seq_data *seq = &asd_ha->seq; 1133 struct asd_ascb *last = list_entry(ascb->list.prev, 1134 struct asd_ascb, 1135 list); 1136 struct asd_dma_tok t = ascb->dma_scb; 1137 1138 memcpy(seq->next_scb.vaddr, ascb->scb, sizeof(*ascb->scb)); 1139 ascb->dma_scb = seq->next_scb; 1140 ascb->scb = ascb->dma_scb.vaddr; 1141 seq->next_scb = t; 1142 last->scb->header.next_scb = 1143 cpu_to_le64(((u64)seq->next_scb.dma_handle)); 1144 } 1145 1146 /** 1147 * asd_start_timers -- (add and) start timers of SCBs 1148 * @list: pointer to struct list_head of the scbs 1149 * @to: timeout in jiffies 1150 * 1151 * If an SCB in the @list has no timer function, assign the default 1152 * one, then start the timer of the SCB. This function is 1153 * intended to be called from asd_post_ascb_list(), just prior to 1154 * posting the SCBs to the sequencer. 1155 */ 1156 static void asd_start_scb_timers(struct list_head *list) 1157 { 1158 struct asd_ascb *ascb; 1159 list_for_each_entry(ascb, list, list) { 1160 if (!ascb->uldd_timer) { 1161 ascb->timer.function = asd_ascb_timedout; 1162 ascb->timer.expires = jiffies + AIC94XX_SCB_TIMEOUT; 1163 add_timer(&ascb->timer); 1164 } 1165 } 1166 } 1167 1168 /** 1169 * asd_post_ascb_list -- post a list of 1 or more aSCBs to the host adapter 1170 * @asd_ha: pointer to a host adapter structure 1171 * @ascb: pointer to the first aSCB in the list 1172 * @num: number of aSCBs in the list (to be posted) 1173 * 1174 * See queueing comment in asd_post_escb_list(). 1175 * 1176 * Additional note on queuing: In order to minimize the ratio of memcpy() 1177 * to the number of ascbs sent, we try to batch-send as many ascbs as possible 1178 * in one go. 1179 * Two cases are possible: 1180 * A) can_queue >= num, 1181 * B) can_queue < num. 1182 * Case A: we can send the whole batch at once. Increment "pending" 1183 * in the beginning of this function, when it is checked, in order to 1184 * eliminate races when this function is called by multiple processes. 1185 * Case B: should never happen. 1186 */ 1187 int asd_post_ascb_list(struct asd_ha_struct *asd_ha, struct asd_ascb *ascb, 1188 int num) 1189 { 1190 unsigned long flags; 1191 LIST_HEAD(list); 1192 int can_queue; 1193 1194 spin_lock_irqsave(&asd_ha->seq.pend_q_lock, flags); 1195 can_queue = asd_ha->hw_prof.max_scbs - asd_ha->seq.pending; 1196 if (can_queue >= num) 1197 asd_ha->seq.pending += num; 1198 else 1199 can_queue = 0; 1200 1201 if (!can_queue) { 1202 spin_unlock_irqrestore(&asd_ha->seq.pend_q_lock, flags); 1203 asd_printk("%s: scb queue full\n", pci_name(asd_ha->pcidev)); 1204 return -SAS_QUEUE_FULL; 1205 } 1206 1207 asd_swap_head_scb(asd_ha, ascb); 1208 1209 __list_add(&list, ascb->list.prev, &ascb->list); 1210 1211 asd_start_scb_timers(&list); 1212 1213 asd_ha->seq.scbpro += num; 1214 list_splice_init(&list, asd_ha->seq.pend_q.prev); 1215 asd_write_reg_dword(asd_ha, SCBPRO, (u32)asd_ha->seq.scbpro); 1216 spin_unlock_irqrestore(&asd_ha->seq.pend_q_lock, flags); 1217 1218 return 0; 1219 } 1220 1221 /** 1222 * asd_post_escb_list -- post a list of 1 or more empty scb 1223 * @asd_ha: pointer to a host adapter structure 1224 * @ascb: pointer to the first empty SCB in the list 1225 * @num: number of aSCBs in the list (to be posted) 1226 * 1227 * This is essentially the same as asd_post_ascb_list, but we do not 1228 * increment pending, add those to the pending list or get indexes. 1229 * See asd_init_escbs() and asd_init_post_escbs(). 1230 * 1231 * Since sending a list of ascbs is a superset of sending a single 1232 * ascb, this function exists to generalize this. More specifically, 1233 * when sending a list of those, we want to do only a _single_ 1234 * memcpy() at swap head, as opposed to for each ascb sent (in the 1235 * case of sending them one by one). That is, we want to minimize the 1236 * ratio of memcpy() operations to the number of ascbs sent. The same 1237 * logic applies to asd_post_ascb_list(). 1238 */ 1239 int asd_post_escb_list(struct asd_ha_struct *asd_ha, struct asd_ascb *ascb, 1240 int num) 1241 { 1242 unsigned long flags; 1243 1244 spin_lock_irqsave(&asd_ha->seq.pend_q_lock, flags); 1245 asd_swap_head_scb(asd_ha, ascb); 1246 asd_ha->seq.scbpro += num; 1247 asd_write_reg_dword(asd_ha, SCBPRO, (u32)asd_ha->seq.scbpro); 1248 spin_unlock_irqrestore(&asd_ha->seq.pend_q_lock, flags); 1249 1250 return 0; 1251 } 1252 1253 /* ---------- LED ---------- */ 1254 1255 /** 1256 * asd_turn_led -- turn on/off an LED 1257 * @asd_ha: pointer to host adapter structure 1258 * @phy_id: the PHY id whose LED we want to manupulate 1259 * @op: 1 to turn on, 0 to turn off 1260 */ 1261 void asd_turn_led(struct asd_ha_struct *asd_ha, int phy_id, int op) 1262 { 1263 if (phy_id < ASD_MAX_PHYS) { 1264 u32 v = asd_read_reg_dword(asd_ha, LmCONTROL(phy_id)); 1265 if (op) 1266 v |= LEDPOL; 1267 else 1268 v &= ~LEDPOL; 1269 asd_write_reg_dword(asd_ha, LmCONTROL(phy_id), v); 1270 } 1271 } 1272 1273 /** 1274 * asd_control_led -- enable/disable an LED on the board 1275 * @asd_ha: pointer to host adapter structure 1276 * @phy_id: integer, the phy id 1277 * @op: integer, 1 to enable, 0 to disable the LED 1278 * 1279 * First we output enable the LED, then we set the source 1280 * to be an external module. 1281 */ 1282 void asd_control_led(struct asd_ha_struct *asd_ha, int phy_id, int op) 1283 { 1284 if (phy_id < ASD_MAX_PHYS) { 1285 u32 v; 1286 1287 v = asd_read_reg_dword(asd_ha, GPIOOER); 1288 if (op) 1289 v |= (1 << phy_id); 1290 else 1291 v &= ~(1 << phy_id); 1292 asd_write_reg_dword(asd_ha, GPIOOER, v); 1293 1294 v = asd_read_reg_dword(asd_ha, GPIOCNFGR); 1295 if (op) 1296 v |= (1 << phy_id); 1297 else 1298 v &= ~(1 << phy_id); 1299 asd_write_reg_dword(asd_ha, GPIOCNFGR, v); 1300 } 1301 } 1302 1303 /* ---------- PHY enable ---------- */ 1304 1305 static int asd_enable_phy(struct asd_ha_struct *asd_ha, int phy_id) 1306 { 1307 struct asd_phy *phy = &asd_ha->phys[phy_id]; 1308 1309 asd_write_reg_byte(asd_ha, LmSEQ_OOB_REG(phy_id, INT_ENABLE_2), 0); 1310 asd_write_reg_byte(asd_ha, LmSEQ_OOB_REG(phy_id, HOT_PLUG_DELAY), 1311 HOTPLUG_DELAY_TIMEOUT); 1312 1313 /* Get defaults from manuf. sector */ 1314 /* XXX we need defaults for those in case MS is broken. */ 1315 asd_write_reg_byte(asd_ha, LmSEQ_OOB_REG(phy_id, PHY_CONTROL_0), 1316 phy->phy_desc->phy_control_0); 1317 asd_write_reg_byte(asd_ha, LmSEQ_OOB_REG(phy_id, PHY_CONTROL_1), 1318 phy->phy_desc->phy_control_1); 1319 asd_write_reg_byte(asd_ha, LmSEQ_OOB_REG(phy_id, PHY_CONTROL_2), 1320 phy->phy_desc->phy_control_2); 1321 asd_write_reg_byte(asd_ha, LmSEQ_OOB_REG(phy_id, PHY_CONTROL_3), 1322 phy->phy_desc->phy_control_3); 1323 1324 asd_write_reg_dword(asd_ha, LmSEQ_TEN_MS_COMINIT_TIMEOUT(phy_id), 1325 ASD_COMINIT_TIMEOUT); 1326 1327 asd_write_reg_addr(asd_ha, LmSEQ_TX_ID_ADDR_FRAME(phy_id), 1328 phy->id_frm_tok->dma_handle); 1329 1330 asd_control_led(asd_ha, phy_id, 1); 1331 1332 return 0; 1333 } 1334 1335 int asd_enable_phys(struct asd_ha_struct *asd_ha, const u8 phy_mask) 1336 { 1337 u8 phy_m; 1338 u8 i; 1339 int num = 0, k; 1340 struct asd_ascb *ascb; 1341 struct asd_ascb *ascb_list; 1342 1343 if (!phy_mask) { 1344 asd_printk("%s called with phy_mask of 0!?\n", __func__); 1345 return 0; 1346 } 1347 1348 for_each_phy(phy_mask, phy_m, i) { 1349 num++; 1350 asd_enable_phy(asd_ha, i); 1351 } 1352 1353 k = num; 1354 ascb_list = asd_ascb_alloc_list(asd_ha, &k, GFP_KERNEL); 1355 if (!ascb_list) { 1356 asd_printk("no memory for control phy ascb list\n"); 1357 return -ENOMEM; 1358 } 1359 num -= k; 1360 1361 ascb = ascb_list; 1362 for_each_phy(phy_mask, phy_m, i) { 1363 asd_build_control_phy(ascb, i, ENABLE_PHY); 1364 ascb = list_entry(ascb->list.next, struct asd_ascb, list); 1365 } 1366 ASD_DPRINTK("posting %d control phy scbs\n", num); 1367 k = asd_post_ascb_list(asd_ha, ascb_list, num); 1368 if (k) 1369 asd_ascb_free_list(ascb_list); 1370 1371 return k; 1372 } 1373