1/*
2 * DO NOT EDIT - This file is automatically generated
3 *		 from the following source files:
4 *
5 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.seq#58 $
6 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.reg#40 $
7 */
8
9#include "aic7xxx_osm.h"
10
11static const ahc_reg_parse_entry_t SCSISEQ_parse_table[] = {
12	{ "SCSIRSTO",		0x01, 0x01 },
13	{ "ENAUTOATNP",		0x02, 0x02 },
14	{ "ENAUTOATNI",		0x04, 0x04 },
15	{ "ENAUTOATNO",		0x08, 0x08 },
16	{ "ENRSELI",		0x10, 0x10 },
17	{ "ENSELI",		0x20, 0x20 },
18	{ "ENSELO",		0x40, 0x40 },
19	{ "TEMODE",		0x80, 0x80 }
20};
21
22int
23ahc_scsiseq_print(u_int regvalue, u_int *cur_col, u_int wrap)
24{
25	return (ahc_print_register(SCSISEQ_parse_table, 8, "SCSISEQ",
26	    0x00, regvalue, cur_col, wrap));
27}
28
29static const ahc_reg_parse_entry_t SXFRCTL0_parse_table[] = {
30	{ "CLRCHN",		0x02, 0x02 },
31	{ "SCAMEN",		0x04, 0x04 },
32	{ "SPIOEN",		0x08, 0x08 },
33	{ "CLRSTCNT",		0x10, 0x10 },
34	{ "FAST20",		0x20, 0x20 },
35	{ "DFPEXP",		0x40, 0x40 },
36	{ "DFON",		0x80, 0x80 }
37};
38
39int
40ahc_sxfrctl0_print(u_int regvalue, u_int *cur_col, u_int wrap)
41{
42	return (ahc_print_register(SXFRCTL0_parse_table, 7, "SXFRCTL0",
43	    0x01, regvalue, cur_col, wrap));
44}
45
46static const ahc_reg_parse_entry_t SXFRCTL1_parse_table[] = {
47	{ "STPWEN",		0x01, 0x01 },
48	{ "ACTNEGEN",		0x02, 0x02 },
49	{ "ENSTIMER",		0x04, 0x04 },
50	{ "ENSPCHK",		0x20, 0x20 },
51	{ "SWRAPEN",		0x40, 0x40 },
52	{ "BITBUCKET",		0x80, 0x80 },
53	{ "STIMESEL",		0x18, 0x18 }
54};
55
56int
57ahc_sxfrctl1_print(u_int regvalue, u_int *cur_col, u_int wrap)
58{
59	return (ahc_print_register(SXFRCTL1_parse_table, 7, "SXFRCTL1",
60	    0x02, regvalue, cur_col, wrap));
61}
62
63static const ahc_reg_parse_entry_t SCSISIGO_parse_table[] = {
64	{ "ACKO",		0x01, 0x01 },
65	{ "REQO",		0x02, 0x02 },
66	{ "BSYO",		0x04, 0x04 },
67	{ "SELO",		0x08, 0x08 },
68	{ "ATNO",		0x10, 0x10 },
69	{ "MSGO",		0x20, 0x20 },
70	{ "IOO",		0x40, 0x40 },
71	{ "CDO",		0x80, 0x80 },
72	{ "P_DATAOUT",		0x00, 0x00 },
73	{ "P_DATAIN",		0x40, 0x40 },
74	{ "P_COMMAND",		0x80, 0x80 },
75	{ "P_MESGOUT",		0xa0, 0xa0 },
76	{ "P_STATUS",		0xc0, 0xc0 },
77	{ "PHASE_MASK",		0xe0, 0xe0 },
78	{ "P_MESGIN",		0xe0, 0xe0 }
79};
80
81int
82ahc_scsisigo_print(u_int regvalue, u_int *cur_col, u_int wrap)
83{
84	return (ahc_print_register(SCSISIGO_parse_table, 15, "SCSISIGO",
85	    0x03, regvalue, cur_col, wrap));
86}
87
88static const ahc_reg_parse_entry_t SCSISIGI_parse_table[] = {
89	{ "ACKI",		0x01, 0x01 },
90	{ "REQI",		0x02, 0x02 },
91	{ "BSYI",		0x04, 0x04 },
92	{ "SELI",		0x08, 0x08 },
93	{ "ATNI",		0x10, 0x10 },
94	{ "MSGI",		0x20, 0x20 },
95	{ "IOI",		0x40, 0x40 },
96	{ "CDI",		0x80, 0x80 },
97	{ "P_DATAOUT",		0x00, 0x00 },
98	{ "P_DATAOUT_DT",	0x20, 0x20 },
99	{ "P_DATAIN",		0x40, 0x40 },
100	{ "P_DATAIN_DT",	0x60, 0x60 },
101	{ "P_COMMAND",		0x80, 0x80 },
102	{ "P_MESGOUT",		0xa0, 0xa0 },
103	{ "P_STATUS",		0xc0, 0xc0 },
104	{ "PHASE_MASK",		0xe0, 0xe0 },
105	{ "P_MESGIN",		0xe0, 0xe0 }
106};
107
108int
109ahc_scsisigi_print(u_int regvalue, u_int *cur_col, u_int wrap)
110{
111	return (ahc_print_register(SCSISIGI_parse_table, 17, "SCSISIGI",
112	    0x03, regvalue, cur_col, wrap));
113}
114
115static const ahc_reg_parse_entry_t SCSIRATE_parse_table[] = {
116	{ "SINGLE_EDGE",	0x10, 0x10 },
117	{ "ENABLE_CRC",		0x40, 0x40 },
118	{ "WIDEXFER",		0x80, 0x80 },
119	{ "SXFR_ULTRA2",	0x0f, 0x0f },
120	{ "SOFS",		0x0f, 0x0f },
121	{ "SXFR",		0x70, 0x70 }
122};
123
124int
125ahc_scsirate_print(u_int regvalue, u_int *cur_col, u_int wrap)
126{
127	return (ahc_print_register(SCSIRATE_parse_table, 6, "SCSIRATE",
128	    0x04, regvalue, cur_col, wrap));
129}
130
131static const ahc_reg_parse_entry_t SCSIID_parse_table[] = {
132	{ "TWIN_CHNLB",		0x80, 0x80 },
133	{ "OID",		0x0f, 0x0f },
134	{ "TWIN_TID",		0x70, 0x70 },
135	{ "SOFS_ULTRA2",	0x7f, 0x7f },
136	{ "TID",		0xf0, 0xf0 }
137};
138
139int
140ahc_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap)
141{
142	return (ahc_print_register(SCSIID_parse_table, 5, "SCSIID",
143	    0x05, regvalue, cur_col, wrap));
144}
145
146int
147ahc_scsidatl_print(u_int regvalue, u_int *cur_col, u_int wrap)
148{
149	return (ahc_print_register(NULL, 0, "SCSIDATL",
150	    0x06, regvalue, cur_col, wrap));
151}
152
153int
154ahc_stcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
155{
156	return (ahc_print_register(NULL, 0, "STCNT",
157	    0x08, regvalue, cur_col, wrap));
158}
159
160static const ahc_reg_parse_entry_t OPTIONMODE_parse_table[] = {
161	{ "DIS_MSGIN_DUALEDGE",	0x01, 0x01 },
162	{ "AUTO_MSGOUT_DE",	0x02, 0x02 },
163	{ "SCSIDATL_IMGEN",	0x04, 0x04 },
164	{ "EXPPHASEDIS",	0x08, 0x08 },
165	{ "BUSFREEREV",		0x10, 0x10 },
166	{ "ATNMGMNTEN",		0x20, 0x20 },
167	{ "AUTOACKEN",		0x40, 0x40 },
168	{ "AUTORATEEN",		0x80, 0x80 },
169	{ "OPTIONMODE_DEFAULTS",0x03, 0x03 }
170};
171
172int
173ahc_optionmode_print(u_int regvalue, u_int *cur_col, u_int wrap)
174{
175	return (ahc_print_register(OPTIONMODE_parse_table, 9, "OPTIONMODE",
176	    0x08, regvalue, cur_col, wrap));
177}
178
179int
180ahc_targcrccnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
181{
182	return (ahc_print_register(NULL, 0, "TARGCRCCNT",
183	    0x0a, regvalue, cur_col, wrap));
184}
185
186static const ahc_reg_parse_entry_t CLRSINT0_parse_table[] = {
187	{ "CLRSPIORDY",		0x02, 0x02 },
188	{ "CLRSWRAP",		0x08, 0x08 },
189	{ "CLRIOERR",		0x08, 0x08 },
190	{ "CLRSELINGO",		0x10, 0x10 },
191	{ "CLRSELDI",		0x20, 0x20 },
192	{ "CLRSELDO",		0x40, 0x40 }
193};
194
195int
196ahc_clrsint0_print(u_int regvalue, u_int *cur_col, u_int wrap)
197{
198	return (ahc_print_register(CLRSINT0_parse_table, 6, "CLRSINT0",
199	    0x0b, regvalue, cur_col, wrap));
200}
201
202static const ahc_reg_parse_entry_t SSTAT0_parse_table[] = {
203	{ "DMADONE",		0x01, 0x01 },
204	{ "SPIORDY",		0x02, 0x02 },
205	{ "SDONE",		0x04, 0x04 },
206	{ "SWRAP",		0x08, 0x08 },
207	{ "IOERR",		0x08, 0x08 },
208	{ "SELINGO",		0x10, 0x10 },
209	{ "SELDI",		0x20, 0x20 },
210	{ "SELDO",		0x40, 0x40 },
211	{ "TARGET",		0x80, 0x80 }
212};
213
214int
215ahc_sstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
216{
217	return (ahc_print_register(SSTAT0_parse_table, 9, "SSTAT0",
218	    0x0b, regvalue, cur_col, wrap));
219}
220
221static const ahc_reg_parse_entry_t CLRSINT1_parse_table[] = {
222	{ "CLRREQINIT",		0x01, 0x01 },
223	{ "CLRPHASECHG",	0x02, 0x02 },
224	{ "CLRSCSIPERR",	0x04, 0x04 },
225	{ "CLRBUSFREE",		0x08, 0x08 },
226	{ "CLRSCSIRSTI",	0x20, 0x20 },
227	{ "CLRATNO",		0x40, 0x40 },
228	{ "CLRSELTIMEO",	0x80, 0x80 }
229};
230
231int
232ahc_clrsint1_print(u_int regvalue, u_int *cur_col, u_int wrap)
233{
234	return (ahc_print_register(CLRSINT1_parse_table, 7, "CLRSINT1",
235	    0x0c, regvalue, cur_col, wrap));
236}
237
238static const ahc_reg_parse_entry_t SSTAT1_parse_table[] = {
239	{ "REQINIT",		0x01, 0x01 },
240	{ "PHASECHG",		0x02, 0x02 },
241	{ "SCSIPERR",		0x04, 0x04 },
242	{ "BUSFREE",		0x08, 0x08 },
243	{ "PHASEMIS",		0x10, 0x10 },
244	{ "SCSIRSTI",		0x20, 0x20 },
245	{ "ATNTARG",		0x40, 0x40 },
246	{ "SELTO",		0x80, 0x80 }
247};
248
249int
250ahc_sstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
251{
252	return (ahc_print_register(SSTAT1_parse_table, 8, "SSTAT1",
253	    0x0c, regvalue, cur_col, wrap));
254}
255
256static const ahc_reg_parse_entry_t SSTAT2_parse_table[] = {
257	{ "DUAL_EDGE_ERR",	0x01, 0x01 },
258	{ "CRCREQERR",		0x02, 0x02 },
259	{ "CRCENDERR",		0x04, 0x04 },
260	{ "CRCVALERR",		0x08, 0x08 },
261	{ "EXP_ACTIVE",		0x10, 0x10 },
262	{ "SHVALID",		0x40, 0x40 },
263	{ "OVERRUN",		0x80, 0x80 },
264	{ "SFCNT",		0x1f, 0x1f }
265};
266
267int
268ahc_sstat2_print(u_int regvalue, u_int *cur_col, u_int wrap)
269{
270	return (ahc_print_register(SSTAT2_parse_table, 8, "SSTAT2",
271	    0x0d, regvalue, cur_col, wrap));
272}
273
274static const ahc_reg_parse_entry_t SSTAT3_parse_table[] = {
275	{ "OFFCNT",		0x0f, 0x0f },
276	{ "U2OFFCNT",		0x7f, 0x7f },
277	{ "SCSICNT",		0xf0, 0xf0 }
278};
279
280int
281ahc_sstat3_print(u_int regvalue, u_int *cur_col, u_int wrap)
282{
283	return (ahc_print_register(SSTAT3_parse_table, 3, "SSTAT3",
284	    0x0e, regvalue, cur_col, wrap));
285}
286
287static const ahc_reg_parse_entry_t SCSIID_ULTRA2_parse_table[] = {
288	{ "OID",		0x0f, 0x0f },
289	{ "TID",		0xf0, 0xf0 }
290};
291
292int
293ahc_scsiid_ultra2_print(u_int regvalue, u_int *cur_col, u_int wrap)
294{
295	return (ahc_print_register(SCSIID_ULTRA2_parse_table, 2, "SCSIID_ULTRA2",
296	    0x0f, regvalue, cur_col, wrap));
297}
298
299static const ahc_reg_parse_entry_t SIMODE0_parse_table[] = {
300	{ "ENDMADONE",		0x01, 0x01 },
301	{ "ENSPIORDY",		0x02, 0x02 },
302	{ "ENSDONE",		0x04, 0x04 },
303	{ "ENSWRAP",		0x08, 0x08 },
304	{ "ENIOERR",		0x08, 0x08 },
305	{ "ENSELINGO",		0x10, 0x10 },
306	{ "ENSELDI",		0x20, 0x20 },
307	{ "ENSELDO",		0x40, 0x40 }
308};
309
310int
311ahc_simode0_print(u_int regvalue, u_int *cur_col, u_int wrap)
312{
313	return (ahc_print_register(SIMODE0_parse_table, 8, "SIMODE0",
314	    0x10, regvalue, cur_col, wrap));
315}
316
317static const ahc_reg_parse_entry_t SIMODE1_parse_table[] = {
318	{ "ENREQINIT",		0x01, 0x01 },
319	{ "ENPHASECHG",		0x02, 0x02 },
320	{ "ENSCSIPERR",		0x04, 0x04 },
321	{ "ENBUSFREE",		0x08, 0x08 },
322	{ "ENPHASEMIS",		0x10, 0x10 },
323	{ "ENSCSIRST",		0x20, 0x20 },
324	{ "ENATNTARG",		0x40, 0x40 },
325	{ "ENSELTIMO",		0x80, 0x80 }
326};
327
328int
329ahc_simode1_print(u_int regvalue, u_int *cur_col, u_int wrap)
330{
331	return (ahc_print_register(SIMODE1_parse_table, 8, "SIMODE1",
332	    0x11, regvalue, cur_col, wrap));
333}
334
335int
336ahc_scsibusl_print(u_int regvalue, u_int *cur_col, u_int wrap)
337{
338	return (ahc_print_register(NULL, 0, "SCSIBUSL",
339	    0x12, regvalue, cur_col, wrap));
340}
341
342int
343ahc_shaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
344{
345	return (ahc_print_register(NULL, 0, "SHADDR",
346	    0x14, regvalue, cur_col, wrap));
347}
348
349static const ahc_reg_parse_entry_t SELTIMER_parse_table[] = {
350	{ "STAGE1",		0x01, 0x01 },
351	{ "STAGE2",		0x02, 0x02 },
352	{ "STAGE3",		0x04, 0x04 },
353	{ "STAGE4",		0x08, 0x08 },
354	{ "STAGE5",		0x10, 0x10 },
355	{ "STAGE6",		0x20, 0x20 }
356};
357
358int
359ahc_seltimer_print(u_int regvalue, u_int *cur_col, u_int wrap)
360{
361	return (ahc_print_register(SELTIMER_parse_table, 6, "SELTIMER",
362	    0x18, regvalue, cur_col, wrap));
363}
364
365static const ahc_reg_parse_entry_t SELID_parse_table[] = {
366	{ "ONEBIT",		0x08, 0x08 },
367	{ "SELID_MASK",		0xf0, 0xf0 }
368};
369
370int
371ahc_selid_print(u_int regvalue, u_int *cur_col, u_int wrap)
372{
373	return (ahc_print_register(SELID_parse_table, 2, "SELID",
374	    0x19, regvalue, cur_col, wrap));
375}
376
377int
378ahc_targid_print(u_int regvalue, u_int *cur_col, u_int wrap)
379{
380	return (ahc_print_register(NULL, 0, "TARGID",
381	    0x1b, regvalue, cur_col, wrap));
382}
383
384static const ahc_reg_parse_entry_t SPIOCAP_parse_table[] = {
385	{ "SSPIOCPS",		0x01, 0x01 },
386	{ "ROM",		0x02, 0x02 },
387	{ "EEPROM",		0x04, 0x04 },
388	{ "SEEPROM",		0x08, 0x08 },
389	{ "EXT_BRDCTL",		0x10, 0x10 },
390	{ "SOFTCMDEN",		0x20, 0x20 },
391	{ "SOFT0",		0x40, 0x40 },
392	{ "SOFT1",		0x80, 0x80 }
393};
394
395int
396ahc_spiocap_print(u_int regvalue, u_int *cur_col, u_int wrap)
397{
398	return (ahc_print_register(SPIOCAP_parse_table, 8, "SPIOCAP",
399	    0x1b, regvalue, cur_col, wrap));
400}
401
402static const ahc_reg_parse_entry_t BRDCTL_parse_table[] = {
403	{ "BRDCTL0",		0x01, 0x01 },
404	{ "BRDSTB_ULTRA2",	0x01, 0x01 },
405	{ "BRDCTL1",		0x02, 0x02 },
406	{ "BRDRW_ULTRA2",	0x02, 0x02 },
407	{ "BRDRW",		0x04, 0x04 },
408	{ "BRDDAT2",		0x04, 0x04 },
409	{ "BRDCS",		0x08, 0x08 },
410	{ "BRDDAT3",		0x08, 0x08 },
411	{ "BRDSTB",		0x10, 0x10 },
412	{ "BRDDAT4",		0x10, 0x10 },
413	{ "BRDDAT5",		0x20, 0x20 },
414	{ "BRDDAT6",		0x40, 0x40 },
415	{ "BRDDAT7",		0x80, 0x80 }
416};
417
418int
419ahc_brdctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
420{
421	return (ahc_print_register(BRDCTL_parse_table, 13, "BRDCTL",
422	    0x1d, regvalue, cur_col, wrap));
423}
424
425static const ahc_reg_parse_entry_t SEECTL_parse_table[] = {
426	{ "SEEDI",		0x01, 0x01 },
427	{ "SEEDO",		0x02, 0x02 },
428	{ "SEECK",		0x04, 0x04 },
429	{ "SEECS",		0x08, 0x08 },
430	{ "SEERDY",		0x10, 0x10 },
431	{ "SEEMS",		0x20, 0x20 },
432	{ "EXTARBREQ",		0x40, 0x40 },
433	{ "EXTARBACK",		0x80, 0x80 }
434};
435
436int
437ahc_seectl_print(u_int regvalue, u_int *cur_col, u_int wrap)
438{
439	return (ahc_print_register(SEECTL_parse_table, 8, "SEECTL",
440	    0x1e, regvalue, cur_col, wrap));
441}
442
443static const ahc_reg_parse_entry_t SBLKCTL_parse_table[] = {
444	{ "XCVR",		0x01, 0x01 },
445	{ "SELWIDE",		0x02, 0x02 },
446	{ "ENAB20",		0x04, 0x04 },
447	{ "SELBUSB",		0x08, 0x08 },
448	{ "ENAB40",		0x08, 0x08 },
449	{ "AUTOFLUSHDIS",	0x20, 0x20 },
450	{ "DIAGLEDON",		0x40, 0x40 },
451	{ "DIAGLEDEN",		0x80, 0x80 }
452};
453
454int
455ahc_sblkctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
456{
457	return (ahc_print_register(SBLKCTL_parse_table, 8, "SBLKCTL",
458	    0x1f, regvalue, cur_col, wrap));
459}
460
461int
462ahc_busy_targets_print(u_int regvalue, u_int *cur_col, u_int wrap)
463{
464	return (ahc_print_register(NULL, 0, "BUSY_TARGETS",
465	    0x20, regvalue, cur_col, wrap));
466}
467
468int
469ahc_ultra_enb_print(u_int regvalue, u_int *cur_col, u_int wrap)
470{
471	return (ahc_print_register(NULL, 0, "ULTRA_ENB",
472	    0x30, regvalue, cur_col, wrap));
473}
474
475int
476ahc_disc_dsb_print(u_int regvalue, u_int *cur_col, u_int wrap)
477{
478	return (ahc_print_register(NULL, 0, "DISC_DSB",
479	    0x32, regvalue, cur_col, wrap));
480}
481
482int
483ahc_mwi_residual_print(u_int regvalue, u_int *cur_col, u_int wrap)
484{
485	return (ahc_print_register(NULL, 0, "MWI_RESIDUAL",
486	    0x38, regvalue, cur_col, wrap));
487}
488
489int
490ahc_next_queued_scb_print(u_int regvalue, u_int *cur_col, u_int wrap)
491{
492	return (ahc_print_register(NULL, 0, "NEXT_QUEUED_SCB",
493	    0x39, regvalue, cur_col, wrap));
494}
495
496int
497ahc_msg_out_print(u_int regvalue, u_int *cur_col, u_int wrap)
498{
499	return (ahc_print_register(NULL, 0, "MSG_OUT",
500	    0x3a, regvalue, cur_col, wrap));
501}
502
503static const ahc_reg_parse_entry_t DMAPARAMS_parse_table[] = {
504	{ "FIFORESET",		0x01, 0x01 },
505	{ "FIFOFLUSH",		0x02, 0x02 },
506	{ "DIRECTION",		0x04, 0x04 },
507	{ "HDMAEN",		0x08, 0x08 },
508	{ "HDMAENACK",		0x08, 0x08 },
509	{ "SDMAEN",		0x10, 0x10 },
510	{ "SDMAENACK",		0x10, 0x10 },
511	{ "SCSIEN",		0x20, 0x20 },
512	{ "WIDEODD",		0x40, 0x40 },
513	{ "PRELOADEN",		0x80, 0x80 }
514};
515
516int
517ahc_dmaparams_print(u_int regvalue, u_int *cur_col, u_int wrap)
518{
519	return (ahc_print_register(DMAPARAMS_parse_table, 10, "DMAPARAMS",
520	    0x3b, regvalue, cur_col, wrap));
521}
522
523static const ahc_reg_parse_entry_t SEQ_FLAGS_parse_table[] = {
524	{ "NO_DISCONNECT",	0x01, 0x01 },
525	{ "SPHASE_PENDING",	0x02, 0x02 },
526	{ "DPHASE_PENDING",	0x04, 0x04 },
527	{ "CMDPHASE_PENDING",	0x08, 0x08 },
528	{ "TARG_CMD_PENDING",	0x10, 0x10 },
529	{ "DPHASE",		0x20, 0x20 },
530	{ "NO_CDB_SENT",	0x40, 0x40 },
531	{ "TARGET_CMD_IS_TAGGED",0x40, 0x40 },
532	{ "NOT_IDENTIFIED",	0x80, 0x80 }
533};
534
535int
536ahc_seq_flags_print(u_int regvalue, u_int *cur_col, u_int wrap)
537{
538	return (ahc_print_register(SEQ_FLAGS_parse_table, 9, "SEQ_FLAGS",
539	    0x3c, regvalue, cur_col, wrap));
540}
541
542int
543ahc_saved_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap)
544{
545	return (ahc_print_register(NULL, 0, "SAVED_SCSIID",
546	    0x3d, regvalue, cur_col, wrap));
547}
548
549int
550ahc_saved_lun_print(u_int regvalue, u_int *cur_col, u_int wrap)
551{
552	return (ahc_print_register(NULL, 0, "SAVED_LUN",
553	    0x3e, regvalue, cur_col, wrap));
554}
555
556static const ahc_reg_parse_entry_t LASTPHASE_parse_table[] = {
557	{ "MSGI",		0x20, 0x20 },
558	{ "IOI",		0x40, 0x40 },
559	{ "CDI",		0x80, 0x80 },
560	{ "P_DATAOUT",		0x00, 0x00 },
561	{ "P_BUSFREE",		0x01, 0x01 },
562	{ "P_DATAIN",		0x40, 0x40 },
563	{ "P_COMMAND",		0x80, 0x80 },
564	{ "P_MESGOUT",		0xa0, 0xa0 },
565	{ "P_STATUS",		0xc0, 0xc0 },
566	{ "PHASE_MASK",		0xe0, 0xe0 },
567	{ "P_MESGIN",		0xe0, 0xe0 }
568};
569
570int
571ahc_lastphase_print(u_int regvalue, u_int *cur_col, u_int wrap)
572{
573	return (ahc_print_register(LASTPHASE_parse_table, 11, "LASTPHASE",
574	    0x3f, regvalue, cur_col, wrap));
575}
576
577int
578ahc_waiting_scbh_print(u_int regvalue, u_int *cur_col, u_int wrap)
579{
580	return (ahc_print_register(NULL, 0, "WAITING_SCBH",
581	    0x40, regvalue, cur_col, wrap));
582}
583
584int
585ahc_disconnected_scbh_print(u_int regvalue, u_int *cur_col, u_int wrap)
586{
587	return (ahc_print_register(NULL, 0, "DISCONNECTED_SCBH",
588	    0x41, regvalue, cur_col, wrap));
589}
590
591int
592ahc_free_scbh_print(u_int regvalue, u_int *cur_col, u_int wrap)
593{
594	return (ahc_print_register(NULL, 0, "FREE_SCBH",
595	    0x42, regvalue, cur_col, wrap));
596}
597
598int
599ahc_hscb_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
600{
601	return (ahc_print_register(NULL, 0, "HSCB_ADDR",
602	    0x44, regvalue, cur_col, wrap));
603}
604
605int
606ahc_shared_data_addr_print(u_int regvalue, u_int *cur_col, u_int wrap)
607{
608	return (ahc_print_register(NULL, 0, "SHARED_DATA_ADDR",
609	    0x48, regvalue, cur_col, wrap));
610}
611
612int
613ahc_kernel_qinpos_print(u_int regvalue, u_int *cur_col, u_int wrap)
614{
615	return (ahc_print_register(NULL, 0, "KERNEL_QINPOS",
616	    0x4c, regvalue, cur_col, wrap));
617}
618
619int
620ahc_qinpos_print(u_int regvalue, u_int *cur_col, u_int wrap)
621{
622	return (ahc_print_register(NULL, 0, "QINPOS",
623	    0x4d, regvalue, cur_col, wrap));
624}
625
626int
627ahc_qoutpos_print(u_int regvalue, u_int *cur_col, u_int wrap)
628{
629	return (ahc_print_register(NULL, 0, "QOUTPOS",
630	    0x4e, regvalue, cur_col, wrap));
631}
632
633int
634ahc_kernel_tqinpos_print(u_int regvalue, u_int *cur_col, u_int wrap)
635{
636	return (ahc_print_register(NULL, 0, "KERNEL_TQINPOS",
637	    0x4f, regvalue, cur_col, wrap));
638}
639
640int
641ahc_tqinpos_print(u_int regvalue, u_int *cur_col, u_int wrap)
642{
643	return (ahc_print_register(NULL, 0, "TQINPOS",
644	    0x50, regvalue, cur_col, wrap));
645}
646
647static const ahc_reg_parse_entry_t ARG_1_parse_table[] = {
648	{ "CONT_TARG_SESSION",	0x02, 0x02 },
649	{ "CONT_MSG_LOOP",	0x04, 0x04 },
650	{ "EXIT_MSG_LOOP",	0x08, 0x08 },
651	{ "MSGOUT_PHASEMIS",	0x10, 0x10 },
652	{ "SEND_REJ",		0x20, 0x20 },
653	{ "SEND_SENSE",		0x40, 0x40 },
654	{ "SEND_MSG",		0x80, 0x80 }
655};
656
657int
658ahc_arg_1_print(u_int regvalue, u_int *cur_col, u_int wrap)
659{
660	return (ahc_print_register(ARG_1_parse_table, 7, "ARG_1",
661	    0x51, regvalue, cur_col, wrap));
662}
663
664int
665ahc_arg_2_print(u_int regvalue, u_int *cur_col, u_int wrap)
666{
667	return (ahc_print_register(NULL, 0, "ARG_2",
668	    0x52, regvalue, cur_col, wrap));
669}
670
671int
672ahc_last_msg_print(u_int regvalue, u_int *cur_col, u_int wrap)
673{
674	return (ahc_print_register(NULL, 0, "LAST_MSG",
675	    0x53, regvalue, cur_col, wrap));
676}
677
678static const ahc_reg_parse_entry_t SCSISEQ_TEMPLATE_parse_table[] = {
679	{ "ENAUTOATNP",		0x02, 0x02 },
680	{ "ENAUTOATNI",		0x04, 0x04 },
681	{ "ENAUTOATNO",		0x08, 0x08 },
682	{ "ENRSELI",		0x10, 0x10 },
683	{ "ENSELI",		0x20, 0x20 },
684	{ "ENSELO",		0x40, 0x40 }
685};
686
687int
688ahc_scsiseq_template_print(u_int regvalue, u_int *cur_col, u_int wrap)
689{
690	return (ahc_print_register(SCSISEQ_TEMPLATE_parse_table, 6, "SCSISEQ_TEMPLATE",
691	    0x54, regvalue, cur_col, wrap));
692}
693
694static const ahc_reg_parse_entry_t HA_274_BIOSGLOBAL_parse_table[] = {
695	{ "HA_274_EXTENDED_TRANS",0x01, 0x01 }
696};
697
698int
699ahc_ha_274_biosglobal_print(u_int regvalue, u_int *cur_col, u_int wrap)
700{
701	return (ahc_print_register(HA_274_BIOSGLOBAL_parse_table, 1, "HA_274_BIOSGLOBAL",
702	    0x56, regvalue, cur_col, wrap));
703}
704
705static const ahc_reg_parse_entry_t SEQ_FLAGS2_parse_table[] = {
706	{ "SCB_DMA",		0x01, 0x01 },
707	{ "TARGET_MSG_PENDING",	0x02, 0x02 }
708};
709
710int
711ahc_seq_flags2_print(u_int regvalue, u_int *cur_col, u_int wrap)
712{
713	return (ahc_print_register(SEQ_FLAGS2_parse_table, 2, "SEQ_FLAGS2",
714	    0x57, regvalue, cur_col, wrap));
715}
716
717static const ahc_reg_parse_entry_t SCSICONF_parse_table[] = {
718	{ "ENSPCHK",		0x20, 0x20 },
719	{ "RESET_SCSI",		0x40, 0x40 },
720	{ "TERM_ENB",		0x80, 0x80 },
721	{ "HSCSIID",		0x07, 0x07 },
722	{ "HWSCSIID",		0x0f, 0x0f }
723};
724
725int
726ahc_scsiconf_print(u_int regvalue, u_int *cur_col, u_int wrap)
727{
728	return (ahc_print_register(SCSICONF_parse_table, 5, "SCSICONF",
729	    0x5a, regvalue, cur_col, wrap));
730}
731
732static const ahc_reg_parse_entry_t INTDEF_parse_table[] = {
733	{ "EDGE_TRIG",		0x80, 0x80 },
734	{ "VECTOR",		0x0f, 0x0f }
735};
736
737int
738ahc_intdef_print(u_int regvalue, u_int *cur_col, u_int wrap)
739{
740	return (ahc_print_register(INTDEF_parse_table, 2, "INTDEF",
741	    0x5c, regvalue, cur_col, wrap));
742}
743
744int
745ahc_hostconf_print(u_int regvalue, u_int *cur_col, u_int wrap)
746{
747	return (ahc_print_register(NULL, 0, "HOSTCONF",
748	    0x5d, regvalue, cur_col, wrap));
749}
750
751static const ahc_reg_parse_entry_t HA_274_BIOSCTRL_parse_table[] = {
752	{ "CHANNEL_B_PRIMARY",	0x08, 0x08 },
753	{ "BIOSMODE",		0x30, 0x30 },
754	{ "BIOSDISABLED",	0x30, 0x30 }
755};
756
757int
758ahc_ha_274_biosctrl_print(u_int regvalue, u_int *cur_col, u_int wrap)
759{
760	return (ahc_print_register(HA_274_BIOSCTRL_parse_table, 3, "HA_274_BIOSCTRL",
761	    0x5f, regvalue, cur_col, wrap));
762}
763
764static const ahc_reg_parse_entry_t SEQCTL_parse_table[] = {
765	{ "LOADRAM",		0x01, 0x01 },
766	{ "SEQRESET",		0x02, 0x02 },
767	{ "STEP",		0x04, 0x04 },
768	{ "BRKADRINTEN",	0x08, 0x08 },
769	{ "FASTMODE",		0x10, 0x10 },
770	{ "FAILDIS",		0x20, 0x20 },
771	{ "PAUSEDIS",		0x40, 0x40 },
772	{ "PERRORDIS",		0x80, 0x80 }
773};
774
775int
776ahc_seqctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
777{
778	return (ahc_print_register(SEQCTL_parse_table, 8, "SEQCTL",
779	    0x60, regvalue, cur_col, wrap));
780}
781
782int
783ahc_seqram_print(u_int regvalue, u_int *cur_col, u_int wrap)
784{
785	return (ahc_print_register(NULL, 0, "SEQRAM",
786	    0x61, regvalue, cur_col, wrap));
787}
788
789int
790ahc_seqaddr0_print(u_int regvalue, u_int *cur_col, u_int wrap)
791{
792	return (ahc_print_register(NULL, 0, "SEQADDR0",
793	    0x62, regvalue, cur_col, wrap));
794}
795
796static const ahc_reg_parse_entry_t SEQADDR1_parse_table[] = {
797	{ "SEQADDR1_MASK",	0x01, 0x01 }
798};
799
800int
801ahc_seqaddr1_print(u_int regvalue, u_int *cur_col, u_int wrap)
802{
803	return (ahc_print_register(SEQADDR1_parse_table, 1, "SEQADDR1",
804	    0x63, regvalue, cur_col, wrap));
805}
806
807int
808ahc_accum_print(u_int regvalue, u_int *cur_col, u_int wrap)
809{
810	return (ahc_print_register(NULL, 0, "ACCUM",
811	    0x64, regvalue, cur_col, wrap));
812}
813
814int
815ahc_sindex_print(u_int regvalue, u_int *cur_col, u_int wrap)
816{
817	return (ahc_print_register(NULL, 0, "SINDEX",
818	    0x65, regvalue, cur_col, wrap));
819}
820
821int
822ahc_dindex_print(u_int regvalue, u_int *cur_col, u_int wrap)
823{
824	return (ahc_print_register(NULL, 0, "DINDEX",
825	    0x66, regvalue, cur_col, wrap));
826}
827
828int
829ahc_allones_print(u_int regvalue, u_int *cur_col, u_int wrap)
830{
831	return (ahc_print_register(NULL, 0, "ALLONES",
832	    0x69, regvalue, cur_col, wrap));
833}
834
835int
836ahc_allzeros_print(u_int regvalue, u_int *cur_col, u_int wrap)
837{
838	return (ahc_print_register(NULL, 0, "ALLZEROS",
839	    0x6a, regvalue, cur_col, wrap));
840}
841
842int
843ahc_none_print(u_int regvalue, u_int *cur_col, u_int wrap)
844{
845	return (ahc_print_register(NULL, 0, "NONE",
846	    0x6a, regvalue, cur_col, wrap));
847}
848
849static const ahc_reg_parse_entry_t FLAGS_parse_table[] = {
850	{ "CARRY",		0x01, 0x01 },
851	{ "ZERO",		0x02, 0x02 }
852};
853
854int
855ahc_flags_print(u_int regvalue, u_int *cur_col, u_int wrap)
856{
857	return (ahc_print_register(FLAGS_parse_table, 2, "FLAGS",
858	    0x6b, regvalue, cur_col, wrap));
859}
860
861int
862ahc_sindir_print(u_int regvalue, u_int *cur_col, u_int wrap)
863{
864	return (ahc_print_register(NULL, 0, "SINDIR",
865	    0x6c, regvalue, cur_col, wrap));
866}
867
868int
869ahc_dindir_print(u_int regvalue, u_int *cur_col, u_int wrap)
870{
871	return (ahc_print_register(NULL, 0, "DINDIR",
872	    0x6d, regvalue, cur_col, wrap));
873}
874
875int
876ahc_stack_print(u_int regvalue, u_int *cur_col, u_int wrap)
877{
878	return (ahc_print_register(NULL, 0, "STACK",
879	    0x6f, regvalue, cur_col, wrap));
880}
881
882int
883ahc_targ_offset_print(u_int regvalue, u_int *cur_col, u_int wrap)
884{
885	return (ahc_print_register(NULL, 0, "TARG_OFFSET",
886	    0x70, regvalue, cur_col, wrap));
887}
888
889int
890ahc_sram_base_print(u_int regvalue, u_int *cur_col, u_int wrap)
891{
892	return (ahc_print_register(NULL, 0, "SRAM_BASE",
893	    0x70, regvalue, cur_col, wrap));
894}
895
896static const ahc_reg_parse_entry_t DSCOMMAND0_parse_table[] = {
897	{ "CIOPARCKEN",		0x01, 0x01 },
898	{ "USCBSIZE32",		0x02, 0x02 },
899	{ "RAMPS",		0x04, 0x04 },
900	{ "INTSCBRAMSEL",	0x08, 0x08 },
901	{ "EXTREQLCK",		0x10, 0x10 },
902	{ "MPARCKEN",		0x20, 0x20 },
903	{ "DPARCKEN",		0x40, 0x40 },
904	{ "CACHETHEN",		0x80, 0x80 }
905};
906
907int
908ahc_dscommand0_print(u_int regvalue, u_int *cur_col, u_int wrap)
909{
910	return (ahc_print_register(DSCOMMAND0_parse_table, 8, "DSCOMMAND0",
911	    0x84, regvalue, cur_col, wrap));
912}
913
914static const ahc_reg_parse_entry_t BUSTIME_parse_table[] = {
915	{ "BON",		0x0f, 0x0f },
916	{ "BOFF",		0xf0, 0xf0 }
917};
918
919int
920ahc_bustime_print(u_int regvalue, u_int *cur_col, u_int wrap)
921{
922	return (ahc_print_register(BUSTIME_parse_table, 2, "BUSTIME",
923	    0x85, regvalue, cur_col, wrap));
924}
925
926static const ahc_reg_parse_entry_t DSCOMMAND1_parse_table[] = {
927	{ "HADDLDSEL0",		0x01, 0x01 },
928	{ "HADDLDSEL1",		0x02, 0x02 },
929	{ "DSLATT",		0xfc, 0xfc }
930};
931
932int
933ahc_dscommand1_print(u_int regvalue, u_int *cur_col, u_int wrap)
934{
935	return (ahc_print_register(DSCOMMAND1_parse_table, 3, "DSCOMMAND1",
936	    0x85, regvalue, cur_col, wrap));
937}
938
939static const ahc_reg_parse_entry_t BUSSPD_parse_table[] = {
940	{ "STBON",		0x07, 0x07 },
941	{ "STBOFF",		0x38, 0x38 },
942	{ "DFTHRSH_75",		0x80, 0x80 },
943	{ "DFTHRSH",		0xc0, 0xc0 },
944	{ "DFTHRSH_100",	0xc0, 0xc0 }
945};
946
947int
948ahc_busspd_print(u_int regvalue, u_int *cur_col, u_int wrap)
949{
950	return (ahc_print_register(BUSSPD_parse_table, 5, "BUSSPD",
951	    0x86, regvalue, cur_col, wrap));
952}
953
954static const ahc_reg_parse_entry_t HS_MAILBOX_parse_table[] = {
955	{ "SEQ_MAILBOX",	0x0f, 0x0f },
956	{ "HOST_TQINPOS",	0x80, 0x80 },
957	{ "HOST_MAILBOX",	0xf0, 0xf0 }
958};
959
960int
961ahc_hs_mailbox_print(u_int regvalue, u_int *cur_col, u_int wrap)
962{
963	return (ahc_print_register(HS_MAILBOX_parse_table, 3, "HS_MAILBOX",
964	    0x86, regvalue, cur_col, wrap));
965}
966
967static const ahc_reg_parse_entry_t DSPCISTATUS_parse_table[] = {
968	{ "DFTHRSH_100",	0xc0, 0xc0 }
969};
970
971int
972ahc_dspcistatus_print(u_int regvalue, u_int *cur_col, u_int wrap)
973{
974	return (ahc_print_register(DSPCISTATUS_parse_table, 1, "DSPCISTATUS",
975	    0x86, regvalue, cur_col, wrap));
976}
977
978static const ahc_reg_parse_entry_t HCNTRL_parse_table[] = {
979	{ "CHIPRST",		0x01, 0x01 },
980	{ "CHIPRSTACK",		0x01, 0x01 },
981	{ "INTEN",		0x02, 0x02 },
982	{ "PAUSE",		0x04, 0x04 },
983	{ "IRQMS",		0x08, 0x08 },
984	{ "SWINT",		0x10, 0x10 },
985	{ "POWRDN",		0x40, 0x40 }
986};
987
988int
989ahc_hcntrl_print(u_int regvalue, u_int *cur_col, u_int wrap)
990{
991	return (ahc_print_register(HCNTRL_parse_table, 7, "HCNTRL",
992	    0x87, regvalue, cur_col, wrap));
993}
994
995int
996ahc_haddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
997{
998	return (ahc_print_register(NULL, 0, "HADDR",
999	    0x88, regvalue, cur_col, wrap));
1000}
1001
1002int
1003ahc_hcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1004{
1005	return (ahc_print_register(NULL, 0, "HCNT",
1006	    0x8c, regvalue, cur_col, wrap));
1007}
1008
1009int
1010ahc_scbptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1011{
1012	return (ahc_print_register(NULL, 0, "SCBPTR",
1013	    0x90, regvalue, cur_col, wrap));
1014}
1015
1016static const ahc_reg_parse_entry_t INTSTAT_parse_table[] = {
1017	{ "SEQINT",		0x01, 0x01 },
1018	{ "CMDCMPLT",		0x02, 0x02 },
1019	{ "SCSIINT",		0x04, 0x04 },
1020	{ "BRKADRINT",		0x08, 0x08 },
1021	{ "BAD_PHASE",		0x01, 0x01 },
1022	{ "INT_PEND",		0x0f, 0x0f },
1023	{ "SEND_REJECT",	0x11, 0x11 },
1024	{ "PROTO_VIOLATION",	0x21, 0x21 },
1025	{ "NO_MATCH",		0x31, 0x31 },
1026	{ "IGN_WIDE_RES",	0x41, 0x41 },
1027	{ "PDATA_REINIT",	0x51, 0x51 },
1028	{ "HOST_MSG_LOOP",	0x61, 0x61 },
1029	{ "BAD_STATUS",		0x71, 0x71 },
1030	{ "PERR_DETECTED",	0x81, 0x81 },
1031	{ "DATA_OVERRUN",	0x91, 0x91 },
1032	{ "MKMSG_FAILED",	0xa1, 0xa1 },
1033	{ "MISSED_BUSFREE",	0xb1, 0xb1 },
1034	{ "SCB_MISMATCH",	0xc1, 0xc1 },
1035	{ "NO_FREE_SCB",	0xd1, 0xd1 },
1036	{ "OUT_OF_RANGE",	0xe1, 0xe1 },
1037	{ "SEQINT_MASK",	0xf1, 0xf1 }
1038};
1039
1040int
1041ahc_intstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
1042{
1043	return (ahc_print_register(INTSTAT_parse_table, 21, "INTSTAT",
1044	    0x91, regvalue, cur_col, wrap));
1045}
1046
1047static const ahc_reg_parse_entry_t CLRINT_parse_table[] = {
1048	{ "CLRSEQINT",		0x01, 0x01 },
1049	{ "CLRCMDINT",		0x02, 0x02 },
1050	{ "CLRSCSIINT",		0x04, 0x04 },
1051	{ "CLRBRKADRINT",	0x08, 0x08 },
1052	{ "CLRPARERR",		0x10, 0x10 }
1053};
1054
1055int
1056ahc_clrint_print(u_int regvalue, u_int *cur_col, u_int wrap)
1057{
1058	return (ahc_print_register(CLRINT_parse_table, 5, "CLRINT",
1059	    0x92, regvalue, cur_col, wrap));
1060}
1061
1062static const ahc_reg_parse_entry_t ERROR_parse_table[] = {
1063	{ "ILLHADDR",		0x01, 0x01 },
1064	{ "ILLSADDR",		0x02, 0x02 },
1065	{ "ILLOPCODE",		0x04, 0x04 },
1066	{ "SQPARERR",		0x08, 0x08 },
1067	{ "DPARERR",		0x10, 0x10 },
1068	{ "MPARERR",		0x20, 0x20 },
1069	{ "PCIERRSTAT",		0x40, 0x40 },
1070	{ "CIOPARERR",		0x80, 0x80 }
1071};
1072
1073int
1074ahc_error_print(u_int regvalue, u_int *cur_col, u_int wrap)
1075{
1076	return (ahc_print_register(ERROR_parse_table, 8, "ERROR",
1077	    0x92, regvalue, cur_col, wrap));
1078}
1079
1080static const ahc_reg_parse_entry_t DFCNTRL_parse_table[] = {
1081	{ "FIFORESET",		0x01, 0x01 },
1082	{ "FIFOFLUSH",		0x02, 0x02 },
1083	{ "DIRECTION",		0x04, 0x04 },
1084	{ "HDMAEN",		0x08, 0x08 },
1085	{ "HDMAENACK",		0x08, 0x08 },
1086	{ "SDMAEN",		0x10, 0x10 },
1087	{ "SDMAENACK",		0x10, 0x10 },
1088	{ "SCSIEN",		0x20, 0x20 },
1089	{ "WIDEODD",		0x40, 0x40 },
1090	{ "PRELOADEN",		0x80, 0x80 }
1091};
1092
1093int
1094ahc_dfcntrl_print(u_int regvalue, u_int *cur_col, u_int wrap)
1095{
1096	return (ahc_print_register(DFCNTRL_parse_table, 10, "DFCNTRL",
1097	    0x93, regvalue, cur_col, wrap));
1098}
1099
1100static const ahc_reg_parse_entry_t DFSTATUS_parse_table[] = {
1101	{ "FIFOEMP",		0x01, 0x01 },
1102	{ "FIFOFULL",		0x02, 0x02 },
1103	{ "DFTHRESH",		0x04, 0x04 },
1104	{ "HDONE",		0x08, 0x08 },
1105	{ "MREQPEND",		0x10, 0x10 },
1106	{ "FIFOQWDEMP",		0x20, 0x20 },
1107	{ "DFCACHETH",		0x40, 0x40 },
1108	{ "PRELOAD_AVAIL",	0x80, 0x80 }
1109};
1110
1111int
1112ahc_dfstatus_print(u_int regvalue, u_int *cur_col, u_int wrap)
1113{
1114	return (ahc_print_register(DFSTATUS_parse_table, 8, "DFSTATUS",
1115	    0x94, regvalue, cur_col, wrap));
1116}
1117
1118int
1119ahc_dfwaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1120{
1121	return (ahc_print_register(NULL, 0, "DFWADDR",
1122	    0x95, regvalue, cur_col, wrap));
1123}
1124
1125int
1126ahc_dfdat_print(u_int regvalue, u_int *cur_col, u_int wrap)
1127{
1128	return (ahc_print_register(NULL, 0, "DFDAT",
1129	    0x99, regvalue, cur_col, wrap));
1130}
1131
1132static const ahc_reg_parse_entry_t SCBCNT_parse_table[] = {
1133	{ "SCBAUTO",		0x80, 0x80 },
1134	{ "SCBCNT_MASK",	0x1f, 0x1f }
1135};
1136
1137int
1138ahc_scbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1139{
1140	return (ahc_print_register(SCBCNT_parse_table, 2, "SCBCNT",
1141	    0x9a, regvalue, cur_col, wrap));
1142}
1143
1144int
1145ahc_qinfifo_print(u_int regvalue, u_int *cur_col, u_int wrap)
1146{
1147	return (ahc_print_register(NULL, 0, "QINFIFO",
1148	    0x9b, regvalue, cur_col, wrap));
1149}
1150
1151int
1152ahc_qoutfifo_print(u_int regvalue, u_int *cur_col, u_int wrap)
1153{
1154	return (ahc_print_register(NULL, 0, "QOUTFIFO",
1155	    0x9d, regvalue, cur_col, wrap));
1156}
1157
1158static const ahc_reg_parse_entry_t CRCCONTROL1_parse_table[] = {
1159	{ "TARGCRCCNTEN",	0x04, 0x04 },
1160	{ "TARGCRCENDEN",	0x08, 0x08 },
1161	{ "CRCREQCHKEN",	0x10, 0x10 },
1162	{ "CRCENDCHKEN",	0x20, 0x20 },
1163	{ "CRCVALCHKEN",	0x40, 0x40 },
1164	{ "CRCONSEEN",		0x80, 0x80 }
1165};
1166
1167int
1168ahc_crccontrol1_print(u_int regvalue, u_int *cur_col, u_int wrap)
1169{
1170	return (ahc_print_register(CRCCONTROL1_parse_table, 6, "CRCCONTROL1",
1171	    0x9d, regvalue, cur_col, wrap));
1172}
1173
1174static const ahc_reg_parse_entry_t SCSIPHASE_parse_table[] = {
1175	{ "DATA_OUT_PHASE",	0x01, 0x01 },
1176	{ "DATA_IN_PHASE",	0x02, 0x02 },
1177	{ "MSG_OUT_PHASE",	0x04, 0x04 },
1178	{ "MSG_IN_PHASE",	0x08, 0x08 },
1179	{ "COMMAND_PHASE",	0x10, 0x10 },
1180	{ "STATUS_PHASE",	0x20, 0x20 },
1181	{ "DATA_PHASE_MASK",	0x03, 0x03 }
1182};
1183
1184int
1185ahc_scsiphase_print(u_int regvalue, u_int *cur_col, u_int wrap)
1186{
1187	return (ahc_print_register(SCSIPHASE_parse_table, 7, "SCSIPHASE",
1188	    0x9e, regvalue, cur_col, wrap));
1189}
1190
1191static const ahc_reg_parse_entry_t SFUNCT_parse_table[] = {
1192	{ "ALT_MODE",		0x80, 0x80 }
1193};
1194
1195int
1196ahc_sfunct_print(u_int regvalue, u_int *cur_col, u_int wrap)
1197{
1198	return (ahc_print_register(SFUNCT_parse_table, 1, "SFUNCT",
1199	    0x9f, regvalue, cur_col, wrap));
1200}
1201
1202int
1203ahc_scb_base_print(u_int regvalue, u_int *cur_col, u_int wrap)
1204{
1205	return (ahc_print_register(NULL, 0, "SCB_BASE",
1206	    0xa0, regvalue, cur_col, wrap));
1207}
1208
1209int
1210ahc_scb_cdb_ptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1211{
1212	return (ahc_print_register(NULL, 0, "SCB_CDB_PTR",
1213	    0xa0, regvalue, cur_col, wrap));
1214}
1215
1216int
1217ahc_scb_residual_sgptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1218{
1219	return (ahc_print_register(NULL, 0, "SCB_RESIDUAL_SGPTR",
1220	    0xa4, regvalue, cur_col, wrap));
1221}
1222
1223int
1224ahc_scb_scsi_status_print(u_int regvalue, u_int *cur_col, u_int wrap)
1225{
1226	return (ahc_print_register(NULL, 0, "SCB_SCSI_STATUS",
1227	    0xa8, regvalue, cur_col, wrap));
1228}
1229
1230int
1231ahc_scb_target_phases_print(u_int regvalue, u_int *cur_col, u_int wrap)
1232{
1233	return (ahc_print_register(NULL, 0, "SCB_TARGET_PHASES",
1234	    0xa9, regvalue, cur_col, wrap));
1235}
1236
1237int
1238ahc_scb_target_data_dir_print(u_int regvalue, u_int *cur_col, u_int wrap)
1239{
1240	return (ahc_print_register(NULL, 0, "SCB_TARGET_DATA_DIR",
1241	    0xaa, regvalue, cur_col, wrap));
1242}
1243
1244int
1245ahc_scb_target_itag_print(u_int regvalue, u_int *cur_col, u_int wrap)
1246{
1247	return (ahc_print_register(NULL, 0, "SCB_TARGET_ITAG",
1248	    0xab, regvalue, cur_col, wrap));
1249}
1250
1251int
1252ahc_scb_dataptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1253{
1254	return (ahc_print_register(NULL, 0, "SCB_DATAPTR",
1255	    0xac, regvalue, cur_col, wrap));
1256}
1257
1258static const ahc_reg_parse_entry_t SCB_DATACNT_parse_table[] = {
1259	{ "SG_LAST_SEG",	0x80, 0x80 },
1260	{ "SG_HIGH_ADDR_BITS",	0x7f, 0x7f }
1261};
1262
1263int
1264ahc_scb_datacnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1265{
1266	return (ahc_print_register(SCB_DATACNT_parse_table, 2, "SCB_DATACNT",
1267	    0xb0, regvalue, cur_col, wrap));
1268}
1269
1270static const ahc_reg_parse_entry_t SCB_SGPTR_parse_table[] = {
1271	{ "SG_LIST_NULL",	0x01, 0x01 },
1272	{ "SG_FULL_RESID",	0x02, 0x02 },
1273	{ "SG_RESID_VALID",	0x04, 0x04 }
1274};
1275
1276int
1277ahc_scb_sgptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1278{
1279	return (ahc_print_register(SCB_SGPTR_parse_table, 3, "SCB_SGPTR",
1280	    0xb4, regvalue, cur_col, wrap));
1281}
1282
1283static const ahc_reg_parse_entry_t SCB_CONTROL_parse_table[] = {
1284	{ "DISCONNECTED",	0x04, 0x04 },
1285	{ "ULTRAENB",		0x08, 0x08 },
1286	{ "MK_MESSAGE",		0x10, 0x10 },
1287	{ "TAG_ENB",		0x20, 0x20 },
1288	{ "DISCENB",		0x40, 0x40 },
1289	{ "TARGET_SCB",		0x80, 0x80 },
1290	{ "STATUS_RCVD",	0x80, 0x80 },
1291	{ "SCB_TAG_TYPE",	0x03, 0x03 }
1292};
1293
1294int
1295ahc_scb_control_print(u_int regvalue, u_int *cur_col, u_int wrap)
1296{
1297	return (ahc_print_register(SCB_CONTROL_parse_table, 8, "SCB_CONTROL",
1298	    0xb8, regvalue, cur_col, wrap));
1299}
1300
1301static const ahc_reg_parse_entry_t SCB_SCSIID_parse_table[] = {
1302	{ "TWIN_CHNLB",		0x80, 0x80 },
1303	{ "OID",		0x0f, 0x0f },
1304	{ "TWIN_TID",		0x70, 0x70 },
1305	{ "TID",		0xf0, 0xf0 }
1306};
1307
1308int
1309ahc_scb_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap)
1310{
1311	return (ahc_print_register(SCB_SCSIID_parse_table, 4, "SCB_SCSIID",
1312	    0xb9, regvalue, cur_col, wrap));
1313}
1314
1315static const ahc_reg_parse_entry_t SCB_LUN_parse_table[] = {
1316	{ "SCB_XFERLEN_ODD",	0x80, 0x80 },
1317	{ "LID",		0x3f, 0x3f }
1318};
1319
1320int
1321ahc_scb_lun_print(u_int regvalue, u_int *cur_col, u_int wrap)
1322{
1323	return (ahc_print_register(SCB_LUN_parse_table, 2, "SCB_LUN",
1324	    0xba, regvalue, cur_col, wrap));
1325}
1326
1327int
1328ahc_scb_tag_print(u_int regvalue, u_int *cur_col, u_int wrap)
1329{
1330	return (ahc_print_register(NULL, 0, "SCB_TAG",
1331	    0xbb, regvalue, cur_col, wrap));
1332}
1333
1334int
1335ahc_scb_cdb_len_print(u_int regvalue, u_int *cur_col, u_int wrap)
1336{
1337	return (ahc_print_register(NULL, 0, "SCB_CDB_LEN",
1338	    0xbc, regvalue, cur_col, wrap));
1339}
1340
1341int
1342ahc_scb_scsirate_print(u_int regvalue, u_int *cur_col, u_int wrap)
1343{
1344	return (ahc_print_register(NULL, 0, "SCB_SCSIRATE",
1345	    0xbd, regvalue, cur_col, wrap));
1346}
1347
1348int
1349ahc_scb_scsioffset_print(u_int regvalue, u_int *cur_col, u_int wrap)
1350{
1351	return (ahc_print_register(NULL, 0, "SCB_SCSIOFFSET",
1352	    0xbe, regvalue, cur_col, wrap));
1353}
1354
1355int
1356ahc_scb_next_print(u_int regvalue, u_int *cur_col, u_int wrap)
1357{
1358	return (ahc_print_register(NULL, 0, "SCB_NEXT",
1359	    0xbf, regvalue, cur_col, wrap));
1360}
1361
1362static const ahc_reg_parse_entry_t SEECTL_2840_parse_table[] = {
1363	{ "DO_2840",		0x01, 0x01 },
1364	{ "CK_2840",		0x02, 0x02 },
1365	{ "CS_2840",		0x04, 0x04 }
1366};
1367
1368int
1369ahc_seectl_2840_print(u_int regvalue, u_int *cur_col, u_int wrap)
1370{
1371	return (ahc_print_register(SEECTL_2840_parse_table, 3, "SEECTL_2840",
1372	    0xc0, regvalue, cur_col, wrap));
1373}
1374
1375static const ahc_reg_parse_entry_t STATUS_2840_parse_table[] = {
1376	{ "DI_2840",		0x01, 0x01 },
1377	{ "EEPROM_TF",		0x80, 0x80 },
1378	{ "ADSEL",		0x1e, 0x1e },
1379	{ "BIOS_SEL",		0x60, 0x60 }
1380};
1381
1382int
1383ahc_status_2840_print(u_int regvalue, u_int *cur_col, u_int wrap)
1384{
1385	return (ahc_print_register(STATUS_2840_parse_table, 4, "STATUS_2840",
1386	    0xc1, regvalue, cur_col, wrap));
1387}
1388
1389int
1390ahc_scb_64_btt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1391{
1392	return (ahc_print_register(NULL, 0, "SCB_64_BTT",
1393	    0xd0, regvalue, cur_col, wrap));
1394}
1395
1396int
1397ahc_cchaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1398{
1399	return (ahc_print_register(NULL, 0, "CCHADDR",
1400	    0xe0, regvalue, cur_col, wrap));
1401}
1402
1403int
1404ahc_cchcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1405{
1406	return (ahc_print_register(NULL, 0, "CCHCNT",
1407	    0xe8, regvalue, cur_col, wrap));
1408}
1409
1410int
1411ahc_ccsgram_print(u_int regvalue, u_int *cur_col, u_int wrap)
1412{
1413	return (ahc_print_register(NULL, 0, "CCSGRAM",
1414	    0xe9, regvalue, cur_col, wrap));
1415}
1416
1417int
1418ahc_ccsgaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1419{
1420	return (ahc_print_register(NULL, 0, "CCSGADDR",
1421	    0xea, regvalue, cur_col, wrap));
1422}
1423
1424static const ahc_reg_parse_entry_t CCSGCTL_parse_table[] = {
1425	{ "CCSGRESET",		0x01, 0x01 },
1426	{ "SG_FETCH_NEEDED",	0x02, 0x02 },
1427	{ "CCSGEN",		0x08, 0x08 },
1428	{ "CCSGDONE",		0x80, 0x80 }
1429};
1430
1431int
1432ahc_ccsgctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
1433{
1434	return (ahc_print_register(CCSGCTL_parse_table, 4, "CCSGCTL",
1435	    0xeb, regvalue, cur_col, wrap));
1436}
1437
1438int
1439ahc_ccscbram_print(u_int regvalue, u_int *cur_col, u_int wrap)
1440{
1441	return (ahc_print_register(NULL, 0, "CCSCBRAM",
1442	    0xec, regvalue, cur_col, wrap));
1443}
1444
1445int
1446ahc_ccscbaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1447{
1448	return (ahc_print_register(NULL, 0, "CCSCBADDR",
1449	    0xed, regvalue, cur_col, wrap));
1450}
1451
1452static const ahc_reg_parse_entry_t CCSCBCTL_parse_table[] = {
1453	{ "CCSCBRESET",		0x01, 0x01 },
1454	{ "CCSCBDIR",		0x04, 0x04 },
1455	{ "CCSCBEN",		0x08, 0x08 },
1456	{ "CCARREN",		0x10, 0x10 },
1457	{ "ARRDONE",		0x40, 0x40 },
1458	{ "CCSCBDONE",		0x80, 0x80 }
1459};
1460
1461int
1462ahc_ccscbctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
1463{
1464	return (ahc_print_register(CCSCBCTL_parse_table, 6, "CCSCBCTL",
1465	    0xee, regvalue, cur_col, wrap));
1466}
1467
1468int
1469ahc_ccscbcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
1470{
1471	return (ahc_print_register(NULL, 0, "CCSCBCNT",
1472	    0xef, regvalue, cur_col, wrap));
1473}
1474
1475int
1476ahc_scbbaddr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1477{
1478	return (ahc_print_register(NULL, 0, "SCBBADDR",
1479	    0xf0, regvalue, cur_col, wrap));
1480}
1481
1482int
1483ahc_ccscbptr_print(u_int regvalue, u_int *cur_col, u_int wrap)
1484{
1485	return (ahc_print_register(NULL, 0, "CCSCBPTR",
1486	    0xf1, regvalue, cur_col, wrap));
1487}
1488
1489int
1490ahc_hnscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap)
1491{
1492	return (ahc_print_register(NULL, 0, "HNSCB_QOFF",
1493	    0xf4, regvalue, cur_col, wrap));
1494}
1495
1496int
1497ahc_snscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap)
1498{
1499	return (ahc_print_register(NULL, 0, "SNSCB_QOFF",
1500	    0xf6, regvalue, cur_col, wrap));
1501}
1502
1503int
1504ahc_sdscb_qoff_print(u_int regvalue, u_int *cur_col, u_int wrap)
1505{
1506	return (ahc_print_register(NULL, 0, "SDSCB_QOFF",
1507	    0xf8, regvalue, cur_col, wrap));
1508}
1509
1510static const ahc_reg_parse_entry_t QOFF_CTLSTA_parse_table[] = {
1511	{ "SDSCB_ROLLOVER",	0x10, 0x10 },
1512	{ "SNSCB_ROLLOVER",	0x20, 0x20 },
1513	{ "SCB_AVAIL",		0x40, 0x40 },
1514	{ "SCB_QSIZE_256",	0x06, 0x06 },
1515	{ "SCB_QSIZE",		0x07, 0x07 }
1516};
1517
1518int
1519ahc_qoff_ctlsta_print(u_int regvalue, u_int *cur_col, u_int wrap)
1520{
1521	return (ahc_print_register(QOFF_CTLSTA_parse_table, 5, "QOFF_CTLSTA",
1522	    0xfa, regvalue, cur_col, wrap));
1523}
1524
1525static const ahc_reg_parse_entry_t DFF_THRSH_parse_table[] = {
1526	{ "RD_DFTHRSH_MIN",	0x00, 0x00 },
1527	{ "WR_DFTHRSH_MIN",	0x00, 0x00 },
1528	{ "RD_DFTHRSH_25",	0x01, 0x01 },
1529	{ "RD_DFTHRSH_50",	0x02, 0x02 },
1530	{ "RD_DFTHRSH_63",	0x03, 0x03 },
1531	{ "RD_DFTHRSH_75",	0x04, 0x04 },
1532	{ "RD_DFTHRSH_85",	0x05, 0x05 },
1533	{ "RD_DFTHRSH_90",	0x06, 0x06 },
1534	{ "RD_DFTHRSH",		0x07, 0x07 },
1535	{ "RD_DFTHRSH_MAX",	0x07, 0x07 },
1536	{ "WR_DFTHRSH_25",	0x10, 0x10 },
1537	{ "WR_DFTHRSH_50",	0x20, 0x20 },
1538	{ "WR_DFTHRSH_63",	0x30, 0x30 },
1539	{ "WR_DFTHRSH_75",	0x40, 0x40 },
1540	{ "WR_DFTHRSH_85",	0x50, 0x50 },
1541	{ "WR_DFTHRSH_90",	0x60, 0x60 },
1542	{ "WR_DFTHRSH",		0x70, 0x70 },
1543	{ "WR_DFTHRSH_MAX",	0x70, 0x70 }
1544};
1545
1546int
1547ahc_dff_thrsh_print(u_int regvalue, u_int *cur_col, u_int wrap)
1548{
1549	return (ahc_print_register(DFF_THRSH_parse_table, 18, "DFF_THRSH",
1550	    0xfb, regvalue, cur_col, wrap));
1551}
1552
1553static const ahc_reg_parse_entry_t SG_CACHE_SHADOW_parse_table[] = {
1554	{ "LAST_SEG_DONE",	0x01, 0x01 },
1555	{ "LAST_SEG",		0x02, 0x02 },
1556	{ "SG_ADDR_MASK",	0xf8, 0xf8 }
1557};
1558
1559int
1560ahc_sg_cache_shadow_print(u_int regvalue, u_int *cur_col, u_int wrap)
1561{
1562	return (ahc_print_register(SG_CACHE_SHADOW_parse_table, 3, "SG_CACHE_SHADOW",
1563	    0xfc, regvalue, cur_col, wrap));
1564}
1565
1566static const ahc_reg_parse_entry_t SG_CACHE_PRE_parse_table[] = {
1567	{ "LAST_SEG_DONE",	0x01, 0x01 },
1568	{ "LAST_SEG",		0x02, 0x02 },
1569	{ "SG_ADDR_MASK",	0xf8, 0xf8 }
1570};
1571
1572int
1573ahc_sg_cache_pre_print(u_int regvalue, u_int *cur_col, u_int wrap)
1574{
1575	return (ahc_print_register(SG_CACHE_PRE_parse_table, 3, "SG_CACHE_PRE",
1576	    0xfc, regvalue, cur_col, wrap));
1577}
1578
1579