1 /* 2 * Product specific probe and attach routines for: 3 * 3940, 2940, aic7895, aic7890, aic7880, 4 * aic7870, aic7860 and aic7850 SCSI controllers 5 * 6 * Copyright (c) 1994-2001 Justin T. Gibbs. 7 * Copyright (c) 2000-2001 Adaptec Inc. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions, and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * substantially similar to the "NO WARRANTY" disclaimer below 18 * ("Disclaimer") and any redistribution must be conditioned upon 19 * including a substantially similar Disclaimer requirement for further 20 * binary redistribution. 21 * 3. Neither the names of the above-listed copyright holders nor the names 22 * of any contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * Alternatively, this software may be distributed under the terms of the 26 * GNU General Public License ("GPL") version 2 as published by the Free 27 * Software Foundation. 28 * 29 * NO WARRANTY 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 * POSSIBILITY OF SUCH DAMAGES. 41 * 42 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#69 $ 43 * 44 * $FreeBSD$ 45 */ 46 47 #ifdef __linux__ 48 #include "aic7xxx_osm.h" 49 #include "aic7xxx_inline.h" 50 #include "aic7xxx_93cx6.h" 51 #else 52 #include <dev/aic7xxx/aic7xxx_osm.h> 53 #include <dev/aic7xxx/aic7xxx_inline.h> 54 #include <dev/aic7xxx/aic7xxx_93cx6.h> 55 #endif 56 57 #include "aic7xxx_pci.h" 58 59 static __inline uint64_t 60 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor) 61 { 62 uint64_t id; 63 64 id = subvendor 65 | (subdevice << 16) 66 | ((uint64_t)vendor << 32) 67 | ((uint64_t)device << 48); 68 69 return (id); 70 } 71 72 #define AHC_PCI_IOADDR PCIR_MAPS /* I/O Address */ 73 #define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */ 74 75 #define DEVID_9005_TYPE(id) ((id) & 0xF) 76 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */ 77 #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */ 78 #define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */ 79 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */ 80 81 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 82 #define DEVID_9005_MAXRATE_U160 0x0 83 #define DEVID_9005_MAXRATE_ULTRA2 0x1 84 #define DEVID_9005_MAXRATE_ULTRA 0x2 85 #define DEVID_9005_MAXRATE_FAST 0x3 86 87 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6) 88 89 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8) 90 #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */ 91 92 #define SUBID_9005_TYPE(id) ((id) & 0xF) 93 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */ 94 #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */ 95 #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */ 96 #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */ 97 98 #define SUBID_9005_TYPE_KNOWN(id) \ 99 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \ 100 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \ 101 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \ 102 || (((id) & 0xF) == SUBID_9005_TYPE_RAID)) 103 104 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4) 105 #define SUBID_9005_MAXRATE_ULTRA2 0x0 106 #define SUBID_9005_MAXRATE_ULTRA 0x1 107 #define SUBID_9005_MAXRATE_U160 0x2 108 #define SUBID_9005_MAXRATE_RESERVED 0x3 109 110 #define SUBID_9005_SEEPTYPE(id) \ 111 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 112 ? ((id) & 0xC0) >> 6 \ 113 : ((id) & 0x300) >> 8) 114 #define SUBID_9005_SEEPTYPE_NONE 0x0 115 #define SUBID_9005_SEEPTYPE_1K 0x1 116 #define SUBID_9005_SEEPTYPE_2K_4K 0x2 117 #define SUBID_9005_SEEPTYPE_RESERVED 0x3 118 #define SUBID_9005_AUTOTERM(id) \ 119 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 120 ? (((id) & 0x400) >> 10) == 0 \ 121 : (((id) & 0x40) >> 6) == 0) 122 123 #define SUBID_9005_NUMCHAN(id) \ 124 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 125 ? ((id) & 0x300) >> 8 \ 126 : ((id) & 0xC00) >> 10) 127 128 #define SUBID_9005_LEGACYCONN(id) \ 129 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 130 ? 0 \ 131 : ((id) & 0x80) >> 7) 132 133 #define SUBID_9005_MFUNCENB(id) \ 134 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \ 135 ? ((id) & 0x800) >> 11 \ 136 : ((id) & 0x1000) >> 12) 137 /* 138 * Informational only. Should use chip register to be 139 * certain, but may be use in identification strings. 140 */ 141 #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000 142 #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000 143 #define SUBID_9005_CARD_SEDIFF_MASK 0x8000 144 145 static ahc_device_setup_t ahc_aic785X_setup; 146 static ahc_device_setup_t ahc_aic7860_setup; 147 static ahc_device_setup_t ahc_apa1480_setup; 148 static ahc_device_setup_t ahc_aic7870_setup; 149 static ahc_device_setup_t ahc_aha394X_setup; 150 static ahc_device_setup_t ahc_aha494X_setup; 151 static ahc_device_setup_t ahc_aha398X_setup; 152 static ahc_device_setup_t ahc_aic7880_setup; 153 static ahc_device_setup_t ahc_aha2940Pro_setup; 154 static ahc_device_setup_t ahc_aha394XU_setup; 155 static ahc_device_setup_t ahc_aha398XU_setup; 156 static ahc_device_setup_t ahc_aic7890_setup; 157 static ahc_device_setup_t ahc_aic7892_setup; 158 static ahc_device_setup_t ahc_aic7895_setup; 159 static ahc_device_setup_t ahc_aic7896_setup; 160 static ahc_device_setup_t ahc_aic7899_setup; 161 static ahc_device_setup_t ahc_aha29160C_setup; 162 static ahc_device_setup_t ahc_raid_setup; 163 static ahc_device_setup_t ahc_aha394XX_setup; 164 static ahc_device_setup_t ahc_aha494XX_setup; 165 static ahc_device_setup_t ahc_aha398XX_setup; 166 167 struct ahc_pci_identity ahc_pci_ident_table [] = 168 { 169 /* aic7850 based controllers */ 170 { 171 ID_AHA_2902_04_10_15_20C_30C, 172 ID_ALL_MASK, 173 "Adaptec 2902/04/10/15/20C/30C SCSI adapter", 174 ahc_aic785X_setup 175 }, 176 /* aic7860 based controllers */ 177 { 178 ID_AHA_2930CU, 179 ID_ALL_MASK, 180 "Adaptec 2930CU SCSI adapter", 181 ahc_aic7860_setup 182 }, 183 { 184 ID_AHA_1480A & ID_DEV_VENDOR_MASK, 185 ID_DEV_VENDOR_MASK, 186 "Adaptec 1480A Ultra SCSI adapter", 187 ahc_apa1480_setup 188 }, 189 { 190 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK, 191 ID_DEV_VENDOR_MASK, 192 "Adaptec 2940A Ultra SCSI adapter", 193 ahc_aic7860_setup 194 }, 195 { 196 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK, 197 ID_DEV_VENDOR_MASK, 198 "Adaptec 2940A/CN Ultra SCSI adapter", 199 ahc_aic7860_setup 200 }, 201 { 202 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK, 203 ID_DEV_VENDOR_MASK, 204 "Adaptec 2930C Ultra SCSI adapter (VAR)", 205 ahc_aic7860_setup 206 }, 207 /* aic7870 based controllers */ 208 { 209 ID_AHA_2940, 210 ID_ALL_MASK, 211 "Adaptec 2940 SCSI adapter", 212 ahc_aic7870_setup 213 }, 214 { 215 ID_AHA_3940, 216 ID_ALL_MASK, 217 "Adaptec 3940 SCSI adapter", 218 ahc_aha394X_setup 219 }, 220 { 221 ID_AHA_398X, 222 ID_ALL_MASK, 223 "Adaptec 398X SCSI RAID adapter", 224 ahc_aha398X_setup 225 }, 226 { 227 ID_AHA_2944, 228 ID_ALL_MASK, 229 "Adaptec 2944 SCSI adapter", 230 ahc_aic7870_setup 231 }, 232 { 233 ID_AHA_3944, 234 ID_ALL_MASK, 235 "Adaptec 3944 SCSI adapter", 236 ahc_aha394X_setup 237 }, 238 { 239 ID_AHA_4944, 240 ID_ALL_MASK, 241 "Adaptec 4944 SCSI adapter", 242 ahc_aha494X_setup 243 }, 244 /* aic7880 based controllers */ 245 { 246 ID_AHA_2940U & ID_DEV_VENDOR_MASK, 247 ID_DEV_VENDOR_MASK, 248 "Adaptec 2940 Ultra SCSI adapter", 249 ahc_aic7880_setup 250 }, 251 { 252 ID_AHA_3940U & ID_DEV_VENDOR_MASK, 253 ID_DEV_VENDOR_MASK, 254 "Adaptec 3940 Ultra SCSI adapter", 255 ahc_aha394XU_setup 256 }, 257 { 258 ID_AHA_2944U & ID_DEV_VENDOR_MASK, 259 ID_DEV_VENDOR_MASK, 260 "Adaptec 2944 Ultra SCSI adapter", 261 ahc_aic7880_setup 262 }, 263 { 264 ID_AHA_3944U & ID_DEV_VENDOR_MASK, 265 ID_DEV_VENDOR_MASK, 266 "Adaptec 3944 Ultra SCSI adapter", 267 ahc_aha394XU_setup 268 }, 269 { 270 ID_AHA_398XU & ID_DEV_VENDOR_MASK, 271 ID_DEV_VENDOR_MASK, 272 "Adaptec 398X Ultra SCSI RAID adapter", 273 ahc_aha398XU_setup 274 }, 275 { 276 /* 277 * XXX Don't know the slot numbers 278 * so we can't identify channels 279 */ 280 ID_AHA_4944U & ID_DEV_VENDOR_MASK, 281 ID_DEV_VENDOR_MASK, 282 "Adaptec 4944 Ultra SCSI adapter", 283 ahc_aic7880_setup 284 }, 285 { 286 ID_AHA_2930U & ID_DEV_VENDOR_MASK, 287 ID_DEV_VENDOR_MASK, 288 "Adaptec 2930 Ultra SCSI adapter", 289 ahc_aic7880_setup 290 }, 291 { 292 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK, 293 ID_DEV_VENDOR_MASK, 294 "Adaptec 2940 Pro Ultra SCSI adapter", 295 ahc_aha2940Pro_setup 296 }, 297 { 298 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK, 299 ID_DEV_VENDOR_MASK, 300 "Adaptec 2940/CN Ultra SCSI adapter", 301 ahc_aic7880_setup 302 }, 303 /* Ignore all SISL (AAC on MB) based controllers. */ 304 { 305 ID_9005_SISL_ID, 306 ID_9005_SISL_MASK, 307 NULL, 308 NULL 309 }, 310 /* aic7890 based controllers */ 311 { 312 ID_AHA_2930U2, 313 ID_ALL_MASK, 314 "Adaptec 2930 Ultra2 SCSI adapter", 315 ahc_aic7890_setup 316 }, 317 { 318 ID_AHA_2940U2B, 319 ID_ALL_MASK, 320 "Adaptec 2940B Ultra2 SCSI adapter", 321 ahc_aic7890_setup 322 }, 323 { 324 ID_AHA_2940U2_OEM, 325 ID_ALL_MASK, 326 "Adaptec 2940 Ultra2 SCSI adapter (OEM)", 327 ahc_aic7890_setup 328 }, 329 { 330 ID_AHA_2940U2, 331 ID_ALL_MASK, 332 "Adaptec 2940 Ultra2 SCSI adapter", 333 ahc_aic7890_setup 334 }, 335 { 336 ID_AHA_2950U2B, 337 ID_ALL_MASK, 338 "Adaptec 2950 Ultra2 SCSI adapter", 339 ahc_aic7890_setup 340 }, 341 { 342 ID_AIC7890_ARO, 343 ID_ALL_MASK, 344 "Adaptec aic7890/91 Ultra2 SCSI adapter (ARO)", 345 ahc_aic7890_setup 346 }, 347 { 348 ID_AAA_131U2, 349 ID_ALL_MASK, 350 "Adaptec AAA-131 Ultra2 RAID adapter", 351 ahc_aic7890_setup 352 }, 353 /* aic7892 based controllers */ 354 { 355 ID_AHA_29160, 356 ID_ALL_MASK, 357 "Adaptec 29160 Ultra160 SCSI adapter", 358 ahc_aic7892_setup 359 }, 360 { 361 ID_AHA_29160_CPQ, 362 ID_ALL_MASK, 363 "Adaptec (Compaq OEM) 29160 Ultra160 SCSI adapter", 364 ahc_aic7892_setup 365 }, 366 { 367 ID_AHA_29160N, 368 ID_ALL_MASK, 369 "Adaptec 29160N Ultra160 SCSI adapter", 370 ahc_aic7892_setup 371 }, 372 { 373 ID_AHA_29160C, 374 ID_ALL_MASK, 375 "Adaptec 29160C Ultra160 SCSI adapter", 376 ahc_aha29160C_setup 377 }, 378 { 379 ID_AHA_29160B, 380 ID_ALL_MASK, 381 "Adaptec 29160B Ultra160 SCSI adapter", 382 ahc_aic7892_setup 383 }, 384 { 385 ID_AHA_19160B, 386 ID_ALL_MASK, 387 "Adaptec 19160B Ultra160 SCSI adapter", 388 ahc_aic7892_setup 389 }, 390 { 391 ID_AIC7892_ARO, 392 ID_ALL_MASK, 393 "Adaptec aic7892 Ultra160 SCSI adapter (ARO)", 394 ahc_aic7892_setup 395 }, 396 /* aic7895 based controllers */ 397 { 398 ID_AHA_2940U_DUAL, 399 ID_ALL_MASK, 400 "Adaptec 2940/DUAL Ultra SCSI adapter", 401 ahc_aic7895_setup 402 }, 403 { 404 ID_AHA_3940AU, 405 ID_ALL_MASK, 406 "Adaptec 3940A Ultra SCSI adapter", 407 ahc_aic7895_setup 408 }, 409 { 410 ID_AHA_3944AU, 411 ID_ALL_MASK, 412 "Adaptec 3944A Ultra SCSI adapter", 413 ahc_aic7895_setup 414 }, 415 { 416 ID_AIC7895_ARO, 417 ID_AIC7895_ARO_MASK, 418 "Adaptec aic7895 Ultra SCSI adapter (ARO)", 419 ahc_aic7895_setup 420 }, 421 /* aic7896/97 based controllers */ 422 { 423 ID_AHA_3950U2B_0, 424 ID_ALL_MASK, 425 "Adaptec 3950B Ultra2 SCSI adapter", 426 ahc_aic7896_setup 427 }, 428 { 429 ID_AHA_3950U2B_1, 430 ID_ALL_MASK, 431 "Adaptec 3950B Ultra2 SCSI adapter", 432 ahc_aic7896_setup 433 }, 434 { 435 ID_AHA_3950U2D_0, 436 ID_ALL_MASK, 437 "Adaptec 3950D Ultra2 SCSI adapter", 438 ahc_aic7896_setup 439 }, 440 { 441 ID_AHA_3950U2D_1, 442 ID_ALL_MASK, 443 "Adaptec 3950D Ultra2 SCSI adapter", 444 ahc_aic7896_setup 445 }, 446 { 447 ID_AIC7896_ARO, 448 ID_ALL_MASK, 449 "Adaptec aic7896/97 Ultra2 SCSI adapter (ARO)", 450 ahc_aic7896_setup 451 }, 452 /* aic7899 based controllers */ 453 { 454 ID_AHA_3960D, 455 ID_ALL_MASK, 456 "Adaptec 3960D Ultra160 SCSI adapter", 457 ahc_aic7899_setup 458 }, 459 { 460 ID_AHA_3960D_CPQ, 461 ID_ALL_MASK, 462 "Adaptec (Compaq OEM) 3960D Ultra160 SCSI adapter", 463 ahc_aic7899_setup 464 }, 465 { 466 ID_AIC7899_ARO, 467 ID_ALL_MASK, 468 "Adaptec aic7899 Ultra160 SCSI adapter (ARO)", 469 ahc_aic7899_setup 470 }, 471 /* Generic chip probes for devices we don't know 'exactly' */ 472 { 473 ID_AIC7850 & ID_DEV_VENDOR_MASK, 474 ID_DEV_VENDOR_MASK, 475 "Adaptec aic7850 SCSI adapter", 476 ahc_aic785X_setup 477 }, 478 { 479 ID_AIC7855 & ID_DEV_VENDOR_MASK, 480 ID_DEV_VENDOR_MASK, 481 "Adaptec aic7855 SCSI adapter", 482 ahc_aic785X_setup 483 }, 484 { 485 ID_AIC7859 & ID_DEV_VENDOR_MASK, 486 ID_DEV_VENDOR_MASK, 487 "Adaptec aic7859 SCSI adapter", 488 ahc_aic7860_setup 489 }, 490 { 491 ID_AIC7860 & ID_DEV_VENDOR_MASK, 492 ID_DEV_VENDOR_MASK, 493 "Adaptec aic7860 Ultra SCSI adapter", 494 ahc_aic7860_setup 495 }, 496 { 497 ID_AIC7870 & ID_DEV_VENDOR_MASK, 498 ID_DEV_VENDOR_MASK, 499 "Adaptec aic7870 SCSI adapter", 500 ahc_aic7870_setup 501 }, 502 { 503 ID_AIC7880 & ID_DEV_VENDOR_MASK, 504 ID_DEV_VENDOR_MASK, 505 "Adaptec aic7880 Ultra SCSI adapter", 506 ahc_aic7880_setup 507 }, 508 { 509 ID_AIC7890 & ID_9005_GENERIC_MASK, 510 ID_9005_GENERIC_MASK, 511 "Adaptec aic7890/91 Ultra2 SCSI adapter", 512 ahc_aic7890_setup 513 }, 514 { 515 ID_AIC7892 & ID_9005_GENERIC_MASK, 516 ID_9005_GENERIC_MASK, 517 "Adaptec aic7892 Ultra160 SCSI adapter", 518 ahc_aic7892_setup 519 }, 520 { 521 ID_AIC7895 & ID_DEV_VENDOR_MASK, 522 ID_DEV_VENDOR_MASK, 523 "Adaptec aic7895 Ultra SCSI adapter", 524 ahc_aic7895_setup 525 }, 526 { 527 ID_AIC7896 & ID_9005_GENERIC_MASK, 528 ID_9005_GENERIC_MASK, 529 "Adaptec aic7896/97 Ultra2 SCSI adapter", 530 ahc_aic7896_setup 531 }, 532 { 533 ID_AIC7899 & ID_9005_GENERIC_MASK, 534 ID_9005_GENERIC_MASK, 535 "Adaptec aic7899 Ultra160 SCSI adapter", 536 ahc_aic7899_setup 537 }, 538 { 539 ID_AIC7810 & ID_DEV_VENDOR_MASK, 540 ID_DEV_VENDOR_MASK, 541 "Adaptec aic7810 RAID memory controller", 542 ahc_raid_setup 543 }, 544 { 545 ID_AIC7815 & ID_DEV_VENDOR_MASK, 546 ID_DEV_VENDOR_MASK, 547 "Adaptec aic7815 RAID memory controller", 548 ahc_raid_setup 549 } 550 }; 551 552 const u_int ahc_num_pci_devs = NUM_ELEMENTS(ahc_pci_ident_table); 553 554 #define AHC_394X_SLOT_CHANNEL_A 4 555 #define AHC_394X_SLOT_CHANNEL_B 5 556 557 #define AHC_398X_SLOT_CHANNEL_A 4 558 #define AHC_398X_SLOT_CHANNEL_B 8 559 #define AHC_398X_SLOT_CHANNEL_C 12 560 561 #define AHC_494X_SLOT_CHANNEL_A 4 562 #define AHC_494X_SLOT_CHANNEL_B 5 563 #define AHC_494X_SLOT_CHANNEL_C 6 564 #define AHC_494X_SLOT_CHANNEL_D 7 565 566 #define DEVCONFIG 0x40 567 #define PCIERRGENDIS 0x80000000ul 568 #define SCBSIZE32 0x00010000ul /* aic789X only */ 569 #define REXTVALID 0x00001000ul /* ultra cards only */ 570 #define MPORTMODE 0x00000400ul /* aic7870+ only */ 571 #define RAMPSM 0x00000200ul /* aic7870+ only */ 572 #define VOLSENSE 0x00000100ul 573 #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/ 574 #define SCBRAMSEL 0x00000080ul 575 #define MRDCEN 0x00000040ul 576 #define EXTSCBTIME 0x00000020ul /* aic7870 only */ 577 #define EXTSCBPEN 0x00000010ul /* aic7870 only */ 578 #define BERREN 0x00000008ul 579 #define DACEN 0x00000004ul 580 #define STPWLEVEL 0x00000002ul 581 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */ 582 583 #define CSIZE_LATTIME 0x0c 584 #define CACHESIZE 0x0000003ful /* only 5 bits */ 585 #define LATTIME 0x0000ff00ul 586 587 /* PCI STATUS definitions */ 588 #define DPE 0x80 589 #define SSE 0x40 590 #define RMA 0x20 591 #define RTA 0x10 592 #define STA 0x08 593 #define DPR 0x01 594 595 static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device, 596 uint16_t subvendor, uint16_t subdevice); 597 static int ahc_ext_scbram_present(struct ahc_softc *ahc); 598 static void ahc_scbram_config(struct ahc_softc *ahc, int enable, 599 int pcheck, int fast, int large); 600 static void ahc_probe_ext_scbram(struct ahc_softc *ahc); 601 static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1); 602 static void ahc_parse_pci_eeprom(struct ahc_softc *ahc, 603 struct seeprom_config *sc); 604 static void configure_termination(struct ahc_softc *ahc, 605 struct seeprom_descriptor *sd, 606 u_int adapter_control, 607 u_int *sxfrctl1); 608 609 static void ahc_new_term_detect(struct ahc_softc *ahc, 610 int *enableSEC_low, 611 int *enableSEC_high, 612 int *enablePRI_low, 613 int *enablePRI_high, 614 int *eeprom_present); 615 static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 616 int *internal68_present, 617 int *externalcable_present, 618 int *eeprom_present); 619 static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 620 int *externalcable_present, 621 int *eeprom_present); 622 static void write_brdctl(struct ahc_softc *ahc, uint8_t value); 623 static uint8_t read_brdctl(struct ahc_softc *ahc); 624 static void ahc_pci_intr(struct ahc_softc *ahc); 625 static int ahc_pci_chip_init(struct ahc_softc *ahc); 626 static int ahc_pci_suspend(struct ahc_softc *ahc); 627 static int ahc_pci_resume(struct ahc_softc *ahc); 628 629 static int 630 ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor, 631 uint16_t subdevice, uint16_t subvendor) 632 { 633 int result; 634 635 /* Default to invalid. */ 636 result = 0; 637 if (vendor == 0x9005 638 && subvendor == 0x9005 639 && subdevice != device 640 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) { 641 642 switch (SUBID_9005_TYPE(subdevice)) { 643 case SUBID_9005_TYPE_MB: 644 break; 645 case SUBID_9005_TYPE_CARD: 646 case SUBID_9005_TYPE_LCCARD: 647 /* 648 * Currently only trust Adaptec cards to 649 * get the sub device info correct. 650 */ 651 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA) 652 result = 1; 653 break; 654 case SUBID_9005_TYPE_RAID: 655 break; 656 default: 657 break; 658 } 659 } 660 return (result); 661 } 662 663 struct ahc_pci_identity * 664 ahc_find_pci_device(ahc_dev_softc_t pci) 665 { 666 uint64_t full_id; 667 uint16_t device; 668 uint16_t vendor; 669 uint16_t subdevice; 670 uint16_t subvendor; 671 struct ahc_pci_identity *entry; 672 u_int i; 673 674 vendor = ahc_pci_read_config(pci, PCIR_DEVVENDOR, /*bytes*/2); 675 device = ahc_pci_read_config(pci, PCIR_DEVICE, /*bytes*/2); 676 subvendor = ahc_pci_read_config(pci, PCIR_SUBVEND_0, /*bytes*/2); 677 subdevice = ahc_pci_read_config(pci, PCIR_SUBDEV_0, /*bytes*/2); 678 full_id = ahc_compose_id(device, vendor, subdevice, subvendor); 679 680 /* 681 * If the second function is not hooked up, ignore it. 682 * Unfortunately, not all MB vendors implement the 683 * subdevice ID as per the Adaptec spec, so do our best 684 * to sanity check it prior to accepting the subdevice 685 * ID as valid. 686 */ 687 if (ahc_get_pci_function(pci) > 0 688 && ahc_9005_subdevinfo_valid(vendor, device, subvendor, subdevice) 689 && SUBID_9005_MFUNCENB(subdevice) == 0) 690 return (NULL); 691 692 for (i = 0; i < ahc_num_pci_devs; i++) { 693 entry = &ahc_pci_ident_table[i]; 694 if (entry->full_id == (full_id & entry->id_mask)) { 695 /* Honor exclusion entries. */ 696 if (entry->name == NULL) 697 return (NULL); 698 return (entry); 699 } 700 } 701 return (NULL); 702 } 703 704 int 705 ahc_pci_config(struct ahc_softc *ahc, struct ahc_pci_identity *entry) 706 { 707 u_int command; 708 u_int our_id; 709 u_int sxfrctl1; 710 u_int scsiseq; 711 u_int dscommand0; 712 uint32_t devconfig; 713 int error; 714 uint8_t sblkctl; 715 716 our_id = 0; 717 error = entry->setup(ahc); 718 if (error != 0) 719 return (error); 720 ahc->chip |= AHC_PCI; 721 ahc->description = entry->name; 722 723 pci_set_power_state(ahc->dev_softc, AHC_POWER_STATE_D0); 724 725 error = ahc_pci_map_registers(ahc); 726 if (error != 0) 727 return (error); 728 729 /* 730 * Before we continue probing the card, ensure that 731 * its interrupts are *disabled*. We don't want 732 * a misstep to hang the machine in an interrupt 733 * storm. 734 */ 735 ahc_intr_enable(ahc, FALSE); 736 737 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4); 738 739 /* 740 * If we need to support high memory, enable dual 741 * address cycles. This bit must be set to enable 742 * high address bit generation even if we are on a 743 * 64bit bus (PCI64BIT set in devconfig). 744 */ 745 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 746 747 if (bootverbose) 748 printf("%s: Enabling 39Bit Addressing\n", 749 ahc_name(ahc)); 750 devconfig |= DACEN; 751 } 752 753 /* Ensure that pci error generation, a test feature, is disabled. */ 754 devconfig |= PCIERRGENDIS; 755 756 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 757 758 /* Ensure busmastering is enabled */ 759 command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2); 760 command |= PCIM_CMD_BUSMASTEREN; 761 762 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, /*bytes*/2); 763 764 /* On all PCI adapters, we allow SCB paging */ 765 ahc->flags |= AHC_PAGESCBS; 766 767 error = ahc_softc_init(ahc); 768 if (error != 0) 769 return (error); 770 771 /* 772 * Disable PCI parity error checking. Users typically 773 * do this to work around broken PCI chipsets that get 774 * the parity timing wrong and thus generate lots of spurious 775 * errors. The chip only allows us to disable *all* parity 776 * error reporting when doing this, so CIO bus, scb ram, and 777 * scratch ram parity errors will be ignored too. 778 */ 779 if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0) 780 ahc->seqctl |= FAILDIS; 781 782 ahc->bus_intr = ahc_pci_intr; 783 ahc->bus_chip_init = ahc_pci_chip_init; 784 ahc->bus_suspend = ahc_pci_suspend; 785 ahc->bus_resume = ahc_pci_resume; 786 787 /* Remeber how the card was setup in case there is no SEEPROM */ 788 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) { 789 ahc_pause(ahc); 790 if ((ahc->features & AHC_ULTRA2) != 0) 791 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 792 else 793 our_id = ahc_inb(ahc, SCSIID) & OID; 794 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN; 795 scsiseq = ahc_inb(ahc, SCSISEQ); 796 } else { 797 sxfrctl1 = STPWEN; 798 our_id = 7; 799 scsiseq = 0; 800 } 801 802 error = ahc_reset(ahc, /*reinit*/FALSE); 803 if (error != 0) 804 return (ENXIO); 805 806 if ((ahc->features & AHC_DT) != 0) { 807 u_int sfunct; 808 809 /* Perform ALT-Mode Setup */ 810 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 811 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 812 ahc_outb(ahc, OPTIONMODE, 813 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS); 814 ahc_outb(ahc, SFUNCT, sfunct); 815 816 /* Normal mode setup */ 817 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN 818 |TARGCRCENDEN); 819 } 820 821 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 822 dscommand0 |= MPARCKEN|CACHETHEN; 823 if ((ahc->features & AHC_ULTRA2) != 0) { 824 825 /* 826 * DPARCKEN doesn't work correctly on 827 * some MBs so don't use it. 828 */ 829 dscommand0 &= ~DPARCKEN; 830 } 831 832 /* 833 * Handle chips that must have cache line 834 * streaming (dis/en)abled. 835 */ 836 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0) 837 dscommand0 |= CACHETHEN; 838 839 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0) 840 dscommand0 &= ~CACHETHEN; 841 842 ahc_outb(ahc, DSCOMMAND0, dscommand0); 843 844 ahc->pci_cachesize = 845 ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, 846 /*bytes*/1) & CACHESIZE; 847 ahc->pci_cachesize *= 4; 848 849 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0 850 && ahc->pci_cachesize == 4) { 851 852 ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME, 853 0, /*bytes*/1); 854 ahc->pci_cachesize = 0; 855 } 856 857 /* 858 * We cannot perform ULTRA speeds without the presense 859 * of the external precision resistor. 860 */ 861 if ((ahc->features & AHC_ULTRA) != 0) { 862 uint32_t devconfig; 863 864 devconfig = ahc_pci_read_config(ahc->dev_softc, 865 DEVCONFIG, /*bytes*/4); 866 if ((devconfig & REXTVALID) == 0) 867 ahc->features &= ~AHC_ULTRA; 868 } 869 870 /* See if we have a SEEPROM and perform auto-term */ 871 check_extport(ahc, &sxfrctl1); 872 873 /* 874 * Take the LED out of diagnostic mode 875 */ 876 sblkctl = ahc_inb(ahc, SBLKCTL); 877 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 878 879 if ((ahc->features & AHC_ULTRA2) != 0) { 880 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX); 881 } else { 882 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100); 883 } 884 885 if (ahc->flags & AHC_USEDEFAULTS) { 886 /* 887 * PCI Adapter default setup 888 * Should only be used if the adapter does not have 889 * a SEEPROM. 890 */ 891 /* See if someone else set us up already */ 892 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0 893 && scsiseq != 0) { 894 printf("%s: Using left over BIOS settings\n", 895 ahc_name(ahc)); 896 ahc->flags &= ~AHC_USEDEFAULTS; 897 ahc->flags |= AHC_BIOS_ENABLED; 898 } else { 899 /* 900 * Assume only one connector and always turn 901 * on termination. 902 */ 903 our_id = 0x07; 904 sxfrctl1 = STPWEN; 905 } 906 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI); 907 908 ahc->our_id = our_id; 909 } 910 911 /* 912 * Take a look to see if we have external SRAM. 913 * We currently do not attempt to use SRAM that is 914 * shared among multiple controllers. 915 */ 916 ahc_probe_ext_scbram(ahc); 917 918 /* 919 * Record our termination setting for the 920 * generic initialization routine. 921 */ 922 if ((sxfrctl1 & STPWEN) != 0) 923 ahc->flags |= AHC_TERM_ENB_A; 924 925 /* 926 * Save chip register configuration data for chip resets 927 * that occur during runtime and resume events. 928 */ 929 ahc->bus_softc.pci_softc.devconfig = 930 ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4); 931 ahc->bus_softc.pci_softc.command = 932 ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1); 933 ahc->bus_softc.pci_softc.csize_lattime = 934 ahc_pci_read_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1); 935 ahc->bus_softc.pci_softc.dscommand0 = ahc_inb(ahc, DSCOMMAND0); 936 ahc->bus_softc.pci_softc.dspcistatus = ahc_inb(ahc, DSPCISTATUS); 937 if ((ahc->features & AHC_DT) != 0) { 938 u_int sfunct; 939 940 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 941 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 942 ahc->bus_softc.pci_softc.optionmode = ahc_inb(ahc, OPTIONMODE); 943 ahc->bus_softc.pci_softc.targcrccnt = ahc_inw(ahc, TARGCRCCNT); 944 ahc_outb(ahc, SFUNCT, sfunct); 945 ahc->bus_softc.pci_softc.crccontrol1 = 946 ahc_inb(ahc, CRCCONTROL1); 947 } 948 if ((ahc->features & AHC_MULTI_FUNC) != 0) 949 ahc->bus_softc.pci_softc.scbbaddr = ahc_inb(ahc, SCBBADDR); 950 951 if ((ahc->features & AHC_ULTRA2) != 0) 952 ahc->bus_softc.pci_softc.dff_thrsh = ahc_inb(ahc, DFF_THRSH); 953 954 /* Core initialization */ 955 error = ahc_init(ahc); 956 if (error != 0) 957 return (error); 958 959 /* 960 * Allow interrupts now that we are completely setup. 961 */ 962 error = ahc_pci_map_int(ahc); 963 if (error != 0) 964 return (error); 965 966 ahc->init_level++; 967 return (0); 968 } 969 970 /* 971 * Test for the presense of external sram in an 972 * "unshared" configuration. 973 */ 974 static int 975 ahc_ext_scbram_present(struct ahc_softc *ahc) 976 { 977 u_int chip; 978 int ramps; 979 int single_user; 980 uint32_t devconfig; 981 982 chip = ahc->chip & AHC_CHIPID_MASK; 983 devconfig = ahc_pci_read_config(ahc->dev_softc, 984 DEVCONFIG, /*bytes*/4); 985 single_user = (devconfig & MPORTMODE) != 0; 986 987 if ((ahc->features & AHC_ULTRA2) != 0) 988 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0; 989 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C) 990 /* 991 * External SCBRAM arbitration is flakey 992 * on these chips. Unfortunately this means 993 * we don't use the extra SCB ram space on the 994 * 3940AUW. 995 */ 996 ramps = 0; 997 else if (chip >= AHC_AIC7870) 998 ramps = (devconfig & RAMPSM) != 0; 999 else 1000 ramps = 0; 1001 1002 if (ramps && single_user) 1003 return (1); 1004 return (0); 1005 } 1006 1007 /* 1008 * Enable external scbram. 1009 */ 1010 static void 1011 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck, 1012 int fast, int large) 1013 { 1014 uint32_t devconfig; 1015 1016 if (ahc->features & AHC_MULTI_FUNC) { 1017 /* 1018 * Set the SCB Base addr (highest address bit) 1019 * depending on which channel we are. 1020 */ 1021 ahc_outb(ahc, SCBBADDR, ahc_get_pci_function(ahc->dev_softc)); 1022 } 1023 1024 ahc->flags &= ~AHC_LSCBS_ENABLED; 1025 if (large) 1026 ahc->flags |= AHC_LSCBS_ENABLED; 1027 devconfig = ahc_pci_read_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4); 1028 if ((ahc->features & AHC_ULTRA2) != 0) { 1029 u_int dscommand0; 1030 1031 dscommand0 = ahc_inb(ahc, DSCOMMAND0); 1032 if (enable) 1033 dscommand0 &= ~INTSCBRAMSEL; 1034 else 1035 dscommand0 |= INTSCBRAMSEL; 1036 if (large) 1037 dscommand0 &= ~USCBSIZE32; 1038 else 1039 dscommand0 |= USCBSIZE32; 1040 ahc_outb(ahc, DSCOMMAND0, dscommand0); 1041 } else { 1042 if (fast) 1043 devconfig &= ~EXTSCBTIME; 1044 else 1045 devconfig |= EXTSCBTIME; 1046 if (enable) 1047 devconfig &= ~SCBRAMSEL; 1048 else 1049 devconfig |= SCBRAMSEL; 1050 if (large) 1051 devconfig &= ~SCBSIZE32; 1052 else 1053 devconfig |= SCBSIZE32; 1054 } 1055 if (pcheck) 1056 devconfig |= EXTSCBPEN; 1057 else 1058 devconfig &= ~EXTSCBPEN; 1059 1060 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, devconfig, /*bytes*/4); 1061 } 1062 1063 /* 1064 * Take a look to see if we have external SRAM. 1065 * We currently do not attempt to use SRAM that is 1066 * shared among multiple controllers. 1067 */ 1068 static void 1069 ahc_probe_ext_scbram(struct ahc_softc *ahc) 1070 { 1071 int num_scbs; 1072 int test_num_scbs; 1073 int enable; 1074 int pcheck; 1075 int fast; 1076 int large; 1077 1078 enable = FALSE; 1079 pcheck = FALSE; 1080 fast = FALSE; 1081 large = FALSE; 1082 num_scbs = 0; 1083 1084 if (ahc_ext_scbram_present(ahc) == 0) 1085 goto done; 1086 1087 /* 1088 * Probe for the best parameters to use. 1089 */ 1090 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large); 1091 num_scbs = ahc_probe_scbs(ahc); 1092 if (num_scbs == 0) { 1093 /* The SRAM wasn't really present. */ 1094 goto done; 1095 } 1096 enable = TRUE; 1097 1098 /* 1099 * Clear any outstanding parity error 1100 * and ensure that parity error reporting 1101 * is enabled. 1102 */ 1103 ahc_outb(ahc, SEQCTL, 0); 1104 ahc_outb(ahc, CLRINT, CLRPARERR); 1105 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1106 1107 /* Now see if we can do parity */ 1108 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large); 1109 num_scbs = ahc_probe_scbs(ahc); 1110 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1111 || (ahc_inb(ahc, ERROR) & MPARERR) == 0) 1112 pcheck = TRUE; 1113 1114 /* Clear any resulting parity error */ 1115 ahc_outb(ahc, CLRINT, CLRPARERR); 1116 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1117 1118 /* Now see if we can do fast timing */ 1119 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large); 1120 test_num_scbs = ahc_probe_scbs(ahc); 1121 if (test_num_scbs == num_scbs 1122 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0 1123 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)) 1124 fast = TRUE; 1125 1126 /* 1127 * See if we can use large SCBs and still maintain 1128 * the same overall count of SCBs. 1129 */ 1130 if ((ahc->features & AHC_LARGE_SCBS) != 0) { 1131 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE); 1132 test_num_scbs = ahc_probe_scbs(ahc); 1133 if (test_num_scbs >= num_scbs) { 1134 large = TRUE; 1135 num_scbs = test_num_scbs; 1136 if (num_scbs >= 64) { 1137 /* 1138 * We have enough space to move the 1139 * "busy targets table" into SCB space 1140 * and make it qualify all the way to the 1141 * lun level. 1142 */ 1143 ahc->flags |= AHC_SCB_BTT; 1144 } 1145 } 1146 } 1147 done: 1148 /* 1149 * Disable parity error reporting until we 1150 * can load instruction ram. 1151 */ 1152 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1153 /* Clear any latched parity error */ 1154 ahc_outb(ahc, CLRINT, CLRPARERR); 1155 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1156 if (bootverbose && enable) { 1157 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n", 1158 ahc_name(ahc), fast ? "fast" : "slow", 1159 pcheck ? ", parity checking enabled" : "", 1160 large ? 64 : 32); 1161 } 1162 ahc_scbram_config(ahc, enable, pcheck, fast, large); 1163 } 1164 1165 /* 1166 * Perform some simple tests that should catch situations where 1167 * our registers are invalidly mapped. 1168 */ 1169 int 1170 ahc_pci_test_register_access(struct ahc_softc *ahc) 1171 { 1172 int error; 1173 u_int status1; 1174 uint32_t cmd; 1175 uint8_t hcntrl; 1176 1177 error = EIO; 1178 1179 /* 1180 * Enable PCI error interrupt status, but suppress NMIs 1181 * generated by SERR raised due to target aborts. 1182 */ 1183 cmd = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/2); 1184 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, 1185 cmd & ~PCIM_CMD_SERRESPEN, /*bytes*/2); 1186 1187 /* 1188 * First a simple test to see if any 1189 * registers can be read. Reading 1190 * HCNTRL has no side effects and has 1191 * at least one bit that is guaranteed to 1192 * be zero so it is a good register to 1193 * use for this test. 1194 */ 1195 hcntrl = ahc_inb(ahc, HCNTRL); 1196 if (hcntrl == 0xFF) 1197 goto fail; 1198 1199 /* 1200 * Next create a situation where write combining 1201 * or read prefetching could be initiated by the 1202 * CPU or host bridge. Our device does not support 1203 * either, so look for data corruption and/or flagged 1204 * PCI errors. First pause without causing another 1205 * chip reset. 1206 */ 1207 hcntrl &= ~CHIPRST; 1208 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE); 1209 while (ahc_is_paused(ahc) == 0) 1210 ; 1211 1212 /* Clear any PCI errors that occurred before our driver attached. */ 1213 status1 = ahc_pci_read_config(ahc->dev_softc, 1214 PCIR_STATUS + 1, /*bytes*/1); 1215 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1216 status1, /*bytes*/1); 1217 ahc_outb(ahc, CLRINT, CLRPARERR); 1218 1219 ahc_outb(ahc, SEQCTL, PERRORDIS); 1220 ahc_outb(ahc, SCBPTR, 0); 1221 ahc_outl(ahc, SCB_BASE, 0x5aa555aa); 1222 if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa) 1223 goto fail; 1224 1225 status1 = ahc_pci_read_config(ahc->dev_softc, 1226 PCIR_STATUS + 1, /*bytes*/1); 1227 if ((status1 & STA) != 0) 1228 goto fail; 1229 1230 error = 0; 1231 1232 fail: 1233 /* Silently clear any latched errors. */ 1234 status1 = ahc_pci_read_config(ahc->dev_softc, 1235 PCIR_STATUS + 1, /*bytes*/1); 1236 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1237 status1, /*bytes*/1); 1238 ahc_outb(ahc, CLRINT, CLRPARERR); 1239 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS); 1240 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2); 1241 return (error); 1242 } 1243 1244 /* 1245 * Check the external port logic for a serial eeprom 1246 * and termination/cable detection contrls. 1247 */ 1248 static void 1249 check_extport(struct ahc_softc *ahc, u_int *sxfrctl1) 1250 { 1251 struct seeprom_descriptor sd; 1252 struct seeprom_config *sc; 1253 int have_seeprom; 1254 int have_autoterm; 1255 1256 sd.sd_ahc = ahc; 1257 sd.sd_control_offset = SEECTL; 1258 sd.sd_status_offset = SEECTL; 1259 sd.sd_dataout_offset = SEECTL; 1260 sc = ahc->seep_config; 1261 1262 /* 1263 * For some multi-channel devices, the c46 is simply too 1264 * small to work. For the other controller types, we can 1265 * get our information from either SEEPROM type. Set the 1266 * type to start our probe with accordingly. 1267 */ 1268 if (ahc->flags & AHC_LARGE_SEEPROM) 1269 sd.sd_chip = C56_66; 1270 else 1271 sd.sd_chip = C46; 1272 1273 sd.sd_MS = SEEMS; 1274 sd.sd_RDY = SEERDY; 1275 sd.sd_CS = SEECS; 1276 sd.sd_CK = SEECK; 1277 sd.sd_DO = SEEDO; 1278 sd.sd_DI = SEEDI; 1279 1280 have_seeprom = ahc_acquire_seeprom(ahc, &sd); 1281 if (have_seeprom) { 1282 1283 if (bootverbose) 1284 printf("%s: Reading SEEPROM...", ahc_name(ahc)); 1285 1286 for (;;) { 1287 u_int start_addr; 1288 1289 start_addr = 32 * (ahc->channel - 'A'); 1290 1291 have_seeprom = ahc_read_seeprom(&sd, (uint16_t *)sc, 1292 start_addr, 1293 sizeof(*sc)/2); 1294 1295 if (have_seeprom) 1296 have_seeprom = ahc_verify_cksum(sc); 1297 1298 if (have_seeprom != 0 || sd.sd_chip == C56_66) { 1299 if (bootverbose) { 1300 if (have_seeprom == 0) 1301 printf ("checksum error\n"); 1302 else 1303 printf ("done.\n"); 1304 } 1305 break; 1306 } 1307 sd.sd_chip = C56_66; 1308 } 1309 ahc_release_seeprom(&sd); 1310 } 1311 1312 if (!have_seeprom) { 1313 /* 1314 * Pull scratch ram settings and treat them as 1315 * if they are the contents of an seeprom if 1316 * the 'ADPT' signature is found in SCB2. 1317 * We manually compose the data as 16bit values 1318 * to avoid endian issues. 1319 */ 1320 ahc_outb(ahc, SCBPTR, 2); 1321 if (ahc_inb(ahc, SCB_BASE) == 'A' 1322 && ahc_inb(ahc, SCB_BASE + 1) == 'D' 1323 && ahc_inb(ahc, SCB_BASE + 2) == 'P' 1324 && ahc_inb(ahc, SCB_BASE + 3) == 'T') { 1325 uint16_t *sc_data; 1326 int i; 1327 1328 sc_data = (uint16_t *)sc; 1329 for (i = 0; i < 32; i++, sc_data++) { 1330 int j; 1331 1332 j = i * 2; 1333 *sc_data = ahc_inb(ahc, SRAM_BASE + j) 1334 | ahc_inb(ahc, SRAM_BASE + j + 1) << 8; 1335 } 1336 have_seeprom = ahc_verify_cksum(sc); 1337 if (have_seeprom) 1338 ahc->flags |= AHC_SCB_CONFIG_USED; 1339 } 1340 /* 1341 * Clear any SCB parity errors in case this data and 1342 * its associated parity was not initialized by the BIOS 1343 */ 1344 ahc_outb(ahc, CLRINT, CLRPARERR); 1345 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 1346 } 1347 1348 if (!have_seeprom) { 1349 if (bootverbose) 1350 printf("%s: No SEEPROM available.\n", ahc_name(ahc)); 1351 ahc->flags |= AHC_USEDEFAULTS; 1352 free(ahc->seep_config, M_DEVBUF); 1353 ahc->seep_config = NULL; 1354 sc = NULL; 1355 } else { 1356 ahc_parse_pci_eeprom(ahc, sc); 1357 } 1358 1359 /* 1360 * Cards that have the external logic necessary to talk to 1361 * a SEEPROM, are almost certain to have the remaining logic 1362 * necessary for auto-termination control. This assumption 1363 * hasn't failed yet... 1364 */ 1365 have_autoterm = have_seeprom; 1366 1367 /* 1368 * Some low-cost chips have SEEPROM and auto-term control built 1369 * in, instead of using a GAL. They can tell us directly 1370 * if the termination logic is enabled. 1371 */ 1372 if ((ahc->features & AHC_SPIOCAP) != 0) { 1373 if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) == 0) 1374 have_autoterm = FALSE; 1375 } 1376 1377 if (have_autoterm) { 1378 ahc->flags |= AHC_HAS_TERM_LOGIC; 1379 ahc_acquire_seeprom(ahc, &sd); 1380 configure_termination(ahc, &sd, sc->adapter_control, sxfrctl1); 1381 ahc_release_seeprom(&sd); 1382 } else if (have_seeprom) { 1383 *sxfrctl1 &= ~STPWEN; 1384 if ((sc->adapter_control & CFSTERM) != 0) 1385 *sxfrctl1 |= STPWEN; 1386 if (bootverbose) 1387 printf("%s: Low byte termination %sabled\n", 1388 ahc_name(ahc), 1389 (*sxfrctl1 & STPWEN) ? "en" : "dis"); 1390 } 1391 } 1392 1393 static void 1394 ahc_parse_pci_eeprom(struct ahc_softc *ahc, struct seeprom_config *sc) 1395 { 1396 /* 1397 * Put the data we've collected down into SRAM 1398 * where ahc_init will find it. 1399 */ 1400 int i; 1401 int max_targ = sc->max_targets & CFMAXTARG; 1402 u_int scsi_conf; 1403 uint16_t discenable; 1404 uint16_t ultraenb; 1405 1406 discenable = 0; 1407 ultraenb = 0; 1408 if ((sc->adapter_control & CFULTRAEN) != 0) { 1409 /* 1410 * Determine if this adapter has a "newstyle" 1411 * SEEPROM format. 1412 */ 1413 for (i = 0; i < max_targ; i++) { 1414 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) { 1415 ahc->flags |= AHC_NEWEEPROM_FMT; 1416 break; 1417 } 1418 } 1419 } 1420 1421 for (i = 0; i < max_targ; i++) { 1422 u_int scsirate; 1423 uint16_t target_mask; 1424 1425 target_mask = 0x01 << i; 1426 if (sc->device_flags[i] & CFDISC) 1427 discenable |= target_mask; 1428 if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) { 1429 if ((sc->device_flags[i] & CFSYNCHISULTRA) != 0) 1430 ultraenb |= target_mask; 1431 } else if ((sc->adapter_control & CFULTRAEN) != 0) { 1432 ultraenb |= target_mask; 1433 } 1434 if ((sc->device_flags[i] & CFXFER) == 0x04 1435 && (ultraenb & target_mask) != 0) { 1436 /* Treat 10MHz as a non-ultra speed */ 1437 sc->device_flags[i] &= ~CFXFER; 1438 ultraenb &= ~target_mask; 1439 } 1440 if ((ahc->features & AHC_ULTRA2) != 0) { 1441 u_int offset; 1442 1443 if (sc->device_flags[i] & CFSYNCH) 1444 offset = MAX_OFFSET_ULTRA2; 1445 else 1446 offset = 0; 1447 ahc_outb(ahc, TARG_OFFSET + i, offset); 1448 1449 /* 1450 * The ultra enable bits contain the 1451 * high bit of the ultra2 sync rate 1452 * field. 1453 */ 1454 scsirate = (sc->device_flags[i] & CFXFER) 1455 | ((ultraenb & target_mask) ? 0x8 : 0x0); 1456 if (sc->device_flags[i] & CFWIDEB) 1457 scsirate |= WIDEXFER; 1458 } else { 1459 scsirate = (sc->device_flags[i] & CFXFER) << 4; 1460 if (sc->device_flags[i] & CFSYNCH) 1461 scsirate |= SOFS; 1462 if (sc->device_flags[i] & CFWIDEB) 1463 scsirate |= WIDEXFER; 1464 } 1465 ahc_outb(ahc, TARG_SCSIRATE + i, scsirate); 1466 } 1467 ahc->our_id = sc->brtime_id & CFSCSIID; 1468 1469 scsi_conf = (ahc->our_id & 0x7); 1470 if (sc->adapter_control & CFSPARITY) 1471 scsi_conf |= ENSPCHK; 1472 if (sc->adapter_control & CFRESETB) 1473 scsi_conf |= RESET_SCSI; 1474 1475 ahc->flags |= (sc->adapter_control & CFBOOTCHAN) >> CFBOOTCHANSHIFT; 1476 1477 if (sc->bios_control & CFEXTEND) 1478 ahc->flags |= AHC_EXTENDED_TRANS_A; 1479 1480 if (sc->bios_control & CFBIOSEN) 1481 ahc->flags |= AHC_BIOS_ENABLED; 1482 if (ahc->features & AHC_ULTRA 1483 && (ahc->flags & AHC_NEWEEPROM_FMT) == 0) { 1484 /* Should we enable Ultra mode? */ 1485 if (!(sc->adapter_control & CFULTRAEN)) 1486 /* Treat us as a non-ultra card */ 1487 ultraenb = 0; 1488 } 1489 1490 if (sc->signature == CFSIGNATURE 1491 || sc->signature == CFSIGNATURE2) { 1492 uint32_t devconfig; 1493 1494 /* Honor the STPWLEVEL settings */ 1495 devconfig = ahc_pci_read_config(ahc->dev_softc, 1496 DEVCONFIG, /*bytes*/4); 1497 devconfig &= ~STPWLEVEL; 1498 if ((sc->bios_control & CFSTPWLEVEL) != 0) 1499 devconfig |= STPWLEVEL; 1500 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, 1501 devconfig, /*bytes*/4); 1502 } 1503 /* Set SCSICONF info */ 1504 ahc_outb(ahc, SCSICONF, scsi_conf); 1505 ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff)); 1506 ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff)); 1507 ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff); 1508 ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff); 1509 } 1510 1511 static void 1512 configure_termination(struct ahc_softc *ahc, 1513 struct seeprom_descriptor *sd, 1514 u_int adapter_control, 1515 u_int *sxfrctl1) 1516 { 1517 uint8_t brddat; 1518 1519 brddat = 0; 1520 1521 /* 1522 * Update the settings in sxfrctl1 to match the 1523 * termination settings 1524 */ 1525 *sxfrctl1 = 0; 1526 1527 /* 1528 * SEECS must be on for the GALS to latch 1529 * the data properly. Be sure to leave MS 1530 * on or we will release the seeprom. 1531 */ 1532 SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS); 1533 if ((adapter_control & CFAUTOTERM) != 0 1534 || (ahc->features & AHC_NEW_TERMCTL) != 0) { 1535 int internal50_present; 1536 int internal68_present; 1537 int externalcable_present; 1538 int eeprom_present; 1539 int enableSEC_low; 1540 int enableSEC_high; 1541 int enablePRI_low; 1542 int enablePRI_high; 1543 int sum; 1544 1545 enableSEC_low = 0; 1546 enableSEC_high = 0; 1547 enablePRI_low = 0; 1548 enablePRI_high = 0; 1549 if ((ahc->features & AHC_NEW_TERMCTL) != 0) { 1550 ahc_new_term_detect(ahc, &enableSEC_low, 1551 &enableSEC_high, 1552 &enablePRI_low, 1553 &enablePRI_high, 1554 &eeprom_present); 1555 if ((adapter_control & CFSEAUTOTERM) == 0) { 1556 if (bootverbose) 1557 printf("%s: Manual SE Termination\n", 1558 ahc_name(ahc)); 1559 enableSEC_low = (adapter_control & CFSELOWTERM); 1560 enableSEC_high = 1561 (adapter_control & CFSEHIGHTERM); 1562 } 1563 if ((adapter_control & CFAUTOTERM) == 0) { 1564 if (bootverbose) 1565 printf("%s: Manual LVD Termination\n", 1566 ahc_name(ahc)); 1567 enablePRI_low = (adapter_control & CFSTERM); 1568 enablePRI_high = (adapter_control & CFWSTERM); 1569 } 1570 /* Make the table calculations below happy */ 1571 internal50_present = 0; 1572 internal68_present = 1; 1573 externalcable_present = 1; 1574 } else if ((ahc->features & AHC_SPIOCAP) != 0) { 1575 aic785X_cable_detect(ahc, &internal50_present, 1576 &externalcable_present, 1577 &eeprom_present); 1578 /* Can never support a wide connector. */ 1579 internal68_present = 0; 1580 } else { 1581 aic787X_cable_detect(ahc, &internal50_present, 1582 &internal68_present, 1583 &externalcable_present, 1584 &eeprom_present); 1585 } 1586 1587 if ((ahc->features & AHC_WIDE) == 0) 1588 internal68_present = 0; 1589 1590 if (bootverbose 1591 && (ahc->features & AHC_ULTRA2) == 0) { 1592 printf("%s: internal 50 cable %s present", 1593 ahc_name(ahc), 1594 internal50_present ? "is":"not"); 1595 1596 if ((ahc->features & AHC_WIDE) != 0) 1597 printf(", internal 68 cable %s present", 1598 internal68_present ? "is":"not"); 1599 printf("\n%s: external cable %s present\n", 1600 ahc_name(ahc), 1601 externalcable_present ? "is":"not"); 1602 } 1603 if (bootverbose) 1604 printf("%s: BIOS eeprom %s present\n", 1605 ahc_name(ahc), eeprom_present ? "is" : "not"); 1606 1607 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) { 1608 /* 1609 * The 50 pin connector is a separate bus, 1610 * so force it to always be terminated. 1611 * In the future, perform current sensing 1612 * to determine if we are in the middle of 1613 * a properly terminated bus. 1614 */ 1615 internal50_present = 0; 1616 } 1617 1618 /* 1619 * Now set the termination based on what 1620 * we found. 1621 * Flash Enable = BRDDAT7 1622 * Secondary High Term Enable = BRDDAT6 1623 * Secondary Low Term Enable = BRDDAT5 (7890) 1624 * Primary High Term Enable = BRDDAT4 (7890) 1625 */ 1626 if ((ahc->features & AHC_ULTRA2) == 0 1627 && (internal50_present != 0) 1628 && (internal68_present != 0) 1629 && (externalcable_present != 0)) { 1630 printf("%s: Illegal cable configuration!!. " 1631 "Only two connectors on the " 1632 "adapter may be used at a " 1633 "time!\n", ahc_name(ahc)); 1634 1635 /* 1636 * Pretend there are no cables in the hope 1637 * that having all of the termination on 1638 * gives us a more stable bus. 1639 */ 1640 internal50_present = 0; 1641 internal68_present = 0; 1642 externalcable_present = 0; 1643 } 1644 1645 if ((ahc->features & AHC_WIDE) != 0 1646 && ((externalcable_present == 0) 1647 || (internal68_present == 0) 1648 || (enableSEC_high != 0))) { 1649 brddat |= BRDDAT6; 1650 if (bootverbose) { 1651 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1652 printf("%s: 68 pin termination " 1653 "Enabled\n", ahc_name(ahc)); 1654 else 1655 printf("%s: %sHigh byte termination " 1656 "Enabled\n", ahc_name(ahc), 1657 enableSEC_high ? "Secondary " 1658 : ""); 1659 } 1660 } 1661 1662 sum = internal50_present + internal68_present 1663 + externalcable_present; 1664 if (sum < 2 || (enableSEC_low != 0)) { 1665 if ((ahc->features & AHC_ULTRA2) != 0) 1666 brddat |= BRDDAT5; 1667 else 1668 *sxfrctl1 |= STPWEN; 1669 if (bootverbose) { 1670 if ((ahc->flags & AHC_INT50_SPEEDFLEX) != 0) 1671 printf("%s: 50 pin termination " 1672 "Enabled\n", ahc_name(ahc)); 1673 else 1674 printf("%s: %sLow byte termination " 1675 "Enabled\n", ahc_name(ahc), 1676 enableSEC_low ? "Secondary " 1677 : ""); 1678 } 1679 } 1680 1681 if (enablePRI_low != 0) { 1682 *sxfrctl1 |= STPWEN; 1683 if (bootverbose) 1684 printf("%s: Primary Low Byte termination " 1685 "Enabled\n", ahc_name(ahc)); 1686 } 1687 1688 /* 1689 * Setup STPWEN before setting up the rest of 1690 * the termination per the tech note on the U160 cards. 1691 */ 1692 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1693 1694 if (enablePRI_high != 0) { 1695 brddat |= BRDDAT4; 1696 if (bootverbose) 1697 printf("%s: Primary High Byte " 1698 "termination Enabled\n", 1699 ahc_name(ahc)); 1700 } 1701 1702 write_brdctl(ahc, brddat); 1703 1704 } else { 1705 if ((adapter_control & CFSTERM) != 0) { 1706 *sxfrctl1 |= STPWEN; 1707 1708 if (bootverbose) 1709 printf("%s: %sLow byte termination Enabled\n", 1710 ahc_name(ahc), 1711 (ahc->features & AHC_ULTRA2) ? "Primary " 1712 : ""); 1713 } 1714 1715 if ((adapter_control & CFWSTERM) != 0 1716 && (ahc->features & AHC_WIDE) != 0) { 1717 brddat |= BRDDAT6; 1718 if (bootverbose) 1719 printf("%s: %sHigh byte termination Enabled\n", 1720 ahc_name(ahc), 1721 (ahc->features & AHC_ULTRA2) 1722 ? "Secondary " : ""); 1723 } 1724 1725 /* 1726 * Setup STPWEN before setting up the rest of 1727 * the termination per the tech note on the U160 cards. 1728 */ 1729 ahc_outb(ahc, SXFRCTL1, *sxfrctl1); 1730 1731 if ((ahc->features & AHC_WIDE) != 0) 1732 write_brdctl(ahc, brddat); 1733 } 1734 SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */ 1735 } 1736 1737 static void 1738 ahc_new_term_detect(struct ahc_softc *ahc, int *enableSEC_low, 1739 int *enableSEC_high, int *enablePRI_low, 1740 int *enablePRI_high, int *eeprom_present) 1741 { 1742 uint8_t brdctl; 1743 1744 /* 1745 * BRDDAT7 = Eeprom 1746 * BRDDAT6 = Enable Secondary High Byte termination 1747 * BRDDAT5 = Enable Secondary Low Byte termination 1748 * BRDDAT4 = Enable Primary high byte termination 1749 * BRDDAT3 = Enable Primary low byte termination 1750 */ 1751 brdctl = read_brdctl(ahc); 1752 *eeprom_present = brdctl & BRDDAT7; 1753 *enableSEC_high = (brdctl & BRDDAT6); 1754 *enableSEC_low = (brdctl & BRDDAT5); 1755 *enablePRI_high = (brdctl & BRDDAT4); 1756 *enablePRI_low = (brdctl & BRDDAT3); 1757 } 1758 1759 static void 1760 aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1761 int *internal68_present, int *externalcable_present, 1762 int *eeprom_present) 1763 { 1764 uint8_t brdctl; 1765 1766 /* 1767 * First read the status of our cables. 1768 * Set the rom bank to 0 since the 1769 * bank setting serves as a multiplexor 1770 * for the cable detection logic. 1771 * BRDDAT5 controls the bank switch. 1772 */ 1773 write_brdctl(ahc, 0); 1774 1775 /* 1776 * Now read the state of the internal 1777 * connectors. BRDDAT6 is INT50 and 1778 * BRDDAT7 is INT68. 1779 */ 1780 brdctl = read_brdctl(ahc); 1781 *internal50_present = (brdctl & BRDDAT6) ? 0 : 1; 1782 *internal68_present = (brdctl & BRDDAT7) ? 0 : 1; 1783 1784 /* 1785 * Set the rom bank to 1 and determine 1786 * the other signals. 1787 */ 1788 write_brdctl(ahc, BRDDAT5); 1789 1790 /* 1791 * Now read the state of the external 1792 * connectors. BRDDAT6 is EXT68 and 1793 * BRDDAT7 is EPROMPS. 1794 */ 1795 brdctl = read_brdctl(ahc); 1796 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1; 1797 *eeprom_present = (brdctl & BRDDAT7) ? 1 : 0; 1798 } 1799 1800 static void 1801 aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present, 1802 int *externalcable_present, int *eeprom_present) 1803 { 1804 uint8_t brdctl; 1805 uint8_t spiocap; 1806 1807 spiocap = ahc_inb(ahc, SPIOCAP); 1808 spiocap &= ~SOFTCMDEN; 1809 spiocap |= EXT_BRDCTL; 1810 ahc_outb(ahc, SPIOCAP, spiocap); 1811 ahc_outb(ahc, BRDCTL, BRDRW|BRDCS); 1812 ahc_flush_device_writes(ahc); 1813 ahc_delay(500); 1814 ahc_outb(ahc, BRDCTL, 0); 1815 ahc_flush_device_writes(ahc); 1816 ahc_delay(500); 1817 brdctl = ahc_inb(ahc, BRDCTL); 1818 *internal50_present = (brdctl & BRDDAT5) ? 0 : 1; 1819 *externalcable_present = (brdctl & BRDDAT6) ? 0 : 1; 1820 *eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) ? 1 : 0; 1821 } 1822 1823 int 1824 ahc_acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd) 1825 { 1826 int wait; 1827 1828 if ((ahc->features & AHC_SPIOCAP) != 0 1829 && (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0) 1830 return (0); 1831 1832 /* 1833 * Request access of the memory port. When access is 1834 * granted, SEERDY will go high. We use a 1 second 1835 * timeout which should be near 1 second more than 1836 * is needed. Reason: after the chip reset, there 1837 * should be no contention. 1838 */ 1839 SEEPROM_OUTB(sd, sd->sd_MS); 1840 wait = 1000; /* 1 second timeout in msec */ 1841 while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) { 1842 ahc_delay(1000); /* delay 1 msec */ 1843 } 1844 if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) { 1845 SEEPROM_OUTB(sd, 0); 1846 return (0); 1847 } 1848 return(1); 1849 } 1850 1851 void 1852 ahc_release_seeprom(struct seeprom_descriptor *sd) 1853 { 1854 /* Release access to the memory port and the serial EEPROM. */ 1855 SEEPROM_OUTB(sd, 0); 1856 } 1857 1858 static void 1859 write_brdctl(struct ahc_softc *ahc, uint8_t value) 1860 { 1861 uint8_t brdctl; 1862 1863 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1864 brdctl = BRDSTB; 1865 if (ahc->channel == 'B') 1866 brdctl |= BRDCS; 1867 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1868 brdctl = 0; 1869 } else { 1870 brdctl = BRDSTB|BRDCS; 1871 } 1872 ahc_outb(ahc, BRDCTL, brdctl); 1873 ahc_flush_device_writes(ahc); 1874 brdctl |= value; 1875 ahc_outb(ahc, BRDCTL, brdctl); 1876 ahc_flush_device_writes(ahc); 1877 if ((ahc->features & AHC_ULTRA2) != 0) 1878 brdctl |= BRDSTB_ULTRA2; 1879 else 1880 brdctl &= ~BRDSTB; 1881 ahc_outb(ahc, BRDCTL, brdctl); 1882 ahc_flush_device_writes(ahc); 1883 if ((ahc->features & AHC_ULTRA2) != 0) 1884 brdctl = 0; 1885 else 1886 brdctl &= ~BRDCS; 1887 ahc_outb(ahc, BRDCTL, brdctl); 1888 } 1889 1890 static uint8_t 1891 read_brdctl(struct ahc_softc *ahc) 1892 { 1893 uint8_t brdctl; 1894 uint8_t value; 1895 1896 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) { 1897 brdctl = BRDRW; 1898 if (ahc->channel == 'B') 1899 brdctl |= BRDCS; 1900 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1901 brdctl = BRDRW_ULTRA2; 1902 } else { 1903 brdctl = BRDRW|BRDCS; 1904 } 1905 ahc_outb(ahc, BRDCTL, brdctl); 1906 ahc_flush_device_writes(ahc); 1907 value = ahc_inb(ahc, BRDCTL); 1908 ahc_outb(ahc, BRDCTL, 0); 1909 return (value); 1910 } 1911 1912 static void 1913 ahc_pci_intr(struct ahc_softc *ahc) 1914 { 1915 u_int error; 1916 u_int status1; 1917 1918 error = ahc_inb(ahc, ERROR); 1919 if ((error & PCIERRSTAT) == 0) 1920 return; 1921 1922 status1 = ahc_pci_read_config(ahc->dev_softc, 1923 PCIR_STATUS + 1, /*bytes*/1); 1924 1925 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n", 1926 ahc_name(ahc), 1927 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 1928 1929 if (status1 & DPE) { 1930 ahc->pci_target_perr_count++; 1931 printf("%s: Data Parity Error Detected during address " 1932 "or write data phase\n", ahc_name(ahc)); 1933 } 1934 if (status1 & SSE) { 1935 printf("%s: Signal System Error Detected\n", ahc_name(ahc)); 1936 } 1937 if (status1 & RMA) { 1938 printf("%s: Received a Master Abort\n", ahc_name(ahc)); 1939 } 1940 if (status1 & RTA) { 1941 printf("%s: Received a Target Abort\n", ahc_name(ahc)); 1942 } 1943 if (status1 & STA) { 1944 printf("%s: Signaled a Target Abort\n", ahc_name(ahc)); 1945 } 1946 if (status1 & DPR) { 1947 printf("%s: Data Parity Error has been reported via PERR#\n", 1948 ahc_name(ahc)); 1949 } 1950 1951 /* Clear latched errors. */ 1952 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1, 1953 status1, /*bytes*/1); 1954 1955 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { 1956 printf("%s: Latched PCIERR interrupt with " 1957 "no status bits set\n", ahc_name(ahc)); 1958 } else { 1959 ahc_outb(ahc, CLRINT, CLRPARERR); 1960 } 1961 1962 if (ahc->pci_target_perr_count > AHC_PCI_TARGET_PERR_THRESH) { 1963 printf( 1964 "%s: WARNING WARNING WARNING WARNING\n" 1965 "%s: Too many PCI parity errors observed as a target.\n" 1966 "%s: Some device on this bus is generating bad parity.\n" 1967 "%s: This is an error *observed by*, not *generated by*, this controller.\n" 1968 "%s: PCI parity error checking has been disabled.\n" 1969 "%s: WARNING WARNING WARNING WARNING\n", 1970 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc), 1971 ahc_name(ahc), ahc_name(ahc), ahc_name(ahc)); 1972 ahc->seqctl |= FAILDIS; 1973 ahc_outb(ahc, SEQCTL, ahc->seqctl); 1974 } 1975 ahc_unpause(ahc); 1976 } 1977 1978 static int 1979 ahc_pci_chip_init(struct ahc_softc *ahc) 1980 { 1981 ahc_outb(ahc, DSCOMMAND0, ahc->bus_softc.pci_softc.dscommand0); 1982 ahc_outb(ahc, DSPCISTATUS, ahc->bus_softc.pci_softc.dspcistatus); 1983 if ((ahc->features & AHC_DT) != 0) { 1984 u_int sfunct; 1985 1986 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE; 1987 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE); 1988 ahc_outb(ahc, OPTIONMODE, ahc->bus_softc.pci_softc.optionmode); 1989 ahc_outw(ahc, TARGCRCCNT, ahc->bus_softc.pci_softc.targcrccnt); 1990 ahc_outb(ahc, SFUNCT, sfunct); 1991 ahc_outb(ahc, CRCCONTROL1, 1992 ahc->bus_softc.pci_softc.crccontrol1); 1993 } 1994 if ((ahc->features & AHC_MULTI_FUNC) != 0) 1995 ahc_outb(ahc, SCBBADDR, ahc->bus_softc.pci_softc.scbbaddr); 1996 1997 if ((ahc->features & AHC_ULTRA2) != 0) 1998 ahc_outb(ahc, DFF_THRSH, ahc->bus_softc.pci_softc.dff_thrsh); 1999 2000 return (ahc_chip_init(ahc)); 2001 } 2002 2003 static int 2004 ahc_pci_suspend(struct ahc_softc *ahc) 2005 { 2006 return (ahc_suspend(ahc)); 2007 } 2008 2009 static int 2010 ahc_pci_resume(struct ahc_softc *ahc) 2011 { 2012 2013 pci_set_power_state(ahc->dev_softc, AHC_POWER_STATE_D0); 2014 2015 /* 2016 * We assume that the OS has restored our register 2017 * mappings, etc. Just update the config space registers 2018 * that the OS doesn't know about and rely on our chip 2019 * reset handler to handle the rest. 2020 */ 2021 ahc_pci_write_config(ahc->dev_softc, DEVCONFIG, /*bytes*/4, 2022 ahc->bus_softc.pci_softc.devconfig); 2023 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, /*bytes*/1, 2024 ahc->bus_softc.pci_softc.command); 2025 ahc_pci_write_config(ahc->dev_softc, CSIZE_LATTIME, /*bytes*/1, 2026 ahc->bus_softc.pci_softc.csize_lattime); 2027 if ((ahc->flags & AHC_HAS_TERM_LOGIC) != 0) { 2028 struct seeprom_descriptor sd; 2029 u_int sxfrctl1; 2030 2031 sd.sd_ahc = ahc; 2032 sd.sd_control_offset = SEECTL; 2033 sd.sd_status_offset = SEECTL; 2034 sd.sd_dataout_offset = SEECTL; 2035 2036 ahc_acquire_seeprom(ahc, &sd); 2037 configure_termination(ahc, &sd, 2038 ahc->seep_config->adapter_control, 2039 &sxfrctl1); 2040 ahc_release_seeprom(&sd); 2041 } 2042 return (ahc_resume(ahc)); 2043 } 2044 2045 static int 2046 ahc_aic785X_setup(struct ahc_softc *ahc) 2047 { 2048 ahc_dev_softc_t pci; 2049 uint8_t rev; 2050 2051 pci = ahc->dev_softc; 2052 ahc->channel = 'A'; 2053 ahc->chip = AHC_AIC7850; 2054 ahc->features = AHC_AIC7850_FE; 2055 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2056 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2057 if (rev >= 1) 2058 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 2059 ahc->instruction_ram_size = 512; 2060 return (0); 2061 } 2062 2063 static int 2064 ahc_aic7860_setup(struct ahc_softc *ahc) 2065 { 2066 ahc_dev_softc_t pci; 2067 uint8_t rev; 2068 2069 pci = ahc->dev_softc; 2070 ahc->channel = 'A'; 2071 ahc->chip = AHC_AIC7860; 2072 ahc->features = AHC_AIC7860_FE; 2073 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2074 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2075 if (rev >= 1) 2076 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 2077 ahc->instruction_ram_size = 512; 2078 return (0); 2079 } 2080 2081 static int 2082 ahc_apa1480_setup(struct ahc_softc *ahc) 2083 { 2084 int error; 2085 2086 error = ahc_aic7860_setup(ahc); 2087 if (error != 0) 2088 return (error); 2089 ahc->features |= AHC_REMOVABLE; 2090 return (0); 2091 } 2092 2093 static int 2094 ahc_aic7870_setup(struct ahc_softc *ahc) 2095 { 2096 2097 ahc->channel = 'A'; 2098 ahc->chip = AHC_AIC7870; 2099 ahc->features = AHC_AIC7870_FE; 2100 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2101 ahc->instruction_ram_size = 512; 2102 return (0); 2103 } 2104 2105 static int 2106 ahc_aha394X_setup(struct ahc_softc *ahc) 2107 { 2108 int error; 2109 2110 error = ahc_aic7870_setup(ahc); 2111 if (error == 0) 2112 error = ahc_aha394XX_setup(ahc); 2113 return (error); 2114 } 2115 2116 static int 2117 ahc_aha398X_setup(struct ahc_softc *ahc) 2118 { 2119 int error; 2120 2121 error = ahc_aic7870_setup(ahc); 2122 if (error == 0) 2123 error = ahc_aha398XX_setup(ahc); 2124 return (error); 2125 } 2126 2127 static int 2128 ahc_aha494X_setup(struct ahc_softc *ahc) 2129 { 2130 int error; 2131 2132 error = ahc_aic7870_setup(ahc); 2133 if (error == 0) 2134 error = ahc_aha494XX_setup(ahc); 2135 return (error); 2136 } 2137 2138 static int 2139 ahc_aic7880_setup(struct ahc_softc *ahc) 2140 { 2141 ahc_dev_softc_t pci; 2142 uint8_t rev; 2143 2144 pci = ahc->dev_softc; 2145 ahc->channel = 'A'; 2146 ahc->chip = AHC_AIC7880; 2147 ahc->features = AHC_AIC7880_FE; 2148 ahc->bugs |= AHC_TMODE_WIDEODD_BUG; 2149 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2150 if (rev >= 1) { 2151 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG; 2152 } else { 2153 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG; 2154 } 2155 ahc->instruction_ram_size = 512; 2156 return (0); 2157 } 2158 2159 static int 2160 ahc_aha2940Pro_setup(struct ahc_softc *ahc) 2161 { 2162 2163 ahc->flags |= AHC_INT50_SPEEDFLEX; 2164 return (ahc_aic7880_setup(ahc)); 2165 } 2166 2167 static int 2168 ahc_aha394XU_setup(struct ahc_softc *ahc) 2169 { 2170 int error; 2171 2172 error = ahc_aic7880_setup(ahc); 2173 if (error == 0) 2174 error = ahc_aha394XX_setup(ahc); 2175 return (error); 2176 } 2177 2178 static int 2179 ahc_aha398XU_setup(struct ahc_softc *ahc) 2180 { 2181 int error; 2182 2183 error = ahc_aic7880_setup(ahc); 2184 if (error == 0) 2185 error = ahc_aha398XX_setup(ahc); 2186 return (error); 2187 } 2188 2189 static int 2190 ahc_aic7890_setup(struct ahc_softc *ahc) 2191 { 2192 ahc_dev_softc_t pci; 2193 uint8_t rev; 2194 2195 pci = ahc->dev_softc; 2196 ahc->channel = 'A'; 2197 ahc->chip = AHC_AIC7890; 2198 ahc->features = AHC_AIC7890_FE; 2199 ahc->flags |= AHC_NEWEEPROM_FMT; 2200 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2201 if (rev == 0) 2202 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG; 2203 ahc->instruction_ram_size = 768; 2204 return (0); 2205 } 2206 2207 static int 2208 ahc_aic7892_setup(struct ahc_softc *ahc) 2209 { 2210 2211 ahc->channel = 'A'; 2212 ahc->chip = AHC_AIC7892; 2213 ahc->features = AHC_AIC7892_FE; 2214 ahc->flags |= AHC_NEWEEPROM_FMT; 2215 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 2216 ahc->instruction_ram_size = 1024; 2217 return (0); 2218 } 2219 2220 static int 2221 ahc_aic7895_setup(struct ahc_softc *ahc) 2222 { 2223 ahc_dev_softc_t pci; 2224 uint8_t rev; 2225 2226 pci = ahc->dev_softc; 2227 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 2228 /* 2229 * The 'C' revision of the aic7895 has a few additional features. 2230 */ 2231 rev = ahc_pci_read_config(pci, PCIR_REVID, /*bytes*/1); 2232 if (rev >= 4) { 2233 ahc->chip = AHC_AIC7895C; 2234 ahc->features = AHC_AIC7895C_FE; 2235 } else { 2236 u_int command; 2237 2238 ahc->chip = AHC_AIC7895; 2239 ahc->features = AHC_AIC7895_FE; 2240 2241 /* 2242 * The BIOS disables the use of MWI transactions 2243 * since it does not have the MWI bug work around 2244 * we have. Disabling MWI reduces performance, so 2245 * turn it on again. 2246 */ 2247 command = ahc_pci_read_config(pci, PCIR_COMMAND, /*bytes*/1); 2248 command |= PCIM_CMD_MWRICEN; 2249 ahc_pci_write_config(pci, PCIR_COMMAND, command, /*bytes*/1); 2250 ahc->bugs |= AHC_PCI_MWI_BUG; 2251 } 2252 /* 2253 * XXX Does CACHETHEN really not work??? What about PCI retry? 2254 * on C level chips. Need to test, but for now, play it safe. 2255 */ 2256 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG 2257 | AHC_CACHETHEN_BUG; 2258 2259 #if 0 2260 uint32_t devconfig; 2261 2262 /* 2263 * Cachesize must also be zero due to stray DAC 2264 * problem when sitting behind some bridges. 2265 */ 2266 ahc_pci_write_config(pci, CSIZE_LATTIME, 0, /*bytes*/1); 2267 devconfig = ahc_pci_read_config(pci, DEVCONFIG, /*bytes*/1); 2268 devconfig |= MRDCEN; 2269 ahc_pci_write_config(pci, DEVCONFIG, devconfig, /*bytes*/1); 2270 #endif 2271 ahc->flags |= AHC_NEWEEPROM_FMT; 2272 ahc->instruction_ram_size = 512; 2273 return (0); 2274 } 2275 2276 static int 2277 ahc_aic7896_setup(struct ahc_softc *ahc) 2278 { 2279 ahc_dev_softc_t pci; 2280 2281 pci = ahc->dev_softc; 2282 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 2283 ahc->chip = AHC_AIC7896; 2284 ahc->features = AHC_AIC7896_FE; 2285 ahc->flags |= AHC_NEWEEPROM_FMT; 2286 ahc->bugs |= AHC_CACHETHEN_DIS_BUG; 2287 ahc->instruction_ram_size = 768; 2288 return (0); 2289 } 2290 2291 static int 2292 ahc_aic7899_setup(struct ahc_softc *ahc) 2293 { 2294 ahc_dev_softc_t pci; 2295 2296 pci = ahc->dev_softc; 2297 ahc->channel = ahc_get_pci_function(pci) == 1 ? 'B' : 'A'; 2298 ahc->chip = AHC_AIC7899; 2299 ahc->features = AHC_AIC7899_FE; 2300 ahc->flags |= AHC_NEWEEPROM_FMT; 2301 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG; 2302 ahc->instruction_ram_size = 1024; 2303 return (0); 2304 } 2305 2306 static int 2307 ahc_aha29160C_setup(struct ahc_softc *ahc) 2308 { 2309 int error; 2310 2311 error = ahc_aic7899_setup(ahc); 2312 if (error != 0) 2313 return (error); 2314 ahc->features |= AHC_REMOVABLE; 2315 return (0); 2316 } 2317 2318 static int 2319 ahc_raid_setup(struct ahc_softc *ahc) 2320 { 2321 printf("RAID functionality unsupported\n"); 2322 return (ENXIO); 2323 } 2324 2325 static int 2326 ahc_aha394XX_setup(struct ahc_softc *ahc) 2327 { 2328 ahc_dev_softc_t pci; 2329 2330 pci = ahc->dev_softc; 2331 switch (ahc_get_pci_slot(pci)) { 2332 case AHC_394X_SLOT_CHANNEL_A: 2333 ahc->channel = 'A'; 2334 break; 2335 case AHC_394X_SLOT_CHANNEL_B: 2336 ahc->channel = 'B'; 2337 break; 2338 default: 2339 printf("adapter at unexpected slot %d\n" 2340 "unable to map to a channel\n", 2341 ahc_get_pci_slot(pci)); 2342 ahc->channel = 'A'; 2343 } 2344 return (0); 2345 } 2346 2347 static int 2348 ahc_aha398XX_setup(struct ahc_softc *ahc) 2349 { 2350 ahc_dev_softc_t pci; 2351 2352 pci = ahc->dev_softc; 2353 switch (ahc_get_pci_slot(pci)) { 2354 case AHC_398X_SLOT_CHANNEL_A: 2355 ahc->channel = 'A'; 2356 break; 2357 case AHC_398X_SLOT_CHANNEL_B: 2358 ahc->channel = 'B'; 2359 break; 2360 case AHC_398X_SLOT_CHANNEL_C: 2361 ahc->channel = 'C'; 2362 break; 2363 default: 2364 printf("adapter at unexpected slot %d\n" 2365 "unable to map to a channel\n", 2366 ahc_get_pci_slot(pci)); 2367 ahc->channel = 'A'; 2368 break; 2369 } 2370 ahc->flags |= AHC_LARGE_SEEPROM; 2371 return (0); 2372 } 2373 2374 static int 2375 ahc_aha494XX_setup(struct ahc_softc *ahc) 2376 { 2377 ahc_dev_softc_t pci; 2378 2379 pci = ahc->dev_softc; 2380 switch (ahc_get_pci_slot(pci)) { 2381 case AHC_494X_SLOT_CHANNEL_A: 2382 ahc->channel = 'A'; 2383 break; 2384 case AHC_494X_SLOT_CHANNEL_B: 2385 ahc->channel = 'B'; 2386 break; 2387 case AHC_494X_SLOT_CHANNEL_C: 2388 ahc->channel = 'C'; 2389 break; 2390 case AHC_494X_SLOT_CHANNEL_D: 2391 ahc->channel = 'D'; 2392 break; 2393 default: 2394 printf("adapter at unexpected slot %d\n" 2395 "unable to map to a channel\n", 2396 ahc_get_pci_slot(pci)); 2397 ahc->channel = 'A'; 2398 } 2399 ahc->flags |= AHC_LARGE_SEEPROM; 2400 return (0); 2401 } 2402