1 /* 2 * Core routines and tables shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2002 Justin T. Gibbs. 5 * Copyright (c) 2000-2002 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.c#155 $ 41 */ 42 43 #include "aic7xxx_osm.h" 44 #include "aic7xxx_inline.h" 45 #include "aicasm/aicasm_insformat.h" 46 47 /***************************** Lookup Tables **********************************/ 48 static const char *const ahc_chip_names[] = { 49 "NONE", 50 "aic7770", 51 "aic7850", 52 "aic7855", 53 "aic7859", 54 "aic7860", 55 "aic7870", 56 "aic7880", 57 "aic7895", 58 "aic7895C", 59 "aic7890/91", 60 "aic7896/97", 61 "aic7892", 62 "aic7899" 63 }; 64 65 /* 66 * Hardware error codes. 67 */ 68 struct ahc_hard_error_entry { 69 uint8_t errno; 70 const char *errmesg; 71 }; 72 73 static const struct ahc_hard_error_entry ahc_hard_errors[] = { 74 { ILLHADDR, "Illegal Host Access" }, 75 { ILLSADDR, "Illegal Sequencer Address referenced" }, 76 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 77 { SQPARERR, "Sequencer Parity Error" }, 78 { DPARERR, "Data-path Parity Error" }, 79 { MPARERR, "Scratch or SCB Memory Parity Error" }, 80 { PCIERRSTAT, "PCI Error detected" }, 81 { CIOPARERR, "CIOBUS Parity Error" }, 82 }; 83 static const u_int num_errors = ARRAY_SIZE(ahc_hard_errors); 84 85 static const struct ahc_phase_table_entry ahc_phase_table[] = 86 { 87 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 88 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 89 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" }, 90 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" }, 91 { P_COMMAND, MSG_NOOP, "in Command phase" }, 92 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 93 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 94 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 95 { P_BUSFREE, MSG_NOOP, "while idle" }, 96 { 0, MSG_NOOP, "in unknown phase" } 97 }; 98 99 /* 100 * In most cases we only wish to itterate over real phases, so 101 * exclude the last element from the count. 102 */ 103 static const u_int num_phases = ARRAY_SIZE(ahc_phase_table) - 1; 104 105 /* 106 * Valid SCSIRATE values. (p. 3-17) 107 * Provides a mapping of tranfer periods in ns to the proper value to 108 * stick in the scsixfer reg. 109 */ 110 static const struct ahc_syncrate ahc_syncrates[] = 111 { 112 /* ultra2 fast/ultra period rate */ 113 { 0x42, 0x000, 9, "80.0" }, 114 { 0x03, 0x000, 10, "40.0" }, 115 { 0x04, 0x000, 11, "33.0" }, 116 { 0x05, 0x100, 12, "20.0" }, 117 { 0x06, 0x110, 15, "16.0" }, 118 { 0x07, 0x120, 18, "13.4" }, 119 { 0x08, 0x000, 25, "10.0" }, 120 { 0x19, 0x010, 31, "8.0" }, 121 { 0x1a, 0x020, 37, "6.67" }, 122 { 0x1b, 0x030, 43, "5.7" }, 123 { 0x1c, 0x040, 50, "5.0" }, 124 { 0x00, 0x050, 56, "4.4" }, 125 { 0x00, 0x060, 62, "4.0" }, 126 { 0x00, 0x070, 68, "3.6" }, 127 { 0x00, 0x000, 0, NULL } 128 }; 129 130 /* Our Sequencer Program */ 131 #include "aic7xxx_seq.h" 132 133 /**************************** Function Declarations ***************************/ 134 static void ahc_force_renegotiation(struct ahc_softc *ahc, 135 struct ahc_devinfo *devinfo); 136 static struct ahc_tmode_tstate* 137 ahc_alloc_tstate(struct ahc_softc *ahc, 138 u_int scsi_id, char channel); 139 #ifdef AHC_TARGET_MODE 140 static void ahc_free_tstate(struct ahc_softc *ahc, 141 u_int scsi_id, char channel, int force); 142 #endif 143 static const struct ahc_syncrate* 144 ahc_devlimited_syncrate(struct ahc_softc *ahc, 145 struct ahc_initiator_tinfo *, 146 u_int *period, 147 u_int *ppr_options, 148 role_t role); 149 static void ahc_update_pending_scbs(struct ahc_softc *ahc); 150 static void ahc_fetch_devinfo(struct ahc_softc *ahc, 151 struct ahc_devinfo *devinfo); 152 static void ahc_scb_devinfo(struct ahc_softc *ahc, 153 struct ahc_devinfo *devinfo, 154 struct scb *scb); 155 static void ahc_assert_atn(struct ahc_softc *ahc); 156 static void ahc_setup_initiator_msgout(struct ahc_softc *ahc, 157 struct ahc_devinfo *devinfo, 158 struct scb *scb); 159 static void ahc_build_transfer_msg(struct ahc_softc *ahc, 160 struct ahc_devinfo *devinfo); 161 static void ahc_construct_sdtr(struct ahc_softc *ahc, 162 struct ahc_devinfo *devinfo, 163 u_int period, u_int offset); 164 static void ahc_construct_wdtr(struct ahc_softc *ahc, 165 struct ahc_devinfo *devinfo, 166 u_int bus_width); 167 static void ahc_construct_ppr(struct ahc_softc *ahc, 168 struct ahc_devinfo *devinfo, 169 u_int period, u_int offset, 170 u_int bus_width, u_int ppr_options); 171 static void ahc_clear_msg_state(struct ahc_softc *ahc); 172 static void ahc_handle_proto_violation(struct ahc_softc *ahc); 173 static void ahc_handle_message_phase(struct ahc_softc *ahc); 174 typedef enum { 175 AHCMSG_1B, 176 AHCMSG_2B, 177 AHCMSG_EXT 178 } ahc_msgtype; 179 static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, 180 u_int msgval, int full); 181 static int ahc_parse_msg(struct ahc_softc *ahc, 182 struct ahc_devinfo *devinfo); 183 static int ahc_handle_msg_reject(struct ahc_softc *ahc, 184 struct ahc_devinfo *devinfo); 185 static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc, 186 struct ahc_devinfo *devinfo); 187 static void ahc_reinitialize_dataptrs(struct ahc_softc *ahc); 188 static void ahc_handle_devreset(struct ahc_softc *ahc, 189 struct ahc_devinfo *devinfo, 190 cam_status status, char *message, 191 int verbose_level); 192 #ifdef AHC_TARGET_MODE 193 static void ahc_setup_target_msgin(struct ahc_softc *ahc, 194 struct ahc_devinfo *devinfo, 195 struct scb *scb); 196 #endif 197 198 static bus_dmamap_callback_t ahc_dmamap_cb; 199 static void ahc_build_free_scb_list(struct ahc_softc *ahc); 200 static int ahc_init_scbdata(struct ahc_softc *ahc); 201 static void ahc_fini_scbdata(struct ahc_softc *ahc); 202 static void ahc_qinfifo_requeue(struct ahc_softc *ahc, 203 struct scb *prev_scb, 204 struct scb *scb); 205 static int ahc_qinfifo_count(struct ahc_softc *ahc); 206 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, 207 u_int prev, u_int scbptr); 208 static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc); 209 static u_int ahc_rem_wscb(struct ahc_softc *ahc, 210 u_int scbpos, u_int prev); 211 static void ahc_reset_current_bus(struct ahc_softc *ahc); 212 #ifdef AHC_DUMP_SEQ 213 static void ahc_dumpseq(struct ahc_softc *ahc); 214 #endif 215 static int ahc_loadseq(struct ahc_softc *ahc); 216 static int ahc_check_patch(struct ahc_softc *ahc, 217 const struct patch **start_patch, 218 u_int start_instr, u_int *skip_addr); 219 static void ahc_download_instr(struct ahc_softc *ahc, 220 u_int instrptr, uint8_t *dconsts); 221 #ifdef AHC_TARGET_MODE 222 static void ahc_queue_lstate_event(struct ahc_softc *ahc, 223 struct ahc_tmode_lstate *lstate, 224 u_int initiator_id, 225 u_int event_type, 226 u_int event_arg); 227 static void ahc_update_scsiid(struct ahc_softc *ahc, 228 u_int targid_mask); 229 static int ahc_handle_target_cmd(struct ahc_softc *ahc, 230 struct target_cmd *cmd); 231 #endif 232 233 static u_int ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl); 234 static void ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl); 235 static void ahc_busy_tcl(struct ahc_softc *ahc, 236 u_int tcl, u_int busyid); 237 238 /************************** SCB and SCB queue management **********************/ 239 static void ahc_run_untagged_queues(struct ahc_softc *ahc); 240 static void ahc_run_untagged_queue(struct ahc_softc *ahc, 241 struct scb_tailq *queue); 242 243 /****************************** Initialization ********************************/ 244 static void ahc_alloc_scbs(struct ahc_softc *ahc); 245 static void ahc_shutdown(void *arg); 246 247 /*************************** Interrupt Services *******************************/ 248 static void ahc_clear_intstat(struct ahc_softc *ahc); 249 static void ahc_run_qoutfifo(struct ahc_softc *ahc); 250 #ifdef AHC_TARGET_MODE 251 static void ahc_run_tqinfifo(struct ahc_softc *ahc, int paused); 252 #endif 253 static void ahc_handle_brkadrint(struct ahc_softc *ahc); 254 static void ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat); 255 static void ahc_handle_scsiint(struct ahc_softc *ahc, 256 u_int intstat); 257 static void ahc_clear_critical_section(struct ahc_softc *ahc); 258 259 /***************************** Error Recovery *********************************/ 260 static void ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb); 261 static int ahc_abort_scbs(struct ahc_softc *ahc, int target, 262 char channel, int lun, u_int tag, 263 role_t role, uint32_t status); 264 static void ahc_calc_residual(struct ahc_softc *ahc, 265 struct scb *scb); 266 267 /*********************** Untagged Transaction Routines ************************/ 268 static inline void ahc_freeze_untagged_queues(struct ahc_softc *ahc); 269 static inline void ahc_release_untagged_queues(struct ahc_softc *ahc); 270 271 /* 272 * Block our completion routine from starting the next untagged 273 * transaction for this target or target lun. 274 */ 275 static inline void 276 ahc_freeze_untagged_queues(struct ahc_softc *ahc) 277 { 278 if ((ahc->flags & AHC_SCB_BTT) == 0) 279 ahc->untagged_queue_lock++; 280 } 281 282 /* 283 * Allow the next untagged transaction for this target or target lun 284 * to be executed. We use a counting semaphore to allow the lock 285 * to be acquired recursively. Once the count drops to zero, the 286 * transaction queues will be run. 287 */ 288 static inline void 289 ahc_release_untagged_queues(struct ahc_softc *ahc) 290 { 291 if ((ahc->flags & AHC_SCB_BTT) == 0) { 292 ahc->untagged_queue_lock--; 293 if (ahc->untagged_queue_lock == 0) 294 ahc_run_untagged_queues(ahc); 295 } 296 } 297 298 /************************* Sequencer Execution Control ************************/ 299 /* 300 * Work around any chip bugs related to halting sequencer execution. 301 * On Ultra2 controllers, we must clear the CIOBUS stretch signal by 302 * reading a register that will set this signal and deassert it. 303 * Without this workaround, if the chip is paused, by an interrupt or 304 * manual pause while accessing scb ram, accesses to certain registers 305 * will hang the system (infinite pci retries). 306 */ 307 static void 308 ahc_pause_bug_fix(struct ahc_softc *ahc) 309 { 310 if ((ahc->features & AHC_ULTRA2) != 0) 311 (void)ahc_inb(ahc, CCSCBCTL); 312 } 313 314 /* 315 * Determine whether the sequencer has halted code execution. 316 * Returns non-zero status if the sequencer is stopped. 317 */ 318 int 319 ahc_is_paused(struct ahc_softc *ahc) 320 { 321 return ((ahc_inb(ahc, HCNTRL) & PAUSE) != 0); 322 } 323 324 /* 325 * Request that the sequencer stop and wait, indefinitely, for it 326 * to stop. The sequencer will only acknowledge that it is paused 327 * once it has reached an instruction boundary and PAUSEDIS is 328 * cleared in the SEQCTL register. The sequencer may use PAUSEDIS 329 * for critical sections. 330 */ 331 void 332 ahc_pause(struct ahc_softc *ahc) 333 { 334 ahc_outb(ahc, HCNTRL, ahc->pause); 335 336 /* 337 * Since the sequencer can disable pausing in a critical section, we 338 * must loop until it actually stops. 339 */ 340 while (ahc_is_paused(ahc) == 0) 341 ; 342 343 ahc_pause_bug_fix(ahc); 344 } 345 346 /* 347 * Allow the sequencer to continue program execution. 348 * We check here to ensure that no additional interrupt 349 * sources that would cause the sequencer to halt have been 350 * asserted. If, for example, a SCSI bus reset is detected 351 * while we are fielding a different, pausing, interrupt type, 352 * we don't want to release the sequencer before going back 353 * into our interrupt handler and dealing with this new 354 * condition. 355 */ 356 void 357 ahc_unpause(struct ahc_softc *ahc) 358 { 359 if ((ahc_inb(ahc, INTSTAT) & (SCSIINT | SEQINT | BRKADRINT)) == 0) 360 ahc_outb(ahc, HCNTRL, ahc->unpause); 361 } 362 363 /************************** Memory mapping routines ***************************/ 364 static struct ahc_dma_seg * 365 ahc_sg_bus_to_virt(struct scb *scb, uint32_t sg_busaddr) 366 { 367 int sg_index; 368 369 sg_index = (sg_busaddr - scb->sg_list_phys)/sizeof(struct ahc_dma_seg); 370 /* sg_list_phys points to entry 1, not 0 */ 371 sg_index++; 372 373 return (&scb->sg_list[sg_index]); 374 } 375 376 static uint32_t 377 ahc_sg_virt_to_bus(struct scb *scb, struct ahc_dma_seg *sg) 378 { 379 int sg_index; 380 381 /* sg_list_phys points to entry 1, not 0 */ 382 sg_index = sg - &scb->sg_list[1]; 383 384 return (scb->sg_list_phys + (sg_index * sizeof(*scb->sg_list))); 385 } 386 387 static uint32_t 388 ahc_hscb_busaddr(struct ahc_softc *ahc, u_int index) 389 { 390 return (ahc->scb_data->hscb_busaddr 391 + (sizeof(struct hardware_scb) * index)); 392 } 393 394 static void 395 ahc_sync_scb(struct ahc_softc *ahc, struct scb *scb, int op) 396 { 397 ahc_dmamap_sync(ahc, ahc->scb_data->hscb_dmat, 398 ahc->scb_data->hscb_dmamap, 399 /*offset*/(scb->hscb - ahc->hscbs) * sizeof(*scb->hscb), 400 /*len*/sizeof(*scb->hscb), op); 401 } 402 403 void 404 ahc_sync_sglist(struct ahc_softc *ahc, struct scb *scb, int op) 405 { 406 if (scb->sg_count == 0) 407 return; 408 409 ahc_dmamap_sync(ahc, ahc->scb_data->sg_dmat, scb->sg_map->sg_dmamap, 410 /*offset*/(scb->sg_list - scb->sg_map->sg_vaddr) 411 * sizeof(struct ahc_dma_seg), 412 /*len*/sizeof(struct ahc_dma_seg) * scb->sg_count, op); 413 } 414 415 #ifdef AHC_TARGET_MODE 416 static uint32_t 417 ahc_targetcmd_offset(struct ahc_softc *ahc, u_int index) 418 { 419 return (((uint8_t *)&ahc->targetcmds[index]) - ahc->qoutfifo); 420 } 421 #endif 422 423 /*********************** Miscellaneous Support Functions ***********************/ 424 /* 425 * Determine whether the sequencer reported a residual 426 * for this SCB/transaction. 427 */ 428 static void 429 ahc_update_residual(struct ahc_softc *ahc, struct scb *scb) 430 { 431 uint32_t sgptr; 432 433 sgptr = ahc_le32toh(scb->hscb->sgptr); 434 if ((sgptr & SG_RESID_VALID) != 0) 435 ahc_calc_residual(ahc, scb); 436 } 437 438 /* 439 * Return pointers to the transfer negotiation information 440 * for the specified our_id/remote_id pair. 441 */ 442 struct ahc_initiator_tinfo * 443 ahc_fetch_transinfo(struct ahc_softc *ahc, char channel, u_int our_id, 444 u_int remote_id, struct ahc_tmode_tstate **tstate) 445 { 446 /* 447 * Transfer data structures are stored from the perspective 448 * of the target role. Since the parameters for a connection 449 * in the initiator role to a given target are the same as 450 * when the roles are reversed, we pretend we are the target. 451 */ 452 if (channel == 'B') 453 our_id += 8; 454 *tstate = ahc->enabled_targets[our_id]; 455 return (&(*tstate)->transinfo[remote_id]); 456 } 457 458 uint16_t 459 ahc_inw(struct ahc_softc *ahc, u_int port) 460 { 461 uint16_t r = ahc_inb(ahc, port+1) << 8; 462 return r | ahc_inb(ahc, port); 463 } 464 465 void 466 ahc_outw(struct ahc_softc *ahc, u_int port, u_int value) 467 { 468 ahc_outb(ahc, port, value & 0xFF); 469 ahc_outb(ahc, port+1, (value >> 8) & 0xFF); 470 } 471 472 uint32_t 473 ahc_inl(struct ahc_softc *ahc, u_int port) 474 { 475 return ((ahc_inb(ahc, port)) 476 | (ahc_inb(ahc, port+1) << 8) 477 | (ahc_inb(ahc, port+2) << 16) 478 | (ahc_inb(ahc, port+3) << 24)); 479 } 480 481 void 482 ahc_outl(struct ahc_softc *ahc, u_int port, uint32_t value) 483 { 484 ahc_outb(ahc, port, (value) & 0xFF); 485 ahc_outb(ahc, port+1, ((value) >> 8) & 0xFF); 486 ahc_outb(ahc, port+2, ((value) >> 16) & 0xFF); 487 ahc_outb(ahc, port+3, ((value) >> 24) & 0xFF); 488 } 489 490 uint64_t 491 ahc_inq(struct ahc_softc *ahc, u_int port) 492 { 493 return ((ahc_inb(ahc, port)) 494 | (ahc_inb(ahc, port+1) << 8) 495 | (ahc_inb(ahc, port+2) << 16) 496 | (ahc_inb(ahc, port+3) << 24) 497 | (((uint64_t)ahc_inb(ahc, port+4)) << 32) 498 | (((uint64_t)ahc_inb(ahc, port+5)) << 40) 499 | (((uint64_t)ahc_inb(ahc, port+6)) << 48) 500 | (((uint64_t)ahc_inb(ahc, port+7)) << 56)); 501 } 502 503 void 504 ahc_outq(struct ahc_softc *ahc, u_int port, uint64_t value) 505 { 506 ahc_outb(ahc, port, value & 0xFF); 507 ahc_outb(ahc, port+1, (value >> 8) & 0xFF); 508 ahc_outb(ahc, port+2, (value >> 16) & 0xFF); 509 ahc_outb(ahc, port+3, (value >> 24) & 0xFF); 510 ahc_outb(ahc, port+4, (value >> 32) & 0xFF); 511 ahc_outb(ahc, port+5, (value >> 40) & 0xFF); 512 ahc_outb(ahc, port+6, (value >> 48) & 0xFF); 513 ahc_outb(ahc, port+7, (value >> 56) & 0xFF); 514 } 515 516 /* 517 * Get a free scb. If there are none, see if we can allocate a new SCB. 518 */ 519 struct scb * 520 ahc_get_scb(struct ahc_softc *ahc) 521 { 522 struct scb *scb; 523 524 if ((scb = SLIST_FIRST(&ahc->scb_data->free_scbs)) == NULL) { 525 ahc_alloc_scbs(ahc); 526 scb = SLIST_FIRST(&ahc->scb_data->free_scbs); 527 if (scb == NULL) 528 return (NULL); 529 } 530 SLIST_REMOVE_HEAD(&ahc->scb_data->free_scbs, links.sle); 531 return (scb); 532 } 533 534 /* 535 * Return an SCB resource to the free list. 536 */ 537 void 538 ahc_free_scb(struct ahc_softc *ahc, struct scb *scb) 539 { 540 struct hardware_scb *hscb; 541 542 hscb = scb->hscb; 543 /* Clean up for the next user */ 544 ahc->scb_data->scbindex[hscb->tag] = NULL; 545 scb->flags = SCB_FREE; 546 hscb->control = 0; 547 548 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, scb, links.sle); 549 550 /* Notify the OSM that a resource is now available. */ 551 ahc_platform_scb_free(ahc, scb); 552 } 553 554 struct scb * 555 ahc_lookup_scb(struct ahc_softc *ahc, u_int tag) 556 { 557 struct scb* scb; 558 559 scb = ahc->scb_data->scbindex[tag]; 560 if (scb != NULL) 561 ahc_sync_scb(ahc, scb, 562 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 563 return (scb); 564 } 565 566 static void 567 ahc_swap_with_next_hscb(struct ahc_softc *ahc, struct scb *scb) 568 { 569 struct hardware_scb *q_hscb; 570 u_int saved_tag; 571 572 /* 573 * Our queuing method is a bit tricky. The card 574 * knows in advance which HSCB to download, and we 575 * can't disappoint it. To achieve this, the next 576 * SCB to download is saved off in ahc->next_queued_scb. 577 * When we are called to queue "an arbitrary scb", 578 * we copy the contents of the incoming HSCB to the one 579 * the sequencer knows about, swap HSCB pointers and 580 * finally assign the SCB to the tag indexed location 581 * in the scb_array. This makes sure that we can still 582 * locate the correct SCB by SCB_TAG. 583 */ 584 q_hscb = ahc->next_queued_scb->hscb; 585 saved_tag = q_hscb->tag; 586 memcpy(q_hscb, scb->hscb, sizeof(*scb->hscb)); 587 if ((scb->flags & SCB_CDB32_PTR) != 0) { 588 q_hscb->shared_data.cdb_ptr = 589 ahc_htole32(ahc_hscb_busaddr(ahc, q_hscb->tag) 590 + offsetof(struct hardware_scb, cdb32)); 591 } 592 q_hscb->tag = saved_tag; 593 q_hscb->next = scb->hscb->tag; 594 595 /* Now swap HSCB pointers. */ 596 ahc->next_queued_scb->hscb = scb->hscb; 597 scb->hscb = q_hscb; 598 599 /* Now define the mapping from tag to SCB in the scbindex */ 600 ahc->scb_data->scbindex[scb->hscb->tag] = scb; 601 } 602 603 /* 604 * Tell the sequencer about a new transaction to execute. 605 */ 606 void 607 ahc_queue_scb(struct ahc_softc *ahc, struct scb *scb) 608 { 609 ahc_swap_with_next_hscb(ahc, scb); 610 611 if (scb->hscb->tag == SCB_LIST_NULL 612 || scb->hscb->next == SCB_LIST_NULL) 613 panic("Attempt to queue invalid SCB tag %x:%x\n", 614 scb->hscb->tag, scb->hscb->next); 615 616 /* 617 * Setup data "oddness". 618 */ 619 scb->hscb->lun &= LID; 620 if (ahc_get_transfer_length(scb) & 0x1) 621 scb->hscb->lun |= SCB_XFERLEN_ODD; 622 623 /* 624 * Keep a history of SCBs we've downloaded in the qinfifo. 625 */ 626 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 627 628 /* 629 * Make sure our data is consistent from the 630 * perspective of the adapter. 631 */ 632 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 633 634 /* Tell the adapter about the newly queued SCB */ 635 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 636 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 637 } else { 638 if ((ahc->features & AHC_AUTOPAUSE) == 0) 639 ahc_pause(ahc); 640 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 641 if ((ahc->features & AHC_AUTOPAUSE) == 0) 642 ahc_unpause(ahc); 643 } 644 } 645 646 struct scsi_sense_data * 647 ahc_get_sense_buf(struct ahc_softc *ahc, struct scb *scb) 648 { 649 int offset; 650 651 offset = scb - ahc->scb_data->scbarray; 652 return (&ahc->scb_data->sense[offset]); 653 } 654 655 static uint32_t 656 ahc_get_sense_bufaddr(struct ahc_softc *ahc, struct scb *scb) 657 { 658 int offset; 659 660 offset = scb - ahc->scb_data->scbarray; 661 return (ahc->scb_data->sense_busaddr 662 + (offset * sizeof(struct scsi_sense_data))); 663 } 664 665 /************************** Interrupt Processing ******************************/ 666 static void 667 ahc_sync_qoutfifo(struct ahc_softc *ahc, int op) 668 { 669 ahc_dmamap_sync(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap, 670 /*offset*/0, /*len*/256, op); 671 } 672 673 static void 674 ahc_sync_tqinfifo(struct ahc_softc *ahc, int op) 675 { 676 #ifdef AHC_TARGET_MODE 677 if ((ahc->flags & AHC_TARGETROLE) != 0) { 678 ahc_dmamap_sync(ahc, ahc->shared_data_dmat, 679 ahc->shared_data_dmamap, 680 ahc_targetcmd_offset(ahc, 0), 681 sizeof(struct target_cmd) * AHC_TMODE_CMDS, 682 op); 683 } 684 #endif 685 } 686 687 /* 688 * See if the firmware has posted any completed commands 689 * into our in-core command complete fifos. 690 */ 691 #define AHC_RUN_QOUTFIFO 0x1 692 #define AHC_RUN_TQINFIFO 0x2 693 static u_int 694 ahc_check_cmdcmpltqueues(struct ahc_softc *ahc) 695 { 696 u_int retval; 697 698 retval = 0; 699 ahc_dmamap_sync(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap, 700 /*offset*/ahc->qoutfifonext, /*len*/1, 701 BUS_DMASYNC_POSTREAD); 702 if (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) 703 retval |= AHC_RUN_QOUTFIFO; 704 #ifdef AHC_TARGET_MODE 705 if ((ahc->flags & AHC_TARGETROLE) != 0 706 && (ahc->flags & AHC_TQINFIFO_BLOCKED) == 0) { 707 ahc_dmamap_sync(ahc, ahc->shared_data_dmat, 708 ahc->shared_data_dmamap, 709 ahc_targetcmd_offset(ahc, ahc->tqinfifofnext), 710 /*len*/sizeof(struct target_cmd), 711 BUS_DMASYNC_POSTREAD); 712 if (ahc->targetcmds[ahc->tqinfifonext].cmd_valid != 0) 713 retval |= AHC_RUN_TQINFIFO; 714 } 715 #endif 716 return (retval); 717 } 718 719 /* 720 * Catch an interrupt from the adapter 721 */ 722 int 723 ahc_intr(struct ahc_softc *ahc) 724 { 725 u_int intstat; 726 727 if ((ahc->pause & INTEN) == 0) { 728 /* 729 * Our interrupt is not enabled on the chip 730 * and may be disabled for re-entrancy reasons, 731 * so just return. This is likely just a shared 732 * interrupt. 733 */ 734 return (0); 735 } 736 /* 737 * Instead of directly reading the interrupt status register, 738 * infer the cause of the interrupt by checking our in-core 739 * completion queues. This avoids a costly PCI bus read in 740 * most cases. 741 */ 742 if ((ahc->flags & (AHC_ALL_INTERRUPTS|AHC_EDGE_INTERRUPT)) == 0 743 && (ahc_check_cmdcmpltqueues(ahc) != 0)) 744 intstat = CMDCMPLT; 745 else { 746 intstat = ahc_inb(ahc, INTSTAT); 747 } 748 749 if ((intstat & INT_PEND) == 0) { 750 #if AHC_PCI_CONFIG > 0 751 if (ahc->unsolicited_ints > 500) { 752 ahc->unsolicited_ints = 0; 753 if ((ahc->chip & AHC_PCI) != 0 754 && (ahc_inb(ahc, ERROR) & PCIERRSTAT) != 0) 755 ahc->bus_intr(ahc); 756 } 757 #endif 758 ahc->unsolicited_ints++; 759 return (0); 760 } 761 ahc->unsolicited_ints = 0; 762 763 if (intstat & CMDCMPLT) { 764 ahc_outb(ahc, CLRINT, CLRCMDINT); 765 766 /* 767 * Ensure that the chip sees that we've cleared 768 * this interrupt before we walk the output fifo. 769 * Otherwise, we may, due to posted bus writes, 770 * clear the interrupt after we finish the scan, 771 * and after the sequencer has added new entries 772 * and asserted the interrupt again. 773 */ 774 ahc_flush_device_writes(ahc); 775 ahc_run_qoutfifo(ahc); 776 #ifdef AHC_TARGET_MODE 777 if ((ahc->flags & AHC_TARGETROLE) != 0) 778 ahc_run_tqinfifo(ahc, /*paused*/FALSE); 779 #endif 780 } 781 782 /* 783 * Handle statuses that may invalidate our cached 784 * copy of INTSTAT separately. 785 */ 786 if (intstat == 0xFF && (ahc->features & AHC_REMOVABLE) != 0) { 787 /* Hot eject. Do nothing */ 788 } else if (intstat & BRKADRINT) { 789 ahc_handle_brkadrint(ahc); 790 } else if ((intstat & (SEQINT|SCSIINT)) != 0) { 791 792 ahc_pause_bug_fix(ahc); 793 794 if ((intstat & SEQINT) != 0) 795 ahc_handle_seqint(ahc, intstat); 796 797 if ((intstat & SCSIINT) != 0) 798 ahc_handle_scsiint(ahc, intstat); 799 } 800 return (1); 801 } 802 803 /************************* Sequencer Execution Control ************************/ 804 /* 805 * Restart the sequencer program from address zero 806 */ 807 static void 808 ahc_restart(struct ahc_softc *ahc) 809 { 810 uint8_t sblkctl; 811 812 ahc_pause(ahc); 813 814 /* No more pending messages. */ 815 ahc_clear_msg_state(ahc); 816 817 ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */ 818 ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */ 819 ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET); 820 ahc_outb(ahc, LASTPHASE, P_BUSFREE); 821 ahc_outb(ahc, SAVED_SCSIID, 0xFF); 822 ahc_outb(ahc, SAVED_LUN, 0xFF); 823 824 /* 825 * Ensure that the sequencer's idea of TQINPOS 826 * matches our own. The sequencer increments TQINPOS 827 * only after it sees a DMA complete and a reset could 828 * occur before the increment leaving the kernel to believe 829 * the command arrived but the sequencer to not. 830 */ 831 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext); 832 833 /* Always allow reselection */ 834 ahc_outb(ahc, SCSISEQ, 835 ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP)); 836 if ((ahc->features & AHC_CMD_CHAN) != 0) { 837 /* Ensure that no DMA operations are in progress */ 838 ahc_outb(ahc, CCSCBCNT, 0); 839 ahc_outb(ahc, CCSGCTL, 0); 840 ahc_outb(ahc, CCSCBCTL, 0); 841 } 842 /* 843 * If we were in the process of DMA'ing SCB data into 844 * an SCB, replace that SCB on the free list. This prevents 845 * an SCB leak. 846 */ 847 if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) { 848 ahc_add_curscb_to_free_list(ahc); 849 ahc_outb(ahc, SEQ_FLAGS2, 850 ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA); 851 } 852 853 /* 854 * Clear any pending sequencer interrupt. It is no 855 * longer relevant since we're resetting the Program 856 * Counter. 857 */ 858 ahc_outb(ahc, CLRINT, CLRSEQINT); 859 860 ahc_outb(ahc, MWI_RESIDUAL, 0); 861 ahc_outb(ahc, SEQCTL, ahc->seqctl); 862 ahc_outb(ahc, SEQADDR0, 0); 863 ahc_outb(ahc, SEQADDR1, 0); 864 865 /* 866 * Take the LED out of diagnostic mode on PM resume, too 867 */ 868 sblkctl = ahc_inb(ahc, SBLKCTL); 869 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON))); 870 871 ahc_unpause(ahc); 872 } 873 874 /************************* Input/Output Queues ********************************/ 875 static void 876 ahc_run_qoutfifo(struct ahc_softc *ahc) 877 { 878 struct scb *scb; 879 u_int scb_index; 880 881 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD); 882 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) { 883 884 scb_index = ahc->qoutfifo[ahc->qoutfifonext]; 885 if ((ahc->qoutfifonext & 0x03) == 0x03) { 886 u_int modnext; 887 888 /* 889 * Clear 32bits of QOUTFIFO at a time 890 * so that we don't clobber an incoming 891 * byte DMA to the array on architectures 892 * that only support 32bit load and store 893 * operations. 894 */ 895 modnext = ahc->qoutfifonext & ~0x3; 896 *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL; 897 ahc_dmamap_sync(ahc, ahc->shared_data_dmat, 898 ahc->shared_data_dmamap, 899 /*offset*/modnext, /*len*/4, 900 BUS_DMASYNC_PREREAD); 901 } 902 ahc->qoutfifonext++; 903 904 scb = ahc_lookup_scb(ahc, scb_index); 905 if (scb == NULL) { 906 printk("%s: WARNING no command for scb %d " 907 "(cmdcmplt)\nQOUTPOS = %d\n", 908 ahc_name(ahc), scb_index, 909 (ahc->qoutfifonext - 1) & 0xFF); 910 continue; 911 } 912 913 /* 914 * Save off the residual 915 * if there is one. 916 */ 917 ahc_update_residual(ahc, scb); 918 ahc_done(ahc, scb); 919 } 920 } 921 922 static void 923 ahc_run_untagged_queues(struct ahc_softc *ahc) 924 { 925 int i; 926 927 for (i = 0; i < 16; i++) 928 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]); 929 } 930 931 static void 932 ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue) 933 { 934 struct scb *scb; 935 936 if (ahc->untagged_queue_lock != 0) 937 return; 938 939 if ((scb = TAILQ_FIRST(queue)) != NULL 940 && (scb->flags & SCB_ACTIVE) == 0) { 941 scb->flags |= SCB_ACTIVE; 942 ahc_queue_scb(ahc, scb); 943 } 944 } 945 946 /************************* Interrupt Handling *********************************/ 947 static void 948 ahc_handle_brkadrint(struct ahc_softc *ahc) 949 { 950 /* 951 * We upset the sequencer :-( 952 * Lookup the error message 953 */ 954 int i; 955 int error; 956 957 error = ahc_inb(ahc, ERROR); 958 for (i = 0; error != 1 && i < num_errors; i++) 959 error >>= 1; 960 printk("%s: brkadrint, %s at seqaddr = 0x%x\n", 961 ahc_name(ahc), ahc_hard_errors[i].errmesg, 962 ahc_inb(ahc, SEQADDR0) | 963 (ahc_inb(ahc, SEQADDR1) << 8)); 964 965 ahc_dump_card_state(ahc); 966 967 /* Tell everyone that this HBA is no longer available */ 968 ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS, 969 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 970 CAM_NO_HBA); 971 972 /* Disable all interrupt sources by resetting the controller */ 973 ahc_shutdown(ahc); 974 } 975 976 static void 977 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) 978 { 979 struct scb *scb; 980 struct ahc_devinfo devinfo; 981 982 ahc_fetch_devinfo(ahc, &devinfo); 983 984 /* 985 * Clear the upper byte that holds SEQINT status 986 * codes and clear the SEQINT bit. We will unpause 987 * the sequencer, if appropriate, after servicing 988 * the request. 989 */ 990 ahc_outb(ahc, CLRINT, CLRSEQINT); 991 switch (intstat & SEQINT_MASK) { 992 case BAD_STATUS: 993 { 994 u_int scb_index; 995 struct hardware_scb *hscb; 996 997 /* 998 * Set the default return value to 0 (don't 999 * send sense). The sense code will change 1000 * this if needed. 1001 */ 1002 ahc_outb(ahc, RETURN_1, 0); 1003 1004 /* 1005 * The sequencer will notify us when a command 1006 * has an error that would be of interest to 1007 * the kernel. This allows us to leave the sequencer 1008 * running in the common case of command completes 1009 * without error. The sequencer will already have 1010 * dma'd the SCB back up to us, so we can reference 1011 * the in kernel copy directly. 1012 */ 1013 scb_index = ahc_inb(ahc, SCB_TAG); 1014 scb = ahc_lookup_scb(ahc, scb_index); 1015 if (scb == NULL) { 1016 ahc_print_devinfo(ahc, &devinfo); 1017 printk("ahc_intr - referenced scb " 1018 "not valid during seqint 0x%x scb(%d)\n", 1019 intstat, scb_index); 1020 ahc_dump_card_state(ahc); 1021 panic("for safety"); 1022 goto unpause; 1023 } 1024 1025 hscb = scb->hscb; 1026 1027 /* Don't want to clobber the original sense code */ 1028 if ((scb->flags & SCB_SENSE) != 0) { 1029 /* 1030 * Clear the SCB_SENSE Flag and have 1031 * the sequencer do a normal command 1032 * complete. 1033 */ 1034 scb->flags &= ~SCB_SENSE; 1035 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); 1036 break; 1037 } 1038 ahc_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR); 1039 /* Freeze the queue until the client sees the error. */ 1040 ahc_freeze_devq(ahc, scb); 1041 ahc_freeze_scb(scb); 1042 ahc_set_scsi_status(scb, hscb->shared_data.status.scsi_status); 1043 switch (hscb->shared_data.status.scsi_status) { 1044 case SCSI_STATUS_OK: 1045 printk("%s: Interrupted for status of 0???\n", 1046 ahc_name(ahc)); 1047 break; 1048 case SCSI_STATUS_CMD_TERMINATED: 1049 case SCSI_STATUS_CHECK_COND: 1050 { 1051 struct ahc_dma_seg *sg; 1052 struct scsi_sense *sc; 1053 struct ahc_initiator_tinfo *targ_info; 1054 struct ahc_tmode_tstate *tstate; 1055 struct ahc_transinfo *tinfo; 1056 #ifdef AHC_DEBUG 1057 if (ahc_debug & AHC_SHOW_SENSE) { 1058 ahc_print_path(ahc, scb); 1059 printk("SCB %d: requests Check Status\n", 1060 scb->hscb->tag); 1061 } 1062 #endif 1063 1064 if (ahc_perform_autosense(scb) == 0) 1065 break; 1066 1067 targ_info = ahc_fetch_transinfo(ahc, 1068 devinfo.channel, 1069 devinfo.our_scsiid, 1070 devinfo.target, 1071 &tstate); 1072 tinfo = &targ_info->curr; 1073 sg = scb->sg_list; 1074 sc = (struct scsi_sense *)(&hscb->shared_data.cdb); 1075 /* 1076 * Save off the residual if there is one. 1077 */ 1078 ahc_update_residual(ahc, scb); 1079 #ifdef AHC_DEBUG 1080 if (ahc_debug & AHC_SHOW_SENSE) { 1081 ahc_print_path(ahc, scb); 1082 printk("Sending Sense\n"); 1083 } 1084 #endif 1085 sg->addr = ahc_get_sense_bufaddr(ahc, scb); 1086 sg->len = ahc_get_sense_bufsize(ahc, scb); 1087 sg->len |= AHC_DMA_LAST_SEG; 1088 1089 /* Fixup byte order */ 1090 sg->addr = ahc_htole32(sg->addr); 1091 sg->len = ahc_htole32(sg->len); 1092 1093 sc->opcode = REQUEST_SENSE; 1094 sc->byte2 = 0; 1095 if (tinfo->protocol_version <= SCSI_REV_2 1096 && SCB_GET_LUN(scb) < 8) 1097 sc->byte2 = SCB_GET_LUN(scb) << 5; 1098 sc->unused[0] = 0; 1099 sc->unused[1] = 0; 1100 sc->length = sg->len; 1101 sc->control = 0; 1102 1103 /* 1104 * We can't allow the target to disconnect. 1105 * This will be an untagged transaction and 1106 * having the target disconnect will make this 1107 * transaction indestinguishable from outstanding 1108 * tagged transactions. 1109 */ 1110 hscb->control = 0; 1111 1112 /* 1113 * This request sense could be because the 1114 * the device lost power or in some other 1115 * way has lost our transfer negotiations. 1116 * Renegotiate if appropriate. Unit attention 1117 * errors will be reported before any data 1118 * phases occur. 1119 */ 1120 if (ahc_get_residual(scb) 1121 == ahc_get_transfer_length(scb)) { 1122 ahc_update_neg_request(ahc, &devinfo, 1123 tstate, targ_info, 1124 AHC_NEG_IF_NON_ASYNC); 1125 } 1126 if (tstate->auto_negotiate & devinfo.target_mask) { 1127 hscb->control |= MK_MESSAGE; 1128 scb->flags &= ~SCB_NEGOTIATE; 1129 scb->flags |= SCB_AUTO_NEGOTIATE; 1130 } 1131 hscb->cdb_len = sizeof(*sc); 1132 hscb->dataptr = sg->addr; 1133 hscb->datacnt = sg->len; 1134 hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID; 1135 hscb->sgptr = ahc_htole32(hscb->sgptr); 1136 scb->sg_count = 1; 1137 scb->flags |= SCB_SENSE; 1138 ahc_qinfifo_requeue_tail(ahc, scb); 1139 ahc_outb(ahc, RETURN_1, SEND_SENSE); 1140 /* 1141 * Ensure we have enough time to actually 1142 * retrieve the sense. 1143 */ 1144 ahc_scb_timer_reset(scb, 5 * 1000000); 1145 break; 1146 } 1147 default: 1148 break; 1149 } 1150 break; 1151 } 1152 case NO_MATCH: 1153 { 1154 /* Ensure we don't leave the selection hardware on */ 1155 ahc_outb(ahc, SCSISEQ, 1156 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 1157 1158 printk("%s:%c:%d: no active SCB for reconnecting " 1159 "target - issuing BUS DEVICE RESET\n", 1160 ahc_name(ahc), devinfo.channel, devinfo.target); 1161 printk("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 1162 "ARG_1 == 0x%x ACCUM = 0x%x\n", 1163 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN), 1164 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM)); 1165 printk("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 1166 "SINDEX == 0x%x\n", 1167 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR), 1168 ahc_index_busy_tcl(ahc, 1169 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID), 1170 ahc_inb(ahc, SAVED_LUN))), 1171 ahc_inb(ahc, SINDEX)); 1172 printk("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 1173 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n", 1174 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID), 1175 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG), 1176 ahc_inb(ahc, SCB_CONTROL)); 1177 printk("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n", 1178 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI)); 1179 printk("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0)); 1180 printk("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL)); 1181 ahc_dump_card_state(ahc); 1182 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET; 1183 ahc->msgout_len = 1; 1184 ahc->msgout_index = 0; 1185 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 1186 ahc_outb(ahc, MSG_OUT, HOST_MSG); 1187 ahc_assert_atn(ahc); 1188 break; 1189 } 1190 case SEND_REJECT: 1191 { 1192 u_int rejbyte = ahc_inb(ahc, ACCUM); 1193 printk("%s:%c:%d: Warning - unknown message received from " 1194 "target (0x%x). Rejecting\n", 1195 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte); 1196 break; 1197 } 1198 case PROTO_VIOLATION: 1199 { 1200 ahc_handle_proto_violation(ahc); 1201 break; 1202 } 1203 case IGN_WIDE_RES: 1204 ahc_handle_ign_wide_residue(ahc, &devinfo); 1205 break; 1206 case PDATA_REINIT: 1207 ahc_reinitialize_dataptrs(ahc); 1208 break; 1209 case BAD_PHASE: 1210 { 1211 u_int lastphase; 1212 1213 lastphase = ahc_inb(ahc, LASTPHASE); 1214 printk("%s:%c:%d: unknown scsi bus phase %x, " 1215 "lastphase = 0x%x. Attempting to continue\n", 1216 ahc_name(ahc), devinfo.channel, devinfo.target, 1217 lastphase, ahc_inb(ahc, SCSISIGI)); 1218 break; 1219 } 1220 case MISSED_BUSFREE: 1221 { 1222 u_int lastphase; 1223 1224 lastphase = ahc_inb(ahc, LASTPHASE); 1225 printk("%s:%c:%d: Missed busfree. " 1226 "Lastphase = 0x%x, Curphase = 0x%x\n", 1227 ahc_name(ahc), devinfo.channel, devinfo.target, 1228 lastphase, ahc_inb(ahc, SCSISIGI)); 1229 ahc_restart(ahc); 1230 return; 1231 } 1232 case HOST_MSG_LOOP: 1233 { 1234 /* 1235 * The sequencer has encountered a message phase 1236 * that requires host assistance for completion. 1237 * While handling the message phase(s), we will be 1238 * notified by the sequencer after each byte is 1239 * transferred so we can track bus phase changes. 1240 * 1241 * If this is the first time we've seen a HOST_MSG_LOOP 1242 * interrupt, initialize the state of the host message 1243 * loop. 1244 */ 1245 if (ahc->msg_type == MSG_TYPE_NONE) { 1246 struct scb *scb; 1247 u_int scb_index; 1248 u_int bus_phase; 1249 1250 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1251 if (bus_phase != P_MESGIN 1252 && bus_phase != P_MESGOUT) { 1253 printk("ahc_intr: HOST_MSG_LOOP bad " 1254 "phase 0x%x\n", 1255 bus_phase); 1256 /* 1257 * Probably transitioned to bus free before 1258 * we got here. Just punt the message. 1259 */ 1260 ahc_clear_intstat(ahc); 1261 ahc_restart(ahc); 1262 return; 1263 } 1264 1265 scb_index = ahc_inb(ahc, SCB_TAG); 1266 scb = ahc_lookup_scb(ahc, scb_index); 1267 if (devinfo.role == ROLE_INITIATOR) { 1268 if (bus_phase == P_MESGOUT) { 1269 if (scb == NULL) 1270 panic("HOST_MSG_LOOP with " 1271 "invalid SCB %x\n", 1272 scb_index); 1273 1274 ahc_setup_initiator_msgout(ahc, 1275 &devinfo, 1276 scb); 1277 } else { 1278 ahc->msg_type = 1279 MSG_TYPE_INITIATOR_MSGIN; 1280 ahc->msgin_index = 0; 1281 } 1282 } 1283 #ifdef AHC_TARGET_MODE 1284 else { 1285 if (bus_phase == P_MESGOUT) { 1286 ahc->msg_type = 1287 MSG_TYPE_TARGET_MSGOUT; 1288 ahc->msgin_index = 0; 1289 } 1290 else 1291 ahc_setup_target_msgin(ahc, 1292 &devinfo, 1293 scb); 1294 } 1295 #endif 1296 } 1297 1298 ahc_handle_message_phase(ahc); 1299 break; 1300 } 1301 case PERR_DETECTED: 1302 { 1303 /* 1304 * If we've cleared the parity error interrupt 1305 * but the sequencer still believes that SCSIPERR 1306 * is true, it must be that the parity error is 1307 * for the currently presented byte on the bus, 1308 * and we are not in a phase (data-in) where we will 1309 * eventually ack this byte. Ack the byte and 1310 * throw it away in the hope that the target will 1311 * take us to message out to deliver the appropriate 1312 * error message. 1313 */ 1314 if ((intstat & SCSIINT) == 0 1315 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) { 1316 1317 if ((ahc->features & AHC_DT) == 0) { 1318 u_int curphase; 1319 1320 /* 1321 * The hardware will only let you ack bytes 1322 * if the expected phase in SCSISIGO matches 1323 * the current phase. Make sure this is 1324 * currently the case. 1325 */ 1326 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1327 ahc_outb(ahc, LASTPHASE, curphase); 1328 ahc_outb(ahc, SCSISIGO, curphase); 1329 } 1330 if ((ahc_inb(ahc, SCSISIGI) & (CDI|MSGI)) == 0) { 1331 int wait; 1332 1333 /* 1334 * In a data phase. Faster to bitbucket 1335 * the data than to individually ack each 1336 * byte. This is also the only strategy 1337 * that will work with AUTOACK enabled. 1338 */ 1339 ahc_outb(ahc, SXFRCTL1, 1340 ahc_inb(ahc, SXFRCTL1) | BITBUCKET); 1341 wait = 5000; 1342 while (--wait != 0) { 1343 if ((ahc_inb(ahc, SCSISIGI) 1344 & (CDI|MSGI)) != 0) 1345 break; 1346 ahc_delay(100); 1347 } 1348 ahc_outb(ahc, SXFRCTL1, 1349 ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET); 1350 if (wait == 0) { 1351 struct scb *scb; 1352 u_int scb_index; 1353 1354 ahc_print_devinfo(ahc, &devinfo); 1355 printk("Unable to clear parity error. " 1356 "Resetting bus.\n"); 1357 scb_index = ahc_inb(ahc, SCB_TAG); 1358 scb = ahc_lookup_scb(ahc, scb_index); 1359 if (scb != NULL) 1360 ahc_set_transaction_status(scb, 1361 CAM_UNCOR_PARITY); 1362 ahc_reset_channel(ahc, devinfo.channel, 1363 /*init reset*/TRUE); 1364 } 1365 } else { 1366 ahc_inb(ahc, SCSIDATL); 1367 } 1368 } 1369 break; 1370 } 1371 case DATA_OVERRUN: 1372 { 1373 /* 1374 * When the sequencer detects an overrun, it 1375 * places the controller in "BITBUCKET" mode 1376 * and allows the target to complete its transfer. 1377 * Unfortunately, none of the counters get updated 1378 * when the controller is in this mode, so we have 1379 * no way of knowing how large the overrun was. 1380 */ 1381 u_int scbindex = ahc_inb(ahc, SCB_TAG); 1382 u_int lastphase = ahc_inb(ahc, LASTPHASE); 1383 u_int i; 1384 1385 scb = ahc_lookup_scb(ahc, scbindex); 1386 for (i = 0; i < num_phases; i++) { 1387 if (lastphase == ahc_phase_table[i].phase) 1388 break; 1389 } 1390 ahc_print_path(ahc, scb); 1391 printk("data overrun detected %s." 1392 " Tag == 0x%x.\n", 1393 ahc_phase_table[i].phasemsg, 1394 scb->hscb->tag); 1395 ahc_print_path(ahc, scb); 1396 printk("%s seen Data Phase. Length = %ld. NumSGs = %d.\n", 1397 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't", 1398 ahc_get_transfer_length(scb), scb->sg_count); 1399 if (scb->sg_count > 0) { 1400 for (i = 0; i < scb->sg_count; i++) { 1401 1402 printk("sg[%d] - Addr 0x%x%x : Length %d\n", 1403 i, 1404 (ahc_le32toh(scb->sg_list[i].len) >> 24 1405 & SG_HIGH_ADDR_BITS), 1406 ahc_le32toh(scb->sg_list[i].addr), 1407 ahc_le32toh(scb->sg_list[i].len) 1408 & AHC_SG_LEN_MASK); 1409 } 1410 } 1411 /* 1412 * Set this and it will take effect when the 1413 * target does a command complete. 1414 */ 1415 ahc_freeze_devq(ahc, scb); 1416 if ((scb->flags & SCB_SENSE) == 0) { 1417 ahc_set_transaction_status(scb, CAM_DATA_RUN_ERR); 1418 } else { 1419 scb->flags &= ~SCB_SENSE; 1420 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); 1421 } 1422 ahc_freeze_scb(scb); 1423 1424 if ((ahc->features & AHC_ULTRA2) != 0) { 1425 /* 1426 * Clear the channel in case we return 1427 * to data phase later. 1428 */ 1429 ahc_outb(ahc, SXFRCTL0, 1430 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN); 1431 ahc_outb(ahc, SXFRCTL0, 1432 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN); 1433 } 1434 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 1435 u_int dscommand1; 1436 1437 /* Ensure HHADDR is 0 for future DMA operations. */ 1438 dscommand1 = ahc_inb(ahc, DSCOMMAND1); 1439 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0); 1440 ahc_outb(ahc, HADDR, 0); 1441 ahc_outb(ahc, DSCOMMAND1, dscommand1); 1442 } 1443 break; 1444 } 1445 case MKMSG_FAILED: 1446 { 1447 u_int scbindex; 1448 1449 printk("%s:%c:%d:%d: Attempt to issue message failed\n", 1450 ahc_name(ahc), devinfo.channel, devinfo.target, 1451 devinfo.lun); 1452 scbindex = ahc_inb(ahc, SCB_TAG); 1453 scb = ahc_lookup_scb(ahc, scbindex); 1454 if (scb != NULL 1455 && (scb->flags & SCB_RECOVERY_SCB) != 0) 1456 /* 1457 * Ensure that we didn't put a second instance of this 1458 * SCB into the QINFIFO. 1459 */ 1460 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), 1461 SCB_GET_CHANNEL(ahc, scb), 1462 SCB_GET_LUN(scb), scb->hscb->tag, 1463 ROLE_INITIATOR, /*status*/0, 1464 SEARCH_REMOVE); 1465 break; 1466 } 1467 case NO_FREE_SCB: 1468 { 1469 printk("%s: No free or disconnected SCBs\n", ahc_name(ahc)); 1470 ahc_dump_card_state(ahc); 1471 panic("for safety"); 1472 break; 1473 } 1474 case SCB_MISMATCH: 1475 { 1476 u_int scbptr; 1477 1478 scbptr = ahc_inb(ahc, SCBPTR); 1479 printk("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n", 1480 scbptr, ahc_inb(ahc, ARG_1), 1481 ahc->scb_data->hscbs[scbptr].tag); 1482 ahc_dump_card_state(ahc); 1483 panic("for safety"); 1484 break; 1485 } 1486 case OUT_OF_RANGE: 1487 { 1488 printk("%s: BTT calculation out of range\n", ahc_name(ahc)); 1489 printk("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 1490 "ARG_1 == 0x%x ACCUM = 0x%x\n", 1491 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN), 1492 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM)); 1493 printk("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 1494 "SINDEX == 0x%x\n, A == 0x%x\n", 1495 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR), 1496 ahc_index_busy_tcl(ahc, 1497 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID), 1498 ahc_inb(ahc, SAVED_LUN))), 1499 ahc_inb(ahc, SINDEX), 1500 ahc_inb(ahc, ACCUM)); 1501 printk("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 1502 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n", 1503 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID), 1504 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG), 1505 ahc_inb(ahc, SCB_CONTROL)); 1506 printk("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n", 1507 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI)); 1508 ahc_dump_card_state(ahc); 1509 panic("for safety"); 1510 break; 1511 } 1512 default: 1513 printk("ahc_intr: seqint, " 1514 "intstat == 0x%x, scsisigi = 0x%x\n", 1515 intstat, ahc_inb(ahc, SCSISIGI)); 1516 break; 1517 } 1518 unpause: 1519 /* 1520 * The sequencer is paused immediately on 1521 * a SEQINT, so we should restart it when 1522 * we're done. 1523 */ 1524 ahc_unpause(ahc); 1525 } 1526 1527 static void 1528 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) 1529 { 1530 u_int scb_index; 1531 u_int status0; 1532 u_int status; 1533 struct scb *scb; 1534 char cur_channel; 1535 char intr_channel; 1536 1537 if ((ahc->features & AHC_TWIN) != 0 1538 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0)) 1539 cur_channel = 'B'; 1540 else 1541 cur_channel = 'A'; 1542 intr_channel = cur_channel; 1543 1544 if ((ahc->features & AHC_ULTRA2) != 0) 1545 status0 = ahc_inb(ahc, SSTAT0) & IOERR; 1546 else 1547 status0 = 0; 1548 status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 1549 if (status == 0 && status0 == 0) { 1550 if ((ahc->features & AHC_TWIN) != 0) { 1551 /* Try the other channel */ 1552 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 1553 status = ahc_inb(ahc, SSTAT1) 1554 & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 1555 intr_channel = (cur_channel == 'A') ? 'B' : 'A'; 1556 } 1557 if (status == 0) { 1558 printk("%s: Spurious SCSI interrupt\n", ahc_name(ahc)); 1559 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1560 ahc_unpause(ahc); 1561 return; 1562 } 1563 } 1564 1565 /* Make sure the sequencer is in a safe location. */ 1566 ahc_clear_critical_section(ahc); 1567 1568 scb_index = ahc_inb(ahc, SCB_TAG); 1569 scb = ahc_lookup_scb(ahc, scb_index); 1570 if (scb != NULL 1571 && (ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 1572 scb = NULL; 1573 1574 if ((ahc->features & AHC_ULTRA2) != 0 1575 && (status0 & IOERR) != 0) { 1576 int now_lvd; 1577 1578 now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40; 1579 printk("%s: Transceiver State Has Changed to %s mode\n", 1580 ahc_name(ahc), now_lvd ? "LVD" : "SE"); 1581 ahc_outb(ahc, CLRSINT0, CLRIOERR); 1582 /* 1583 * When transitioning to SE mode, the reset line 1584 * glitches, triggering an arbitration bug in some 1585 * Ultra2 controllers. This bug is cleared when we 1586 * assert the reset line. Since a reset glitch has 1587 * already occurred with this transition and a 1588 * transceiver state change is handled just like 1589 * a bus reset anyway, asserting the reset line 1590 * ourselves is safe. 1591 */ 1592 ahc_reset_channel(ahc, intr_channel, 1593 /*Initiate Reset*/now_lvd == 0); 1594 } else if ((status & SCSIRSTI) != 0) { 1595 printk("%s: Someone reset channel %c\n", 1596 ahc_name(ahc), intr_channel); 1597 if (intr_channel != cur_channel) 1598 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 1599 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE); 1600 } else if ((status & SCSIPERR) != 0) { 1601 /* 1602 * Determine the bus phase and queue an appropriate message. 1603 * SCSIPERR is latched true as soon as a parity error 1604 * occurs. If the sequencer acked the transfer that 1605 * caused the parity error and the currently presented 1606 * transfer on the bus has correct parity, SCSIPERR will 1607 * be cleared by CLRSCSIPERR. Use this to determine if 1608 * we should look at the last phase the sequencer recorded, 1609 * or the current phase presented on the bus. 1610 */ 1611 struct ahc_devinfo devinfo; 1612 u_int mesg_out; 1613 u_int curphase; 1614 u_int errorphase; 1615 u_int lastphase; 1616 u_int scsirate; 1617 u_int i; 1618 u_int sstat2; 1619 int silent; 1620 1621 lastphase = ahc_inb(ahc, LASTPHASE); 1622 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1623 sstat2 = ahc_inb(ahc, SSTAT2); 1624 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); 1625 /* 1626 * For all phases save DATA, the sequencer won't 1627 * automatically ack a byte that has a parity error 1628 * in it. So the only way that the current phase 1629 * could be 'data-in' is if the parity error is for 1630 * an already acked byte in the data phase. During 1631 * synchronous data-in transfers, we may actually 1632 * ack bytes before latching the current phase in 1633 * LASTPHASE, leading to the discrepancy between 1634 * curphase and lastphase. 1635 */ 1636 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0 1637 || curphase == P_DATAIN || curphase == P_DATAIN_DT) 1638 errorphase = curphase; 1639 else 1640 errorphase = lastphase; 1641 1642 for (i = 0; i < num_phases; i++) { 1643 if (errorphase == ahc_phase_table[i].phase) 1644 break; 1645 } 1646 mesg_out = ahc_phase_table[i].mesg_out; 1647 silent = FALSE; 1648 if (scb != NULL) { 1649 if (SCB_IS_SILENT(scb)) 1650 silent = TRUE; 1651 else 1652 ahc_print_path(ahc, scb); 1653 scb->flags |= SCB_TRANSMISSION_ERROR; 1654 } else 1655 printk("%s:%c:%d: ", ahc_name(ahc), intr_channel, 1656 SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID))); 1657 scsirate = ahc_inb(ahc, SCSIRATE); 1658 if (silent == FALSE) { 1659 printk("parity error detected %s. " 1660 "SEQADDR(0x%x) SCSIRATE(0x%x)\n", 1661 ahc_phase_table[i].phasemsg, 1662 ahc_inw(ahc, SEQADDR0), 1663 scsirate); 1664 if ((ahc->features & AHC_DT) != 0) { 1665 if ((sstat2 & CRCVALERR) != 0) 1666 printk("\tCRC Value Mismatch\n"); 1667 if ((sstat2 & CRCENDERR) != 0) 1668 printk("\tNo terminal CRC packet " 1669 "recevied\n"); 1670 if ((sstat2 & CRCREQERR) != 0) 1671 printk("\tIllegal CRC packet " 1672 "request\n"); 1673 if ((sstat2 & DUAL_EDGE_ERR) != 0) 1674 printk("\tUnexpected %sDT Data Phase\n", 1675 (scsirate & SINGLE_EDGE) 1676 ? "" : "non-"); 1677 } 1678 } 1679 1680 if ((ahc->features & AHC_DT) != 0 1681 && (sstat2 & DUAL_EDGE_ERR) != 0) { 1682 /* 1683 * This error applies regardless of 1684 * data direction, so ignore the value 1685 * in the phase table. 1686 */ 1687 mesg_out = MSG_INITIATOR_DET_ERR; 1688 } 1689 1690 /* 1691 * We've set the hardware to assert ATN if we 1692 * get a parity error on "in" phases, so all we 1693 * need to do is stuff the message buffer with 1694 * the appropriate message. "In" phases have set 1695 * mesg_out to something other than MSG_NOP. 1696 */ 1697 if (mesg_out != MSG_NOOP) { 1698 if (ahc->msg_type != MSG_TYPE_NONE) 1699 ahc->send_msg_perror = TRUE; 1700 else 1701 ahc_outb(ahc, MSG_OUT, mesg_out); 1702 } 1703 /* 1704 * Force a renegotiation with this target just in 1705 * case we are out of sync for some external reason 1706 * unknown (or unreported) by the target. 1707 */ 1708 ahc_fetch_devinfo(ahc, &devinfo); 1709 ahc_force_renegotiation(ahc, &devinfo); 1710 1711 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1712 ahc_unpause(ahc); 1713 } else if ((status & SELTO) != 0) { 1714 u_int scbptr; 1715 1716 /* Stop the selection */ 1717 ahc_outb(ahc, SCSISEQ, 0); 1718 1719 /* No more pending messages */ 1720 ahc_clear_msg_state(ahc); 1721 1722 /* Clear interrupt state */ 1723 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 1724 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 1725 1726 /* 1727 * Although the driver does not care about the 1728 * 'Selection in Progress' status bit, the busy 1729 * LED does. SELINGO is only cleared by a successful 1730 * selection, so we must manually clear it to insure 1731 * the LED turns off just incase no future successful 1732 * selections occur (e.g. no devices on the bus). 1733 */ 1734 ahc_outb(ahc, CLRSINT0, CLRSELINGO); 1735 1736 scbptr = ahc_inb(ahc, WAITING_SCBH); 1737 ahc_outb(ahc, SCBPTR, scbptr); 1738 scb_index = ahc_inb(ahc, SCB_TAG); 1739 1740 scb = ahc_lookup_scb(ahc, scb_index); 1741 if (scb == NULL) { 1742 printk("%s: ahc_intr - referenced scb not " 1743 "valid during SELTO scb(%d, %d)\n", 1744 ahc_name(ahc), scbptr, scb_index); 1745 ahc_dump_card_state(ahc); 1746 } else { 1747 struct ahc_devinfo devinfo; 1748 #ifdef AHC_DEBUG 1749 if ((ahc_debug & AHC_SHOW_SELTO) != 0) { 1750 ahc_print_path(ahc, scb); 1751 printk("Saw Selection Timeout for SCB 0x%x\n", 1752 scb_index); 1753 } 1754 #endif 1755 ahc_scb_devinfo(ahc, &devinfo, scb); 1756 ahc_set_transaction_status(scb, CAM_SEL_TIMEOUT); 1757 ahc_freeze_devq(ahc, scb); 1758 1759 /* 1760 * Cancel any pending transactions on the device 1761 * now that it seems to be missing. This will 1762 * also revert us to async/narrow transfers until 1763 * we can renegotiate with the device. 1764 */ 1765 ahc_handle_devreset(ahc, &devinfo, 1766 CAM_SEL_TIMEOUT, 1767 "Selection Timeout", 1768 /*verbose_level*/1); 1769 } 1770 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1771 ahc_restart(ahc); 1772 } else if ((status & BUSFREE) != 0 1773 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) { 1774 struct ahc_devinfo devinfo; 1775 u_int lastphase; 1776 u_int saved_scsiid; 1777 u_int saved_lun; 1778 u_int target; 1779 u_int initiator_role_id; 1780 char channel; 1781 int printerror; 1782 1783 /* 1784 * Clear our selection hardware as soon as possible. 1785 * We may have an entry in the waiting Q for this target, 1786 * that is affected by this busfree and we don't want to 1787 * go about selecting the target while we handle the event. 1788 */ 1789 ahc_outb(ahc, SCSISEQ, 1790 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 1791 1792 /* 1793 * Disable busfree interrupts and clear the busfree 1794 * interrupt status. We do this here so that several 1795 * bus transactions occur prior to clearing the SCSIINT 1796 * latch. It can take a bit for the clearing to take effect. 1797 */ 1798 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 1799 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR); 1800 1801 /* 1802 * Look at what phase we were last in. 1803 * If its message out, chances are pretty good 1804 * that the busfree was in response to one of 1805 * our abort requests. 1806 */ 1807 lastphase = ahc_inb(ahc, LASTPHASE); 1808 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID); 1809 saved_lun = ahc_inb(ahc, SAVED_LUN); 1810 target = SCSIID_TARGET(ahc, saved_scsiid); 1811 initiator_role_id = SCSIID_OUR_ID(saved_scsiid); 1812 channel = SCSIID_CHANNEL(ahc, saved_scsiid); 1813 ahc_compile_devinfo(&devinfo, initiator_role_id, 1814 target, saved_lun, channel, ROLE_INITIATOR); 1815 printerror = 1; 1816 1817 if (lastphase == P_MESGOUT) { 1818 u_int tag; 1819 1820 tag = SCB_LIST_NULL; 1821 if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE) 1822 || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) { 1823 if (ahc->msgout_buf[ahc->msgout_index - 1] 1824 == MSG_ABORT_TAG) 1825 tag = scb->hscb->tag; 1826 ahc_print_path(ahc, scb); 1827 printk("SCB %d - Abort%s Completed.\n", 1828 scb->hscb->tag, tag == SCB_LIST_NULL ? 1829 "" : " Tag"); 1830 ahc_abort_scbs(ahc, target, channel, 1831 saved_lun, tag, 1832 ROLE_INITIATOR, 1833 CAM_REQ_ABORTED); 1834 printerror = 0; 1835 } else if (ahc_sent_msg(ahc, AHCMSG_1B, 1836 MSG_BUS_DEV_RESET, TRUE)) { 1837 #ifdef __FreeBSD__ 1838 /* 1839 * Don't mark the user's request for this BDR 1840 * as completing with CAM_BDR_SENT. CAM3 1841 * specifies CAM_REQ_CMP. 1842 */ 1843 if (scb != NULL 1844 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV 1845 && ahc_match_scb(ahc, scb, target, channel, 1846 CAM_LUN_WILDCARD, 1847 SCB_LIST_NULL, 1848 ROLE_INITIATOR)) { 1849 ahc_set_transaction_status(scb, CAM_REQ_CMP); 1850 } 1851 #endif 1852 ahc_compile_devinfo(&devinfo, 1853 initiator_role_id, 1854 target, 1855 CAM_LUN_WILDCARD, 1856 channel, 1857 ROLE_INITIATOR); 1858 ahc_handle_devreset(ahc, &devinfo, 1859 CAM_BDR_SENT, 1860 "Bus Device Reset", 1861 /*verbose_level*/0); 1862 printerror = 0; 1863 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, 1864 MSG_EXT_PPR, FALSE)) { 1865 struct ahc_initiator_tinfo *tinfo; 1866 struct ahc_tmode_tstate *tstate; 1867 1868 /* 1869 * PPR Rejected. Try non-ppr negotiation 1870 * and retry command. 1871 */ 1872 tinfo = ahc_fetch_transinfo(ahc, 1873 devinfo.channel, 1874 devinfo.our_scsiid, 1875 devinfo.target, 1876 &tstate); 1877 tinfo->curr.transport_version = 2; 1878 tinfo->goal.transport_version = 2; 1879 tinfo->goal.ppr_options = 0; 1880 ahc_qinfifo_requeue_tail(ahc, scb); 1881 printerror = 0; 1882 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, 1883 MSG_EXT_WDTR, FALSE)) { 1884 /* 1885 * Negotiation Rejected. Go-narrow and 1886 * retry command. 1887 */ 1888 ahc_set_width(ahc, &devinfo, 1889 MSG_EXT_WDTR_BUS_8_BIT, 1890 AHC_TRANS_CUR|AHC_TRANS_GOAL, 1891 /*paused*/TRUE); 1892 ahc_qinfifo_requeue_tail(ahc, scb); 1893 printerror = 0; 1894 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, 1895 MSG_EXT_SDTR, FALSE)) { 1896 /* 1897 * Negotiation Rejected. Go-async and 1898 * retry command. 1899 */ 1900 ahc_set_syncrate(ahc, &devinfo, 1901 /*syncrate*/NULL, 1902 /*period*/0, /*offset*/0, 1903 /*ppr_options*/0, 1904 AHC_TRANS_CUR|AHC_TRANS_GOAL, 1905 /*paused*/TRUE); 1906 ahc_qinfifo_requeue_tail(ahc, scb); 1907 printerror = 0; 1908 } 1909 } 1910 if (printerror != 0) { 1911 u_int i; 1912 1913 if (scb != NULL) { 1914 u_int tag; 1915 1916 if ((scb->hscb->control & TAG_ENB) != 0) 1917 tag = scb->hscb->tag; 1918 else 1919 tag = SCB_LIST_NULL; 1920 ahc_print_path(ahc, scb); 1921 ahc_abort_scbs(ahc, target, channel, 1922 SCB_GET_LUN(scb), tag, 1923 ROLE_INITIATOR, 1924 CAM_UNEXP_BUSFREE); 1925 } else { 1926 /* 1927 * We had not fully identified this connection, 1928 * so we cannot abort anything. 1929 */ 1930 printk("%s: ", ahc_name(ahc)); 1931 } 1932 for (i = 0; i < num_phases; i++) { 1933 if (lastphase == ahc_phase_table[i].phase) 1934 break; 1935 } 1936 if (lastphase != P_BUSFREE) { 1937 /* 1938 * Renegotiate with this device at the 1939 * next opportunity just in case this busfree 1940 * is due to a negotiation mismatch with the 1941 * device. 1942 */ 1943 ahc_force_renegotiation(ahc, &devinfo); 1944 } 1945 printk("Unexpected busfree %s\n" 1946 "SEQADDR == 0x%x\n", 1947 ahc_phase_table[i].phasemsg, 1948 ahc_inb(ahc, SEQADDR0) 1949 | (ahc_inb(ahc, SEQADDR1) << 8)); 1950 } 1951 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1952 ahc_restart(ahc); 1953 } else { 1954 printk("%s: Missing case in ahc_handle_scsiint. status = %x\n", 1955 ahc_name(ahc), status); 1956 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1957 } 1958 } 1959 1960 /* 1961 * Force renegotiation to occur the next time we initiate 1962 * a command to the current device. 1963 */ 1964 static void 1965 ahc_force_renegotiation(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 1966 { 1967 struct ahc_initiator_tinfo *targ_info; 1968 struct ahc_tmode_tstate *tstate; 1969 1970 targ_info = ahc_fetch_transinfo(ahc, 1971 devinfo->channel, 1972 devinfo->our_scsiid, 1973 devinfo->target, 1974 &tstate); 1975 ahc_update_neg_request(ahc, devinfo, tstate, 1976 targ_info, AHC_NEG_IF_NON_ASYNC); 1977 } 1978 1979 #define AHC_MAX_STEPS 2000 1980 static void 1981 ahc_clear_critical_section(struct ahc_softc *ahc) 1982 { 1983 int stepping; 1984 int steps; 1985 u_int simode0; 1986 u_int simode1; 1987 1988 if (ahc->num_critical_sections == 0) 1989 return; 1990 1991 stepping = FALSE; 1992 steps = 0; 1993 simode0 = 0; 1994 simode1 = 0; 1995 for (;;) { 1996 struct cs *cs; 1997 u_int seqaddr; 1998 u_int i; 1999 2000 seqaddr = ahc_inb(ahc, SEQADDR0) 2001 | (ahc_inb(ahc, SEQADDR1) << 8); 2002 2003 /* 2004 * Seqaddr represents the next instruction to execute, 2005 * so we are really executing the instruction just 2006 * before it. 2007 */ 2008 if (seqaddr != 0) 2009 seqaddr -= 1; 2010 cs = ahc->critical_sections; 2011 for (i = 0; i < ahc->num_critical_sections; i++, cs++) { 2012 2013 if (cs->begin < seqaddr && cs->end >= seqaddr) 2014 break; 2015 } 2016 2017 if (i == ahc->num_critical_sections) 2018 break; 2019 2020 if (steps > AHC_MAX_STEPS) { 2021 printk("%s: Infinite loop in critical section\n", 2022 ahc_name(ahc)); 2023 ahc_dump_card_state(ahc); 2024 panic("critical section loop"); 2025 } 2026 2027 steps++; 2028 if (stepping == FALSE) { 2029 2030 /* 2031 * Disable all interrupt sources so that the 2032 * sequencer will not be stuck by a pausing 2033 * interrupt condition while we attempt to 2034 * leave a critical section. 2035 */ 2036 simode0 = ahc_inb(ahc, SIMODE0); 2037 ahc_outb(ahc, SIMODE0, 0); 2038 simode1 = ahc_inb(ahc, SIMODE1); 2039 if ((ahc->features & AHC_DT) != 0) 2040 /* 2041 * On DT class controllers, we 2042 * use the enhanced busfree logic. 2043 * Unfortunately we cannot re-enable 2044 * busfree detection within the 2045 * current connection, so we must 2046 * leave it on while single stepping. 2047 */ 2048 ahc_outb(ahc, SIMODE1, simode1 & ENBUSFREE); 2049 else 2050 ahc_outb(ahc, SIMODE1, 0); 2051 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2052 ahc_outb(ahc, SEQCTL, ahc->seqctl | STEP); 2053 stepping = TRUE; 2054 } 2055 if ((ahc->features & AHC_DT) != 0) { 2056 ahc_outb(ahc, CLRSINT1, CLRBUSFREE); 2057 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2058 } 2059 ahc_outb(ahc, HCNTRL, ahc->unpause); 2060 while (!ahc_is_paused(ahc)) 2061 ahc_delay(200); 2062 } 2063 if (stepping) { 2064 ahc_outb(ahc, SIMODE0, simode0); 2065 ahc_outb(ahc, SIMODE1, simode1); 2066 ahc_outb(ahc, SEQCTL, ahc->seqctl); 2067 } 2068 } 2069 2070 /* 2071 * Clear any pending interrupt status. 2072 */ 2073 static void 2074 ahc_clear_intstat(struct ahc_softc *ahc) 2075 { 2076 /* Clear any interrupt conditions this may have caused */ 2077 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 2078 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| 2079 CLRREQINIT); 2080 ahc_flush_device_writes(ahc); 2081 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); 2082 ahc_flush_device_writes(ahc); 2083 ahc_outb(ahc, CLRINT, CLRSCSIINT); 2084 ahc_flush_device_writes(ahc); 2085 } 2086 2087 /**************************** Debugging Routines ******************************/ 2088 #ifdef AHC_DEBUG 2089 uint32_t ahc_debug = AHC_DEBUG_OPTS; 2090 #endif 2091 2092 #if 0 /* unused */ 2093 static void 2094 ahc_print_scb(struct scb *scb) 2095 { 2096 int i; 2097 2098 struct hardware_scb *hscb = scb->hscb; 2099 2100 printk("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n", 2101 (void *)scb, 2102 hscb->control, 2103 hscb->scsiid, 2104 hscb->lun, 2105 hscb->cdb_len); 2106 printk("Shared Data: "); 2107 for (i = 0; i < sizeof(hscb->shared_data.cdb); i++) 2108 printk("%#02x", hscb->shared_data.cdb[i]); 2109 printk(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n", 2110 ahc_le32toh(hscb->dataptr), 2111 ahc_le32toh(hscb->datacnt), 2112 ahc_le32toh(hscb->sgptr), 2113 hscb->tag); 2114 if (scb->sg_count > 0) { 2115 for (i = 0; i < scb->sg_count; i++) { 2116 printk("sg[%d] - Addr 0x%x%x : Length %d\n", 2117 i, 2118 (ahc_le32toh(scb->sg_list[i].len) >> 24 2119 & SG_HIGH_ADDR_BITS), 2120 ahc_le32toh(scb->sg_list[i].addr), 2121 ahc_le32toh(scb->sg_list[i].len)); 2122 } 2123 } 2124 } 2125 #endif 2126 2127 /************************* Transfer Negotiation *******************************/ 2128 /* 2129 * Allocate per target mode instance (ID we respond to as a target) 2130 * transfer negotiation data structures. 2131 */ 2132 static struct ahc_tmode_tstate * 2133 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel) 2134 { 2135 struct ahc_tmode_tstate *master_tstate; 2136 struct ahc_tmode_tstate *tstate; 2137 int i; 2138 2139 master_tstate = ahc->enabled_targets[ahc->our_id]; 2140 if (channel == 'B') { 2141 scsi_id += 8; 2142 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8]; 2143 } 2144 if (ahc->enabled_targets[scsi_id] != NULL 2145 && ahc->enabled_targets[scsi_id] != master_tstate) 2146 panic("%s: ahc_alloc_tstate - Target already allocated", 2147 ahc_name(ahc)); 2148 tstate = kmalloc(sizeof(*tstate), GFP_ATOMIC); 2149 if (tstate == NULL) 2150 return (NULL); 2151 2152 /* 2153 * If we have allocated a master tstate, copy user settings from 2154 * the master tstate (taken from SRAM or the EEPROM) for this 2155 * channel, but reset our current and goal settings to async/narrow 2156 * until an initiator talks to us. 2157 */ 2158 if (master_tstate != NULL) { 2159 memcpy(tstate, master_tstate, sizeof(*tstate)); 2160 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns)); 2161 tstate->ultraenb = 0; 2162 for (i = 0; i < AHC_NUM_TARGETS; i++) { 2163 memset(&tstate->transinfo[i].curr, 0, 2164 sizeof(tstate->transinfo[i].curr)); 2165 memset(&tstate->transinfo[i].goal, 0, 2166 sizeof(tstate->transinfo[i].goal)); 2167 } 2168 } else 2169 memset(tstate, 0, sizeof(*tstate)); 2170 ahc->enabled_targets[scsi_id] = tstate; 2171 return (tstate); 2172 } 2173 2174 #ifdef AHC_TARGET_MODE 2175 /* 2176 * Free per target mode instance (ID we respond to as a target) 2177 * transfer negotiation data structures. 2178 */ 2179 static void 2180 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force) 2181 { 2182 struct ahc_tmode_tstate *tstate; 2183 2184 /* 2185 * Don't clean up our "master" tstate. 2186 * It has our default user settings. 2187 */ 2188 if (((channel == 'B' && scsi_id == ahc->our_id_b) 2189 || (channel == 'A' && scsi_id == ahc->our_id)) 2190 && force == FALSE) 2191 return; 2192 2193 if (channel == 'B') 2194 scsi_id += 8; 2195 tstate = ahc->enabled_targets[scsi_id]; 2196 if (tstate != NULL) 2197 kfree(tstate); 2198 ahc->enabled_targets[scsi_id] = NULL; 2199 } 2200 #endif 2201 2202 /* 2203 * Called when we have an active connection to a target on the bus, 2204 * this function finds the nearest syncrate to the input period limited 2205 * by the capabilities of the bus connectivity of and sync settings for 2206 * the target. 2207 */ 2208 static const struct ahc_syncrate * 2209 ahc_devlimited_syncrate(struct ahc_softc *ahc, 2210 struct ahc_initiator_tinfo *tinfo, 2211 u_int *period, u_int *ppr_options, role_t role) 2212 { 2213 struct ahc_transinfo *transinfo; 2214 u_int maxsync; 2215 2216 if ((ahc->features & AHC_ULTRA2) != 0) { 2217 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 2218 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 2219 maxsync = AHC_SYNCRATE_DT; 2220 } else { 2221 maxsync = AHC_SYNCRATE_ULTRA; 2222 /* Can't do DT on an SE bus */ 2223 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 2224 } 2225 } else if ((ahc->features & AHC_ULTRA) != 0) { 2226 maxsync = AHC_SYNCRATE_ULTRA; 2227 } else { 2228 maxsync = AHC_SYNCRATE_FAST; 2229 } 2230 /* 2231 * Never allow a value higher than our current goal 2232 * period otherwise we may allow a target initiated 2233 * negotiation to go above the limit as set by the 2234 * user. In the case of an initiator initiated 2235 * sync negotiation, we limit based on the user 2236 * setting. This allows the system to still accept 2237 * incoming negotiations even if target initiated 2238 * negotiation is not performed. 2239 */ 2240 if (role == ROLE_TARGET) 2241 transinfo = &tinfo->user; 2242 else 2243 transinfo = &tinfo->goal; 2244 *ppr_options &= transinfo->ppr_options; 2245 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) { 2246 maxsync = max(maxsync, (u_int)AHC_SYNCRATE_ULTRA2); 2247 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 2248 } 2249 if (transinfo->period == 0) { 2250 *period = 0; 2251 *ppr_options = 0; 2252 return (NULL); 2253 } 2254 *period = max(*period, (u_int)transinfo->period); 2255 return (ahc_find_syncrate(ahc, period, ppr_options, maxsync)); 2256 } 2257 2258 /* 2259 * Look up the valid period to SCSIRATE conversion in our table. 2260 * Return the period and offset that should be sent to the target 2261 * if this was the beginning of an SDTR. 2262 */ 2263 const struct ahc_syncrate * 2264 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, 2265 u_int *ppr_options, u_int maxsync) 2266 { 2267 const struct ahc_syncrate *syncrate; 2268 2269 if ((ahc->features & AHC_DT) == 0) 2270 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 2271 2272 /* Skip all DT only entries if DT is not available */ 2273 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0 2274 && maxsync < AHC_SYNCRATE_ULTRA2) 2275 maxsync = AHC_SYNCRATE_ULTRA2; 2276 2277 /* Now set the maxsync based on the card capabilities 2278 * DT is already done above */ 2279 if ((ahc->features & (AHC_DT | AHC_ULTRA2)) == 0 2280 && maxsync < AHC_SYNCRATE_ULTRA) 2281 maxsync = AHC_SYNCRATE_ULTRA; 2282 if ((ahc->features & (AHC_DT | AHC_ULTRA2 | AHC_ULTRA)) == 0 2283 && maxsync < AHC_SYNCRATE_FAST) 2284 maxsync = AHC_SYNCRATE_FAST; 2285 2286 for (syncrate = &ahc_syncrates[maxsync]; 2287 syncrate->rate != NULL; 2288 syncrate++) { 2289 2290 /* 2291 * The Ultra2 table doesn't go as low 2292 * as for the Fast/Ultra cards. 2293 */ 2294 if ((ahc->features & AHC_ULTRA2) != 0 2295 && (syncrate->sxfr_u2 == 0)) 2296 break; 2297 2298 if (*period <= syncrate->period) { 2299 /* 2300 * When responding to a target that requests 2301 * sync, the requested rate may fall between 2302 * two rates that we can output, but still be 2303 * a rate that we can receive. Because of this, 2304 * we want to respond to the target with 2305 * the same rate that it sent to us even 2306 * if the period we use to send data to it 2307 * is lower. Only lower the response period 2308 * if we must. 2309 */ 2310 if (syncrate == &ahc_syncrates[maxsync]) 2311 *period = syncrate->period; 2312 2313 /* 2314 * At some speeds, we only support 2315 * ST transfers. 2316 */ 2317 if ((syncrate->sxfr_u2 & ST_SXFR) != 0) 2318 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 2319 break; 2320 } 2321 } 2322 2323 if ((*period == 0) 2324 || (syncrate->rate == NULL) 2325 || ((ahc->features & AHC_ULTRA2) != 0 2326 && (syncrate->sxfr_u2 == 0))) { 2327 /* Use asynchronous transfers. */ 2328 *period = 0; 2329 syncrate = NULL; 2330 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 2331 } 2332 return (syncrate); 2333 } 2334 2335 /* 2336 * Convert from an entry in our syncrate table to the SCSI equivalent 2337 * sync "period" factor. 2338 */ 2339 u_int 2340 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) 2341 { 2342 const struct ahc_syncrate *syncrate; 2343 2344 if ((ahc->features & AHC_ULTRA2) != 0) 2345 scsirate &= SXFR_ULTRA2; 2346 else 2347 scsirate &= SXFR; 2348 2349 /* now set maxsync based on card capabilities */ 2350 if ((ahc->features & AHC_DT) == 0 && maxsync < AHC_SYNCRATE_ULTRA2) 2351 maxsync = AHC_SYNCRATE_ULTRA2; 2352 if ((ahc->features & (AHC_DT | AHC_ULTRA2)) == 0 2353 && maxsync < AHC_SYNCRATE_ULTRA) 2354 maxsync = AHC_SYNCRATE_ULTRA; 2355 if ((ahc->features & (AHC_DT | AHC_ULTRA2 | AHC_ULTRA)) == 0 2356 && maxsync < AHC_SYNCRATE_FAST) 2357 maxsync = AHC_SYNCRATE_FAST; 2358 2359 2360 syncrate = &ahc_syncrates[maxsync]; 2361 while (syncrate->rate != NULL) { 2362 2363 if ((ahc->features & AHC_ULTRA2) != 0) { 2364 if (syncrate->sxfr_u2 == 0) 2365 break; 2366 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2)) 2367 return (syncrate->period); 2368 } else if (scsirate == (syncrate->sxfr & SXFR)) { 2369 return (syncrate->period); 2370 } 2371 syncrate++; 2372 } 2373 return (0); /* async */ 2374 } 2375 2376 /* 2377 * Truncate the given synchronous offset to a value the 2378 * current adapter type and syncrate are capable of. 2379 */ 2380 static void 2381 ahc_validate_offset(struct ahc_softc *ahc, 2382 struct ahc_initiator_tinfo *tinfo, 2383 const struct ahc_syncrate *syncrate, 2384 u_int *offset, int wide, role_t role) 2385 { 2386 u_int maxoffset; 2387 2388 /* Limit offset to what we can do */ 2389 if (syncrate == NULL) { 2390 maxoffset = 0; 2391 } else if ((ahc->features & AHC_ULTRA2) != 0) { 2392 maxoffset = MAX_OFFSET_ULTRA2; 2393 } else { 2394 if (wide) 2395 maxoffset = MAX_OFFSET_16BIT; 2396 else 2397 maxoffset = MAX_OFFSET_8BIT; 2398 } 2399 *offset = min(*offset, maxoffset); 2400 if (tinfo != NULL) { 2401 if (role == ROLE_TARGET) 2402 *offset = min(*offset, (u_int)tinfo->user.offset); 2403 else 2404 *offset = min(*offset, (u_int)tinfo->goal.offset); 2405 } 2406 } 2407 2408 /* 2409 * Truncate the given transfer width parameter to a value the 2410 * current adapter type is capable of. 2411 */ 2412 static void 2413 ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo, 2414 u_int *bus_width, role_t role) 2415 { 2416 switch (*bus_width) { 2417 default: 2418 if (ahc->features & AHC_WIDE) { 2419 /* Respond Wide */ 2420 *bus_width = MSG_EXT_WDTR_BUS_16_BIT; 2421 break; 2422 } 2423 /* FALLTHROUGH */ 2424 case MSG_EXT_WDTR_BUS_8_BIT: 2425 *bus_width = MSG_EXT_WDTR_BUS_8_BIT; 2426 break; 2427 } 2428 if (tinfo != NULL) { 2429 if (role == ROLE_TARGET) 2430 *bus_width = min((u_int)tinfo->user.width, *bus_width); 2431 else 2432 *bus_width = min((u_int)tinfo->goal.width, *bus_width); 2433 } 2434 } 2435 2436 /* 2437 * Update the bitmask of targets for which the controller should 2438 * negotiate with at the next convenient opportunity. This currently 2439 * means the next time we send the initial identify messages for 2440 * a new transaction. 2441 */ 2442 int 2443 ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2444 struct ahc_tmode_tstate *tstate, 2445 struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type) 2446 { 2447 u_int auto_negotiate_orig; 2448 2449 auto_negotiate_orig = tstate->auto_negotiate; 2450 if (neg_type == AHC_NEG_ALWAYS) { 2451 /* 2452 * Force our "current" settings to be 2453 * unknown so that unless a bus reset 2454 * occurs the need to renegotiate is 2455 * recorded persistently. 2456 */ 2457 if ((ahc->features & AHC_WIDE) != 0) 2458 tinfo->curr.width = AHC_WIDTH_UNKNOWN; 2459 tinfo->curr.period = AHC_PERIOD_UNKNOWN; 2460 tinfo->curr.offset = AHC_OFFSET_UNKNOWN; 2461 } 2462 if (tinfo->curr.period != tinfo->goal.period 2463 || tinfo->curr.width != tinfo->goal.width 2464 || tinfo->curr.offset != tinfo->goal.offset 2465 || tinfo->curr.ppr_options != tinfo->goal.ppr_options 2466 || (neg_type == AHC_NEG_IF_NON_ASYNC 2467 && (tinfo->goal.offset != 0 2468 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT 2469 || tinfo->goal.ppr_options != 0))) 2470 tstate->auto_negotiate |= devinfo->target_mask; 2471 else 2472 tstate->auto_negotiate &= ~devinfo->target_mask; 2473 2474 return (auto_negotiate_orig != tstate->auto_negotiate); 2475 } 2476 2477 /* 2478 * Update the user/goal/curr tables of synchronous negotiation 2479 * parameters as well as, in the case of a current or active update, 2480 * any data structures on the host controller. In the case of an 2481 * active update, the specified target is currently talking to us on 2482 * the bus, so the transfer parameter update must take effect 2483 * immediately. 2484 */ 2485 void 2486 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2487 const struct ahc_syncrate *syncrate, u_int period, 2488 u_int offset, u_int ppr_options, u_int type, int paused) 2489 { 2490 struct ahc_initiator_tinfo *tinfo; 2491 struct ahc_tmode_tstate *tstate; 2492 u_int old_period; 2493 u_int old_offset; 2494 u_int old_ppr; 2495 int active; 2496 int update_needed; 2497 2498 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 2499 update_needed = 0; 2500 2501 if (syncrate == NULL) { 2502 period = 0; 2503 offset = 0; 2504 } 2505 2506 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2507 devinfo->target, &tstate); 2508 2509 if ((type & AHC_TRANS_USER) != 0) { 2510 tinfo->user.period = period; 2511 tinfo->user.offset = offset; 2512 tinfo->user.ppr_options = ppr_options; 2513 } 2514 2515 if ((type & AHC_TRANS_GOAL) != 0) { 2516 tinfo->goal.period = period; 2517 tinfo->goal.offset = offset; 2518 tinfo->goal.ppr_options = ppr_options; 2519 } 2520 2521 old_period = tinfo->curr.period; 2522 old_offset = tinfo->curr.offset; 2523 old_ppr = tinfo->curr.ppr_options; 2524 2525 if ((type & AHC_TRANS_CUR) != 0 2526 && (old_period != period 2527 || old_offset != offset 2528 || old_ppr != ppr_options)) { 2529 u_int scsirate; 2530 2531 update_needed++; 2532 scsirate = tinfo->scsirate; 2533 if ((ahc->features & AHC_ULTRA2) != 0) { 2534 2535 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC); 2536 if (syncrate != NULL) { 2537 scsirate |= syncrate->sxfr_u2; 2538 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) 2539 scsirate |= ENABLE_CRC; 2540 else 2541 scsirate |= SINGLE_EDGE; 2542 } 2543 } else { 2544 2545 scsirate &= ~(SXFR|SOFS); 2546 /* 2547 * Ensure Ultra mode is set properly for 2548 * this target. 2549 */ 2550 tstate->ultraenb &= ~devinfo->target_mask; 2551 if (syncrate != NULL) { 2552 if (syncrate->sxfr & ULTRA_SXFR) { 2553 tstate->ultraenb |= 2554 devinfo->target_mask; 2555 } 2556 scsirate |= syncrate->sxfr & SXFR; 2557 scsirate |= offset & SOFS; 2558 } 2559 if (active) { 2560 u_int sxfrctl0; 2561 2562 sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 2563 sxfrctl0 &= ~FAST20; 2564 if (tstate->ultraenb & devinfo->target_mask) 2565 sxfrctl0 |= FAST20; 2566 ahc_outb(ahc, SXFRCTL0, sxfrctl0); 2567 } 2568 } 2569 if (active) { 2570 ahc_outb(ahc, SCSIRATE, scsirate); 2571 if ((ahc->features & AHC_ULTRA2) != 0) 2572 ahc_outb(ahc, SCSIOFFSET, offset); 2573 } 2574 2575 tinfo->scsirate = scsirate; 2576 tinfo->curr.period = period; 2577 tinfo->curr.offset = offset; 2578 tinfo->curr.ppr_options = ppr_options; 2579 2580 ahc_send_async(ahc, devinfo->channel, devinfo->target, 2581 CAM_LUN_WILDCARD, AC_TRANSFER_NEG); 2582 if (bootverbose) { 2583 if (offset != 0) { 2584 printk("%s: target %d synchronous at %sMHz%s, " 2585 "offset = 0x%x\n", ahc_name(ahc), 2586 devinfo->target, syncrate->rate, 2587 (ppr_options & MSG_EXT_PPR_DT_REQ) 2588 ? " DT" : "", offset); 2589 } else { 2590 printk("%s: target %d using " 2591 "asynchronous transfers\n", 2592 ahc_name(ahc), devinfo->target); 2593 } 2594 } 2595 } 2596 2597 update_needed += ahc_update_neg_request(ahc, devinfo, tstate, 2598 tinfo, AHC_NEG_TO_GOAL); 2599 2600 if (update_needed) 2601 ahc_update_pending_scbs(ahc); 2602 } 2603 2604 /* 2605 * Update the user/goal/curr tables of wide negotiation 2606 * parameters as well as, in the case of a current or active update, 2607 * any data structures on the host controller. In the case of an 2608 * active update, the specified target is currently talking to us on 2609 * the bus, so the transfer parameter update must take effect 2610 * immediately. 2611 */ 2612 void 2613 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2614 u_int width, u_int type, int paused) 2615 { 2616 struct ahc_initiator_tinfo *tinfo; 2617 struct ahc_tmode_tstate *tstate; 2618 u_int oldwidth; 2619 int active; 2620 int update_needed; 2621 2622 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 2623 update_needed = 0; 2624 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2625 devinfo->target, &tstate); 2626 2627 if ((type & AHC_TRANS_USER) != 0) 2628 tinfo->user.width = width; 2629 2630 if ((type & AHC_TRANS_GOAL) != 0) 2631 tinfo->goal.width = width; 2632 2633 oldwidth = tinfo->curr.width; 2634 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { 2635 u_int scsirate; 2636 2637 update_needed++; 2638 scsirate = tinfo->scsirate; 2639 scsirate &= ~WIDEXFER; 2640 if (width == MSG_EXT_WDTR_BUS_16_BIT) 2641 scsirate |= WIDEXFER; 2642 2643 tinfo->scsirate = scsirate; 2644 2645 if (active) 2646 ahc_outb(ahc, SCSIRATE, scsirate); 2647 2648 tinfo->curr.width = width; 2649 2650 ahc_send_async(ahc, devinfo->channel, devinfo->target, 2651 CAM_LUN_WILDCARD, AC_TRANSFER_NEG); 2652 if (bootverbose) { 2653 printk("%s: target %d using %dbit transfers\n", 2654 ahc_name(ahc), devinfo->target, 2655 8 * (0x01 << width)); 2656 } 2657 } 2658 2659 update_needed += ahc_update_neg_request(ahc, devinfo, tstate, 2660 tinfo, AHC_NEG_TO_GOAL); 2661 if (update_needed) 2662 ahc_update_pending_scbs(ahc); 2663 } 2664 2665 /* 2666 * Update the current state of tagged queuing for a given target. 2667 */ 2668 static void 2669 ahc_set_tags(struct ahc_softc *ahc, struct scsi_cmnd *cmd, 2670 struct ahc_devinfo *devinfo, ahc_queue_alg alg) 2671 { 2672 struct scsi_device *sdev = cmd->device; 2673 2674 ahc_platform_set_tags(ahc, sdev, devinfo, alg); 2675 ahc_send_async(ahc, devinfo->channel, devinfo->target, 2676 devinfo->lun, AC_TRANSFER_NEG); 2677 } 2678 2679 /* 2680 * When the transfer settings for a connection change, update any 2681 * in-transit SCBs to contain the new data so the hardware will 2682 * be set correctly during future (re)selections. 2683 */ 2684 static void 2685 ahc_update_pending_scbs(struct ahc_softc *ahc) 2686 { 2687 struct scb *pending_scb; 2688 int pending_scb_count; 2689 int i; 2690 int paused; 2691 u_int saved_scbptr; 2692 2693 /* 2694 * Traverse the pending SCB list and ensure that all of the 2695 * SCBs there have the proper settings. 2696 */ 2697 pending_scb_count = 0; 2698 LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) { 2699 struct ahc_devinfo devinfo; 2700 struct hardware_scb *pending_hscb; 2701 struct ahc_initiator_tinfo *tinfo; 2702 struct ahc_tmode_tstate *tstate; 2703 2704 ahc_scb_devinfo(ahc, &devinfo, pending_scb); 2705 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 2706 devinfo.our_scsiid, 2707 devinfo.target, &tstate); 2708 pending_hscb = pending_scb->hscb; 2709 pending_hscb->control &= ~ULTRAENB; 2710 if ((tstate->ultraenb & devinfo.target_mask) != 0) 2711 pending_hscb->control |= ULTRAENB; 2712 pending_hscb->scsirate = tinfo->scsirate; 2713 pending_hscb->scsioffset = tinfo->curr.offset; 2714 if ((tstate->auto_negotiate & devinfo.target_mask) == 0 2715 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) { 2716 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE; 2717 pending_hscb->control &= ~MK_MESSAGE; 2718 } 2719 ahc_sync_scb(ahc, pending_scb, 2720 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2721 pending_scb_count++; 2722 } 2723 2724 if (pending_scb_count == 0) 2725 return; 2726 2727 if (ahc_is_paused(ahc)) { 2728 paused = 1; 2729 } else { 2730 paused = 0; 2731 ahc_pause(ahc); 2732 } 2733 2734 saved_scbptr = ahc_inb(ahc, SCBPTR); 2735 /* Ensure that the hscbs down on the card match the new information */ 2736 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 2737 struct hardware_scb *pending_hscb; 2738 u_int control; 2739 u_int scb_tag; 2740 2741 ahc_outb(ahc, SCBPTR, i); 2742 scb_tag = ahc_inb(ahc, SCB_TAG); 2743 pending_scb = ahc_lookup_scb(ahc, scb_tag); 2744 if (pending_scb == NULL) 2745 continue; 2746 2747 pending_hscb = pending_scb->hscb; 2748 control = ahc_inb(ahc, SCB_CONTROL); 2749 control &= ~(ULTRAENB|MK_MESSAGE); 2750 control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE); 2751 ahc_outb(ahc, SCB_CONTROL, control); 2752 ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate); 2753 ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset); 2754 } 2755 ahc_outb(ahc, SCBPTR, saved_scbptr); 2756 2757 if (paused == 0) 2758 ahc_unpause(ahc); 2759 } 2760 2761 /**************************** Pathing Information *****************************/ 2762 static void 2763 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2764 { 2765 u_int saved_scsiid; 2766 role_t role; 2767 int our_id; 2768 2769 if (ahc_inb(ahc, SSTAT0) & TARGET) 2770 role = ROLE_TARGET; 2771 else 2772 role = ROLE_INITIATOR; 2773 2774 if (role == ROLE_TARGET 2775 && (ahc->features & AHC_MULTI_TID) != 0 2776 && (ahc_inb(ahc, SEQ_FLAGS) 2777 & (CMDPHASE_PENDING|TARG_CMD_PENDING|NO_DISCONNECT)) != 0) { 2778 /* We were selected, so pull our id from TARGIDIN */ 2779 our_id = ahc_inb(ahc, TARGIDIN) & OID; 2780 } else if ((ahc->features & AHC_ULTRA2) != 0) 2781 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 2782 else 2783 our_id = ahc_inb(ahc, SCSIID) & OID; 2784 2785 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID); 2786 ahc_compile_devinfo(devinfo, 2787 our_id, 2788 SCSIID_TARGET(ahc, saved_scsiid), 2789 ahc_inb(ahc, SAVED_LUN), 2790 SCSIID_CHANNEL(ahc, saved_scsiid), 2791 role); 2792 } 2793 2794 static const struct ahc_phase_table_entry* 2795 ahc_lookup_phase_entry(int phase) 2796 { 2797 const struct ahc_phase_table_entry *entry; 2798 const struct ahc_phase_table_entry *last_entry; 2799 2800 /* 2801 * num_phases doesn't include the default entry which 2802 * will be returned if the phase doesn't match. 2803 */ 2804 last_entry = &ahc_phase_table[num_phases]; 2805 for (entry = ahc_phase_table; entry < last_entry; entry++) { 2806 if (phase == entry->phase) 2807 break; 2808 } 2809 return (entry); 2810 } 2811 2812 void 2813 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target, 2814 u_int lun, char channel, role_t role) 2815 { 2816 devinfo->our_scsiid = our_id; 2817 devinfo->target = target; 2818 devinfo->lun = lun; 2819 devinfo->target_offset = target; 2820 devinfo->channel = channel; 2821 devinfo->role = role; 2822 if (channel == 'B') 2823 devinfo->target_offset += 8; 2824 devinfo->target_mask = (0x01 << devinfo->target_offset); 2825 } 2826 2827 void 2828 ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2829 { 2830 printk("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel, 2831 devinfo->target, devinfo->lun); 2832 } 2833 2834 static void 2835 ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2836 struct scb *scb) 2837 { 2838 role_t role; 2839 int our_id; 2840 2841 our_id = SCSIID_OUR_ID(scb->hscb->scsiid); 2842 role = ROLE_INITIATOR; 2843 if ((scb->flags & SCB_TARGET_SCB) != 0) 2844 role = ROLE_TARGET; 2845 ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb), 2846 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role); 2847 } 2848 2849 2850 /************************ Message Phase Processing ****************************/ 2851 static void 2852 ahc_assert_atn(struct ahc_softc *ahc) 2853 { 2854 u_int scsisigo; 2855 2856 scsisigo = ATNO; 2857 if ((ahc->features & AHC_DT) == 0) 2858 scsisigo |= ahc_inb(ahc, SCSISIGI); 2859 ahc_outb(ahc, SCSISIGO, scsisigo); 2860 } 2861 2862 /* 2863 * When an initiator transaction with the MK_MESSAGE flag either reconnects 2864 * or enters the initial message out phase, we are interrupted. Fill our 2865 * outgoing message buffer with the appropriate message and beging handing 2866 * the message phase(s) manually. 2867 */ 2868 static void 2869 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2870 struct scb *scb) 2871 { 2872 /* 2873 * To facilitate adding multiple messages together, 2874 * each routine should increment the index and len 2875 * variables instead of setting them explicitly. 2876 */ 2877 ahc->msgout_index = 0; 2878 ahc->msgout_len = 0; 2879 2880 if ((scb->flags & SCB_DEVICE_RESET) == 0 2881 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) { 2882 u_int identify_msg; 2883 2884 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb); 2885 if ((scb->hscb->control & DISCENB) != 0) 2886 identify_msg |= MSG_IDENTIFY_DISCFLAG; 2887 ahc->msgout_buf[ahc->msgout_index++] = identify_msg; 2888 ahc->msgout_len++; 2889 2890 if ((scb->hscb->control & TAG_ENB) != 0) { 2891 ahc->msgout_buf[ahc->msgout_index++] = 2892 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE); 2893 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag; 2894 ahc->msgout_len += 2; 2895 } 2896 } 2897 2898 if (scb->flags & SCB_DEVICE_RESET) { 2899 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET; 2900 ahc->msgout_len++; 2901 ahc_print_path(ahc, scb); 2902 printk("Bus Device Reset Message Sent\n"); 2903 /* 2904 * Clear our selection hardware in advance of 2905 * the busfree. We may have an entry in the waiting 2906 * Q for this target, and we don't want to go about 2907 * selecting while we handle the busfree and blow it 2908 * away. 2909 */ 2910 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 2911 } else if ((scb->flags & SCB_ABORT) != 0) { 2912 if ((scb->hscb->control & TAG_ENB) != 0) 2913 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG; 2914 else 2915 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT; 2916 ahc->msgout_len++; 2917 ahc_print_path(ahc, scb); 2918 printk("Abort%s Message Sent\n", 2919 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : ""); 2920 /* 2921 * Clear our selection hardware in advance of 2922 * the busfree. We may have an entry in the waiting 2923 * Q for this target, and we don't want to go about 2924 * selecting while we handle the busfree and blow it 2925 * away. 2926 */ 2927 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 2928 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) { 2929 ahc_build_transfer_msg(ahc, devinfo); 2930 } else { 2931 printk("ahc_intr: AWAITING_MSG for an SCB that " 2932 "does not have a waiting message\n"); 2933 printk("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid, 2934 devinfo->target_mask); 2935 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " 2936 "SCB flags = %x", scb->hscb->tag, scb->hscb->control, 2937 ahc_inb(ahc, MSG_OUT), scb->flags); 2938 } 2939 2940 /* 2941 * Clear the MK_MESSAGE flag from the SCB so we aren't 2942 * asked to send this message again. 2943 */ 2944 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE); 2945 scb->hscb->control &= ~MK_MESSAGE; 2946 ahc->msgout_index = 0; 2947 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2948 } 2949 2950 /* 2951 * Build an appropriate transfer negotiation message for the 2952 * currently active target. 2953 */ 2954 static void 2955 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2956 { 2957 /* 2958 * We need to initiate transfer negotiations. 2959 * If our current and goal settings are identical, 2960 * we want to renegotiate due to a check condition. 2961 */ 2962 struct ahc_initiator_tinfo *tinfo; 2963 struct ahc_tmode_tstate *tstate; 2964 const struct ahc_syncrate *rate; 2965 int dowide; 2966 int dosync; 2967 int doppr; 2968 u_int period; 2969 u_int ppr_options; 2970 u_int offset; 2971 2972 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2973 devinfo->target, &tstate); 2974 /* 2975 * Filter our period based on the current connection. 2976 * If we can't perform DT transfers on this segment (not in LVD 2977 * mode for instance), then our decision to issue a PPR message 2978 * may change. 2979 */ 2980 period = tinfo->goal.period; 2981 offset = tinfo->goal.offset; 2982 ppr_options = tinfo->goal.ppr_options; 2983 /* Target initiated PPR is not allowed in the SCSI spec */ 2984 if (devinfo->role == ROLE_TARGET) 2985 ppr_options = 0; 2986 rate = ahc_devlimited_syncrate(ahc, tinfo, &period, 2987 &ppr_options, devinfo->role); 2988 dowide = tinfo->curr.width != tinfo->goal.width; 2989 dosync = tinfo->curr.offset != offset || tinfo->curr.period != period; 2990 /* 2991 * Only use PPR if we have options that need it, even if the device 2992 * claims to support it. There might be an expander in the way 2993 * that doesn't. 2994 */ 2995 doppr = ppr_options != 0; 2996 2997 if (!dowide && !dosync && !doppr) { 2998 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 2999 dosync = tinfo->goal.offset != 0; 3000 } 3001 3002 if (!dowide && !dosync && !doppr) { 3003 /* 3004 * Force async with a WDTR message if we have a wide bus, 3005 * or just issue an SDTR with a 0 offset. 3006 */ 3007 if ((ahc->features & AHC_WIDE) != 0) 3008 dowide = 1; 3009 else 3010 dosync = 1; 3011 3012 if (bootverbose) { 3013 ahc_print_devinfo(ahc, devinfo); 3014 printk("Ensuring async\n"); 3015 } 3016 } 3017 3018 /* Target initiated PPR is not allowed in the SCSI spec */ 3019 if (devinfo->role == ROLE_TARGET) 3020 doppr = 0; 3021 3022 /* 3023 * Both the PPR message and SDTR message require the 3024 * goal syncrate to be limited to what the target device 3025 * is capable of handling (based on whether an LVD->SE 3026 * expander is on the bus), so combine these two cases. 3027 * Regardless, guarantee that if we are using WDTR and SDTR 3028 * messages that WDTR comes first. 3029 */ 3030 if (doppr || (dosync && !dowide)) { 3031 3032 offset = tinfo->goal.offset; 3033 ahc_validate_offset(ahc, tinfo, rate, &offset, 3034 doppr ? tinfo->goal.width 3035 : tinfo->curr.width, 3036 devinfo->role); 3037 if (doppr) { 3038 ahc_construct_ppr(ahc, devinfo, period, offset, 3039 tinfo->goal.width, ppr_options); 3040 } else { 3041 ahc_construct_sdtr(ahc, devinfo, period, offset); 3042 } 3043 } else { 3044 ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width); 3045 } 3046 } 3047 3048 /* 3049 * Build a synchronous negotiation message in our message 3050 * buffer based on the input parameters. 3051 */ 3052 static void 3053 ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3054 u_int period, u_int offset) 3055 { 3056 if (offset == 0) 3057 period = AHC_ASYNC_XFER_PERIOD; 3058 ahc->msgout_index += spi_populate_sync_msg( 3059 ahc->msgout_buf + ahc->msgout_index, period, offset); 3060 ahc->msgout_len += 5; 3061 if (bootverbose) { 3062 printk("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n", 3063 ahc_name(ahc), devinfo->channel, devinfo->target, 3064 devinfo->lun, period, offset); 3065 } 3066 } 3067 3068 /* 3069 * Build a wide negotiation message in our message 3070 * buffer based on the input parameters. 3071 */ 3072 static void 3073 ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3074 u_int bus_width) 3075 { 3076 ahc->msgout_index += spi_populate_width_msg( 3077 ahc->msgout_buf + ahc->msgout_index, bus_width); 3078 ahc->msgout_len += 4; 3079 if (bootverbose) { 3080 printk("(%s:%c:%d:%d): Sending WDTR %x\n", 3081 ahc_name(ahc), devinfo->channel, devinfo->target, 3082 devinfo->lun, bus_width); 3083 } 3084 } 3085 3086 /* 3087 * Build a parallel protocol request message in our message 3088 * buffer based on the input parameters. 3089 */ 3090 static void 3091 ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3092 u_int period, u_int offset, u_int bus_width, 3093 u_int ppr_options) 3094 { 3095 if (offset == 0) 3096 period = AHC_ASYNC_XFER_PERIOD; 3097 ahc->msgout_index += spi_populate_ppr_msg( 3098 ahc->msgout_buf + ahc->msgout_index, period, offset, 3099 bus_width, ppr_options); 3100 ahc->msgout_len += 8; 3101 if (bootverbose) { 3102 printk("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, " 3103 "offset %x, ppr_options %x\n", ahc_name(ahc), 3104 devinfo->channel, devinfo->target, devinfo->lun, 3105 bus_width, period, offset, ppr_options); 3106 } 3107 } 3108 3109 /* 3110 * Clear any active message state. 3111 */ 3112 static void 3113 ahc_clear_msg_state(struct ahc_softc *ahc) 3114 { 3115 ahc->msgout_len = 0; 3116 ahc->msgin_index = 0; 3117 ahc->msg_type = MSG_TYPE_NONE; 3118 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) { 3119 /* 3120 * The target didn't care to respond to our 3121 * message request, so clear ATN. 3122 */ 3123 ahc_outb(ahc, CLRSINT1, CLRATNO); 3124 } 3125 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 3126 ahc_outb(ahc, SEQ_FLAGS2, 3127 ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING); 3128 } 3129 3130 static void 3131 ahc_handle_proto_violation(struct ahc_softc *ahc) 3132 { 3133 struct ahc_devinfo devinfo; 3134 struct scb *scb; 3135 u_int scbid; 3136 u_int seq_flags; 3137 u_int curphase; 3138 u_int lastphase; 3139 int found; 3140 3141 ahc_fetch_devinfo(ahc, &devinfo); 3142 scbid = ahc_inb(ahc, SCB_TAG); 3143 scb = ahc_lookup_scb(ahc, scbid); 3144 seq_flags = ahc_inb(ahc, SEQ_FLAGS); 3145 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 3146 lastphase = ahc_inb(ahc, LASTPHASE); 3147 if ((seq_flags & NOT_IDENTIFIED) != 0) { 3148 3149 /* 3150 * The reconnecting target either did not send an 3151 * identify message, or did, but we didn't find an SCB 3152 * to match. 3153 */ 3154 ahc_print_devinfo(ahc, &devinfo); 3155 printk("Target did not send an IDENTIFY message. " 3156 "LASTPHASE = 0x%x.\n", lastphase); 3157 scb = NULL; 3158 } else if (scb == NULL) { 3159 /* 3160 * We don't seem to have an SCB active for this 3161 * transaction. Print an error and reset the bus. 3162 */ 3163 ahc_print_devinfo(ahc, &devinfo); 3164 printk("No SCB found during protocol violation\n"); 3165 goto proto_violation_reset; 3166 } else { 3167 ahc_set_transaction_status(scb, CAM_SEQUENCE_FAIL); 3168 if ((seq_flags & NO_CDB_SENT) != 0) { 3169 ahc_print_path(ahc, scb); 3170 printk("No or incomplete CDB sent to device.\n"); 3171 } else if ((ahc_inb(ahc, SCB_CONTROL) & STATUS_RCVD) == 0) { 3172 /* 3173 * The target never bothered to provide status to 3174 * us prior to completing the command. Since we don't 3175 * know the disposition of this command, we must attempt 3176 * to abort it. Assert ATN and prepare to send an abort 3177 * message. 3178 */ 3179 ahc_print_path(ahc, scb); 3180 printk("Completed command without status.\n"); 3181 } else { 3182 ahc_print_path(ahc, scb); 3183 printk("Unknown protocol violation.\n"); 3184 ahc_dump_card_state(ahc); 3185 } 3186 } 3187 if ((lastphase & ~P_DATAIN_DT) == 0 3188 || lastphase == P_COMMAND) { 3189 proto_violation_reset: 3190 /* 3191 * Target either went directly to data/command 3192 * phase or didn't respond to our ATN. 3193 * The only safe thing to do is to blow 3194 * it away with a bus reset. 3195 */ 3196 found = ahc_reset_channel(ahc, 'A', TRUE); 3197 printk("%s: Issued Channel %c Bus Reset. " 3198 "%d SCBs aborted\n", ahc_name(ahc), 'A', found); 3199 } else { 3200 /* 3201 * Leave the selection hardware off in case 3202 * this abort attempt will affect yet to 3203 * be sent commands. 3204 */ 3205 ahc_outb(ahc, SCSISEQ, 3206 ahc_inb(ahc, SCSISEQ) & ~ENSELO); 3207 ahc_assert_atn(ahc); 3208 ahc_outb(ahc, MSG_OUT, HOST_MSG); 3209 if (scb == NULL) { 3210 ahc_print_devinfo(ahc, &devinfo); 3211 ahc->msgout_buf[0] = MSG_ABORT_TASK; 3212 ahc->msgout_len = 1; 3213 ahc->msgout_index = 0; 3214 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3215 } else { 3216 ahc_print_path(ahc, scb); 3217 scb->flags |= SCB_ABORT; 3218 } 3219 printk("Protocol violation %s. Attempting to abort.\n", 3220 ahc_lookup_phase_entry(curphase)->phasemsg); 3221 } 3222 } 3223 3224 /* 3225 * Manual message loop handler. 3226 */ 3227 static void 3228 ahc_handle_message_phase(struct ahc_softc *ahc) 3229 { 3230 struct ahc_devinfo devinfo; 3231 u_int bus_phase; 3232 int end_session; 3233 3234 ahc_fetch_devinfo(ahc, &devinfo); 3235 end_session = FALSE; 3236 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 3237 3238 reswitch: 3239 switch (ahc->msg_type) { 3240 case MSG_TYPE_INITIATOR_MSGOUT: 3241 { 3242 int lastbyte; 3243 int phasemis; 3244 int msgdone; 3245 3246 if (ahc->msgout_len == 0) 3247 panic("HOST_MSG_LOOP interrupt with no active message"); 3248 3249 #ifdef AHC_DEBUG 3250 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 3251 ahc_print_devinfo(ahc, &devinfo); 3252 printk("INITIATOR_MSG_OUT"); 3253 } 3254 #endif 3255 phasemis = bus_phase != P_MESGOUT; 3256 if (phasemis) { 3257 #ifdef AHC_DEBUG 3258 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 3259 printk(" PHASEMIS %s\n", 3260 ahc_lookup_phase_entry(bus_phase) 3261 ->phasemsg); 3262 } 3263 #endif 3264 if (bus_phase == P_MESGIN) { 3265 /* 3266 * Change gears and see if 3267 * this messages is of interest to 3268 * us or should be passed back to 3269 * the sequencer. 3270 */ 3271 ahc_outb(ahc, CLRSINT1, CLRATNO); 3272 ahc->send_msg_perror = FALSE; 3273 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN; 3274 ahc->msgin_index = 0; 3275 goto reswitch; 3276 } 3277 end_session = TRUE; 3278 break; 3279 } 3280 3281 if (ahc->send_msg_perror) { 3282 ahc_outb(ahc, CLRSINT1, CLRATNO); 3283 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 3284 #ifdef AHC_DEBUG 3285 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 3286 printk(" byte 0x%x\n", ahc->send_msg_perror); 3287 #endif 3288 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR); 3289 break; 3290 } 3291 3292 msgdone = ahc->msgout_index == ahc->msgout_len; 3293 if (msgdone) { 3294 /* 3295 * The target has requested a retry. 3296 * Re-assert ATN, reset our message index to 3297 * 0, and try again. 3298 */ 3299 ahc->msgout_index = 0; 3300 ahc_assert_atn(ahc); 3301 } 3302 3303 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1); 3304 if (lastbyte) { 3305 /* Last byte is signified by dropping ATN */ 3306 ahc_outb(ahc, CLRSINT1, CLRATNO); 3307 } 3308 3309 /* 3310 * Clear our interrupt status and present 3311 * the next byte on the bus. 3312 */ 3313 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 3314 #ifdef AHC_DEBUG 3315 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 3316 printk(" byte 0x%x\n", 3317 ahc->msgout_buf[ahc->msgout_index]); 3318 #endif 3319 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 3320 break; 3321 } 3322 case MSG_TYPE_INITIATOR_MSGIN: 3323 { 3324 int phasemis; 3325 int message_done; 3326 3327 #ifdef AHC_DEBUG 3328 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 3329 ahc_print_devinfo(ahc, &devinfo); 3330 printk("INITIATOR_MSG_IN"); 3331 } 3332 #endif 3333 phasemis = bus_phase != P_MESGIN; 3334 if (phasemis) { 3335 #ifdef AHC_DEBUG 3336 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 3337 printk(" PHASEMIS %s\n", 3338 ahc_lookup_phase_entry(bus_phase) 3339 ->phasemsg); 3340 } 3341 #endif 3342 ahc->msgin_index = 0; 3343 if (bus_phase == P_MESGOUT 3344 && (ahc->send_msg_perror == TRUE 3345 || (ahc->msgout_len != 0 3346 && ahc->msgout_index == 0))) { 3347 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 3348 goto reswitch; 3349 } 3350 end_session = TRUE; 3351 break; 3352 } 3353 3354 /* Pull the byte in without acking it */ 3355 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL); 3356 #ifdef AHC_DEBUG 3357 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 3358 printk(" byte 0x%x\n", 3359 ahc->msgin_buf[ahc->msgin_index]); 3360 #endif 3361 3362 message_done = ahc_parse_msg(ahc, &devinfo); 3363 3364 if (message_done) { 3365 /* 3366 * Clear our incoming message buffer in case there 3367 * is another message following this one. 3368 */ 3369 ahc->msgin_index = 0; 3370 3371 /* 3372 * If this message illicited a response, 3373 * assert ATN so the target takes us to the 3374 * message out phase. 3375 */ 3376 if (ahc->msgout_len != 0) { 3377 #ifdef AHC_DEBUG 3378 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 3379 ahc_print_devinfo(ahc, &devinfo); 3380 printk("Asserting ATN for response\n"); 3381 } 3382 #endif 3383 ahc_assert_atn(ahc); 3384 } 3385 } else 3386 ahc->msgin_index++; 3387 3388 if (message_done == MSGLOOP_TERMINATED) { 3389 end_session = TRUE; 3390 } else { 3391 /* Ack the byte */ 3392 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 3393 ahc_inb(ahc, SCSIDATL); 3394 } 3395 break; 3396 } 3397 case MSG_TYPE_TARGET_MSGIN: 3398 { 3399 int msgdone; 3400 int msgout_request; 3401 3402 if (ahc->msgout_len == 0) 3403 panic("Target MSGIN with no active message"); 3404 3405 /* 3406 * If we interrupted a mesgout session, the initiator 3407 * will not know this until our first REQ. So, we 3408 * only honor mesgout requests after we've sent our 3409 * first byte. 3410 */ 3411 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0 3412 && ahc->msgout_index > 0) 3413 msgout_request = TRUE; 3414 else 3415 msgout_request = FALSE; 3416 3417 if (msgout_request) { 3418 3419 /* 3420 * Change gears and see if 3421 * this messages is of interest to 3422 * us or should be passed back to 3423 * the sequencer. 3424 */ 3425 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT; 3426 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO); 3427 ahc->msgin_index = 0; 3428 /* Dummy read to REQ for first byte */ 3429 ahc_inb(ahc, SCSIDATL); 3430 ahc_outb(ahc, SXFRCTL0, 3431 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 3432 break; 3433 } 3434 3435 msgdone = ahc->msgout_index == ahc->msgout_len; 3436 if (msgdone) { 3437 ahc_outb(ahc, SXFRCTL0, 3438 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 3439 end_session = TRUE; 3440 break; 3441 } 3442 3443 /* 3444 * Present the next byte on the bus. 3445 */ 3446 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN); 3447 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 3448 break; 3449 } 3450 case MSG_TYPE_TARGET_MSGOUT: 3451 { 3452 int lastbyte; 3453 int msgdone; 3454 3455 /* 3456 * The initiator signals that this is 3457 * the last byte by dropping ATN. 3458 */ 3459 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0; 3460 3461 /* 3462 * Read the latched byte, but turn off SPIOEN first 3463 * so that we don't inadvertently cause a REQ for the 3464 * next byte. 3465 */ 3466 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 3467 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL); 3468 msgdone = ahc_parse_msg(ahc, &devinfo); 3469 if (msgdone == MSGLOOP_TERMINATED) { 3470 /* 3471 * The message is *really* done in that it caused 3472 * us to go to bus free. The sequencer has already 3473 * been reset at this point, so pull the ejection 3474 * handle. 3475 */ 3476 return; 3477 } 3478 3479 ahc->msgin_index++; 3480 3481 /* 3482 * XXX Read spec about initiator dropping ATN too soon 3483 * and use msgdone to detect it. 3484 */ 3485 if (msgdone == MSGLOOP_MSGCOMPLETE) { 3486 ahc->msgin_index = 0; 3487 3488 /* 3489 * If this message illicited a response, transition 3490 * to the Message in phase and send it. 3491 */ 3492 if (ahc->msgout_len != 0) { 3493 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO); 3494 ahc_outb(ahc, SXFRCTL0, 3495 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 3496 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 3497 ahc->msgin_index = 0; 3498 break; 3499 } 3500 } 3501 3502 if (lastbyte) 3503 end_session = TRUE; 3504 else { 3505 /* Ask for the next byte. */ 3506 ahc_outb(ahc, SXFRCTL0, 3507 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 3508 } 3509 3510 break; 3511 } 3512 default: 3513 panic("Unknown REQINIT message type"); 3514 } 3515 3516 if (end_session) { 3517 ahc_clear_msg_state(ahc); 3518 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP); 3519 } else 3520 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 3521 } 3522 3523 /* 3524 * See if we sent a particular extended message to the target. 3525 * If "full" is true, return true only if the target saw the full 3526 * message. If "full" is false, return true if the target saw at 3527 * least the first byte of the message. 3528 */ 3529 static int 3530 ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full) 3531 { 3532 int found; 3533 u_int index; 3534 3535 found = FALSE; 3536 index = 0; 3537 3538 while (index < ahc->msgout_len) { 3539 if (ahc->msgout_buf[index] == MSG_EXTENDED) { 3540 u_int end_index; 3541 3542 end_index = index + 1 + ahc->msgout_buf[index + 1]; 3543 if (ahc->msgout_buf[index+2] == msgval 3544 && type == AHCMSG_EXT) { 3545 3546 if (full) { 3547 if (ahc->msgout_index > end_index) 3548 found = TRUE; 3549 } else if (ahc->msgout_index > index) 3550 found = TRUE; 3551 } 3552 index = end_index; 3553 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK 3554 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 3555 3556 /* Skip tag type and tag id or residue param*/ 3557 index += 2; 3558 } else { 3559 /* Single byte message */ 3560 if (type == AHCMSG_1B 3561 && ahc->msgout_buf[index] == msgval 3562 && ahc->msgout_index > index) 3563 found = TRUE; 3564 index++; 3565 } 3566 3567 if (found) 3568 break; 3569 } 3570 return (found); 3571 } 3572 3573 /* 3574 * Wait for a complete incoming message, parse it, and respond accordingly. 3575 */ 3576 static int 3577 ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3578 { 3579 struct ahc_initiator_tinfo *tinfo; 3580 struct ahc_tmode_tstate *tstate; 3581 int reject; 3582 int done; 3583 int response; 3584 u_int targ_scsirate; 3585 3586 done = MSGLOOP_IN_PROG; 3587 response = FALSE; 3588 reject = FALSE; 3589 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 3590 devinfo->target, &tstate); 3591 targ_scsirate = tinfo->scsirate; 3592 3593 /* 3594 * Parse as much of the message as is available, 3595 * rejecting it if we don't support it. When 3596 * the entire message is available and has been 3597 * handled, return MSGLOOP_MSGCOMPLETE, indicating 3598 * that we have parsed an entire message. 3599 * 3600 * In the case of extended messages, we accept the length 3601 * byte outright and perform more checking once we know the 3602 * extended message type. 3603 */ 3604 switch (ahc->msgin_buf[0]) { 3605 case MSG_DISCONNECT: 3606 case MSG_SAVEDATAPOINTER: 3607 case MSG_CMDCOMPLETE: 3608 case MSG_RESTOREPOINTERS: 3609 case MSG_IGN_WIDE_RESIDUE: 3610 /* 3611 * End our message loop as these are messages 3612 * the sequencer handles on its own. 3613 */ 3614 done = MSGLOOP_TERMINATED; 3615 break; 3616 case MSG_MESSAGE_REJECT: 3617 response = ahc_handle_msg_reject(ahc, devinfo); 3618 /* FALLTHROUGH */ 3619 case MSG_NOOP: 3620 done = MSGLOOP_MSGCOMPLETE; 3621 break; 3622 case MSG_EXTENDED: 3623 { 3624 /* Wait for enough of the message to begin validation */ 3625 if (ahc->msgin_index < 2) 3626 break; 3627 switch (ahc->msgin_buf[2]) { 3628 case MSG_EXT_SDTR: 3629 { 3630 const struct ahc_syncrate *syncrate; 3631 u_int period; 3632 u_int ppr_options; 3633 u_int offset; 3634 u_int saved_offset; 3635 3636 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 3637 reject = TRUE; 3638 break; 3639 } 3640 3641 /* 3642 * Wait until we have both args before validating 3643 * and acting on this message. 3644 * 3645 * Add one to MSG_EXT_SDTR_LEN to account for 3646 * the extended message preamble. 3647 */ 3648 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 3649 break; 3650 3651 period = ahc->msgin_buf[3]; 3652 ppr_options = 0; 3653 saved_offset = offset = ahc->msgin_buf[4]; 3654 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period, 3655 &ppr_options, 3656 devinfo->role); 3657 ahc_validate_offset(ahc, tinfo, syncrate, &offset, 3658 targ_scsirate & WIDEXFER, 3659 devinfo->role); 3660 if (bootverbose) { 3661 printk("(%s:%c:%d:%d): Received " 3662 "SDTR period %x, offset %x\n\t" 3663 "Filtered to period %x, offset %x\n", 3664 ahc_name(ahc), devinfo->channel, 3665 devinfo->target, devinfo->lun, 3666 ahc->msgin_buf[3], saved_offset, 3667 period, offset); 3668 } 3669 ahc_set_syncrate(ahc, devinfo, 3670 syncrate, period, 3671 offset, ppr_options, 3672 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3673 /*paused*/TRUE); 3674 3675 /* 3676 * See if we initiated Sync Negotiation 3677 * and didn't have to fall down to async 3678 * transfers. 3679 */ 3680 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) { 3681 /* We started it */ 3682 if (saved_offset != offset) { 3683 /* Went too low - force async */ 3684 reject = TRUE; 3685 } 3686 } else { 3687 /* 3688 * Send our own SDTR in reply 3689 */ 3690 if (bootverbose 3691 && devinfo->role == ROLE_INITIATOR) { 3692 printk("(%s:%c:%d:%d): Target " 3693 "Initiated SDTR\n", 3694 ahc_name(ahc), devinfo->channel, 3695 devinfo->target, devinfo->lun); 3696 } 3697 ahc->msgout_index = 0; 3698 ahc->msgout_len = 0; 3699 ahc_construct_sdtr(ahc, devinfo, 3700 period, offset); 3701 ahc->msgout_index = 0; 3702 response = TRUE; 3703 } 3704 done = MSGLOOP_MSGCOMPLETE; 3705 break; 3706 } 3707 case MSG_EXT_WDTR: 3708 { 3709 u_int bus_width; 3710 u_int saved_width; 3711 u_int sending_reply; 3712 3713 sending_reply = FALSE; 3714 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 3715 reject = TRUE; 3716 break; 3717 } 3718 3719 /* 3720 * Wait until we have our arg before validating 3721 * and acting on this message. 3722 * 3723 * Add one to MSG_EXT_WDTR_LEN to account for 3724 * the extended message preamble. 3725 */ 3726 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 3727 break; 3728 3729 bus_width = ahc->msgin_buf[3]; 3730 saved_width = bus_width; 3731 ahc_validate_width(ahc, tinfo, &bus_width, 3732 devinfo->role); 3733 if (bootverbose) { 3734 printk("(%s:%c:%d:%d): Received WDTR " 3735 "%x filtered to %x\n", 3736 ahc_name(ahc), devinfo->channel, 3737 devinfo->target, devinfo->lun, 3738 saved_width, bus_width); 3739 } 3740 3741 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) { 3742 /* 3743 * Don't send a WDTR back to the 3744 * target, since we asked first. 3745 * If the width went higher than our 3746 * request, reject it. 3747 */ 3748 if (saved_width > bus_width) { 3749 reject = TRUE; 3750 printk("(%s:%c:%d:%d): requested %dBit " 3751 "transfers. Rejecting...\n", 3752 ahc_name(ahc), devinfo->channel, 3753 devinfo->target, devinfo->lun, 3754 8 * (0x01 << bus_width)); 3755 bus_width = 0; 3756 } 3757 } else { 3758 /* 3759 * Send our own WDTR in reply 3760 */ 3761 if (bootverbose 3762 && devinfo->role == ROLE_INITIATOR) { 3763 printk("(%s:%c:%d:%d): Target " 3764 "Initiated WDTR\n", 3765 ahc_name(ahc), devinfo->channel, 3766 devinfo->target, devinfo->lun); 3767 } 3768 ahc->msgout_index = 0; 3769 ahc->msgout_len = 0; 3770 ahc_construct_wdtr(ahc, devinfo, bus_width); 3771 ahc->msgout_index = 0; 3772 response = TRUE; 3773 sending_reply = TRUE; 3774 } 3775 /* 3776 * After a wide message, we are async, but 3777 * some devices don't seem to honor this portion 3778 * of the spec. Force a renegotiation of the 3779 * sync component of our transfer agreement even 3780 * if our goal is async. By updating our width 3781 * after forcing the negotiation, we avoid 3782 * renegotiating for width. 3783 */ 3784 ahc_update_neg_request(ahc, devinfo, tstate, 3785 tinfo, AHC_NEG_ALWAYS); 3786 ahc_set_width(ahc, devinfo, bus_width, 3787 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3788 /*paused*/TRUE); 3789 if (sending_reply == FALSE && reject == FALSE) { 3790 3791 /* 3792 * We will always have an SDTR to send. 3793 */ 3794 ahc->msgout_index = 0; 3795 ahc->msgout_len = 0; 3796 ahc_build_transfer_msg(ahc, devinfo); 3797 ahc->msgout_index = 0; 3798 response = TRUE; 3799 } 3800 done = MSGLOOP_MSGCOMPLETE; 3801 break; 3802 } 3803 case MSG_EXT_PPR: 3804 { 3805 const struct ahc_syncrate *syncrate; 3806 u_int period; 3807 u_int offset; 3808 u_int bus_width; 3809 u_int ppr_options; 3810 u_int saved_width; 3811 u_int saved_offset; 3812 u_int saved_ppr_options; 3813 3814 if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) { 3815 reject = TRUE; 3816 break; 3817 } 3818 3819 /* 3820 * Wait until we have all args before validating 3821 * and acting on this message. 3822 * 3823 * Add one to MSG_EXT_PPR_LEN to account for 3824 * the extended message preamble. 3825 */ 3826 if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1)) 3827 break; 3828 3829 period = ahc->msgin_buf[3]; 3830 offset = ahc->msgin_buf[5]; 3831 bus_width = ahc->msgin_buf[6]; 3832 saved_width = bus_width; 3833 ppr_options = ahc->msgin_buf[7]; 3834 /* 3835 * According to the spec, a DT only 3836 * period factor with no DT option 3837 * set implies async. 3838 */ 3839 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0 3840 && period == 9) 3841 offset = 0; 3842 saved_ppr_options = ppr_options; 3843 saved_offset = offset; 3844 3845 /* 3846 * Mask out any options we don't support 3847 * on any controller. Transfer options are 3848 * only available if we are negotiating wide. 3849 */ 3850 ppr_options &= MSG_EXT_PPR_DT_REQ; 3851 if (bus_width == 0) 3852 ppr_options = 0; 3853 3854 ahc_validate_width(ahc, tinfo, &bus_width, 3855 devinfo->role); 3856 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period, 3857 &ppr_options, 3858 devinfo->role); 3859 ahc_validate_offset(ahc, tinfo, syncrate, 3860 &offset, bus_width, 3861 devinfo->role); 3862 3863 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) { 3864 /* 3865 * If we are unable to do any of the 3866 * requested options (we went too low), 3867 * then we'll have to reject the message. 3868 */ 3869 if (saved_width > bus_width 3870 || saved_offset != offset 3871 || saved_ppr_options != ppr_options) { 3872 reject = TRUE; 3873 period = 0; 3874 offset = 0; 3875 bus_width = 0; 3876 ppr_options = 0; 3877 syncrate = NULL; 3878 } 3879 } else { 3880 if (devinfo->role != ROLE_TARGET) 3881 printk("(%s:%c:%d:%d): Target " 3882 "Initiated PPR\n", 3883 ahc_name(ahc), devinfo->channel, 3884 devinfo->target, devinfo->lun); 3885 else 3886 printk("(%s:%c:%d:%d): Initiator " 3887 "Initiated PPR\n", 3888 ahc_name(ahc), devinfo->channel, 3889 devinfo->target, devinfo->lun); 3890 ahc->msgout_index = 0; 3891 ahc->msgout_len = 0; 3892 ahc_construct_ppr(ahc, devinfo, period, offset, 3893 bus_width, ppr_options); 3894 ahc->msgout_index = 0; 3895 response = TRUE; 3896 } 3897 if (bootverbose) { 3898 printk("(%s:%c:%d:%d): Received PPR width %x, " 3899 "period %x, offset %x,options %x\n" 3900 "\tFiltered to width %x, period %x, " 3901 "offset %x, options %x\n", 3902 ahc_name(ahc), devinfo->channel, 3903 devinfo->target, devinfo->lun, 3904 saved_width, ahc->msgin_buf[3], 3905 saved_offset, saved_ppr_options, 3906 bus_width, period, offset, ppr_options); 3907 } 3908 ahc_set_width(ahc, devinfo, bus_width, 3909 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3910 /*paused*/TRUE); 3911 ahc_set_syncrate(ahc, devinfo, 3912 syncrate, period, 3913 offset, ppr_options, 3914 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3915 /*paused*/TRUE); 3916 done = MSGLOOP_MSGCOMPLETE; 3917 break; 3918 } 3919 default: 3920 /* Unknown extended message. Reject it. */ 3921 reject = TRUE; 3922 break; 3923 } 3924 break; 3925 } 3926 #ifdef AHC_TARGET_MODE 3927 case MSG_BUS_DEV_RESET: 3928 ahc_handle_devreset(ahc, devinfo, 3929 CAM_BDR_SENT, 3930 "Bus Device Reset Received", 3931 /*verbose_level*/0); 3932 ahc_restart(ahc); 3933 done = MSGLOOP_TERMINATED; 3934 break; 3935 case MSG_ABORT_TAG: 3936 case MSG_ABORT: 3937 case MSG_CLEAR_QUEUE: 3938 { 3939 int tag; 3940 3941 /* Target mode messages */ 3942 if (devinfo->role != ROLE_TARGET) { 3943 reject = TRUE; 3944 break; 3945 } 3946 tag = SCB_LIST_NULL; 3947 if (ahc->msgin_buf[0] == MSG_ABORT_TAG) 3948 tag = ahc_inb(ahc, INITIATOR_TAG); 3949 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3950 devinfo->lun, tag, ROLE_TARGET, 3951 CAM_REQ_ABORTED); 3952 3953 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3954 if (tstate != NULL) { 3955 struct ahc_tmode_lstate* lstate; 3956 3957 lstate = tstate->enabled_luns[devinfo->lun]; 3958 if (lstate != NULL) { 3959 ahc_queue_lstate_event(ahc, lstate, 3960 devinfo->our_scsiid, 3961 ahc->msgin_buf[0], 3962 /*arg*/tag); 3963 ahc_send_lstate_events(ahc, lstate); 3964 } 3965 } 3966 ahc_restart(ahc); 3967 done = MSGLOOP_TERMINATED; 3968 break; 3969 } 3970 #endif 3971 case MSG_TERM_IO_PROC: 3972 default: 3973 reject = TRUE; 3974 break; 3975 } 3976 3977 if (reject) { 3978 /* 3979 * Setup to reject the message. 3980 */ 3981 ahc->msgout_index = 0; 3982 ahc->msgout_len = 1; 3983 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT; 3984 done = MSGLOOP_MSGCOMPLETE; 3985 response = TRUE; 3986 } 3987 3988 if (done != MSGLOOP_IN_PROG && !response) 3989 /* Clear the outgoing message buffer */ 3990 ahc->msgout_len = 0; 3991 3992 return (done); 3993 } 3994 3995 /* 3996 * Process a message reject message. 3997 */ 3998 static int 3999 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 4000 { 4001 /* 4002 * What we care about here is if we had an 4003 * outstanding SDTR or WDTR message for this 4004 * target. If we did, this is a signal that 4005 * the target is refusing negotiation. 4006 */ 4007 struct scb *scb; 4008 struct ahc_initiator_tinfo *tinfo; 4009 struct ahc_tmode_tstate *tstate; 4010 u_int scb_index; 4011 u_int last_msg; 4012 int response = 0; 4013 4014 scb_index = ahc_inb(ahc, SCB_TAG); 4015 scb = ahc_lookup_scb(ahc, scb_index); 4016 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, 4017 devinfo->our_scsiid, 4018 devinfo->target, &tstate); 4019 /* Might be necessary */ 4020 last_msg = ahc_inb(ahc, LAST_MSG); 4021 4022 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) { 4023 /* 4024 * Target does not support the PPR message. 4025 * Attempt to negotiate SPI-2 style. 4026 */ 4027 if (bootverbose) { 4028 printk("(%s:%c:%d:%d): PPR Rejected. " 4029 "Trying WDTR/SDTR\n", 4030 ahc_name(ahc), devinfo->channel, 4031 devinfo->target, devinfo->lun); 4032 } 4033 tinfo->goal.ppr_options = 0; 4034 tinfo->curr.transport_version = 2; 4035 tinfo->goal.transport_version = 2; 4036 ahc->msgout_index = 0; 4037 ahc->msgout_len = 0; 4038 ahc_build_transfer_msg(ahc, devinfo); 4039 ahc->msgout_index = 0; 4040 response = 1; 4041 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) { 4042 4043 /* note 8bit xfers */ 4044 printk("(%s:%c:%d:%d): refuses WIDE negotiation. Using " 4045 "8bit transfers\n", ahc_name(ahc), 4046 devinfo->channel, devinfo->target, devinfo->lun); 4047 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 4048 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 4049 /*paused*/TRUE); 4050 /* 4051 * No need to clear the sync rate. If the target 4052 * did not accept the command, our syncrate is 4053 * unaffected. If the target started the negotiation, 4054 * but rejected our response, we already cleared the 4055 * sync rate before sending our WDTR. 4056 */ 4057 if (tinfo->goal.offset != tinfo->curr.offset) { 4058 4059 /* Start the sync negotiation */ 4060 ahc->msgout_index = 0; 4061 ahc->msgout_len = 0; 4062 ahc_build_transfer_msg(ahc, devinfo); 4063 ahc->msgout_index = 0; 4064 response = 1; 4065 } 4066 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) { 4067 /* note asynch xfers and clear flag */ 4068 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, 4069 /*offset*/0, /*ppr_options*/0, 4070 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 4071 /*paused*/TRUE); 4072 printk("(%s:%c:%d:%d): refuses synchronous negotiation. " 4073 "Using asynchronous transfers\n", 4074 ahc_name(ahc), devinfo->channel, 4075 devinfo->target, devinfo->lun); 4076 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) { 4077 int tag_type; 4078 int mask; 4079 4080 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK); 4081 4082 if (tag_type == MSG_SIMPLE_TASK) { 4083 printk("(%s:%c:%d:%d): refuses tagged commands. " 4084 "Performing non-tagged I/O\n", ahc_name(ahc), 4085 devinfo->channel, devinfo->target, devinfo->lun); 4086 ahc_set_tags(ahc, scb->io_ctx, devinfo, AHC_QUEUE_NONE); 4087 mask = ~0x23; 4088 } else { 4089 printk("(%s:%c:%d:%d): refuses %s tagged commands. " 4090 "Performing simple queue tagged I/O only\n", 4091 ahc_name(ahc), devinfo->channel, devinfo->target, 4092 devinfo->lun, tag_type == MSG_ORDERED_TASK 4093 ? "ordered" : "head of queue"); 4094 ahc_set_tags(ahc, scb->io_ctx, devinfo, AHC_QUEUE_BASIC); 4095 mask = ~0x03; 4096 } 4097 4098 /* 4099 * Resend the identify for this CCB as the target 4100 * may believe that the selection is invalid otherwise. 4101 */ 4102 ahc_outb(ahc, SCB_CONTROL, 4103 ahc_inb(ahc, SCB_CONTROL) & mask); 4104 scb->hscb->control &= mask; 4105 ahc_set_transaction_tag(scb, /*enabled*/FALSE, 4106 /*type*/MSG_SIMPLE_TASK); 4107 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); 4108 ahc_assert_atn(ahc); 4109 4110 /* 4111 * This transaction is now at the head of 4112 * the untagged queue for this target. 4113 */ 4114 if ((ahc->flags & AHC_SCB_BTT) == 0) { 4115 struct scb_tailq *untagged_q; 4116 4117 untagged_q = 4118 &(ahc->untagged_queues[devinfo->target_offset]); 4119 TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe); 4120 scb->flags |= SCB_UNTAGGEDQ; 4121 } 4122 ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun), 4123 scb->hscb->tag); 4124 4125 /* 4126 * Requeue all tagged commands for this target 4127 * currently in our possession so they can be 4128 * converted to untagged commands. 4129 */ 4130 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), 4131 SCB_GET_CHANNEL(ahc, scb), 4132 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL, 4133 ROLE_INITIATOR, CAM_REQUEUE_REQ, 4134 SEARCH_COMPLETE); 4135 } else { 4136 /* 4137 * Otherwise, we ignore it. 4138 */ 4139 printk("%s:%c:%d: Message reject for %x -- ignored\n", 4140 ahc_name(ahc), devinfo->channel, devinfo->target, 4141 last_msg); 4142 } 4143 return (response); 4144 } 4145 4146 /* 4147 * Process an ingnore wide residue message. 4148 */ 4149 static void 4150 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 4151 { 4152 u_int scb_index; 4153 struct scb *scb; 4154 4155 scb_index = ahc_inb(ahc, SCB_TAG); 4156 scb = ahc_lookup_scb(ahc, scb_index); 4157 /* 4158 * XXX Actually check data direction in the sequencer? 4159 * Perhaps add datadir to some spare bits in the hscb? 4160 */ 4161 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0 4162 || ahc_get_transfer_dir(scb) != CAM_DIR_IN) { 4163 /* 4164 * Ignore the message if we haven't 4165 * seen an appropriate data phase yet. 4166 */ 4167 } else { 4168 /* 4169 * If the residual occurred on the last 4170 * transfer and the transfer request was 4171 * expected to end on an odd count, do 4172 * nothing. Otherwise, subtract a byte 4173 * and update the residual count accordingly. 4174 */ 4175 uint32_t sgptr; 4176 4177 sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR); 4178 if ((sgptr & SG_LIST_NULL) != 0 4179 && (ahc_inb(ahc, SCB_LUN) & SCB_XFERLEN_ODD) != 0) { 4180 /* 4181 * If the residual occurred on the last 4182 * transfer and the transfer request was 4183 * expected to end on an odd count, do 4184 * nothing. 4185 */ 4186 } else { 4187 struct ahc_dma_seg *sg; 4188 uint32_t data_cnt; 4189 uint32_t data_addr; 4190 uint32_t sglen; 4191 4192 /* Pull in all of the sgptr */ 4193 sgptr = ahc_inl(ahc, SCB_RESIDUAL_SGPTR); 4194 data_cnt = ahc_inl(ahc, SCB_RESIDUAL_DATACNT); 4195 4196 if ((sgptr & SG_LIST_NULL) != 0) { 4197 /* 4198 * The residual data count is not updated 4199 * for the command run to completion case. 4200 * Explicitly zero the count. 4201 */ 4202 data_cnt &= ~AHC_SG_LEN_MASK; 4203 } 4204 4205 data_addr = ahc_inl(ahc, SHADDR); 4206 4207 data_cnt += 1; 4208 data_addr -= 1; 4209 sgptr &= SG_PTR_MASK; 4210 4211 sg = ahc_sg_bus_to_virt(scb, sgptr); 4212 4213 /* 4214 * The residual sg ptr points to the next S/G 4215 * to load so we must go back one. 4216 */ 4217 sg--; 4218 sglen = ahc_le32toh(sg->len) & AHC_SG_LEN_MASK; 4219 if (sg != scb->sg_list 4220 && sglen < (data_cnt & AHC_SG_LEN_MASK)) { 4221 4222 sg--; 4223 sglen = ahc_le32toh(sg->len); 4224 /* 4225 * Preserve High Address and SG_LIST bits 4226 * while setting the count to 1. 4227 */ 4228 data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK)); 4229 data_addr = ahc_le32toh(sg->addr) 4230 + (sglen & AHC_SG_LEN_MASK) - 1; 4231 4232 /* 4233 * Increment sg so it points to the 4234 * "next" sg. 4235 */ 4236 sg++; 4237 sgptr = ahc_sg_virt_to_bus(scb, sg); 4238 } 4239 ahc_outl(ahc, SCB_RESIDUAL_SGPTR, sgptr); 4240 ahc_outl(ahc, SCB_RESIDUAL_DATACNT, data_cnt); 4241 /* 4242 * Toggle the "oddness" of the transfer length 4243 * to handle this mid-transfer ignore wide 4244 * residue. This ensures that the oddness is 4245 * correct for subsequent data transfers. 4246 */ 4247 ahc_outb(ahc, SCB_LUN, 4248 ahc_inb(ahc, SCB_LUN) ^ SCB_XFERLEN_ODD); 4249 } 4250 } 4251 } 4252 4253 4254 /* 4255 * Reinitialize the data pointers for the active transfer 4256 * based on its current residual. 4257 */ 4258 static void 4259 ahc_reinitialize_dataptrs(struct ahc_softc *ahc) 4260 { 4261 struct scb *scb; 4262 struct ahc_dma_seg *sg; 4263 u_int scb_index; 4264 uint32_t sgptr; 4265 uint32_t resid; 4266 uint32_t dataptr; 4267 4268 scb_index = ahc_inb(ahc, SCB_TAG); 4269 scb = ahc_lookup_scb(ahc, scb_index); 4270 sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24) 4271 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16) 4272 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8) 4273 | ahc_inb(ahc, SCB_RESIDUAL_SGPTR); 4274 4275 sgptr &= SG_PTR_MASK; 4276 sg = ahc_sg_bus_to_virt(scb, sgptr); 4277 4278 /* The residual sg_ptr always points to the next sg */ 4279 sg--; 4280 4281 resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16) 4282 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8) 4283 | ahc_inb(ahc, SCB_RESIDUAL_DATACNT); 4284 4285 dataptr = ahc_le32toh(sg->addr) 4286 + (ahc_le32toh(sg->len) & AHC_SG_LEN_MASK) 4287 - resid; 4288 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 4289 u_int dscommand1; 4290 4291 dscommand1 = ahc_inb(ahc, DSCOMMAND1); 4292 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0); 4293 ahc_outb(ahc, HADDR, 4294 (ahc_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS); 4295 ahc_outb(ahc, DSCOMMAND1, dscommand1); 4296 } 4297 ahc_outb(ahc, HADDR + 3, dataptr >> 24); 4298 ahc_outb(ahc, HADDR + 2, dataptr >> 16); 4299 ahc_outb(ahc, HADDR + 1, dataptr >> 8); 4300 ahc_outb(ahc, HADDR, dataptr); 4301 ahc_outb(ahc, HCNT + 2, resid >> 16); 4302 ahc_outb(ahc, HCNT + 1, resid >> 8); 4303 ahc_outb(ahc, HCNT, resid); 4304 if ((ahc->features & AHC_ULTRA2) == 0) { 4305 ahc_outb(ahc, STCNT + 2, resid >> 16); 4306 ahc_outb(ahc, STCNT + 1, resid >> 8); 4307 ahc_outb(ahc, STCNT, resid); 4308 } 4309 } 4310 4311 /* 4312 * Handle the effects of issuing a bus device reset message. 4313 */ 4314 static void 4315 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 4316 cam_status status, char *message, int verbose_level) 4317 { 4318 #ifdef AHC_TARGET_MODE 4319 struct ahc_tmode_tstate* tstate; 4320 u_int lun; 4321 #endif 4322 int found; 4323 4324 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 4325 CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role, 4326 status); 4327 4328 #ifdef AHC_TARGET_MODE 4329 /* 4330 * Send an immediate notify ccb to all target mord peripheral 4331 * drivers affected by this action. 4332 */ 4333 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 4334 if (tstate != NULL) { 4335 for (lun = 0; lun < AHC_NUM_LUNS; lun++) { 4336 struct ahc_tmode_lstate* lstate; 4337 4338 lstate = tstate->enabled_luns[lun]; 4339 if (lstate == NULL) 4340 continue; 4341 4342 ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid, 4343 MSG_BUS_DEV_RESET, /*arg*/0); 4344 ahc_send_lstate_events(ahc, lstate); 4345 } 4346 } 4347 #endif 4348 4349 /* 4350 * Go back to async/narrow transfers and renegotiate. 4351 */ 4352 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 4353 AHC_TRANS_CUR, /*paused*/TRUE); 4354 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, 4355 /*period*/0, /*offset*/0, /*ppr_options*/0, 4356 AHC_TRANS_CUR, /*paused*/TRUE); 4357 4358 if (status != CAM_SEL_TIMEOUT) 4359 ahc_send_async(ahc, devinfo->channel, devinfo->target, 4360 CAM_LUN_WILDCARD, AC_SENT_BDR); 4361 4362 if (message != NULL 4363 && (verbose_level <= bootverbose)) 4364 printk("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc), 4365 message, devinfo->channel, devinfo->target, found); 4366 } 4367 4368 #ifdef AHC_TARGET_MODE 4369 static void 4370 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 4371 struct scb *scb) 4372 { 4373 4374 /* 4375 * To facilitate adding multiple messages together, 4376 * each routine should increment the index and len 4377 * variables instead of setting them explicitly. 4378 */ 4379 ahc->msgout_index = 0; 4380 ahc->msgout_len = 0; 4381 4382 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0) 4383 ahc_build_transfer_msg(ahc, devinfo); 4384 else 4385 panic("ahc_intr: AWAITING target message with no message"); 4386 4387 ahc->msgout_index = 0; 4388 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 4389 } 4390 #endif 4391 /**************************** Initialization **********************************/ 4392 /* 4393 * Allocate a controller structure for a new device 4394 * and perform initial initializion. 4395 */ 4396 struct ahc_softc * 4397 ahc_alloc(void *platform_arg, char *name) 4398 { 4399 struct ahc_softc *ahc; 4400 int i; 4401 4402 #ifndef __FreeBSD__ 4403 ahc = kmalloc(sizeof(*ahc), GFP_ATOMIC); 4404 if (!ahc) { 4405 printk("aic7xxx: cannot malloc softc!\n"); 4406 kfree(name); 4407 return NULL; 4408 } 4409 #else 4410 ahc = device_get_softc((device_t)platform_arg); 4411 #endif 4412 memset(ahc, 0, sizeof(*ahc)); 4413 ahc->seep_config = kmalloc(sizeof(*ahc->seep_config), GFP_ATOMIC); 4414 if (ahc->seep_config == NULL) { 4415 #ifndef __FreeBSD__ 4416 kfree(ahc); 4417 #endif 4418 kfree(name); 4419 return (NULL); 4420 } 4421 LIST_INIT(&ahc->pending_scbs); 4422 /* We don't know our unit number until the OSM sets it */ 4423 ahc->name = name; 4424 ahc->unit = -1; 4425 ahc->description = NULL; 4426 ahc->channel = 'A'; 4427 ahc->channel_b = 'B'; 4428 ahc->chip = AHC_NONE; 4429 ahc->features = AHC_FENONE; 4430 ahc->bugs = AHC_BUGNONE; 4431 ahc->flags = AHC_FNONE; 4432 /* 4433 * Default to all error reporting enabled with the 4434 * sequencer operating at its fastest speed. 4435 * The bus attach code may modify this. 4436 */ 4437 ahc->seqctl = FASTMODE; 4438 4439 for (i = 0; i < AHC_NUM_TARGETS; i++) 4440 TAILQ_INIT(&ahc->untagged_queues[i]); 4441 if (ahc_platform_alloc(ahc, platform_arg) != 0) { 4442 ahc_free(ahc); 4443 ahc = NULL; 4444 } 4445 return (ahc); 4446 } 4447 4448 int 4449 ahc_softc_init(struct ahc_softc *ahc) 4450 { 4451 4452 /* The IRQMS bit is only valid on VL and EISA chips */ 4453 if ((ahc->chip & AHC_PCI) == 0) 4454 ahc->unpause = ahc_inb(ahc, HCNTRL) & IRQMS; 4455 else 4456 ahc->unpause = 0; 4457 ahc->pause = ahc->unpause | PAUSE; 4458 /* XXX The shared scb data stuff should be deprecated */ 4459 if (ahc->scb_data == NULL) { 4460 ahc->scb_data = kzalloc(sizeof(*ahc->scb_data), GFP_ATOMIC); 4461 if (ahc->scb_data == NULL) 4462 return (ENOMEM); 4463 } 4464 4465 return (0); 4466 } 4467 4468 void 4469 ahc_set_unit(struct ahc_softc *ahc, int unit) 4470 { 4471 ahc->unit = unit; 4472 } 4473 4474 void 4475 ahc_set_name(struct ahc_softc *ahc, char *name) 4476 { 4477 if (ahc->name != NULL) 4478 kfree(ahc->name); 4479 ahc->name = name; 4480 } 4481 4482 void 4483 ahc_free(struct ahc_softc *ahc) 4484 { 4485 int i; 4486 4487 switch (ahc->init_level) { 4488 default: 4489 case 5: 4490 ahc_shutdown(ahc); 4491 /* FALLTHROUGH */ 4492 case 4: 4493 ahc_dmamap_unload(ahc, ahc->shared_data_dmat, 4494 ahc->shared_data_dmamap); 4495 /* FALLTHROUGH */ 4496 case 3: 4497 ahc_dmamem_free(ahc, ahc->shared_data_dmat, ahc->qoutfifo, 4498 ahc->shared_data_dmamap); 4499 ahc_dmamap_destroy(ahc, ahc->shared_data_dmat, 4500 ahc->shared_data_dmamap); 4501 /* FALLTHROUGH */ 4502 case 2: 4503 ahc_dma_tag_destroy(ahc, ahc->shared_data_dmat); 4504 case 1: 4505 break; 4506 case 0: 4507 break; 4508 } 4509 4510 ahc_platform_free(ahc); 4511 ahc_fini_scbdata(ahc); 4512 for (i = 0; i < AHC_NUM_TARGETS; i++) { 4513 struct ahc_tmode_tstate *tstate; 4514 4515 tstate = ahc->enabled_targets[i]; 4516 if (tstate != NULL) { 4517 #ifdef AHC_TARGET_MODE 4518 int j; 4519 4520 for (j = 0; j < AHC_NUM_LUNS; j++) { 4521 struct ahc_tmode_lstate *lstate; 4522 4523 lstate = tstate->enabled_luns[j]; 4524 if (lstate != NULL) { 4525 xpt_free_path(lstate->path); 4526 kfree(lstate); 4527 } 4528 } 4529 #endif 4530 kfree(tstate); 4531 } 4532 } 4533 #ifdef AHC_TARGET_MODE 4534 if (ahc->black_hole != NULL) { 4535 xpt_free_path(ahc->black_hole->path); 4536 kfree(ahc->black_hole); 4537 } 4538 #endif 4539 if (ahc->name != NULL) 4540 kfree(ahc->name); 4541 if (ahc->seep_config != NULL) 4542 kfree(ahc->seep_config); 4543 #ifndef __FreeBSD__ 4544 kfree(ahc); 4545 #endif 4546 return; 4547 } 4548 4549 static void 4550 ahc_shutdown(void *arg) 4551 { 4552 struct ahc_softc *ahc; 4553 int i; 4554 4555 ahc = (struct ahc_softc *)arg; 4556 4557 /* This will reset most registers to 0, but not all */ 4558 ahc_reset(ahc, /*reinit*/FALSE); 4559 ahc_outb(ahc, SCSISEQ, 0); 4560 ahc_outb(ahc, SXFRCTL0, 0); 4561 ahc_outb(ahc, DSPCISTATUS, 0); 4562 4563 for (i = TARG_SCSIRATE; i < SCSICONF; i++) 4564 ahc_outb(ahc, i, 0); 4565 } 4566 4567 /* 4568 * Reset the controller and record some information about it 4569 * that is only available just after a reset. If "reinit" is 4570 * non-zero, this reset occurred after initial configuration 4571 * and the caller requests that the chip be fully reinitialized 4572 * to a runable state. Chip interrupts are *not* enabled after 4573 * a reinitialization. The caller must enable interrupts via 4574 * ahc_intr_enable(). 4575 */ 4576 int 4577 ahc_reset(struct ahc_softc *ahc, int reinit) 4578 { 4579 u_int sblkctl; 4580 u_int sxfrctl1_a, sxfrctl1_b; 4581 int error; 4582 int wait; 4583 4584 /* 4585 * Preserve the value of the SXFRCTL1 register for all channels. 4586 * It contains settings that affect termination and we don't want 4587 * to disturb the integrity of the bus. 4588 */ 4589 ahc_pause(ahc); 4590 sxfrctl1_b = 0; 4591 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) { 4592 u_int sblkctl; 4593 4594 /* 4595 * Save channel B's settings in case this chip 4596 * is setup for TWIN channel operation. 4597 */ 4598 sblkctl = ahc_inb(ahc, SBLKCTL); 4599 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 4600 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1); 4601 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 4602 } 4603 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1); 4604 4605 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); 4606 4607 /* 4608 * Ensure that the reset has finished. We delay 1000us 4609 * prior to reading the register to make sure the chip 4610 * has sufficiently completed its reset to handle register 4611 * accesses. 4612 */ 4613 wait = 1000; 4614 do { 4615 ahc_delay(1000); 4616 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)); 4617 4618 if (wait == 0) { 4619 printk("%s: WARNING - Failed chip reset! " 4620 "Trying to initialize anyway.\n", ahc_name(ahc)); 4621 } 4622 ahc_outb(ahc, HCNTRL, ahc->pause); 4623 4624 /* Determine channel configuration */ 4625 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); 4626 /* No Twin Channel PCI cards */ 4627 if ((ahc->chip & AHC_PCI) != 0) 4628 sblkctl &= ~SELBUSB; 4629 switch (sblkctl) { 4630 case 0: 4631 /* Single Narrow Channel */ 4632 break; 4633 case 2: 4634 /* Wide Channel */ 4635 ahc->features |= AHC_WIDE; 4636 break; 4637 case 8: 4638 /* Twin Channel */ 4639 ahc->features |= AHC_TWIN; 4640 break; 4641 default: 4642 printk(" Unsupported adapter type. Ignoring\n"); 4643 return(-1); 4644 } 4645 4646 /* 4647 * Reload sxfrctl1. 4648 * 4649 * We must always initialize STPWEN to 1 before we 4650 * restore the saved values. STPWEN is initialized 4651 * to a tri-state condition which can only be cleared 4652 * by turning it on. 4653 */ 4654 if ((ahc->features & AHC_TWIN) != 0) { 4655 u_int sblkctl; 4656 4657 sblkctl = ahc_inb(ahc, SBLKCTL); 4658 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 4659 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b); 4660 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 4661 } 4662 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a); 4663 4664 error = 0; 4665 if (reinit != 0) 4666 /* 4667 * If a recovery action has forced a chip reset, 4668 * re-initialize the chip to our liking. 4669 */ 4670 error = ahc->bus_chip_init(ahc); 4671 #ifdef AHC_DUMP_SEQ 4672 else 4673 ahc_dumpseq(ahc); 4674 #endif 4675 4676 return (error); 4677 } 4678 4679 /* 4680 * Determine the number of SCBs available on the controller 4681 */ 4682 int 4683 ahc_probe_scbs(struct ahc_softc *ahc) { 4684 int i; 4685 4686 for (i = 0; i < AHC_SCB_MAX; i++) { 4687 4688 ahc_outb(ahc, SCBPTR, i); 4689 ahc_outb(ahc, SCB_BASE, i); 4690 if (ahc_inb(ahc, SCB_BASE) != i) 4691 break; 4692 ahc_outb(ahc, SCBPTR, 0); 4693 if (ahc_inb(ahc, SCB_BASE) != 0) 4694 break; 4695 } 4696 return (i); 4697 } 4698 4699 static void 4700 ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4701 { 4702 dma_addr_t *baddr; 4703 4704 baddr = (dma_addr_t *)arg; 4705 *baddr = segs->ds_addr; 4706 } 4707 4708 static void 4709 ahc_build_free_scb_list(struct ahc_softc *ahc) 4710 { 4711 int scbsize; 4712 int i; 4713 4714 scbsize = 32; 4715 if ((ahc->flags & AHC_LSCBS_ENABLED) != 0) 4716 scbsize = 64; 4717 4718 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 4719 int j; 4720 4721 ahc_outb(ahc, SCBPTR, i); 4722 4723 /* 4724 * Touch all SCB bytes to avoid parity errors 4725 * should one of our debugging routines read 4726 * an otherwise uninitiatlized byte. 4727 */ 4728 for (j = 0; j < scbsize; j++) 4729 ahc_outb(ahc, SCB_BASE+j, 0xFF); 4730 4731 /* Clear the control byte. */ 4732 ahc_outb(ahc, SCB_CONTROL, 0); 4733 4734 /* Set the next pointer */ 4735 if ((ahc->flags & AHC_PAGESCBS) != 0) 4736 ahc_outb(ahc, SCB_NEXT, i+1); 4737 else 4738 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 4739 4740 /* Make the tag number, SCSIID, and lun invalid */ 4741 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 4742 ahc_outb(ahc, SCB_SCSIID, 0xFF); 4743 ahc_outb(ahc, SCB_LUN, 0xFF); 4744 } 4745 4746 if ((ahc->flags & AHC_PAGESCBS) != 0) { 4747 /* SCB 0 heads the free list. */ 4748 ahc_outb(ahc, FREE_SCBH, 0); 4749 } else { 4750 /* No free list. */ 4751 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL); 4752 } 4753 4754 /* Make sure that the last SCB terminates the free list */ 4755 ahc_outb(ahc, SCBPTR, i-1); 4756 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 4757 } 4758 4759 static int 4760 ahc_init_scbdata(struct ahc_softc *ahc) 4761 { 4762 struct scb_data *scb_data; 4763 4764 scb_data = ahc->scb_data; 4765 SLIST_INIT(&scb_data->free_scbs); 4766 SLIST_INIT(&scb_data->sg_maps); 4767 4768 /* Allocate SCB resources */ 4769 scb_data->scbarray = kcalloc(AHC_SCB_MAX_ALLOC, sizeof(struct scb), 4770 GFP_ATOMIC); 4771 if (scb_data->scbarray == NULL) 4772 return (ENOMEM); 4773 4774 /* Determine the number of hardware SCBs and initialize them */ 4775 4776 scb_data->maxhscbs = ahc_probe_scbs(ahc); 4777 if (ahc->scb_data->maxhscbs == 0) { 4778 printk("%s: No SCB space found\n", ahc_name(ahc)); 4779 return (ENXIO); 4780 } 4781 4782 /* 4783 * Create our DMA tags. These tags define the kinds of device 4784 * accessible memory allocations and memory mappings we will 4785 * need to perform during normal operation. 4786 * 4787 * Unless we need to further restrict the allocation, we rely 4788 * on the restrictions of the parent dmat, hence the common 4789 * use of MAXADDR and MAXSIZE. 4790 */ 4791 4792 /* DMA tag for our hardware scb structures */ 4793 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, 4794 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4795 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 4796 /*highaddr*/BUS_SPACE_MAXADDR, 4797 /*filter*/NULL, /*filterarg*/NULL, 4798 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb), 4799 /*nsegments*/1, 4800 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 4801 /*flags*/0, &scb_data->hscb_dmat) != 0) { 4802 goto error_exit; 4803 } 4804 4805 scb_data->init_level++; 4806 4807 /* Allocation for our hscbs */ 4808 if (ahc_dmamem_alloc(ahc, scb_data->hscb_dmat, 4809 (void **)&scb_data->hscbs, 4810 BUS_DMA_NOWAIT, &scb_data->hscb_dmamap) != 0) { 4811 goto error_exit; 4812 } 4813 4814 scb_data->init_level++; 4815 4816 /* And permanently map them */ 4817 ahc_dmamap_load(ahc, scb_data->hscb_dmat, scb_data->hscb_dmamap, 4818 scb_data->hscbs, 4819 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb), 4820 ahc_dmamap_cb, &scb_data->hscb_busaddr, /*flags*/0); 4821 4822 scb_data->init_level++; 4823 4824 /* DMA tag for our sense buffers */ 4825 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, 4826 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4827 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 4828 /*highaddr*/BUS_SPACE_MAXADDR, 4829 /*filter*/NULL, /*filterarg*/NULL, 4830 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data), 4831 /*nsegments*/1, 4832 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 4833 /*flags*/0, &scb_data->sense_dmat) != 0) { 4834 goto error_exit; 4835 } 4836 4837 scb_data->init_level++; 4838 4839 /* Allocate them */ 4840 if (ahc_dmamem_alloc(ahc, scb_data->sense_dmat, 4841 (void **)&scb_data->sense, 4842 BUS_DMA_NOWAIT, &scb_data->sense_dmamap) != 0) { 4843 goto error_exit; 4844 } 4845 4846 scb_data->init_level++; 4847 4848 /* And permanently map them */ 4849 ahc_dmamap_load(ahc, scb_data->sense_dmat, scb_data->sense_dmamap, 4850 scb_data->sense, 4851 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data), 4852 ahc_dmamap_cb, &scb_data->sense_busaddr, /*flags*/0); 4853 4854 scb_data->init_level++; 4855 4856 /* DMA tag for our S/G structures. We allocate in page sized chunks */ 4857 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/8, 4858 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4859 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 4860 /*highaddr*/BUS_SPACE_MAXADDR, 4861 /*filter*/NULL, /*filterarg*/NULL, 4862 PAGE_SIZE, /*nsegments*/1, 4863 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 4864 /*flags*/0, &scb_data->sg_dmat) != 0) { 4865 goto error_exit; 4866 } 4867 4868 scb_data->init_level++; 4869 4870 /* Perform initial CCB allocation */ 4871 memset(scb_data->hscbs, 0, 4872 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb)); 4873 ahc_alloc_scbs(ahc); 4874 4875 if (scb_data->numscbs == 0) { 4876 printk("%s: ahc_init_scbdata - " 4877 "Unable to allocate initial scbs\n", 4878 ahc_name(ahc)); 4879 goto error_exit; 4880 } 4881 4882 /* 4883 * Reserve the next queued SCB. 4884 */ 4885 ahc->next_queued_scb = ahc_get_scb(ahc); 4886 4887 /* 4888 * Note that we were successful 4889 */ 4890 return (0); 4891 4892 error_exit: 4893 4894 return (ENOMEM); 4895 } 4896 4897 static void 4898 ahc_fini_scbdata(struct ahc_softc *ahc) 4899 { 4900 struct scb_data *scb_data; 4901 4902 scb_data = ahc->scb_data; 4903 if (scb_data == NULL) 4904 return; 4905 4906 switch (scb_data->init_level) { 4907 default: 4908 case 7: 4909 { 4910 struct sg_map_node *sg_map; 4911 4912 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) { 4913 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 4914 ahc_dmamap_unload(ahc, scb_data->sg_dmat, 4915 sg_map->sg_dmamap); 4916 ahc_dmamem_free(ahc, scb_data->sg_dmat, 4917 sg_map->sg_vaddr, 4918 sg_map->sg_dmamap); 4919 kfree(sg_map); 4920 } 4921 ahc_dma_tag_destroy(ahc, scb_data->sg_dmat); 4922 } 4923 case 6: 4924 ahc_dmamap_unload(ahc, scb_data->sense_dmat, 4925 scb_data->sense_dmamap); 4926 case 5: 4927 ahc_dmamem_free(ahc, scb_data->sense_dmat, scb_data->sense, 4928 scb_data->sense_dmamap); 4929 ahc_dmamap_destroy(ahc, scb_data->sense_dmat, 4930 scb_data->sense_dmamap); 4931 case 4: 4932 ahc_dma_tag_destroy(ahc, scb_data->sense_dmat); 4933 case 3: 4934 ahc_dmamap_unload(ahc, scb_data->hscb_dmat, 4935 scb_data->hscb_dmamap); 4936 case 2: 4937 ahc_dmamem_free(ahc, scb_data->hscb_dmat, scb_data->hscbs, 4938 scb_data->hscb_dmamap); 4939 ahc_dmamap_destroy(ahc, scb_data->hscb_dmat, 4940 scb_data->hscb_dmamap); 4941 case 1: 4942 ahc_dma_tag_destroy(ahc, scb_data->hscb_dmat); 4943 break; 4944 case 0: 4945 break; 4946 } 4947 if (scb_data->scbarray != NULL) 4948 kfree(scb_data->scbarray); 4949 } 4950 4951 static void 4952 ahc_alloc_scbs(struct ahc_softc *ahc) 4953 { 4954 struct scb_data *scb_data; 4955 struct scb *next_scb; 4956 struct sg_map_node *sg_map; 4957 dma_addr_t physaddr; 4958 struct ahc_dma_seg *segs; 4959 int newcount; 4960 int i; 4961 4962 scb_data = ahc->scb_data; 4963 if (scb_data->numscbs >= AHC_SCB_MAX_ALLOC) 4964 /* Can't allocate any more */ 4965 return; 4966 4967 next_scb = &scb_data->scbarray[scb_data->numscbs]; 4968 4969 sg_map = kmalloc(sizeof(*sg_map), GFP_ATOMIC); 4970 4971 if (sg_map == NULL) 4972 return; 4973 4974 /* Allocate S/G space for the next batch of SCBS */ 4975 if (ahc_dmamem_alloc(ahc, scb_data->sg_dmat, 4976 (void **)&sg_map->sg_vaddr, 4977 BUS_DMA_NOWAIT, &sg_map->sg_dmamap) != 0) { 4978 kfree(sg_map); 4979 return; 4980 } 4981 4982 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 4983 4984 ahc_dmamap_load(ahc, scb_data->sg_dmat, sg_map->sg_dmamap, 4985 sg_map->sg_vaddr, PAGE_SIZE, ahc_dmamap_cb, 4986 &sg_map->sg_physaddr, /*flags*/0); 4987 4988 segs = sg_map->sg_vaddr; 4989 physaddr = sg_map->sg_physaddr; 4990 4991 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg))); 4992 newcount = min(newcount, (AHC_SCB_MAX_ALLOC - scb_data->numscbs)); 4993 for (i = 0; i < newcount; i++) { 4994 struct scb_platform_data *pdata; 4995 4996 pdata = kmalloc(sizeof(*pdata), GFP_ATOMIC); 4997 if (pdata == NULL) 4998 break; 4999 next_scb->platform_data = pdata; 5000 next_scb->sg_map = sg_map; 5001 next_scb->sg_list = segs; 5002 /* 5003 * The sequencer always starts with the second entry. 5004 * The first entry is embedded in the scb. 5005 */ 5006 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); 5007 next_scb->ahc_softc = ahc; 5008 next_scb->flags = SCB_FREE; 5009 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; 5010 next_scb->hscb->tag = ahc->scb_data->numscbs; 5011 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, 5012 next_scb, links.sle); 5013 segs += AHC_NSEG; 5014 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg)); 5015 next_scb++; 5016 ahc->scb_data->numscbs++; 5017 } 5018 } 5019 5020 void 5021 ahc_controller_info(struct ahc_softc *ahc, char *buf) 5022 { 5023 int len; 5024 5025 len = sprintf(buf, "%s: ", ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]); 5026 buf += len; 5027 if ((ahc->features & AHC_TWIN) != 0) 5028 len = sprintf(buf, "Twin Channel, A SCSI Id=%d, " 5029 "B SCSI Id=%d, primary %c, ", 5030 ahc->our_id, ahc->our_id_b, 5031 (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A'); 5032 else { 5033 const char *speed; 5034 const char *type; 5035 5036 speed = ""; 5037 if ((ahc->features & AHC_ULTRA) != 0) { 5038 speed = "Ultra "; 5039 } else if ((ahc->features & AHC_DT) != 0) { 5040 speed = "Ultra160 "; 5041 } else if ((ahc->features & AHC_ULTRA2) != 0) { 5042 speed = "Ultra2 "; 5043 } 5044 if ((ahc->features & AHC_WIDE) != 0) { 5045 type = "Wide"; 5046 } else { 5047 type = "Single"; 5048 } 5049 len = sprintf(buf, "%s%s Channel %c, SCSI Id=%d, ", 5050 speed, type, ahc->channel, ahc->our_id); 5051 } 5052 buf += len; 5053 5054 if ((ahc->flags & AHC_PAGESCBS) != 0) 5055 sprintf(buf, "%d/%d SCBs", 5056 ahc->scb_data->maxhscbs, AHC_MAX_QUEUE); 5057 else 5058 sprintf(buf, "%d SCBs", ahc->scb_data->maxhscbs); 5059 } 5060 5061 int 5062 ahc_chip_init(struct ahc_softc *ahc) 5063 { 5064 int term; 5065 int error; 5066 u_int i; 5067 u_int scsi_conf; 5068 u_int scsiseq_template; 5069 uint32_t physaddr; 5070 5071 ahc_outb(ahc, SEQ_FLAGS, 0); 5072 ahc_outb(ahc, SEQ_FLAGS2, 0); 5073 5074 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/ 5075 if (ahc->features & AHC_TWIN) { 5076 5077 /* 5078 * Setup Channel B first. 5079 */ 5080 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB); 5081 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0; 5082 ahc_outb(ahc, SCSIID, ahc->our_id_b); 5083 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 5084 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 5085 |term|ahc->seltime_b|ENSTIMER|ACTNEGEN); 5086 if ((ahc->features & AHC_ULTRA2) != 0) 5087 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR); 5088 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 5089 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 5090 5091 /* Select Channel A */ 5092 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 5093 } 5094 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0; 5095 if ((ahc->features & AHC_ULTRA2) != 0) 5096 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 5097 else 5098 ahc_outb(ahc, SCSIID, ahc->our_id); 5099 scsi_conf = ahc_inb(ahc, SCSICONF); 5100 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 5101 |term|ahc->seltime 5102 |ENSTIMER|ACTNEGEN); 5103 if ((ahc->features & AHC_ULTRA2) != 0) 5104 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR); 5105 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 5106 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 5107 5108 /* There are no untagged SCBs active yet. */ 5109 for (i = 0; i < 16; i++) { 5110 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0)); 5111 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5112 int lun; 5113 5114 /* 5115 * The SCB based BTT allows an entry per 5116 * target and lun pair. 5117 */ 5118 for (lun = 1; lun < AHC_NUM_LUNS; lun++) 5119 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun)); 5120 } 5121 } 5122 5123 /* All of our queues are empty */ 5124 for (i = 0; i < 256; i++) 5125 ahc->qoutfifo[i] = SCB_LIST_NULL; 5126 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD); 5127 5128 for (i = 0; i < 256; i++) 5129 ahc->qinfifo[i] = SCB_LIST_NULL; 5130 5131 if ((ahc->features & AHC_MULTI_TID) != 0) { 5132 ahc_outb(ahc, TARGID, 0); 5133 ahc_outb(ahc, TARGID + 1, 0); 5134 } 5135 5136 /* 5137 * Tell the sequencer where it can find our arrays in memory. 5138 */ 5139 physaddr = ahc->scb_data->hscb_busaddr; 5140 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF); 5141 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF); 5142 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF); 5143 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF); 5144 5145 physaddr = ahc->shared_data_busaddr; 5146 ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF); 5147 ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF); 5148 ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF); 5149 ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF); 5150 5151 /* 5152 * Initialize the group code to command length table. 5153 * This overrides the values in TARG_SCSIRATE, so only 5154 * setup the table after we have processed that information. 5155 */ 5156 ahc_outb(ahc, CMDSIZE_TABLE, 5); 5157 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9); 5158 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9); 5159 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0); 5160 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15); 5161 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11); 5162 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0); 5163 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0); 5164 5165 if ((ahc->features & AHC_HS_MAILBOX) != 0) 5166 ahc_outb(ahc, HS_MAILBOX, 0); 5167 5168 /* Tell the sequencer of our initial queue positions */ 5169 if ((ahc->features & AHC_TARGETMODE) != 0) { 5170 ahc->tqinfifonext = 1; 5171 ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1); 5172 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext); 5173 } 5174 ahc->qinfifonext = 0; 5175 ahc->qoutfifonext = 0; 5176 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5177 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256); 5178 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 5179 ahc_outb(ahc, SNSCB_QOFF, ahc->qinfifonext); 5180 ahc_outb(ahc, SDSCB_QOFF, 0); 5181 } else { 5182 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 5183 ahc_outb(ahc, QINPOS, ahc->qinfifonext); 5184 ahc_outb(ahc, QOUTPOS, ahc->qoutfifonext); 5185 } 5186 5187 /* We don't have any waiting selections */ 5188 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL); 5189 5190 /* Our disconnection list is empty too */ 5191 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL); 5192 5193 /* Message out buffer starts empty */ 5194 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 5195 5196 /* 5197 * Setup the allowed SCSI Sequences based on operational mode. 5198 * If we are a target, we'll enable select in operations once 5199 * we've had a lun enabled. 5200 */ 5201 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP; 5202 if ((ahc->flags & AHC_INITIATORROLE) != 0) 5203 scsiseq_template |= ENRSELI; 5204 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template); 5205 5206 /* Initialize our list of free SCBs. */ 5207 ahc_build_free_scb_list(ahc); 5208 5209 /* 5210 * Tell the sequencer which SCB will be the next one it receives. 5211 */ 5212 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag); 5213 5214 /* 5215 * Load the Sequencer program and Enable the adapter 5216 * in "fast" mode. 5217 */ 5218 if (bootverbose) 5219 printk("%s: Downloading Sequencer Program...", 5220 ahc_name(ahc)); 5221 5222 error = ahc_loadseq(ahc); 5223 if (error != 0) 5224 return (error); 5225 5226 if ((ahc->features & AHC_ULTRA2) != 0) { 5227 int wait; 5228 5229 /* 5230 * Wait for up to 500ms for our transceivers 5231 * to settle. If the adapter does not have 5232 * a cable attached, the transceivers may 5233 * never settle, so don't complain if we 5234 * fail here. 5235 */ 5236 for (wait = 5000; 5237 (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait; 5238 wait--) 5239 ahc_delay(100); 5240 } 5241 ahc_restart(ahc); 5242 return (0); 5243 } 5244 5245 /* 5246 * Start the board, ready for normal operation 5247 */ 5248 int 5249 ahc_init(struct ahc_softc *ahc) 5250 { 5251 int max_targ; 5252 u_int i; 5253 u_int scsi_conf; 5254 u_int ultraenb; 5255 u_int discenable; 5256 u_int tagenable; 5257 size_t driver_data_size; 5258 5259 #ifdef AHC_DEBUG 5260 if ((ahc_debug & AHC_DEBUG_SEQUENCER) != 0) 5261 ahc->flags |= AHC_SEQUENCER_DEBUG; 5262 #endif 5263 5264 #ifdef AHC_PRINT_SRAM 5265 printk("Scratch Ram:"); 5266 for (i = 0x20; i < 0x5f; i++) { 5267 if (((i % 8) == 0) && (i != 0)) { 5268 printk ("\n "); 5269 } 5270 printk (" 0x%x", ahc_inb(ahc, i)); 5271 } 5272 if ((ahc->features & AHC_MORE_SRAM) != 0) { 5273 for (i = 0x70; i < 0x7f; i++) { 5274 if (((i % 8) == 0) && (i != 0)) { 5275 printk ("\n "); 5276 } 5277 printk (" 0x%x", ahc_inb(ahc, i)); 5278 } 5279 } 5280 printk ("\n"); 5281 /* 5282 * Reading uninitialized scratch ram may 5283 * generate parity errors. 5284 */ 5285 ahc_outb(ahc, CLRINT, CLRPARERR); 5286 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 5287 #endif 5288 max_targ = 15; 5289 5290 /* 5291 * Assume we have a board at this stage and it has been reset. 5292 */ 5293 if ((ahc->flags & AHC_USEDEFAULTS) != 0) 5294 ahc->our_id = ahc->our_id_b = 7; 5295 5296 /* 5297 * Default to allowing initiator operations. 5298 */ 5299 ahc->flags |= AHC_INITIATORROLE; 5300 5301 /* 5302 * Only allow target mode features if this unit has them enabled. 5303 */ 5304 if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0) 5305 ahc->features &= ~AHC_TARGETMODE; 5306 5307 ahc->init_level++; 5308 5309 /* 5310 * DMA tag for our command fifos and other data in system memory 5311 * the card's sequencer must be able to access. For initiator 5312 * roles, we need to allocate space for the qinfifo and qoutfifo. 5313 * The qinfifo and qoutfifo are composed of 256 1 byte elements. 5314 * When providing for the target mode role, we must additionally 5315 * provide space for the incoming target command fifo and an extra 5316 * byte to deal with a dma bug in some chip versions. 5317 */ 5318 driver_data_size = 2 * 256 * sizeof(uint8_t); 5319 if ((ahc->features & AHC_TARGETMODE) != 0) 5320 driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd) 5321 + /*DMA WideOdd Bug Buffer*/1; 5322 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, 5323 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 5324 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 5325 /*highaddr*/BUS_SPACE_MAXADDR, 5326 /*filter*/NULL, /*filterarg*/NULL, 5327 driver_data_size, 5328 /*nsegments*/1, 5329 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 5330 /*flags*/0, &ahc->shared_data_dmat) != 0) { 5331 return (ENOMEM); 5332 } 5333 5334 ahc->init_level++; 5335 5336 /* Allocation of driver data */ 5337 if (ahc_dmamem_alloc(ahc, ahc->shared_data_dmat, 5338 (void **)&ahc->qoutfifo, 5339 BUS_DMA_NOWAIT, &ahc->shared_data_dmamap) != 0) { 5340 return (ENOMEM); 5341 } 5342 5343 ahc->init_level++; 5344 5345 /* And permanently map it in */ 5346 ahc_dmamap_load(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap, 5347 ahc->qoutfifo, driver_data_size, ahc_dmamap_cb, 5348 &ahc->shared_data_busaddr, /*flags*/0); 5349 5350 if ((ahc->features & AHC_TARGETMODE) != 0) { 5351 ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo; 5352 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS]; 5353 ahc->dma_bug_buf = ahc->shared_data_busaddr 5354 + driver_data_size - 1; 5355 /* All target command blocks start out invalid. */ 5356 for (i = 0; i < AHC_TMODE_CMDS; i++) 5357 ahc->targetcmds[i].cmd_valid = 0; 5358 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD); 5359 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256]; 5360 } 5361 ahc->qinfifo = &ahc->qoutfifo[256]; 5362 5363 ahc->init_level++; 5364 5365 /* Allocate SCB data now that buffer_dmat is initialized */ 5366 if (ahc->scb_data->maxhscbs == 0) 5367 if (ahc_init_scbdata(ahc) != 0) 5368 return (ENOMEM); 5369 5370 /* 5371 * Allocate a tstate to house information for our 5372 * initiator presence on the bus as well as the user 5373 * data for any target mode initiator. 5374 */ 5375 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) { 5376 printk("%s: unable to allocate ahc_tmode_tstate. " 5377 "Failing attach\n", ahc_name(ahc)); 5378 return (ENOMEM); 5379 } 5380 5381 if ((ahc->features & AHC_TWIN) != 0) { 5382 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) { 5383 printk("%s: unable to allocate ahc_tmode_tstate. " 5384 "Failing attach\n", ahc_name(ahc)); 5385 return (ENOMEM); 5386 } 5387 } 5388 5389 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX_ALLOC) { 5390 ahc->flags |= AHC_PAGESCBS; 5391 } else { 5392 ahc->flags &= ~AHC_PAGESCBS; 5393 } 5394 5395 #ifdef AHC_DEBUG 5396 if (ahc_debug & AHC_SHOW_MISC) { 5397 printk("%s: hardware scb %u bytes; kernel scb %u bytes; " 5398 "ahc_dma %u bytes\n", 5399 ahc_name(ahc), 5400 (u_int)sizeof(struct hardware_scb), 5401 (u_int)sizeof(struct scb), 5402 (u_int)sizeof(struct ahc_dma_seg)); 5403 } 5404 #endif /* AHC_DEBUG */ 5405 5406 /* 5407 * Look at the information that board initialization or 5408 * the board bios has left us. 5409 */ 5410 if (ahc->features & AHC_TWIN) { 5411 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 5412 if ((scsi_conf & RESET_SCSI) != 0 5413 && (ahc->flags & AHC_INITIATORROLE) != 0) 5414 ahc->flags |= AHC_RESET_BUS_B; 5415 } 5416 5417 scsi_conf = ahc_inb(ahc, SCSICONF); 5418 if ((scsi_conf & RESET_SCSI) != 0 5419 && (ahc->flags & AHC_INITIATORROLE) != 0) 5420 ahc->flags |= AHC_RESET_BUS_A; 5421 5422 ultraenb = 0; 5423 tagenable = ALL_TARGETS_MASK; 5424 5425 /* Grab the disconnection disable table and invert it for our needs */ 5426 if ((ahc->flags & AHC_USEDEFAULTS) != 0) { 5427 printk("%s: Host Adapter Bios disabled. Using default SCSI " 5428 "device parameters\n", ahc_name(ahc)); 5429 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B| 5430 AHC_TERM_ENB_A|AHC_TERM_ENB_B; 5431 discenable = ALL_TARGETS_MASK; 5432 if ((ahc->features & AHC_ULTRA) != 0) 5433 ultraenb = ALL_TARGETS_MASK; 5434 } else { 5435 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8) 5436 | ahc_inb(ahc, DISC_DSB)); 5437 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0) 5438 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8) 5439 | ahc_inb(ahc, ULTRA_ENB); 5440 } 5441 5442 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0) 5443 max_targ = 7; 5444 5445 for (i = 0; i <= max_targ; i++) { 5446 struct ahc_initiator_tinfo *tinfo; 5447 struct ahc_tmode_tstate *tstate; 5448 u_int our_id; 5449 u_int target_id; 5450 char channel; 5451 5452 channel = 'A'; 5453 our_id = ahc->our_id; 5454 target_id = i; 5455 if (i > 7 && (ahc->features & AHC_TWIN) != 0) { 5456 channel = 'B'; 5457 our_id = ahc->our_id_b; 5458 target_id = i % 8; 5459 } 5460 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, 5461 target_id, &tstate); 5462 /* Default to async narrow across the board */ 5463 memset(tinfo, 0, sizeof(*tinfo)); 5464 if (ahc->flags & AHC_USEDEFAULTS) { 5465 if ((ahc->features & AHC_WIDE) != 0) 5466 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 5467 5468 /* 5469 * These will be truncated when we determine the 5470 * connection type we have with the target. 5471 */ 5472 tinfo->user.period = ahc_syncrates->period; 5473 tinfo->user.offset = MAX_OFFSET; 5474 } else { 5475 u_int scsirate; 5476 uint16_t mask; 5477 5478 /* Take the settings leftover in scratch RAM. */ 5479 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i); 5480 mask = (0x01 << i); 5481 if ((ahc->features & AHC_ULTRA2) != 0) { 5482 u_int offset; 5483 u_int maxsync; 5484 5485 if ((scsirate & SOFS) == 0x0F) { 5486 /* 5487 * Haven't negotiated yet, 5488 * so the format is different. 5489 */ 5490 scsirate = (scsirate & SXFR) >> 4 5491 | (ultraenb & mask) 5492 ? 0x08 : 0x0 5493 | (scsirate & WIDEXFER); 5494 offset = MAX_OFFSET_ULTRA2; 5495 } else 5496 offset = ahc_inb(ahc, TARG_OFFSET + i); 5497 if ((scsirate & ~WIDEXFER) == 0 && offset != 0) 5498 /* Set to the lowest sync rate, 5MHz */ 5499 scsirate |= 0x1c; 5500 maxsync = AHC_SYNCRATE_ULTRA2; 5501 if ((ahc->features & AHC_DT) != 0) 5502 maxsync = AHC_SYNCRATE_DT; 5503 tinfo->user.period = 5504 ahc_find_period(ahc, scsirate, maxsync); 5505 if (offset == 0) 5506 tinfo->user.period = 0; 5507 else 5508 tinfo->user.offset = MAX_OFFSET; 5509 if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/ 5510 && (ahc->features & AHC_DT) != 0) 5511 tinfo->user.ppr_options = 5512 MSG_EXT_PPR_DT_REQ; 5513 } else if ((scsirate & SOFS) != 0) { 5514 if ((scsirate & SXFR) == 0x40 5515 && (ultraenb & mask) != 0) { 5516 /* Treat 10MHz as a non-ultra speed */ 5517 scsirate &= ~SXFR; 5518 ultraenb &= ~mask; 5519 } 5520 tinfo->user.period = 5521 ahc_find_period(ahc, scsirate, 5522 (ultraenb & mask) 5523 ? AHC_SYNCRATE_ULTRA 5524 : AHC_SYNCRATE_FAST); 5525 if (tinfo->user.period != 0) 5526 tinfo->user.offset = MAX_OFFSET; 5527 } 5528 if (tinfo->user.period == 0) 5529 tinfo->user.offset = 0; 5530 if ((scsirate & WIDEXFER) != 0 5531 && (ahc->features & AHC_WIDE) != 0) 5532 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 5533 tinfo->user.protocol_version = 4; 5534 if ((ahc->features & AHC_DT) != 0) 5535 tinfo->user.transport_version = 3; 5536 else 5537 tinfo->user.transport_version = 2; 5538 tinfo->goal.protocol_version = 2; 5539 tinfo->goal.transport_version = 2; 5540 tinfo->curr.protocol_version = 2; 5541 tinfo->curr.transport_version = 2; 5542 } 5543 tstate->ultraenb = 0; 5544 } 5545 ahc->user_discenable = discenable; 5546 ahc->user_tagenable = tagenable; 5547 5548 return (ahc->bus_chip_init(ahc)); 5549 } 5550 5551 void 5552 ahc_intr_enable(struct ahc_softc *ahc, int enable) 5553 { 5554 u_int hcntrl; 5555 5556 hcntrl = ahc_inb(ahc, HCNTRL); 5557 hcntrl &= ~INTEN; 5558 ahc->pause &= ~INTEN; 5559 ahc->unpause &= ~INTEN; 5560 if (enable) { 5561 hcntrl |= INTEN; 5562 ahc->pause |= INTEN; 5563 ahc->unpause |= INTEN; 5564 } 5565 ahc_outb(ahc, HCNTRL, hcntrl); 5566 } 5567 5568 /* 5569 * Ensure that the card is paused in a location 5570 * outside of all critical sections and that all 5571 * pending work is completed prior to returning. 5572 * This routine should only be called from outside 5573 * an interrupt context. 5574 */ 5575 void 5576 ahc_pause_and_flushwork(struct ahc_softc *ahc) 5577 { 5578 int intstat; 5579 int maxloops; 5580 int paused; 5581 5582 maxloops = 1000; 5583 ahc->flags |= AHC_ALL_INTERRUPTS; 5584 paused = FALSE; 5585 do { 5586 if (paused) { 5587 ahc_unpause(ahc); 5588 /* 5589 * Give the sequencer some time to service 5590 * any active selections. 5591 */ 5592 ahc_delay(500); 5593 } 5594 ahc_intr(ahc); 5595 ahc_pause(ahc); 5596 paused = TRUE; 5597 ahc_outb(ahc, SCSISEQ, ahc_inb(ahc, SCSISEQ) & ~ENSELO); 5598 intstat = ahc_inb(ahc, INTSTAT); 5599 if ((intstat & INT_PEND) == 0) { 5600 ahc_clear_critical_section(ahc); 5601 intstat = ahc_inb(ahc, INTSTAT); 5602 } 5603 } while (--maxloops 5604 && (intstat != 0xFF || (ahc->features & AHC_REMOVABLE) == 0) 5605 && ((intstat & INT_PEND) != 0 5606 || (ahc_inb(ahc, SSTAT0) & (SELDO|SELINGO)) != 0)); 5607 if (maxloops == 0) { 5608 printk("Infinite interrupt loop, INTSTAT = %x", 5609 ahc_inb(ahc, INTSTAT)); 5610 } 5611 ahc_platform_flushwork(ahc); 5612 ahc->flags &= ~AHC_ALL_INTERRUPTS; 5613 } 5614 5615 #ifdef CONFIG_PM 5616 int 5617 ahc_suspend(struct ahc_softc *ahc) 5618 { 5619 5620 ahc_pause_and_flushwork(ahc); 5621 5622 if (LIST_FIRST(&ahc->pending_scbs) != NULL) { 5623 ahc_unpause(ahc); 5624 return (EBUSY); 5625 } 5626 5627 #ifdef AHC_TARGET_MODE 5628 /* 5629 * XXX What about ATIOs that have not yet been serviced? 5630 * Perhaps we should just refuse to be suspended if we 5631 * are acting in a target role. 5632 */ 5633 if (ahc->pending_device != NULL) { 5634 ahc_unpause(ahc); 5635 return (EBUSY); 5636 } 5637 #endif 5638 ahc_shutdown(ahc); 5639 return (0); 5640 } 5641 5642 int 5643 ahc_resume(struct ahc_softc *ahc) 5644 { 5645 5646 ahc_reset(ahc, /*reinit*/TRUE); 5647 ahc_intr_enable(ahc, TRUE); 5648 ahc_restart(ahc); 5649 return (0); 5650 } 5651 #endif 5652 /************************** Busy Target Table *********************************/ 5653 /* 5654 * Return the untagged transaction id for a given target/channel lun. 5655 * Optionally, clear the entry. 5656 */ 5657 static u_int 5658 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl) 5659 { 5660 u_int scbid; 5661 u_int target_offset; 5662 5663 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5664 u_int saved_scbptr; 5665 5666 saved_scbptr = ahc_inb(ahc, SCBPTR); 5667 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5668 scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl)); 5669 ahc_outb(ahc, SCBPTR, saved_scbptr); 5670 } else { 5671 target_offset = TCL_TARGET_OFFSET(tcl); 5672 scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset); 5673 } 5674 5675 return (scbid); 5676 } 5677 5678 static void 5679 ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl) 5680 { 5681 u_int target_offset; 5682 5683 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5684 u_int saved_scbptr; 5685 5686 saved_scbptr = ahc_inb(ahc, SCBPTR); 5687 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5688 ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL); 5689 ahc_outb(ahc, SCBPTR, saved_scbptr); 5690 } else { 5691 target_offset = TCL_TARGET_OFFSET(tcl); 5692 ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL); 5693 } 5694 } 5695 5696 static void 5697 ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid) 5698 { 5699 u_int target_offset; 5700 5701 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5702 u_int saved_scbptr; 5703 5704 saved_scbptr = ahc_inb(ahc, SCBPTR); 5705 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5706 ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid); 5707 ahc_outb(ahc, SCBPTR, saved_scbptr); 5708 } else { 5709 target_offset = TCL_TARGET_OFFSET(tcl); 5710 ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid); 5711 } 5712 } 5713 5714 /************************** SCB and SCB queue management **********************/ 5715 int 5716 ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target, 5717 char channel, int lun, u_int tag, role_t role) 5718 { 5719 int targ = SCB_GET_TARGET(ahc, scb); 5720 char chan = SCB_GET_CHANNEL(ahc, scb); 5721 int slun = SCB_GET_LUN(scb); 5722 int match; 5723 5724 match = ((chan == channel) || (channel == ALL_CHANNELS)); 5725 if (match != 0) 5726 match = ((targ == target) || (target == CAM_TARGET_WILDCARD)); 5727 if (match != 0) 5728 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD)); 5729 if (match != 0) { 5730 #ifdef AHC_TARGET_MODE 5731 int group; 5732 5733 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code); 5734 if (role == ROLE_INITIATOR) { 5735 match = (group != XPT_FC_GROUP_TMODE) 5736 && ((tag == scb->hscb->tag) 5737 || (tag == SCB_LIST_NULL)); 5738 } else if (role == ROLE_TARGET) { 5739 match = (group == XPT_FC_GROUP_TMODE) 5740 && ((tag == scb->io_ctx->csio.tag_id) 5741 || (tag == SCB_LIST_NULL)); 5742 } 5743 #else /* !AHC_TARGET_MODE */ 5744 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL)); 5745 #endif /* AHC_TARGET_MODE */ 5746 } 5747 5748 return match; 5749 } 5750 5751 static void 5752 ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb) 5753 { 5754 int target; 5755 char channel; 5756 int lun; 5757 5758 target = SCB_GET_TARGET(ahc, scb); 5759 lun = SCB_GET_LUN(scb); 5760 channel = SCB_GET_CHANNEL(ahc, scb); 5761 5762 ahc_search_qinfifo(ahc, target, channel, lun, 5763 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 5764 CAM_REQUEUE_REQ, SEARCH_COMPLETE); 5765 5766 ahc_platform_freeze_devq(ahc, scb); 5767 } 5768 5769 void 5770 ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb) 5771 { 5772 struct scb *prev_scb; 5773 5774 prev_scb = NULL; 5775 if (ahc_qinfifo_count(ahc) != 0) { 5776 u_int prev_tag; 5777 uint8_t prev_pos; 5778 5779 prev_pos = ahc->qinfifonext - 1; 5780 prev_tag = ahc->qinfifo[prev_pos]; 5781 prev_scb = ahc_lookup_scb(ahc, prev_tag); 5782 } 5783 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5784 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5785 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 5786 } else { 5787 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 5788 } 5789 } 5790 5791 static void 5792 ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb, 5793 struct scb *scb) 5794 { 5795 if (prev_scb == NULL) { 5796 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag); 5797 } else { 5798 prev_scb->hscb->next = scb->hscb->tag; 5799 ahc_sync_scb(ahc, prev_scb, 5800 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 5801 } 5802 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 5803 scb->hscb->next = ahc->next_queued_scb->hscb->tag; 5804 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 5805 } 5806 5807 static int 5808 ahc_qinfifo_count(struct ahc_softc *ahc) 5809 { 5810 uint8_t qinpos; 5811 uint8_t diff; 5812 5813 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5814 qinpos = ahc_inb(ahc, SNSCB_QOFF); 5815 ahc_outb(ahc, SNSCB_QOFF, qinpos); 5816 } else 5817 qinpos = ahc_inb(ahc, QINPOS); 5818 diff = ahc->qinfifonext - qinpos; 5819 return (diff); 5820 } 5821 5822 int 5823 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, 5824 int lun, u_int tag, role_t role, uint32_t status, 5825 ahc_search_action action) 5826 { 5827 struct scb *scb; 5828 struct scb *prev_scb; 5829 uint8_t qinstart; 5830 uint8_t qinpos; 5831 uint8_t qintail; 5832 uint8_t next; 5833 uint8_t prev; 5834 uint8_t curscbptr; 5835 int found; 5836 int have_qregs; 5837 5838 qintail = ahc->qinfifonext; 5839 have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0; 5840 if (have_qregs) { 5841 qinstart = ahc_inb(ahc, SNSCB_QOFF); 5842 ahc_outb(ahc, SNSCB_QOFF, qinstart); 5843 } else 5844 qinstart = ahc_inb(ahc, QINPOS); 5845 qinpos = qinstart; 5846 found = 0; 5847 prev_scb = NULL; 5848 5849 if (action == SEARCH_COMPLETE) { 5850 /* 5851 * Don't attempt to run any queued untagged transactions 5852 * until we are done with the abort process. 5853 */ 5854 ahc_freeze_untagged_queues(ahc); 5855 } 5856 5857 /* 5858 * Start with an empty queue. Entries that are not chosen 5859 * for removal will be re-added to the queue as we go. 5860 */ 5861 ahc->qinfifonext = qinpos; 5862 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag); 5863 5864 while (qinpos != qintail) { 5865 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]); 5866 if (scb == NULL) { 5867 printk("qinpos = %d, SCB index = %d\n", 5868 qinpos, ahc->qinfifo[qinpos]); 5869 panic("Loop 1\n"); 5870 } 5871 5872 if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) { 5873 /* 5874 * We found an scb that needs to be acted on. 5875 */ 5876 found++; 5877 switch (action) { 5878 case SEARCH_COMPLETE: 5879 { 5880 cam_status ostat; 5881 cam_status cstat; 5882 5883 ostat = ahc_get_transaction_status(scb); 5884 if (ostat == CAM_REQ_INPROG) 5885 ahc_set_transaction_status(scb, status); 5886 cstat = ahc_get_transaction_status(scb); 5887 if (cstat != CAM_REQ_CMP) 5888 ahc_freeze_scb(scb); 5889 if ((scb->flags & SCB_ACTIVE) == 0) 5890 printk("Inactive SCB in qinfifo\n"); 5891 ahc_done(ahc, scb); 5892 5893 /* FALLTHROUGH */ 5894 } 5895 case SEARCH_REMOVE: 5896 break; 5897 case SEARCH_COUNT: 5898 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5899 prev_scb = scb; 5900 break; 5901 } 5902 } else { 5903 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5904 prev_scb = scb; 5905 } 5906 qinpos++; 5907 } 5908 5909 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5910 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 5911 } else { 5912 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 5913 } 5914 5915 if (action != SEARCH_COUNT 5916 && (found != 0) 5917 && (qinstart != ahc->qinfifonext)) { 5918 /* 5919 * The sequencer may be in the process of dmaing 5920 * down the SCB at the beginning of the queue. 5921 * This could be problematic if either the first, 5922 * or the second SCB is removed from the queue 5923 * (the first SCB includes a pointer to the "next" 5924 * SCB to dma). If we have removed any entries, swap 5925 * the first element in the queue with the next HSCB 5926 * so the sequencer will notice that NEXT_QUEUED_SCB 5927 * has changed during its dma attempt and will retry 5928 * the DMA. 5929 */ 5930 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]); 5931 5932 if (scb == NULL) { 5933 printk("found = %d, qinstart = %d, qinfifionext = %d\n", 5934 found, qinstart, ahc->qinfifonext); 5935 panic("First/Second Qinfifo fixup\n"); 5936 } 5937 /* 5938 * ahc_swap_with_next_hscb forces our next pointer to 5939 * point to the reserved SCB for future commands. Save 5940 * and restore our original next pointer to maintain 5941 * queue integrity. 5942 */ 5943 next = scb->hscb->next; 5944 ahc->scb_data->scbindex[scb->hscb->tag] = NULL; 5945 ahc_swap_with_next_hscb(ahc, scb); 5946 scb->hscb->next = next; 5947 ahc->qinfifo[qinstart] = scb->hscb->tag; 5948 5949 /* Tell the card about the new head of the qinfifo. */ 5950 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag); 5951 5952 /* Fixup the tail "next" pointer. */ 5953 qintail = ahc->qinfifonext - 1; 5954 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]); 5955 scb->hscb->next = ahc->next_queued_scb->hscb->tag; 5956 } 5957 5958 /* 5959 * Search waiting for selection list. 5960 */ 5961 curscbptr = ahc_inb(ahc, SCBPTR); 5962 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */ 5963 prev = SCB_LIST_NULL; 5964 5965 while (next != SCB_LIST_NULL) { 5966 uint8_t scb_index; 5967 5968 ahc_outb(ahc, SCBPTR, next); 5969 scb_index = ahc_inb(ahc, SCB_TAG); 5970 if (scb_index >= ahc->scb_data->numscbs) { 5971 printk("Waiting List inconsistency. " 5972 "SCB index == %d, yet numscbs == %d.", 5973 scb_index, ahc->scb_data->numscbs); 5974 ahc_dump_card_state(ahc); 5975 panic("for safety"); 5976 } 5977 scb = ahc_lookup_scb(ahc, scb_index); 5978 if (scb == NULL) { 5979 printk("scb_index = %d, next = %d\n", 5980 scb_index, next); 5981 panic("Waiting List traversal\n"); 5982 } 5983 if (ahc_match_scb(ahc, scb, target, channel, 5984 lun, SCB_LIST_NULL, role)) { 5985 /* 5986 * We found an scb that needs to be acted on. 5987 */ 5988 found++; 5989 switch (action) { 5990 case SEARCH_COMPLETE: 5991 { 5992 cam_status ostat; 5993 cam_status cstat; 5994 5995 ostat = ahc_get_transaction_status(scb); 5996 if (ostat == CAM_REQ_INPROG) 5997 ahc_set_transaction_status(scb, 5998 status); 5999 cstat = ahc_get_transaction_status(scb); 6000 if (cstat != CAM_REQ_CMP) 6001 ahc_freeze_scb(scb); 6002 if ((scb->flags & SCB_ACTIVE) == 0) 6003 printk("Inactive SCB in Waiting List\n"); 6004 ahc_done(ahc, scb); 6005 /* FALLTHROUGH */ 6006 } 6007 case SEARCH_REMOVE: 6008 next = ahc_rem_wscb(ahc, next, prev); 6009 break; 6010 case SEARCH_COUNT: 6011 prev = next; 6012 next = ahc_inb(ahc, SCB_NEXT); 6013 break; 6014 } 6015 } else { 6016 6017 prev = next; 6018 next = ahc_inb(ahc, SCB_NEXT); 6019 } 6020 } 6021 ahc_outb(ahc, SCBPTR, curscbptr); 6022 6023 found += ahc_search_untagged_queues(ahc, /*ahc_io_ctx_t*/NULL, target, 6024 channel, lun, status, action); 6025 6026 if (action == SEARCH_COMPLETE) 6027 ahc_release_untagged_queues(ahc); 6028 return (found); 6029 } 6030 6031 int 6032 ahc_search_untagged_queues(struct ahc_softc *ahc, ahc_io_ctx_t ctx, 6033 int target, char channel, int lun, uint32_t status, 6034 ahc_search_action action) 6035 { 6036 struct scb *scb; 6037 int maxtarget; 6038 int found; 6039 int i; 6040 6041 if (action == SEARCH_COMPLETE) { 6042 /* 6043 * Don't attempt to run any queued untagged transactions 6044 * until we are done with the abort process. 6045 */ 6046 ahc_freeze_untagged_queues(ahc); 6047 } 6048 6049 found = 0; 6050 i = 0; 6051 if ((ahc->flags & AHC_SCB_BTT) == 0) { 6052 6053 maxtarget = 16; 6054 if (target != CAM_TARGET_WILDCARD) { 6055 6056 i = target; 6057 if (channel == 'B') 6058 i += 8; 6059 maxtarget = i + 1; 6060 } 6061 } else { 6062 maxtarget = 0; 6063 } 6064 6065 for (; i < maxtarget; i++) { 6066 struct scb_tailq *untagged_q; 6067 struct scb *next_scb; 6068 6069 untagged_q = &(ahc->untagged_queues[i]); 6070 next_scb = TAILQ_FIRST(untagged_q); 6071 while (next_scb != NULL) { 6072 6073 scb = next_scb; 6074 next_scb = TAILQ_NEXT(scb, links.tqe); 6075 6076 /* 6077 * The head of the list may be the currently 6078 * active untagged command for a device. 6079 * We're only searching for commands that 6080 * have not been started. A transaction 6081 * marked active but still in the qinfifo 6082 * is removed by the qinfifo scanning code 6083 * above. 6084 */ 6085 if ((scb->flags & SCB_ACTIVE) != 0) 6086 continue; 6087 6088 if (ahc_match_scb(ahc, scb, target, channel, lun, 6089 SCB_LIST_NULL, ROLE_INITIATOR) == 0 6090 || (ctx != NULL && ctx != scb->io_ctx)) 6091 continue; 6092 6093 /* 6094 * We found an scb that needs to be acted on. 6095 */ 6096 found++; 6097 switch (action) { 6098 case SEARCH_COMPLETE: 6099 { 6100 cam_status ostat; 6101 cam_status cstat; 6102 6103 ostat = ahc_get_transaction_status(scb); 6104 if (ostat == CAM_REQ_INPROG) 6105 ahc_set_transaction_status(scb, status); 6106 cstat = ahc_get_transaction_status(scb); 6107 if (cstat != CAM_REQ_CMP) 6108 ahc_freeze_scb(scb); 6109 if ((scb->flags & SCB_ACTIVE) == 0) 6110 printk("Inactive SCB in untaggedQ\n"); 6111 ahc_done(ahc, scb); 6112 break; 6113 } 6114 case SEARCH_REMOVE: 6115 scb->flags &= ~SCB_UNTAGGEDQ; 6116 TAILQ_REMOVE(untagged_q, scb, links.tqe); 6117 break; 6118 case SEARCH_COUNT: 6119 break; 6120 } 6121 } 6122 } 6123 6124 if (action == SEARCH_COMPLETE) 6125 ahc_release_untagged_queues(ahc); 6126 return (found); 6127 } 6128 6129 int 6130 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel, 6131 int lun, u_int tag, int stop_on_first, int remove, 6132 int save_state) 6133 { 6134 struct scb *scbp; 6135 u_int next; 6136 u_int prev; 6137 u_int count; 6138 u_int active_scb; 6139 6140 count = 0; 6141 next = ahc_inb(ahc, DISCONNECTED_SCBH); 6142 prev = SCB_LIST_NULL; 6143 6144 if (save_state) { 6145 /* restore this when we're done */ 6146 active_scb = ahc_inb(ahc, SCBPTR); 6147 } else 6148 /* Silence compiler */ 6149 active_scb = SCB_LIST_NULL; 6150 6151 while (next != SCB_LIST_NULL) { 6152 u_int scb_index; 6153 6154 ahc_outb(ahc, SCBPTR, next); 6155 scb_index = ahc_inb(ahc, SCB_TAG); 6156 if (scb_index >= ahc->scb_data->numscbs) { 6157 printk("Disconnected List inconsistency. " 6158 "SCB index == %d, yet numscbs == %d.", 6159 scb_index, ahc->scb_data->numscbs); 6160 ahc_dump_card_state(ahc); 6161 panic("for safety"); 6162 } 6163 6164 if (next == prev) { 6165 panic("Disconnected List Loop. " 6166 "cur SCBPTR == %x, prev SCBPTR == %x.", 6167 next, prev); 6168 } 6169 scbp = ahc_lookup_scb(ahc, scb_index); 6170 if (ahc_match_scb(ahc, scbp, target, channel, lun, 6171 tag, ROLE_INITIATOR)) { 6172 count++; 6173 if (remove) { 6174 next = 6175 ahc_rem_scb_from_disc_list(ahc, prev, next); 6176 } else { 6177 prev = next; 6178 next = ahc_inb(ahc, SCB_NEXT); 6179 } 6180 if (stop_on_first) 6181 break; 6182 } else { 6183 prev = next; 6184 next = ahc_inb(ahc, SCB_NEXT); 6185 } 6186 } 6187 if (save_state) 6188 ahc_outb(ahc, SCBPTR, active_scb); 6189 return (count); 6190 } 6191 6192 /* 6193 * Remove an SCB from the on chip list of disconnected transactions. 6194 * This is empty/unused if we are not performing SCB paging. 6195 */ 6196 static u_int 6197 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr) 6198 { 6199 u_int next; 6200 6201 ahc_outb(ahc, SCBPTR, scbptr); 6202 next = ahc_inb(ahc, SCB_NEXT); 6203 6204 ahc_outb(ahc, SCB_CONTROL, 0); 6205 6206 ahc_add_curscb_to_free_list(ahc); 6207 6208 if (prev != SCB_LIST_NULL) { 6209 ahc_outb(ahc, SCBPTR, prev); 6210 ahc_outb(ahc, SCB_NEXT, next); 6211 } else 6212 ahc_outb(ahc, DISCONNECTED_SCBH, next); 6213 6214 return (next); 6215 } 6216 6217 /* 6218 * Add the SCB as selected by SCBPTR onto the on chip list of 6219 * free hardware SCBs. This list is empty/unused if we are not 6220 * performing SCB paging. 6221 */ 6222 static void 6223 ahc_add_curscb_to_free_list(struct ahc_softc *ahc) 6224 { 6225 /* 6226 * Invalidate the tag so that our abort 6227 * routines don't think it's active. 6228 */ 6229 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 6230 6231 if ((ahc->flags & AHC_PAGESCBS) != 0) { 6232 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH)); 6233 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR)); 6234 } 6235 } 6236 6237 /* 6238 * Manipulate the waiting for selection list and return the 6239 * scb that follows the one that we remove. 6240 */ 6241 static u_int 6242 ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev) 6243 { 6244 u_int curscb, next; 6245 6246 /* 6247 * Select the SCB we want to abort and 6248 * pull the next pointer out of it. 6249 */ 6250 curscb = ahc_inb(ahc, SCBPTR); 6251 ahc_outb(ahc, SCBPTR, scbpos); 6252 next = ahc_inb(ahc, SCB_NEXT); 6253 6254 /* Clear the necessary fields */ 6255 ahc_outb(ahc, SCB_CONTROL, 0); 6256 6257 ahc_add_curscb_to_free_list(ahc); 6258 6259 /* update the waiting list */ 6260 if (prev == SCB_LIST_NULL) { 6261 /* First in the list */ 6262 ahc_outb(ahc, WAITING_SCBH, next); 6263 6264 /* 6265 * Ensure we aren't attempting to perform 6266 * selection for this entry. 6267 */ 6268 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 6269 } else { 6270 /* 6271 * Select the scb that pointed to us 6272 * and update its next pointer. 6273 */ 6274 ahc_outb(ahc, SCBPTR, prev); 6275 ahc_outb(ahc, SCB_NEXT, next); 6276 } 6277 6278 /* 6279 * Point us back at the original scb position. 6280 */ 6281 ahc_outb(ahc, SCBPTR, curscb); 6282 return next; 6283 } 6284 6285 /******************************** Error Handling ******************************/ 6286 /* 6287 * Abort all SCBs that match the given description (target/channel/lun/tag), 6288 * setting their status to the passed in status if the status has not already 6289 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 6290 * is paused before it is called. 6291 */ 6292 static int 6293 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, 6294 int lun, u_int tag, role_t role, uint32_t status) 6295 { 6296 struct scb *scbp; 6297 struct scb *scbp_next; 6298 u_int active_scb; 6299 int i, j; 6300 int maxtarget; 6301 int minlun; 6302 int maxlun; 6303 6304 int found; 6305 6306 /* 6307 * Don't attempt to run any queued untagged transactions 6308 * until we are done with the abort process. 6309 */ 6310 ahc_freeze_untagged_queues(ahc); 6311 6312 /* restore this when we're done */ 6313 active_scb = ahc_inb(ahc, SCBPTR); 6314 6315 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL, 6316 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE); 6317 6318 /* 6319 * Clean out the busy target table for any untagged commands. 6320 */ 6321 i = 0; 6322 maxtarget = 16; 6323 if (target != CAM_TARGET_WILDCARD) { 6324 i = target; 6325 if (channel == 'B') 6326 i += 8; 6327 maxtarget = i + 1; 6328 } 6329 6330 if (lun == CAM_LUN_WILDCARD) { 6331 6332 /* 6333 * Unless we are using an SCB based 6334 * busy targets table, there is only 6335 * one table entry for all luns of 6336 * a target. 6337 */ 6338 minlun = 0; 6339 maxlun = 1; 6340 if ((ahc->flags & AHC_SCB_BTT) != 0) 6341 maxlun = AHC_NUM_LUNS; 6342 } else { 6343 minlun = lun; 6344 maxlun = lun + 1; 6345 } 6346 6347 if (role != ROLE_TARGET) { 6348 for (;i < maxtarget; i++) { 6349 for (j = minlun;j < maxlun; j++) { 6350 u_int scbid; 6351 u_int tcl; 6352 6353 tcl = BUILD_TCL(i << 4, j); 6354 scbid = ahc_index_busy_tcl(ahc, tcl); 6355 scbp = ahc_lookup_scb(ahc, scbid); 6356 if (scbp == NULL 6357 || ahc_match_scb(ahc, scbp, target, channel, 6358 lun, tag, role) == 0) 6359 continue; 6360 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j)); 6361 } 6362 } 6363 6364 /* 6365 * Go through the disconnected list and remove any entries we 6366 * have queued for completion, 0'ing their control byte too. 6367 * We save the active SCB and restore it ourselves, so there 6368 * is no reason for this search to restore it too. 6369 */ 6370 ahc_search_disc_list(ahc, target, channel, lun, tag, 6371 /*stop_on_first*/FALSE, /*remove*/TRUE, 6372 /*save_state*/FALSE); 6373 } 6374 6375 /* 6376 * Go through the hardware SCB array looking for commands that 6377 * were active but not on any list. In some cases, these remnants 6378 * might not still have mappings in the scbindex array (e.g. unexpected 6379 * bus free with the same scb queued for an abort). Don't hold this 6380 * against them. 6381 */ 6382 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 6383 u_int scbid; 6384 6385 ahc_outb(ahc, SCBPTR, i); 6386 scbid = ahc_inb(ahc, SCB_TAG); 6387 scbp = ahc_lookup_scb(ahc, scbid); 6388 if ((scbp == NULL && scbid != SCB_LIST_NULL) 6389 || (scbp != NULL 6390 && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role))) 6391 ahc_add_curscb_to_free_list(ahc); 6392 } 6393 6394 /* 6395 * Go through the pending CCB list and look for 6396 * commands for this target that are still active. 6397 * These are other tagged commands that were 6398 * disconnected when the reset occurred. 6399 */ 6400 scbp_next = LIST_FIRST(&ahc->pending_scbs); 6401 while (scbp_next != NULL) { 6402 scbp = scbp_next; 6403 scbp_next = LIST_NEXT(scbp, pending_links); 6404 if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) { 6405 cam_status ostat; 6406 6407 ostat = ahc_get_transaction_status(scbp); 6408 if (ostat == CAM_REQ_INPROG) 6409 ahc_set_transaction_status(scbp, status); 6410 if (ahc_get_transaction_status(scbp) != CAM_REQ_CMP) 6411 ahc_freeze_scb(scbp); 6412 if ((scbp->flags & SCB_ACTIVE) == 0) 6413 printk("Inactive SCB on pending list\n"); 6414 ahc_done(ahc, scbp); 6415 found++; 6416 } 6417 } 6418 ahc_outb(ahc, SCBPTR, active_scb); 6419 ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status); 6420 ahc_release_untagged_queues(ahc); 6421 return found; 6422 } 6423 6424 static void 6425 ahc_reset_current_bus(struct ahc_softc *ahc) 6426 { 6427 uint8_t scsiseq; 6428 6429 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST); 6430 scsiseq = ahc_inb(ahc, SCSISEQ); 6431 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO); 6432 ahc_flush_device_writes(ahc); 6433 ahc_delay(AHC_BUSRESET_DELAY); 6434 /* Turn off the bus reset */ 6435 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO); 6436 6437 ahc_clear_intstat(ahc); 6438 6439 /* Re-enable reset interrupts */ 6440 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST); 6441 } 6442 6443 int 6444 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) 6445 { 6446 struct ahc_devinfo devinfo; 6447 u_int initiator, target, max_scsiid; 6448 u_int sblkctl; 6449 u_int scsiseq; 6450 u_int simode1; 6451 int found; 6452 int restart_needed; 6453 char cur_channel; 6454 6455 ahc->pending_device = NULL; 6456 6457 ahc_compile_devinfo(&devinfo, 6458 CAM_TARGET_WILDCARD, 6459 CAM_TARGET_WILDCARD, 6460 CAM_LUN_WILDCARD, 6461 channel, ROLE_UNKNOWN); 6462 ahc_pause(ahc); 6463 6464 /* Make sure the sequencer is in a safe location. */ 6465 ahc_clear_critical_section(ahc); 6466 6467 /* 6468 * Run our command complete fifos to ensure that we perform 6469 * completion processing on any commands that 'completed' 6470 * before the reset occurred. 6471 */ 6472 ahc_run_qoutfifo(ahc); 6473 #ifdef AHC_TARGET_MODE 6474 /* 6475 * XXX - In Twin mode, the tqinfifo may have commands 6476 * for an unaffected channel in it. However, if 6477 * we have run out of ATIO resources to drain that 6478 * queue, we may not get them all out here. Further, 6479 * the blocked transactions for the reset channel 6480 * should just be killed off, irrespecitve of whether 6481 * we are blocked on ATIO resources. Write a routine 6482 * to compact the tqinfifo appropriately. 6483 */ 6484 if ((ahc->flags & AHC_TARGETROLE) != 0) { 6485 ahc_run_tqinfifo(ahc, /*paused*/TRUE); 6486 } 6487 #endif 6488 6489 /* 6490 * Reset the bus if we are initiating this reset 6491 */ 6492 sblkctl = ahc_inb(ahc, SBLKCTL); 6493 cur_channel = 'A'; 6494 if ((ahc->features & AHC_TWIN) != 0 6495 && ((sblkctl & SELBUSB) != 0)) 6496 cur_channel = 'B'; 6497 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 6498 if (cur_channel != channel) { 6499 /* Case 1: Command for another bus is active 6500 * Stealthily reset the other bus without 6501 * upsetting the current bus. 6502 */ 6503 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB); 6504 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST); 6505 #ifdef AHC_TARGET_MODE 6506 /* 6507 * Bus resets clear ENSELI, so we cannot 6508 * defer re-enabling bus reset interrupts 6509 * if we are in target mode. 6510 */ 6511 if ((ahc->flags & AHC_TARGETROLE) != 0) 6512 simode1 |= ENSCSIRST; 6513 #endif 6514 ahc_outb(ahc, SIMODE1, simode1); 6515 if (initiate_reset) 6516 ahc_reset_current_bus(ahc); 6517 ahc_clear_intstat(ahc); 6518 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP)); 6519 ahc_outb(ahc, SBLKCTL, sblkctl); 6520 restart_needed = FALSE; 6521 } else { 6522 /* Case 2: A command from this bus is active or we're idle */ 6523 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST); 6524 #ifdef AHC_TARGET_MODE 6525 /* 6526 * Bus resets clear ENSELI, so we cannot 6527 * defer re-enabling bus reset interrupts 6528 * if we are in target mode. 6529 */ 6530 if ((ahc->flags & AHC_TARGETROLE) != 0) 6531 simode1 |= ENSCSIRST; 6532 #endif 6533 ahc_outb(ahc, SIMODE1, simode1); 6534 if (initiate_reset) 6535 ahc_reset_current_bus(ahc); 6536 ahc_clear_intstat(ahc); 6537 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP)); 6538 restart_needed = TRUE; 6539 } 6540 6541 /* 6542 * Clean up all the state information for the 6543 * pending transactions on this bus. 6544 */ 6545 found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel, 6546 CAM_LUN_WILDCARD, SCB_LIST_NULL, 6547 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET); 6548 6549 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7; 6550 6551 #ifdef AHC_TARGET_MODE 6552 /* 6553 * Send an immediate notify ccb to all target more peripheral 6554 * drivers affected by this action. 6555 */ 6556 for (target = 0; target <= max_scsiid; target++) { 6557 struct ahc_tmode_tstate* tstate; 6558 u_int lun; 6559 6560 tstate = ahc->enabled_targets[target]; 6561 if (tstate == NULL) 6562 continue; 6563 for (lun = 0; lun < AHC_NUM_LUNS; lun++) { 6564 struct ahc_tmode_lstate* lstate; 6565 6566 lstate = tstate->enabled_luns[lun]; 6567 if (lstate == NULL) 6568 continue; 6569 6570 ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD, 6571 EVENT_TYPE_BUS_RESET, /*arg*/0); 6572 ahc_send_lstate_events(ahc, lstate); 6573 } 6574 } 6575 #endif 6576 /* Notify the XPT that a bus reset occurred */ 6577 ahc_send_async(ahc, devinfo.channel, CAM_TARGET_WILDCARD, 6578 CAM_LUN_WILDCARD, AC_BUS_RESET); 6579 6580 /* 6581 * Revert to async/narrow transfers until we renegotiate. 6582 */ 6583 for (target = 0; target <= max_scsiid; target++) { 6584 6585 if (ahc->enabled_targets[target] == NULL) 6586 continue; 6587 for (initiator = 0; initiator <= max_scsiid; initiator++) { 6588 struct ahc_devinfo devinfo; 6589 6590 ahc_compile_devinfo(&devinfo, target, initiator, 6591 CAM_LUN_WILDCARD, 6592 channel, ROLE_UNKNOWN); 6593 ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 6594 AHC_TRANS_CUR, /*paused*/TRUE); 6595 ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL, 6596 /*period*/0, /*offset*/0, 6597 /*ppr_options*/0, AHC_TRANS_CUR, 6598 /*paused*/TRUE); 6599 } 6600 } 6601 6602 if (restart_needed) 6603 ahc_restart(ahc); 6604 else 6605 ahc_unpause(ahc); 6606 return found; 6607 } 6608 6609 6610 /***************************** Residual Processing ****************************/ 6611 /* 6612 * Calculate the residual for a just completed SCB. 6613 */ 6614 static void 6615 ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb) 6616 { 6617 struct hardware_scb *hscb; 6618 struct status_pkt *spkt; 6619 uint32_t sgptr; 6620 uint32_t resid_sgptr; 6621 uint32_t resid; 6622 6623 /* 6624 * 5 cases. 6625 * 1) No residual. 6626 * SG_RESID_VALID clear in sgptr. 6627 * 2) Transferless command 6628 * 3) Never performed any transfers. 6629 * sgptr has SG_FULL_RESID set. 6630 * 4) No residual but target did not 6631 * save data pointers after the 6632 * last transfer, so sgptr was 6633 * never updated. 6634 * 5) We have a partial residual. 6635 * Use residual_sgptr to determine 6636 * where we are. 6637 */ 6638 6639 hscb = scb->hscb; 6640 sgptr = ahc_le32toh(hscb->sgptr); 6641 if ((sgptr & SG_RESID_VALID) == 0) 6642 /* Case 1 */ 6643 return; 6644 sgptr &= ~SG_RESID_VALID; 6645 6646 if ((sgptr & SG_LIST_NULL) != 0) 6647 /* Case 2 */ 6648 return; 6649 6650 spkt = &hscb->shared_data.status; 6651 resid_sgptr = ahc_le32toh(spkt->residual_sg_ptr); 6652 if ((sgptr & SG_FULL_RESID) != 0) { 6653 /* Case 3 */ 6654 resid = ahc_get_transfer_length(scb); 6655 } else if ((resid_sgptr & SG_LIST_NULL) != 0) { 6656 /* Case 4 */ 6657 return; 6658 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) { 6659 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr); 6660 } else { 6661 struct ahc_dma_seg *sg; 6662 6663 /* 6664 * Remainder of the SG where the transfer 6665 * stopped. 6666 */ 6667 resid = ahc_le32toh(spkt->residual_datacnt) & AHC_SG_LEN_MASK; 6668 sg = ahc_sg_bus_to_virt(scb, resid_sgptr & SG_PTR_MASK); 6669 6670 /* The residual sg_ptr always points to the next sg */ 6671 sg--; 6672 6673 /* 6674 * Add up the contents of all residual 6675 * SG segments that are after the SG where 6676 * the transfer stopped. 6677 */ 6678 while ((ahc_le32toh(sg->len) & AHC_DMA_LAST_SEG) == 0) { 6679 sg++; 6680 resid += ahc_le32toh(sg->len) & AHC_SG_LEN_MASK; 6681 } 6682 } 6683 if ((scb->flags & SCB_SENSE) == 0) 6684 ahc_set_residual(scb, resid); 6685 else 6686 ahc_set_sense_residual(scb, resid); 6687 6688 #ifdef AHC_DEBUG 6689 if ((ahc_debug & AHC_SHOW_MISC) != 0) { 6690 ahc_print_path(ahc, scb); 6691 printk("Handled %sResidual of %d bytes\n", 6692 (scb->flags & SCB_SENSE) ? "Sense " : "", resid); 6693 } 6694 #endif 6695 } 6696 6697 /******************************* Target Mode **********************************/ 6698 #ifdef AHC_TARGET_MODE 6699 /* 6700 * Add a target mode event to this lun's queue 6701 */ 6702 static void 6703 ahc_queue_lstate_event(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate, 6704 u_int initiator_id, u_int event_type, u_int event_arg) 6705 { 6706 struct ahc_tmode_event *event; 6707 int pending; 6708 6709 xpt_freeze_devq(lstate->path, /*count*/1); 6710 if (lstate->event_w_idx >= lstate->event_r_idx) 6711 pending = lstate->event_w_idx - lstate->event_r_idx; 6712 else 6713 pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1 6714 - (lstate->event_r_idx - lstate->event_w_idx); 6715 6716 if (event_type == EVENT_TYPE_BUS_RESET 6717 || event_type == MSG_BUS_DEV_RESET) { 6718 /* 6719 * Any earlier events are irrelevant, so reset our buffer. 6720 * This has the effect of allowing us to deal with reset 6721 * floods (an external device holding down the reset line) 6722 * without losing the event that is really interesting. 6723 */ 6724 lstate->event_r_idx = 0; 6725 lstate->event_w_idx = 0; 6726 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE); 6727 } 6728 6729 if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) { 6730 xpt_print_path(lstate->path); 6731 printk("immediate event %x:%x lost\n", 6732 lstate->event_buffer[lstate->event_r_idx].event_type, 6733 lstate->event_buffer[lstate->event_r_idx].event_arg); 6734 lstate->event_r_idx++; 6735 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6736 lstate->event_r_idx = 0; 6737 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE); 6738 } 6739 6740 event = &lstate->event_buffer[lstate->event_w_idx]; 6741 event->initiator_id = initiator_id; 6742 event->event_type = event_type; 6743 event->event_arg = event_arg; 6744 lstate->event_w_idx++; 6745 if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6746 lstate->event_w_idx = 0; 6747 } 6748 6749 /* 6750 * Send any target mode events queued up waiting 6751 * for immediate notify resources. 6752 */ 6753 void 6754 ahc_send_lstate_events(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate) 6755 { 6756 struct ccb_hdr *ccbh; 6757 struct ccb_immed_notify *inot; 6758 6759 while (lstate->event_r_idx != lstate->event_w_idx 6760 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) { 6761 struct ahc_tmode_event *event; 6762 6763 event = &lstate->event_buffer[lstate->event_r_idx]; 6764 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle); 6765 inot = (struct ccb_immed_notify *)ccbh; 6766 switch (event->event_type) { 6767 case EVENT_TYPE_BUS_RESET: 6768 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN; 6769 break; 6770 default: 6771 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN; 6772 inot->message_args[0] = event->event_type; 6773 inot->message_args[1] = event->event_arg; 6774 break; 6775 } 6776 inot->initiator_id = event->initiator_id; 6777 inot->sense_len = 0; 6778 xpt_done((union ccb *)inot); 6779 lstate->event_r_idx++; 6780 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6781 lstate->event_r_idx = 0; 6782 } 6783 } 6784 #endif 6785 6786 /******************** Sequencer Program Patching/Download *********************/ 6787 6788 #ifdef AHC_DUMP_SEQ 6789 void 6790 ahc_dumpseq(struct ahc_softc* ahc) 6791 { 6792 int i; 6793 6794 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 6795 ahc_outb(ahc, SEQADDR0, 0); 6796 ahc_outb(ahc, SEQADDR1, 0); 6797 for (i = 0; i < ahc->instruction_ram_size; i++) { 6798 uint8_t ins_bytes[4]; 6799 6800 ahc_insb(ahc, SEQRAM, ins_bytes, 4); 6801 printk("0x%08x\n", ins_bytes[0] << 24 6802 | ins_bytes[1] << 16 6803 | ins_bytes[2] << 8 6804 | ins_bytes[3]); 6805 } 6806 } 6807 #endif 6808 6809 static int 6810 ahc_loadseq(struct ahc_softc *ahc) 6811 { 6812 struct cs cs_table[NUM_CRITICAL_SECTIONS]; 6813 u_int begin_set[NUM_CRITICAL_SECTIONS]; 6814 u_int end_set[NUM_CRITICAL_SECTIONS]; 6815 const struct patch *cur_patch; 6816 u_int cs_count; 6817 u_int cur_cs; 6818 u_int i; 6819 u_int skip_addr; 6820 u_int sg_prefetch_cnt; 6821 int downloaded; 6822 uint8_t download_consts[7]; 6823 6824 /* 6825 * Start out with 0 critical sections 6826 * that apply to this firmware load. 6827 */ 6828 cs_count = 0; 6829 cur_cs = 0; 6830 memset(begin_set, 0, sizeof(begin_set)); 6831 memset(end_set, 0, sizeof(end_set)); 6832 6833 /* Setup downloadable constant table */ 6834 download_consts[QOUTFIFO_OFFSET] = 0; 6835 if (ahc->targetcmds != NULL) 6836 download_consts[QOUTFIFO_OFFSET] += 32; 6837 download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1; 6838 download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1; 6839 download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1); 6840 sg_prefetch_cnt = ahc->pci_cachesize; 6841 if (sg_prefetch_cnt < (2 * sizeof(struct ahc_dma_seg))) 6842 sg_prefetch_cnt = 2 * sizeof(struct ahc_dma_seg); 6843 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt; 6844 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_cnt - 1); 6845 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_cnt - 1); 6846 6847 cur_patch = patches; 6848 downloaded = 0; 6849 skip_addr = 0; 6850 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 6851 ahc_outb(ahc, SEQADDR0, 0); 6852 ahc_outb(ahc, SEQADDR1, 0); 6853 6854 for (i = 0; i < sizeof(seqprog)/4; i++) { 6855 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { 6856 /* 6857 * Don't download this instruction as it 6858 * is in a patch that was removed. 6859 */ 6860 continue; 6861 } 6862 6863 if (downloaded == ahc->instruction_ram_size) { 6864 /* 6865 * We're about to exceed the instruction 6866 * storage capacity for this chip. Fail 6867 * the load. 6868 */ 6869 printk("\n%s: Program too large for instruction memory " 6870 "size of %d!\n", ahc_name(ahc), 6871 ahc->instruction_ram_size); 6872 return (ENOMEM); 6873 } 6874 6875 /* 6876 * Move through the CS table until we find a CS 6877 * that might apply to this instruction. 6878 */ 6879 for (; cur_cs < NUM_CRITICAL_SECTIONS; cur_cs++) { 6880 if (critical_sections[cur_cs].end <= i) { 6881 if (begin_set[cs_count] == TRUE 6882 && end_set[cs_count] == FALSE) { 6883 cs_table[cs_count].end = downloaded; 6884 end_set[cs_count] = TRUE; 6885 cs_count++; 6886 } 6887 continue; 6888 } 6889 if (critical_sections[cur_cs].begin <= i 6890 && begin_set[cs_count] == FALSE) { 6891 cs_table[cs_count].begin = downloaded; 6892 begin_set[cs_count] = TRUE; 6893 } 6894 break; 6895 } 6896 ahc_download_instr(ahc, i, download_consts); 6897 downloaded++; 6898 } 6899 6900 ahc->num_critical_sections = cs_count; 6901 if (cs_count != 0) { 6902 6903 cs_count *= sizeof(struct cs); 6904 ahc->critical_sections = kmalloc(cs_count, GFP_ATOMIC); 6905 if (ahc->critical_sections == NULL) 6906 panic("ahc_loadseq: Could not malloc"); 6907 memcpy(ahc->critical_sections, cs_table, cs_count); 6908 } 6909 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); 6910 6911 if (bootverbose) { 6912 printk(" %d instructions downloaded\n", downloaded); 6913 printk("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n", 6914 ahc_name(ahc), ahc->features, ahc->bugs, ahc->flags); 6915 } 6916 return (0); 6917 } 6918 6919 static int 6920 ahc_check_patch(struct ahc_softc *ahc, const struct patch **start_patch, 6921 u_int start_instr, u_int *skip_addr) 6922 { 6923 const struct patch *cur_patch; 6924 const struct patch *last_patch; 6925 u_int num_patches; 6926 6927 num_patches = ARRAY_SIZE(patches); 6928 last_patch = &patches[num_patches]; 6929 cur_patch = *start_patch; 6930 6931 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 6932 6933 if (cur_patch->patch_func(ahc) == 0) { 6934 6935 /* Start rejecting code */ 6936 *skip_addr = start_instr + cur_patch->skip_instr; 6937 cur_patch += cur_patch->skip_patch; 6938 } else { 6939 /* Accepted this patch. Advance to the next 6940 * one and wait for our intruction pointer to 6941 * hit this point. 6942 */ 6943 cur_patch++; 6944 } 6945 } 6946 6947 *start_patch = cur_patch; 6948 if (start_instr < *skip_addr) 6949 /* Still skipping */ 6950 return (0); 6951 6952 return (1); 6953 } 6954 6955 static void 6956 ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts) 6957 { 6958 union ins_formats instr; 6959 struct ins_format1 *fmt1_ins; 6960 struct ins_format3 *fmt3_ins; 6961 u_int opcode; 6962 6963 /* 6964 * The firmware is always compiled into a little endian format. 6965 */ 6966 instr.integer = ahc_le32toh(*(uint32_t*)&seqprog[instrptr * 4]); 6967 6968 fmt1_ins = &instr.format1; 6969 fmt3_ins = NULL; 6970 6971 /* Pull the opcode */ 6972 opcode = instr.format1.opcode; 6973 switch (opcode) { 6974 case AIC_OP_JMP: 6975 case AIC_OP_JC: 6976 case AIC_OP_JNC: 6977 case AIC_OP_CALL: 6978 case AIC_OP_JNE: 6979 case AIC_OP_JNZ: 6980 case AIC_OP_JE: 6981 case AIC_OP_JZ: 6982 { 6983 const struct patch *cur_patch; 6984 int address_offset; 6985 u_int address; 6986 u_int skip_addr; 6987 u_int i; 6988 6989 fmt3_ins = &instr.format3; 6990 address_offset = 0; 6991 address = fmt3_ins->address; 6992 cur_patch = patches; 6993 skip_addr = 0; 6994 6995 for (i = 0; i < address;) { 6996 6997 ahc_check_patch(ahc, &cur_patch, i, &skip_addr); 6998 6999 if (skip_addr > i) { 7000 int end_addr; 7001 7002 end_addr = min(address, skip_addr); 7003 address_offset += end_addr - i; 7004 i = skip_addr; 7005 } else { 7006 i++; 7007 } 7008 } 7009 address -= address_offset; 7010 fmt3_ins->address = address; 7011 /* FALLTHROUGH */ 7012 } 7013 case AIC_OP_OR: 7014 case AIC_OP_AND: 7015 case AIC_OP_XOR: 7016 case AIC_OP_ADD: 7017 case AIC_OP_ADC: 7018 case AIC_OP_BMOV: 7019 if (fmt1_ins->parity != 0) { 7020 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 7021 } 7022 fmt1_ins->parity = 0; 7023 if ((ahc->features & AHC_CMD_CHAN) == 0 7024 && opcode == AIC_OP_BMOV) { 7025 /* 7026 * Block move was added at the same time 7027 * as the command channel. Verify that 7028 * this is only a move of a single element 7029 * and convert the BMOV to a MOV 7030 * (AND with an immediate of FF). 7031 */ 7032 if (fmt1_ins->immediate != 1) 7033 panic("%s: BMOV not supported\n", 7034 ahc_name(ahc)); 7035 fmt1_ins->opcode = AIC_OP_AND; 7036 fmt1_ins->immediate = 0xff; 7037 } 7038 /* FALLTHROUGH */ 7039 case AIC_OP_ROL: 7040 if ((ahc->features & AHC_ULTRA2) != 0) { 7041 int i, count; 7042 7043 /* Calculate odd parity for the instruction */ 7044 for (i = 0, count = 0; i < 31; i++) { 7045 uint32_t mask; 7046 7047 mask = 0x01 << i; 7048 if ((instr.integer & mask) != 0) 7049 count++; 7050 } 7051 if ((count & 0x01) == 0) 7052 instr.format1.parity = 1; 7053 } else { 7054 /* Compress the instruction for older sequencers */ 7055 if (fmt3_ins != NULL) { 7056 instr.integer = 7057 fmt3_ins->immediate 7058 | (fmt3_ins->source << 8) 7059 | (fmt3_ins->address << 16) 7060 | (fmt3_ins->opcode << 25); 7061 } else { 7062 instr.integer = 7063 fmt1_ins->immediate 7064 | (fmt1_ins->source << 8) 7065 | (fmt1_ins->destination << 16) 7066 | (fmt1_ins->ret << 24) 7067 | (fmt1_ins->opcode << 25); 7068 } 7069 } 7070 /* The sequencer is a little endian cpu */ 7071 instr.integer = ahc_htole32(instr.integer); 7072 ahc_outsb(ahc, SEQRAM, instr.bytes, 4); 7073 break; 7074 default: 7075 panic("Unknown opcode encountered in seq program"); 7076 break; 7077 } 7078 } 7079 7080 int 7081 ahc_print_register(const ahc_reg_parse_entry_t *table, u_int num_entries, 7082 const char *name, u_int address, u_int value, 7083 u_int *cur_column, u_int wrap_point) 7084 { 7085 int printed; 7086 u_int printed_mask; 7087 7088 if (cur_column != NULL && *cur_column >= wrap_point) { 7089 printk("\n"); 7090 *cur_column = 0; 7091 } 7092 printed = printk("%s[0x%x]", name, value); 7093 if (table == NULL) { 7094 printed += printk(" "); 7095 *cur_column += printed; 7096 return (printed); 7097 } 7098 printed_mask = 0; 7099 while (printed_mask != 0xFF) { 7100 int entry; 7101 7102 for (entry = 0; entry < num_entries; entry++) { 7103 if (((value & table[entry].mask) 7104 != table[entry].value) 7105 || ((printed_mask & table[entry].mask) 7106 == table[entry].mask)) 7107 continue; 7108 7109 printed += printk("%s%s", 7110 printed_mask == 0 ? ":(" : "|", 7111 table[entry].name); 7112 printed_mask |= table[entry].mask; 7113 7114 break; 7115 } 7116 if (entry >= num_entries) 7117 break; 7118 } 7119 if (printed_mask != 0) 7120 printed += printk(") "); 7121 else 7122 printed += printk(" "); 7123 if (cur_column != NULL) 7124 *cur_column += printed; 7125 return (printed); 7126 } 7127 7128 void 7129 ahc_dump_card_state(struct ahc_softc *ahc) 7130 { 7131 struct scb *scb; 7132 struct scb_tailq *untagged_q; 7133 u_int cur_col; 7134 int paused; 7135 int target; 7136 int maxtarget; 7137 int i; 7138 uint8_t last_phase; 7139 uint8_t qinpos; 7140 uint8_t qintail; 7141 uint8_t qoutpos; 7142 uint8_t scb_index; 7143 uint8_t saved_scbptr; 7144 7145 if (ahc_is_paused(ahc)) { 7146 paused = 1; 7147 } else { 7148 paused = 0; 7149 ahc_pause(ahc); 7150 } 7151 7152 saved_scbptr = ahc_inb(ahc, SCBPTR); 7153 last_phase = ahc_inb(ahc, LASTPHASE); 7154 printk(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n" 7155 "%s: Dumping Card State %s, at SEQADDR 0x%x\n", 7156 ahc_name(ahc), ahc_lookup_phase_entry(last_phase)->phasemsg, 7157 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 7158 if (paused) 7159 printk("Card was paused\n"); 7160 printk("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n", 7161 ahc_inb(ahc, ACCUM), ahc_inb(ahc, SINDEX), ahc_inb(ahc, DINDEX), 7162 ahc_inb(ahc, ARG_2)); 7163 printk("HCNT = 0x%x SCBPTR = 0x%x\n", ahc_inb(ahc, HCNT), 7164 ahc_inb(ahc, SCBPTR)); 7165 cur_col = 0; 7166 if ((ahc->features & AHC_DT) != 0) 7167 ahc_scsiphase_print(ahc_inb(ahc, SCSIPHASE), &cur_col, 50); 7168 ahc_scsisigi_print(ahc_inb(ahc, SCSISIGI), &cur_col, 50); 7169 ahc_error_print(ahc_inb(ahc, ERROR), &cur_col, 50); 7170 ahc_scsibusl_print(ahc_inb(ahc, SCSIBUSL), &cur_col, 50); 7171 ahc_lastphase_print(ahc_inb(ahc, LASTPHASE), &cur_col, 50); 7172 ahc_scsiseq_print(ahc_inb(ahc, SCSISEQ), &cur_col, 50); 7173 ahc_sblkctl_print(ahc_inb(ahc, SBLKCTL), &cur_col, 50); 7174 ahc_scsirate_print(ahc_inb(ahc, SCSIRATE), &cur_col, 50); 7175 ahc_seqctl_print(ahc_inb(ahc, SEQCTL), &cur_col, 50); 7176 ahc_seq_flags_print(ahc_inb(ahc, SEQ_FLAGS), &cur_col, 50); 7177 ahc_sstat0_print(ahc_inb(ahc, SSTAT0), &cur_col, 50); 7178 ahc_sstat1_print(ahc_inb(ahc, SSTAT1), &cur_col, 50); 7179 ahc_sstat2_print(ahc_inb(ahc, SSTAT2), &cur_col, 50); 7180 ahc_sstat3_print(ahc_inb(ahc, SSTAT3), &cur_col, 50); 7181 ahc_simode0_print(ahc_inb(ahc, SIMODE0), &cur_col, 50); 7182 ahc_simode1_print(ahc_inb(ahc, SIMODE1), &cur_col, 50); 7183 ahc_sxfrctl0_print(ahc_inb(ahc, SXFRCTL0), &cur_col, 50); 7184 ahc_dfcntrl_print(ahc_inb(ahc, DFCNTRL), &cur_col, 50); 7185 ahc_dfstatus_print(ahc_inb(ahc, DFSTATUS), &cur_col, 50); 7186 if (cur_col != 0) 7187 printk("\n"); 7188 printk("STACK:"); 7189 for (i = 0; i < STACK_SIZE; i++) 7190 printk(" 0x%x", ahc_inb(ahc, STACK)|(ahc_inb(ahc, STACK) << 8)); 7191 printk("\nSCB count = %d\n", ahc->scb_data->numscbs); 7192 printk("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag); 7193 printk("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB)); 7194 /* QINFIFO */ 7195 printk("QINFIFO entries: "); 7196 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 7197 qinpos = ahc_inb(ahc, SNSCB_QOFF); 7198 ahc_outb(ahc, SNSCB_QOFF, qinpos); 7199 } else 7200 qinpos = ahc_inb(ahc, QINPOS); 7201 qintail = ahc->qinfifonext; 7202 while (qinpos != qintail) { 7203 printk("%d ", ahc->qinfifo[qinpos]); 7204 qinpos++; 7205 } 7206 printk("\n"); 7207 7208 printk("Waiting Queue entries: "); 7209 scb_index = ahc_inb(ahc, WAITING_SCBH); 7210 i = 0; 7211 while (scb_index != SCB_LIST_NULL && i++ < 256) { 7212 ahc_outb(ahc, SCBPTR, scb_index); 7213 printk("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG)); 7214 scb_index = ahc_inb(ahc, SCB_NEXT); 7215 } 7216 printk("\n"); 7217 7218 printk("Disconnected Queue entries: "); 7219 scb_index = ahc_inb(ahc, DISCONNECTED_SCBH); 7220 i = 0; 7221 while (scb_index != SCB_LIST_NULL && i++ < 256) { 7222 ahc_outb(ahc, SCBPTR, scb_index); 7223 printk("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG)); 7224 scb_index = ahc_inb(ahc, SCB_NEXT); 7225 } 7226 printk("\n"); 7227 7228 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD); 7229 printk("QOUTFIFO entries: "); 7230 qoutpos = ahc->qoutfifonext; 7231 i = 0; 7232 while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) { 7233 printk("%d ", ahc->qoutfifo[qoutpos]); 7234 qoutpos++; 7235 } 7236 printk("\n"); 7237 7238 printk("Sequencer Free SCB List: "); 7239 scb_index = ahc_inb(ahc, FREE_SCBH); 7240 i = 0; 7241 while (scb_index != SCB_LIST_NULL && i++ < 256) { 7242 ahc_outb(ahc, SCBPTR, scb_index); 7243 printk("%d ", scb_index); 7244 scb_index = ahc_inb(ahc, SCB_NEXT); 7245 } 7246 printk("\n"); 7247 7248 printk("Sequencer SCB Info: "); 7249 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 7250 ahc_outb(ahc, SCBPTR, i); 7251 cur_col = printk("\n%3d ", i); 7252 7253 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), &cur_col, 60); 7254 ahc_scb_scsiid_print(ahc_inb(ahc, SCB_SCSIID), &cur_col, 60); 7255 ahc_scb_lun_print(ahc_inb(ahc, SCB_LUN), &cur_col, 60); 7256 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60); 7257 } 7258 printk("\n"); 7259 7260 printk("Pending list: "); 7261 i = 0; 7262 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) { 7263 if (i++ > 256) 7264 break; 7265 cur_col = printk("\n%3d ", scb->hscb->tag); 7266 ahc_scb_control_print(scb->hscb->control, &cur_col, 60); 7267 ahc_scb_scsiid_print(scb->hscb->scsiid, &cur_col, 60); 7268 ahc_scb_lun_print(scb->hscb->lun, &cur_col, 60); 7269 if ((ahc->flags & AHC_PAGESCBS) == 0) { 7270 ahc_outb(ahc, SCBPTR, scb->hscb->tag); 7271 printk("("); 7272 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), 7273 &cur_col, 60); 7274 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60); 7275 printk(")"); 7276 } 7277 } 7278 printk("\n"); 7279 7280 printk("Kernel Free SCB list: "); 7281 i = 0; 7282 SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) { 7283 if (i++ > 256) 7284 break; 7285 printk("%d ", scb->hscb->tag); 7286 } 7287 printk("\n"); 7288 7289 maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7; 7290 for (target = 0; target <= maxtarget; target++) { 7291 untagged_q = &ahc->untagged_queues[target]; 7292 if (TAILQ_FIRST(untagged_q) == NULL) 7293 continue; 7294 printk("Untagged Q(%d): ", target); 7295 i = 0; 7296 TAILQ_FOREACH(scb, untagged_q, links.tqe) { 7297 if (i++ > 256) 7298 break; 7299 printk("%d ", scb->hscb->tag); 7300 } 7301 printk("\n"); 7302 } 7303 7304 printk("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n"); 7305 ahc_outb(ahc, SCBPTR, saved_scbptr); 7306 if (paused == 0) 7307 ahc_unpause(ahc); 7308 } 7309 7310 /************************* Target Mode ****************************************/ 7311 #ifdef AHC_TARGET_MODE 7312 cam_status 7313 ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb, 7314 struct ahc_tmode_tstate **tstate, 7315 struct ahc_tmode_lstate **lstate, 7316 int notfound_failure) 7317 { 7318 7319 if ((ahc->features & AHC_TARGETMODE) == 0) 7320 return (CAM_REQ_INVALID); 7321 7322 /* 7323 * Handle the 'black hole' device that sucks up 7324 * requests to unattached luns on enabled targets. 7325 */ 7326 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD 7327 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) { 7328 *tstate = NULL; 7329 *lstate = ahc->black_hole; 7330 } else { 7331 u_int max_id; 7332 7333 max_id = (ahc->features & AHC_WIDE) ? 16 : 8; 7334 if (ccb->ccb_h.target_id >= max_id) 7335 return (CAM_TID_INVALID); 7336 7337 if (ccb->ccb_h.target_lun >= AHC_NUM_LUNS) 7338 return (CAM_LUN_INVALID); 7339 7340 *tstate = ahc->enabled_targets[ccb->ccb_h.target_id]; 7341 *lstate = NULL; 7342 if (*tstate != NULL) 7343 *lstate = 7344 (*tstate)->enabled_luns[ccb->ccb_h.target_lun]; 7345 } 7346 7347 if (notfound_failure != 0 && *lstate == NULL) 7348 return (CAM_PATH_INVALID); 7349 7350 return (CAM_REQ_CMP); 7351 } 7352 7353 void 7354 ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb) 7355 { 7356 struct ahc_tmode_tstate *tstate; 7357 struct ahc_tmode_lstate *lstate; 7358 struct ccb_en_lun *cel; 7359 cam_status status; 7360 u_long s; 7361 u_int target; 7362 u_int lun; 7363 u_int target_mask; 7364 u_int our_id; 7365 int error; 7366 char channel; 7367 7368 status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate, 7369 /*notfound_failure*/FALSE); 7370 7371 if (status != CAM_REQ_CMP) { 7372 ccb->ccb_h.status = status; 7373 return; 7374 } 7375 7376 if (cam_sim_bus(sim) == 0) 7377 our_id = ahc->our_id; 7378 else 7379 our_id = ahc->our_id_b; 7380 7381 if (ccb->ccb_h.target_id != our_id) { 7382 /* 7383 * our_id represents our initiator ID, or 7384 * the ID of the first target to have an 7385 * enabled lun in target mode. There are 7386 * two cases that may preclude enabling a 7387 * target id other than our_id. 7388 * 7389 * o our_id is for an active initiator role. 7390 * Since the hardware does not support 7391 * reselections to the initiator role at 7392 * anything other than our_id, and our_id 7393 * is used by the hardware to indicate the 7394 * ID to use for both select-out and 7395 * reselect-out operations, the only target 7396 * ID we can support in this mode is our_id. 7397 * 7398 * o The MULTARGID feature is not available and 7399 * a previous target mode ID has been enabled. 7400 */ 7401 if ((ahc->features & AHC_MULTIROLE) != 0) { 7402 7403 if ((ahc->features & AHC_MULTI_TID) != 0 7404 && (ahc->flags & AHC_INITIATORROLE) != 0) { 7405 /* 7406 * Only allow additional targets if 7407 * the initiator role is disabled. 7408 * The hardware cannot handle a re-select-in 7409 * on the initiator id during a re-select-out 7410 * on a different target id. 7411 */ 7412 status = CAM_TID_INVALID; 7413 } else if ((ahc->flags & AHC_INITIATORROLE) != 0 7414 || ahc->enabled_luns > 0) { 7415 /* 7416 * Only allow our target id to change 7417 * if the initiator role is not configured 7418 * and there are no enabled luns which 7419 * are attached to the currently registered 7420 * scsi id. 7421 */ 7422 status = CAM_TID_INVALID; 7423 } 7424 } else if ((ahc->features & AHC_MULTI_TID) == 0 7425 && ahc->enabled_luns > 0) { 7426 7427 status = CAM_TID_INVALID; 7428 } 7429 } 7430 7431 if (status != CAM_REQ_CMP) { 7432 ccb->ccb_h.status = status; 7433 return; 7434 } 7435 7436 /* 7437 * We now have an id that is valid. 7438 * If we aren't in target mode, switch modes. 7439 */ 7440 if ((ahc->flags & AHC_TARGETROLE) == 0 7441 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) { 7442 u_long s; 7443 ahc_flag saved_flags; 7444 7445 printk("Configuring Target Mode\n"); 7446 ahc_lock(ahc, &s); 7447 if (LIST_FIRST(&ahc->pending_scbs) != NULL) { 7448 ccb->ccb_h.status = CAM_BUSY; 7449 ahc_unlock(ahc, &s); 7450 return; 7451 } 7452 saved_flags = ahc->flags; 7453 ahc->flags |= AHC_TARGETROLE; 7454 if ((ahc->features & AHC_MULTIROLE) == 0) 7455 ahc->flags &= ~AHC_INITIATORROLE; 7456 ahc_pause(ahc); 7457 error = ahc_loadseq(ahc); 7458 if (error != 0) { 7459 /* 7460 * Restore original configuration and notify 7461 * the caller that we cannot support target mode. 7462 * Since the adapter started out in this 7463 * configuration, the firmware load will succeed, 7464 * so there is no point in checking ahc_loadseq's 7465 * return value. 7466 */ 7467 ahc->flags = saved_flags; 7468 (void)ahc_loadseq(ahc); 7469 ahc_restart(ahc); 7470 ahc_unlock(ahc, &s); 7471 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL; 7472 return; 7473 } 7474 ahc_restart(ahc); 7475 ahc_unlock(ahc, &s); 7476 } 7477 cel = &ccb->cel; 7478 target = ccb->ccb_h.target_id; 7479 lun = ccb->ccb_h.target_lun; 7480 channel = SIM_CHANNEL(ahc, sim); 7481 target_mask = 0x01 << target; 7482 if (channel == 'B') 7483 target_mask <<= 8; 7484 7485 if (cel->enable != 0) { 7486 u_int scsiseq; 7487 7488 /* Are we already enabled?? */ 7489 if (lstate != NULL) { 7490 xpt_print_path(ccb->ccb_h.path); 7491 printk("Lun already enabled\n"); 7492 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA; 7493 return; 7494 } 7495 7496 if (cel->grp6_len != 0 7497 || cel->grp7_len != 0) { 7498 /* 7499 * Don't (yet?) support vendor 7500 * specific commands. 7501 */ 7502 ccb->ccb_h.status = CAM_REQ_INVALID; 7503 printk("Non-zero Group Codes\n"); 7504 return; 7505 } 7506 7507 /* 7508 * Seems to be okay. 7509 * Setup our data structures. 7510 */ 7511 if (target != CAM_TARGET_WILDCARD && tstate == NULL) { 7512 tstate = ahc_alloc_tstate(ahc, target, channel); 7513 if (tstate == NULL) { 7514 xpt_print_path(ccb->ccb_h.path); 7515 printk("Couldn't allocate tstate\n"); 7516 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 7517 return; 7518 } 7519 } 7520 lstate = kzalloc(sizeof(*lstate), GFP_ATOMIC); 7521 if (lstate == NULL) { 7522 xpt_print_path(ccb->ccb_h.path); 7523 printk("Couldn't allocate lstate\n"); 7524 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 7525 return; 7526 } 7527 status = xpt_create_path(&lstate->path, /*periph*/NULL, 7528 xpt_path_path_id(ccb->ccb_h.path), 7529 xpt_path_target_id(ccb->ccb_h.path), 7530 xpt_path_lun_id(ccb->ccb_h.path)); 7531 if (status != CAM_REQ_CMP) { 7532 kfree(lstate); 7533 xpt_print_path(ccb->ccb_h.path); 7534 printk("Couldn't allocate path\n"); 7535 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 7536 return; 7537 } 7538 SLIST_INIT(&lstate->accept_tios); 7539 SLIST_INIT(&lstate->immed_notifies); 7540 ahc_lock(ahc, &s); 7541 ahc_pause(ahc); 7542 if (target != CAM_TARGET_WILDCARD) { 7543 tstate->enabled_luns[lun] = lstate; 7544 ahc->enabled_luns++; 7545 7546 if ((ahc->features & AHC_MULTI_TID) != 0) { 7547 u_int targid_mask; 7548 7549 targid_mask = ahc_inb(ahc, TARGID) 7550 | (ahc_inb(ahc, TARGID + 1) << 8); 7551 7552 targid_mask |= target_mask; 7553 ahc_outb(ahc, TARGID, targid_mask); 7554 ahc_outb(ahc, TARGID+1, (targid_mask >> 8)); 7555 7556 ahc_update_scsiid(ahc, targid_mask); 7557 } else { 7558 u_int our_id; 7559 char channel; 7560 7561 channel = SIM_CHANNEL(ahc, sim); 7562 our_id = SIM_SCSI_ID(ahc, sim); 7563 7564 /* 7565 * This can only happen if selections 7566 * are not enabled 7567 */ 7568 if (target != our_id) { 7569 u_int sblkctl; 7570 char cur_channel; 7571 int swap; 7572 7573 sblkctl = ahc_inb(ahc, SBLKCTL); 7574 cur_channel = (sblkctl & SELBUSB) 7575 ? 'B' : 'A'; 7576 if ((ahc->features & AHC_TWIN) == 0) 7577 cur_channel = 'A'; 7578 swap = cur_channel != channel; 7579 if (channel == 'A') 7580 ahc->our_id = target; 7581 else 7582 ahc->our_id_b = target; 7583 7584 if (swap) 7585 ahc_outb(ahc, SBLKCTL, 7586 sblkctl ^ SELBUSB); 7587 7588 ahc_outb(ahc, SCSIID, target); 7589 7590 if (swap) 7591 ahc_outb(ahc, SBLKCTL, sblkctl); 7592 } 7593 } 7594 } else 7595 ahc->black_hole = lstate; 7596 /* Allow select-in operations */ 7597 if (ahc->black_hole != NULL && ahc->enabled_luns > 0) { 7598 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 7599 scsiseq |= ENSELI; 7600 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq); 7601 scsiseq = ahc_inb(ahc, SCSISEQ); 7602 scsiseq |= ENSELI; 7603 ahc_outb(ahc, SCSISEQ, scsiseq); 7604 } 7605 ahc_unpause(ahc); 7606 ahc_unlock(ahc, &s); 7607 ccb->ccb_h.status = CAM_REQ_CMP; 7608 xpt_print_path(ccb->ccb_h.path); 7609 printk("Lun now enabled for target mode\n"); 7610 } else { 7611 struct scb *scb; 7612 int i, empty; 7613 7614 if (lstate == NULL) { 7615 ccb->ccb_h.status = CAM_LUN_INVALID; 7616 return; 7617 } 7618 7619 ahc_lock(ahc, &s); 7620 7621 ccb->ccb_h.status = CAM_REQ_CMP; 7622 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) { 7623 struct ccb_hdr *ccbh; 7624 7625 ccbh = &scb->io_ctx->ccb_h; 7626 if (ccbh->func_code == XPT_CONT_TARGET_IO 7627 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){ 7628 printk("CTIO pending\n"); 7629 ccb->ccb_h.status = CAM_REQ_INVALID; 7630 ahc_unlock(ahc, &s); 7631 return; 7632 } 7633 } 7634 7635 if (SLIST_FIRST(&lstate->accept_tios) != NULL) { 7636 printk("ATIOs pending\n"); 7637 ccb->ccb_h.status = CAM_REQ_INVALID; 7638 } 7639 7640 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) { 7641 printk("INOTs pending\n"); 7642 ccb->ccb_h.status = CAM_REQ_INVALID; 7643 } 7644 7645 if (ccb->ccb_h.status != CAM_REQ_CMP) { 7646 ahc_unlock(ahc, &s); 7647 return; 7648 } 7649 7650 xpt_print_path(ccb->ccb_h.path); 7651 printk("Target mode disabled\n"); 7652 xpt_free_path(lstate->path); 7653 kfree(lstate); 7654 7655 ahc_pause(ahc); 7656 /* Can we clean up the target too? */ 7657 if (target != CAM_TARGET_WILDCARD) { 7658 tstate->enabled_luns[lun] = NULL; 7659 ahc->enabled_luns--; 7660 for (empty = 1, i = 0; i < 8; i++) 7661 if (tstate->enabled_luns[i] != NULL) { 7662 empty = 0; 7663 break; 7664 } 7665 7666 if (empty) { 7667 ahc_free_tstate(ahc, target, channel, 7668 /*force*/FALSE); 7669 if (ahc->features & AHC_MULTI_TID) { 7670 u_int targid_mask; 7671 7672 targid_mask = ahc_inb(ahc, TARGID) 7673 | (ahc_inb(ahc, TARGID + 1) 7674 << 8); 7675 7676 targid_mask &= ~target_mask; 7677 ahc_outb(ahc, TARGID, targid_mask); 7678 ahc_outb(ahc, TARGID+1, 7679 (targid_mask >> 8)); 7680 ahc_update_scsiid(ahc, targid_mask); 7681 } 7682 } 7683 } else { 7684 7685 ahc->black_hole = NULL; 7686 7687 /* 7688 * We can't allow selections without 7689 * our black hole device. 7690 */ 7691 empty = TRUE; 7692 } 7693 if (ahc->enabled_luns == 0) { 7694 /* Disallow select-in */ 7695 u_int scsiseq; 7696 7697 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 7698 scsiseq &= ~ENSELI; 7699 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq); 7700 scsiseq = ahc_inb(ahc, SCSISEQ); 7701 scsiseq &= ~ENSELI; 7702 ahc_outb(ahc, SCSISEQ, scsiseq); 7703 7704 if ((ahc->features & AHC_MULTIROLE) == 0) { 7705 printk("Configuring Initiator Mode\n"); 7706 ahc->flags &= ~AHC_TARGETROLE; 7707 ahc->flags |= AHC_INITIATORROLE; 7708 /* 7709 * Returning to a configuration that 7710 * fit previously will always succeed. 7711 */ 7712 (void)ahc_loadseq(ahc); 7713 ahc_restart(ahc); 7714 /* 7715 * Unpaused. The extra unpause 7716 * that follows is harmless. 7717 */ 7718 } 7719 } 7720 ahc_unpause(ahc); 7721 ahc_unlock(ahc, &s); 7722 } 7723 } 7724 7725 static void 7726 ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask) 7727 { 7728 u_int scsiid_mask; 7729 u_int scsiid; 7730 7731 if ((ahc->features & AHC_MULTI_TID) == 0) 7732 panic("ahc_update_scsiid called on non-multitid unit\n"); 7733 7734 /* 7735 * Since we will rely on the TARGID mask 7736 * for selection enables, ensure that OID 7737 * in SCSIID is not set to some other ID 7738 * that we don't want to allow selections on. 7739 */ 7740 if ((ahc->features & AHC_ULTRA2) != 0) 7741 scsiid = ahc_inb(ahc, SCSIID_ULTRA2); 7742 else 7743 scsiid = ahc_inb(ahc, SCSIID); 7744 scsiid_mask = 0x1 << (scsiid & OID); 7745 if ((targid_mask & scsiid_mask) == 0) { 7746 u_int our_id; 7747 7748 /* ffs counts from 1 */ 7749 our_id = ffs(targid_mask); 7750 if (our_id == 0) 7751 our_id = ahc->our_id; 7752 else 7753 our_id--; 7754 scsiid &= TID; 7755 scsiid |= our_id; 7756 } 7757 if ((ahc->features & AHC_ULTRA2) != 0) 7758 ahc_outb(ahc, SCSIID_ULTRA2, scsiid); 7759 else 7760 ahc_outb(ahc, SCSIID, scsiid); 7761 } 7762 7763 static void 7764 ahc_run_tqinfifo(struct ahc_softc *ahc, int paused) 7765 { 7766 struct target_cmd *cmd; 7767 7768 /* 7769 * If the card supports auto-access pause, 7770 * we can access the card directly regardless 7771 * of whether it is paused or not. 7772 */ 7773 if ((ahc->features & AHC_AUTOPAUSE) != 0) 7774 paused = TRUE; 7775 7776 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_POSTREAD); 7777 while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) { 7778 7779 /* 7780 * Only advance through the queue if we 7781 * have the resources to process the command. 7782 */ 7783 if (ahc_handle_target_cmd(ahc, cmd) != 0) 7784 break; 7785 7786 cmd->cmd_valid = 0; 7787 ahc_dmamap_sync(ahc, ahc->shared_data_dmat, 7788 ahc->shared_data_dmamap, 7789 ahc_targetcmd_offset(ahc, ahc->tqinfifonext), 7790 sizeof(struct target_cmd), 7791 BUS_DMASYNC_PREREAD); 7792 ahc->tqinfifonext++; 7793 7794 /* 7795 * Lazily update our position in the target mode incoming 7796 * command queue as seen by the sequencer. 7797 */ 7798 if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) { 7799 if ((ahc->features & AHC_HS_MAILBOX) != 0) { 7800 u_int hs_mailbox; 7801 7802 hs_mailbox = ahc_inb(ahc, HS_MAILBOX); 7803 hs_mailbox &= ~HOST_TQINPOS; 7804 hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS; 7805 ahc_outb(ahc, HS_MAILBOX, hs_mailbox); 7806 } else { 7807 if (!paused) 7808 ahc_pause(ahc); 7809 ahc_outb(ahc, KERNEL_TQINPOS, 7810 ahc->tqinfifonext & HOST_TQINPOS); 7811 if (!paused) 7812 ahc_unpause(ahc); 7813 } 7814 } 7815 } 7816 } 7817 7818 static int 7819 ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd) 7820 { 7821 struct ahc_tmode_tstate *tstate; 7822 struct ahc_tmode_lstate *lstate; 7823 struct ccb_accept_tio *atio; 7824 uint8_t *byte; 7825 int initiator; 7826 int target; 7827 int lun; 7828 7829 initiator = SCSIID_TARGET(ahc, cmd->scsiid); 7830 target = SCSIID_OUR_ID(cmd->scsiid); 7831 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK); 7832 7833 byte = cmd->bytes; 7834 tstate = ahc->enabled_targets[target]; 7835 lstate = NULL; 7836 if (tstate != NULL) 7837 lstate = tstate->enabled_luns[lun]; 7838 7839 /* 7840 * Commands for disabled luns go to the black hole driver. 7841 */ 7842 if (lstate == NULL) 7843 lstate = ahc->black_hole; 7844 7845 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios); 7846 if (atio == NULL) { 7847 ahc->flags |= AHC_TQINFIFO_BLOCKED; 7848 /* 7849 * Wait for more ATIOs from the peripheral driver for this lun. 7850 */ 7851 if (bootverbose) 7852 printk("%s: ATIOs exhausted\n", ahc_name(ahc)); 7853 return (1); 7854 } else 7855 ahc->flags &= ~AHC_TQINFIFO_BLOCKED; 7856 #if 0 7857 printk("Incoming command from %d for %d:%d%s\n", 7858 initiator, target, lun, 7859 lstate == ahc->black_hole ? "(Black Holed)" : ""); 7860 #endif 7861 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle); 7862 7863 if (lstate == ahc->black_hole) { 7864 /* Fill in the wildcards */ 7865 atio->ccb_h.target_id = target; 7866 atio->ccb_h.target_lun = lun; 7867 } 7868 7869 /* 7870 * Package it up and send it off to 7871 * whomever has this lun enabled. 7872 */ 7873 atio->sense_len = 0; 7874 atio->init_id = initiator; 7875 if (byte[0] != 0xFF) { 7876 /* Tag was included */ 7877 atio->tag_action = *byte++; 7878 atio->tag_id = *byte++; 7879 atio->ccb_h.flags = CAM_TAG_ACTION_VALID; 7880 } else { 7881 atio->ccb_h.flags = 0; 7882 } 7883 byte++; 7884 7885 /* Okay. Now determine the cdb size based on the command code */ 7886 switch (*byte >> CMD_GROUP_CODE_SHIFT) { 7887 case 0: 7888 atio->cdb_len = 6; 7889 break; 7890 case 1: 7891 case 2: 7892 atio->cdb_len = 10; 7893 break; 7894 case 4: 7895 atio->cdb_len = 16; 7896 break; 7897 case 5: 7898 atio->cdb_len = 12; 7899 break; 7900 case 3: 7901 default: 7902 /* Only copy the opcode. */ 7903 atio->cdb_len = 1; 7904 printk("Reserved or VU command code type encountered\n"); 7905 break; 7906 } 7907 7908 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len); 7909 7910 atio->ccb_h.status |= CAM_CDB_RECVD; 7911 7912 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) { 7913 /* 7914 * We weren't allowed to disconnect. 7915 * We're hanging on the bus until a 7916 * continue target I/O comes in response 7917 * to this accept tio. 7918 */ 7919 #if 0 7920 printk("Received Immediate Command %d:%d:%d - %p\n", 7921 initiator, target, lun, ahc->pending_device); 7922 #endif 7923 ahc->pending_device = lstate; 7924 ahc_freeze_ccb((union ccb *)atio); 7925 atio->ccb_h.flags |= CAM_DIS_DISCONNECT; 7926 } 7927 xpt_done((union ccb*)atio); 7928 return (0); 7929 } 7930 7931 #endif 7932