1 /* 2 * Core routines and tables shareable across OS platforms. 3 * 4 * Copyright (c) 1994-2002 Justin T. Gibbs. 5 * Copyright (c) 2000-2002 Adaptec Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * substantially similar to the "NO WARRANTY" disclaimer below 16 * ("Disclaimer") and any redistribution must be conditioned upon 17 * including a substantially similar Disclaimer requirement for further 18 * binary redistribution. 19 * 3. Neither the names of the above-listed copyright holders nor the names 20 * of any contributors may be used to endorse or promote products derived 21 * from this software without specific prior written permission. 22 * 23 * Alternatively, this software may be distributed under the terms of the 24 * GNU General Public License ("GPL") version 2 as published by the Free 25 * Software Foundation. 26 * 27 * NO WARRANTY 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGES. 39 * 40 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.c#155 $ 41 */ 42 43 #ifdef __linux__ 44 #include "aic7xxx_osm.h" 45 #include "aic7xxx_inline.h" 46 #include "aicasm/aicasm_insformat.h" 47 #else 48 #include <dev/aic7xxx/aic7xxx_osm.h> 49 #include <dev/aic7xxx/aic7xxx_inline.h> 50 #include <dev/aic7xxx/aicasm/aicasm_insformat.h> 51 #endif 52 53 /***************************** Lookup Tables **********************************/ 54 char *ahc_chip_names[] = 55 { 56 "NONE", 57 "aic7770", 58 "aic7850", 59 "aic7855", 60 "aic7859", 61 "aic7860", 62 "aic7870", 63 "aic7880", 64 "aic7895", 65 "aic7895C", 66 "aic7890/91", 67 "aic7896/97", 68 "aic7892", 69 "aic7899" 70 }; 71 static const u_int num_chip_names = ARRAY_SIZE(ahc_chip_names); 72 73 /* 74 * Hardware error codes. 75 */ 76 struct ahc_hard_error_entry { 77 uint8_t errno; 78 char *errmesg; 79 }; 80 81 static struct ahc_hard_error_entry ahc_hard_errors[] = { 82 { ILLHADDR, "Illegal Host Access" }, 83 { ILLSADDR, "Illegal Sequencer Address referrenced" }, 84 { ILLOPCODE, "Illegal Opcode in sequencer program" }, 85 { SQPARERR, "Sequencer Parity Error" }, 86 { DPARERR, "Data-path Parity Error" }, 87 { MPARERR, "Scratch or SCB Memory Parity Error" }, 88 { PCIERRSTAT, "PCI Error detected" }, 89 { CIOPARERR, "CIOBUS Parity Error" }, 90 }; 91 static const u_int num_errors = ARRAY_SIZE(ahc_hard_errors); 92 93 static struct ahc_phase_table_entry ahc_phase_table[] = 94 { 95 { P_DATAOUT, MSG_NOOP, "in Data-out phase" }, 96 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" }, 97 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" }, 98 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" }, 99 { P_COMMAND, MSG_NOOP, "in Command phase" }, 100 { P_MESGOUT, MSG_NOOP, "in Message-out phase" }, 101 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" }, 102 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" }, 103 { P_BUSFREE, MSG_NOOP, "while idle" }, 104 { 0, MSG_NOOP, "in unknown phase" } 105 }; 106 107 /* 108 * In most cases we only wish to itterate over real phases, so 109 * exclude the last element from the count. 110 */ 111 static const u_int num_phases = ARRAY_SIZE(ahc_phase_table) - 1; 112 113 /* 114 * Valid SCSIRATE values. (p. 3-17) 115 * Provides a mapping of tranfer periods in ns to the proper value to 116 * stick in the scsixfer reg. 117 */ 118 static struct ahc_syncrate ahc_syncrates[] = 119 { 120 /* ultra2 fast/ultra period rate */ 121 { 0x42, 0x000, 9, "80.0" }, 122 { 0x03, 0x000, 10, "40.0" }, 123 { 0x04, 0x000, 11, "33.0" }, 124 { 0x05, 0x100, 12, "20.0" }, 125 { 0x06, 0x110, 15, "16.0" }, 126 { 0x07, 0x120, 18, "13.4" }, 127 { 0x08, 0x000, 25, "10.0" }, 128 { 0x19, 0x010, 31, "8.0" }, 129 { 0x1a, 0x020, 37, "6.67" }, 130 { 0x1b, 0x030, 43, "5.7" }, 131 { 0x1c, 0x040, 50, "5.0" }, 132 { 0x00, 0x050, 56, "4.4" }, 133 { 0x00, 0x060, 62, "4.0" }, 134 { 0x00, 0x070, 68, "3.6" }, 135 { 0x00, 0x000, 0, NULL } 136 }; 137 138 /* Our Sequencer Program */ 139 #include "aic7xxx_seq.h" 140 141 /**************************** Function Declarations ***************************/ 142 static void ahc_force_renegotiation(struct ahc_softc *ahc, 143 struct ahc_devinfo *devinfo); 144 static struct ahc_tmode_tstate* 145 ahc_alloc_tstate(struct ahc_softc *ahc, 146 u_int scsi_id, char channel); 147 #ifdef AHC_TARGET_MODE 148 static void ahc_free_tstate(struct ahc_softc *ahc, 149 u_int scsi_id, char channel, int force); 150 #endif 151 static struct ahc_syncrate* 152 ahc_devlimited_syncrate(struct ahc_softc *ahc, 153 struct ahc_initiator_tinfo *, 154 u_int *period, 155 u_int *ppr_options, 156 role_t role); 157 static void ahc_update_pending_scbs(struct ahc_softc *ahc); 158 static void ahc_fetch_devinfo(struct ahc_softc *ahc, 159 struct ahc_devinfo *devinfo); 160 static void ahc_scb_devinfo(struct ahc_softc *ahc, 161 struct ahc_devinfo *devinfo, 162 struct scb *scb); 163 static void ahc_assert_atn(struct ahc_softc *ahc); 164 static void ahc_setup_initiator_msgout(struct ahc_softc *ahc, 165 struct ahc_devinfo *devinfo, 166 struct scb *scb); 167 static void ahc_build_transfer_msg(struct ahc_softc *ahc, 168 struct ahc_devinfo *devinfo); 169 static void ahc_construct_sdtr(struct ahc_softc *ahc, 170 struct ahc_devinfo *devinfo, 171 u_int period, u_int offset); 172 static void ahc_construct_wdtr(struct ahc_softc *ahc, 173 struct ahc_devinfo *devinfo, 174 u_int bus_width); 175 static void ahc_construct_ppr(struct ahc_softc *ahc, 176 struct ahc_devinfo *devinfo, 177 u_int period, u_int offset, 178 u_int bus_width, u_int ppr_options); 179 static void ahc_clear_msg_state(struct ahc_softc *ahc); 180 static void ahc_handle_proto_violation(struct ahc_softc *ahc); 181 static void ahc_handle_message_phase(struct ahc_softc *ahc); 182 typedef enum { 183 AHCMSG_1B, 184 AHCMSG_2B, 185 AHCMSG_EXT 186 } ahc_msgtype; 187 static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, 188 u_int msgval, int full); 189 static int ahc_parse_msg(struct ahc_softc *ahc, 190 struct ahc_devinfo *devinfo); 191 static int ahc_handle_msg_reject(struct ahc_softc *ahc, 192 struct ahc_devinfo *devinfo); 193 static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc, 194 struct ahc_devinfo *devinfo); 195 static void ahc_reinitialize_dataptrs(struct ahc_softc *ahc); 196 static void ahc_handle_devreset(struct ahc_softc *ahc, 197 struct ahc_devinfo *devinfo, 198 cam_status status, char *message, 199 int verbose_level); 200 #ifdef AHC_TARGET_MODE 201 static void ahc_setup_target_msgin(struct ahc_softc *ahc, 202 struct ahc_devinfo *devinfo, 203 struct scb *scb); 204 #endif 205 206 static bus_dmamap_callback_t ahc_dmamap_cb; 207 static void ahc_build_free_scb_list(struct ahc_softc *ahc); 208 static int ahc_init_scbdata(struct ahc_softc *ahc); 209 static void ahc_fini_scbdata(struct ahc_softc *ahc); 210 static void ahc_qinfifo_requeue(struct ahc_softc *ahc, 211 struct scb *prev_scb, 212 struct scb *scb); 213 static int ahc_qinfifo_count(struct ahc_softc *ahc); 214 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, 215 u_int prev, u_int scbptr); 216 static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc); 217 static u_int ahc_rem_wscb(struct ahc_softc *ahc, 218 u_int scbpos, u_int prev); 219 static void ahc_reset_current_bus(struct ahc_softc *ahc); 220 #ifdef AHC_DUMP_SEQ 221 static void ahc_dumpseq(struct ahc_softc *ahc); 222 #endif 223 static int ahc_loadseq(struct ahc_softc *ahc); 224 static int ahc_check_patch(struct ahc_softc *ahc, 225 struct patch **start_patch, 226 u_int start_instr, u_int *skip_addr); 227 static void ahc_download_instr(struct ahc_softc *ahc, 228 u_int instrptr, uint8_t *dconsts); 229 #ifdef AHC_TARGET_MODE 230 static void ahc_queue_lstate_event(struct ahc_softc *ahc, 231 struct ahc_tmode_lstate *lstate, 232 u_int initiator_id, 233 u_int event_type, 234 u_int event_arg); 235 static void ahc_update_scsiid(struct ahc_softc *ahc, 236 u_int targid_mask); 237 static int ahc_handle_target_cmd(struct ahc_softc *ahc, 238 struct target_cmd *cmd); 239 #endif 240 /************************* Sequencer Execution Control ************************/ 241 /* 242 * Restart the sequencer program from address zero 243 */ 244 void 245 ahc_restart(struct ahc_softc *ahc) 246 { 247 248 ahc_pause(ahc); 249 250 /* No more pending messages. */ 251 ahc_clear_msg_state(ahc); 252 253 ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */ 254 ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */ 255 ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET); 256 ahc_outb(ahc, LASTPHASE, P_BUSFREE); 257 ahc_outb(ahc, SAVED_SCSIID, 0xFF); 258 ahc_outb(ahc, SAVED_LUN, 0xFF); 259 260 /* 261 * Ensure that the sequencer's idea of TQINPOS 262 * matches our own. The sequencer increments TQINPOS 263 * only after it sees a DMA complete and a reset could 264 * occur before the increment leaving the kernel to believe 265 * the command arrived but the sequencer to not. 266 */ 267 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext); 268 269 /* Always allow reselection */ 270 ahc_outb(ahc, SCSISEQ, 271 ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP)); 272 if ((ahc->features & AHC_CMD_CHAN) != 0) { 273 /* Ensure that no DMA operations are in progress */ 274 ahc_outb(ahc, CCSCBCNT, 0); 275 ahc_outb(ahc, CCSGCTL, 0); 276 ahc_outb(ahc, CCSCBCTL, 0); 277 } 278 /* 279 * If we were in the process of DMA'ing SCB data into 280 * an SCB, replace that SCB on the free list. This prevents 281 * an SCB leak. 282 */ 283 if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) { 284 ahc_add_curscb_to_free_list(ahc); 285 ahc_outb(ahc, SEQ_FLAGS2, 286 ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA); 287 } 288 289 /* 290 * Clear any pending sequencer interrupt. It is no 291 * longer relevant since we're resetting the Program 292 * Counter. 293 */ 294 ahc_outb(ahc, CLRINT, CLRSEQINT); 295 296 ahc_outb(ahc, MWI_RESIDUAL, 0); 297 ahc_outb(ahc, SEQCTL, ahc->seqctl); 298 ahc_outb(ahc, SEQADDR0, 0); 299 ahc_outb(ahc, SEQADDR1, 0); 300 301 ahc_unpause(ahc); 302 } 303 304 /************************* Input/Output Queues ********************************/ 305 void 306 ahc_run_qoutfifo(struct ahc_softc *ahc) 307 { 308 struct scb *scb; 309 u_int scb_index; 310 311 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD); 312 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) { 313 314 scb_index = ahc->qoutfifo[ahc->qoutfifonext]; 315 if ((ahc->qoutfifonext & 0x03) == 0x03) { 316 u_int modnext; 317 318 /* 319 * Clear 32bits of QOUTFIFO at a time 320 * so that we don't clobber an incoming 321 * byte DMA to the array on architectures 322 * that only support 32bit load and store 323 * operations. 324 */ 325 modnext = ahc->qoutfifonext & ~0x3; 326 *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL; 327 ahc_dmamap_sync(ahc, ahc->shared_data_dmat, 328 ahc->shared_data_dmamap, 329 /*offset*/modnext, /*len*/4, 330 BUS_DMASYNC_PREREAD); 331 } 332 ahc->qoutfifonext++; 333 334 scb = ahc_lookup_scb(ahc, scb_index); 335 if (scb == NULL) { 336 printf("%s: WARNING no command for scb %d " 337 "(cmdcmplt)\nQOUTPOS = %d\n", 338 ahc_name(ahc), scb_index, 339 (ahc->qoutfifonext - 1) & 0xFF); 340 continue; 341 } 342 343 /* 344 * Save off the residual 345 * if there is one. 346 */ 347 ahc_update_residual(ahc, scb); 348 ahc_done(ahc, scb); 349 } 350 } 351 352 void 353 ahc_run_untagged_queues(struct ahc_softc *ahc) 354 { 355 int i; 356 357 for (i = 0; i < 16; i++) 358 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]); 359 } 360 361 void 362 ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue) 363 { 364 struct scb *scb; 365 366 if (ahc->untagged_queue_lock != 0) 367 return; 368 369 if ((scb = TAILQ_FIRST(queue)) != NULL 370 && (scb->flags & SCB_ACTIVE) == 0) { 371 scb->flags |= SCB_ACTIVE; 372 ahc_queue_scb(ahc, scb); 373 } 374 } 375 376 /************************* Interrupt Handling *********************************/ 377 void 378 ahc_handle_brkadrint(struct ahc_softc *ahc) 379 { 380 /* 381 * We upset the sequencer :-( 382 * Lookup the error message 383 */ 384 int i; 385 int error; 386 387 error = ahc_inb(ahc, ERROR); 388 for (i = 0; error != 1 && i < num_errors; i++) 389 error >>= 1; 390 printf("%s: brkadrint, %s at seqaddr = 0x%x\n", 391 ahc_name(ahc), ahc_hard_errors[i].errmesg, 392 ahc_inb(ahc, SEQADDR0) | 393 (ahc_inb(ahc, SEQADDR1) << 8)); 394 395 ahc_dump_card_state(ahc); 396 397 /* Tell everyone that this HBA is no longer available */ 398 ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS, 399 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN, 400 CAM_NO_HBA); 401 402 /* Disable all interrupt sources by resetting the controller */ 403 ahc_shutdown(ahc); 404 } 405 406 void 407 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat) 408 { 409 struct scb *scb; 410 struct ahc_devinfo devinfo; 411 412 ahc_fetch_devinfo(ahc, &devinfo); 413 414 /* 415 * Clear the upper byte that holds SEQINT status 416 * codes and clear the SEQINT bit. We will unpause 417 * the sequencer, if appropriate, after servicing 418 * the request. 419 */ 420 ahc_outb(ahc, CLRINT, CLRSEQINT); 421 switch (intstat & SEQINT_MASK) { 422 case BAD_STATUS: 423 { 424 u_int scb_index; 425 struct hardware_scb *hscb; 426 427 /* 428 * Set the default return value to 0 (don't 429 * send sense). The sense code will change 430 * this if needed. 431 */ 432 ahc_outb(ahc, RETURN_1, 0); 433 434 /* 435 * The sequencer will notify us when a command 436 * has an error that would be of interest to 437 * the kernel. This allows us to leave the sequencer 438 * running in the common case of command completes 439 * without error. The sequencer will already have 440 * dma'd the SCB back up to us, so we can reference 441 * the in kernel copy directly. 442 */ 443 scb_index = ahc_inb(ahc, SCB_TAG); 444 scb = ahc_lookup_scb(ahc, scb_index); 445 if (scb == NULL) { 446 ahc_print_devinfo(ahc, &devinfo); 447 printf("ahc_intr - referenced scb " 448 "not valid during seqint 0x%x scb(%d)\n", 449 intstat, scb_index); 450 ahc_dump_card_state(ahc); 451 panic("for safety"); 452 goto unpause; 453 } 454 455 hscb = scb->hscb; 456 457 /* Don't want to clobber the original sense code */ 458 if ((scb->flags & SCB_SENSE) != 0) { 459 /* 460 * Clear the SCB_SENSE Flag and have 461 * the sequencer do a normal command 462 * complete. 463 */ 464 scb->flags &= ~SCB_SENSE; 465 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); 466 break; 467 } 468 ahc_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR); 469 /* Freeze the queue until the client sees the error. */ 470 ahc_freeze_devq(ahc, scb); 471 ahc_freeze_scb(scb); 472 ahc_set_scsi_status(scb, hscb->shared_data.status.scsi_status); 473 switch (hscb->shared_data.status.scsi_status) { 474 case SCSI_STATUS_OK: 475 printf("%s: Interrupted for staus of 0???\n", 476 ahc_name(ahc)); 477 break; 478 case SCSI_STATUS_CMD_TERMINATED: 479 case SCSI_STATUS_CHECK_COND: 480 { 481 struct ahc_dma_seg *sg; 482 struct scsi_sense *sc; 483 struct ahc_initiator_tinfo *targ_info; 484 struct ahc_tmode_tstate *tstate; 485 struct ahc_transinfo *tinfo; 486 #ifdef AHC_DEBUG 487 if (ahc_debug & AHC_SHOW_SENSE) { 488 ahc_print_path(ahc, scb); 489 printf("SCB %d: requests Check Status\n", 490 scb->hscb->tag); 491 } 492 #endif 493 494 if (ahc_perform_autosense(scb) == 0) 495 break; 496 497 targ_info = ahc_fetch_transinfo(ahc, 498 devinfo.channel, 499 devinfo.our_scsiid, 500 devinfo.target, 501 &tstate); 502 tinfo = &targ_info->curr; 503 sg = scb->sg_list; 504 sc = (struct scsi_sense *)(&hscb->shared_data.cdb); 505 /* 506 * Save off the residual if there is one. 507 */ 508 ahc_update_residual(ahc, scb); 509 #ifdef AHC_DEBUG 510 if (ahc_debug & AHC_SHOW_SENSE) { 511 ahc_print_path(ahc, scb); 512 printf("Sending Sense\n"); 513 } 514 #endif 515 sg->addr = ahc_get_sense_bufaddr(ahc, scb); 516 sg->len = ahc_get_sense_bufsize(ahc, scb); 517 sg->len |= AHC_DMA_LAST_SEG; 518 519 /* Fixup byte order */ 520 sg->addr = ahc_htole32(sg->addr); 521 sg->len = ahc_htole32(sg->len); 522 523 sc->opcode = REQUEST_SENSE; 524 sc->byte2 = 0; 525 if (tinfo->protocol_version <= SCSI_REV_2 526 && SCB_GET_LUN(scb) < 8) 527 sc->byte2 = SCB_GET_LUN(scb) << 5; 528 sc->unused[0] = 0; 529 sc->unused[1] = 0; 530 sc->length = sg->len; 531 sc->control = 0; 532 533 /* 534 * We can't allow the target to disconnect. 535 * This will be an untagged transaction and 536 * having the target disconnect will make this 537 * transaction indestinguishable from outstanding 538 * tagged transactions. 539 */ 540 hscb->control = 0; 541 542 /* 543 * This request sense could be because the 544 * the device lost power or in some other 545 * way has lost our transfer negotiations. 546 * Renegotiate if appropriate. Unit attention 547 * errors will be reported before any data 548 * phases occur. 549 */ 550 if (ahc_get_residual(scb) 551 == ahc_get_transfer_length(scb)) { 552 ahc_update_neg_request(ahc, &devinfo, 553 tstate, targ_info, 554 AHC_NEG_IF_NON_ASYNC); 555 } 556 if (tstate->auto_negotiate & devinfo.target_mask) { 557 hscb->control |= MK_MESSAGE; 558 scb->flags &= ~SCB_NEGOTIATE; 559 scb->flags |= SCB_AUTO_NEGOTIATE; 560 } 561 hscb->cdb_len = sizeof(*sc); 562 hscb->dataptr = sg->addr; 563 hscb->datacnt = sg->len; 564 hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID; 565 hscb->sgptr = ahc_htole32(hscb->sgptr); 566 scb->sg_count = 1; 567 scb->flags |= SCB_SENSE; 568 ahc_qinfifo_requeue_tail(ahc, scb); 569 ahc_outb(ahc, RETURN_1, SEND_SENSE); 570 /* 571 * Ensure we have enough time to actually 572 * retrieve the sense. 573 */ 574 ahc_scb_timer_reset(scb, 5 * 1000000); 575 break; 576 } 577 default: 578 break; 579 } 580 break; 581 } 582 case NO_MATCH: 583 { 584 /* Ensure we don't leave the selection hardware on */ 585 ahc_outb(ahc, SCSISEQ, 586 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 587 588 printf("%s:%c:%d: no active SCB for reconnecting " 589 "target - issuing BUS DEVICE RESET\n", 590 ahc_name(ahc), devinfo.channel, devinfo.target); 591 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 592 "ARG_1 == 0x%x ACCUM = 0x%x\n", 593 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN), 594 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM)); 595 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 596 "SINDEX == 0x%x\n", 597 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR), 598 ahc_index_busy_tcl(ahc, 599 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID), 600 ahc_inb(ahc, SAVED_LUN))), 601 ahc_inb(ahc, SINDEX)); 602 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 603 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n", 604 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID), 605 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG), 606 ahc_inb(ahc, SCB_CONTROL)); 607 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n", 608 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI)); 609 printf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0)); 610 printf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL)); 611 ahc_dump_card_state(ahc); 612 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET; 613 ahc->msgout_len = 1; 614 ahc->msgout_index = 0; 615 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 616 ahc_outb(ahc, MSG_OUT, HOST_MSG); 617 ahc_assert_atn(ahc); 618 break; 619 } 620 case SEND_REJECT: 621 { 622 u_int rejbyte = ahc_inb(ahc, ACCUM); 623 printf("%s:%c:%d: Warning - unknown message received from " 624 "target (0x%x). Rejecting\n", 625 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte); 626 break; 627 } 628 case PROTO_VIOLATION: 629 { 630 ahc_handle_proto_violation(ahc); 631 break; 632 } 633 case IGN_WIDE_RES: 634 ahc_handle_ign_wide_residue(ahc, &devinfo); 635 break; 636 case PDATA_REINIT: 637 ahc_reinitialize_dataptrs(ahc); 638 break; 639 case BAD_PHASE: 640 { 641 u_int lastphase; 642 643 lastphase = ahc_inb(ahc, LASTPHASE); 644 printf("%s:%c:%d: unknown scsi bus phase %x, " 645 "lastphase = 0x%x. Attempting to continue\n", 646 ahc_name(ahc), devinfo.channel, devinfo.target, 647 lastphase, ahc_inb(ahc, SCSISIGI)); 648 break; 649 } 650 case MISSED_BUSFREE: 651 { 652 u_int lastphase; 653 654 lastphase = ahc_inb(ahc, LASTPHASE); 655 printf("%s:%c:%d: Missed busfree. " 656 "Lastphase = 0x%x, Curphase = 0x%x\n", 657 ahc_name(ahc), devinfo.channel, devinfo.target, 658 lastphase, ahc_inb(ahc, SCSISIGI)); 659 ahc_restart(ahc); 660 return; 661 } 662 case HOST_MSG_LOOP: 663 { 664 /* 665 * The sequencer has encountered a message phase 666 * that requires host assistance for completion. 667 * While handling the message phase(s), we will be 668 * notified by the sequencer after each byte is 669 * transfered so we can track bus phase changes. 670 * 671 * If this is the first time we've seen a HOST_MSG_LOOP 672 * interrupt, initialize the state of the host message 673 * loop. 674 */ 675 if (ahc->msg_type == MSG_TYPE_NONE) { 676 struct scb *scb; 677 u_int scb_index; 678 u_int bus_phase; 679 680 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 681 if (bus_phase != P_MESGIN 682 && bus_phase != P_MESGOUT) { 683 printf("ahc_intr: HOST_MSG_LOOP bad " 684 "phase 0x%x\n", 685 bus_phase); 686 /* 687 * Probably transitioned to bus free before 688 * we got here. Just punt the message. 689 */ 690 ahc_clear_intstat(ahc); 691 ahc_restart(ahc); 692 return; 693 } 694 695 scb_index = ahc_inb(ahc, SCB_TAG); 696 scb = ahc_lookup_scb(ahc, scb_index); 697 if (devinfo.role == ROLE_INITIATOR) { 698 if (bus_phase == P_MESGOUT) { 699 if (scb == NULL) 700 panic("HOST_MSG_LOOP with " 701 "invalid SCB %x\n", 702 scb_index); 703 704 ahc_setup_initiator_msgout(ahc, 705 &devinfo, 706 scb); 707 } else { 708 ahc->msg_type = 709 MSG_TYPE_INITIATOR_MSGIN; 710 ahc->msgin_index = 0; 711 } 712 } 713 #ifdef AHC_TARGET_MODE 714 else { 715 if (bus_phase == P_MESGOUT) { 716 ahc->msg_type = 717 MSG_TYPE_TARGET_MSGOUT; 718 ahc->msgin_index = 0; 719 } 720 else 721 ahc_setup_target_msgin(ahc, 722 &devinfo, 723 scb); 724 } 725 #endif 726 } 727 728 ahc_handle_message_phase(ahc); 729 break; 730 } 731 case PERR_DETECTED: 732 { 733 /* 734 * If we've cleared the parity error interrupt 735 * but the sequencer still believes that SCSIPERR 736 * is true, it must be that the parity error is 737 * for the currently presented byte on the bus, 738 * and we are not in a phase (data-in) where we will 739 * eventually ack this byte. Ack the byte and 740 * throw it away in the hope that the target will 741 * take us to message out to deliver the appropriate 742 * error message. 743 */ 744 if ((intstat & SCSIINT) == 0 745 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) { 746 747 if ((ahc->features & AHC_DT) == 0) { 748 u_int curphase; 749 750 /* 751 * The hardware will only let you ack bytes 752 * if the expected phase in SCSISIGO matches 753 * the current phase. Make sure this is 754 * currently the case. 755 */ 756 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 757 ahc_outb(ahc, LASTPHASE, curphase); 758 ahc_outb(ahc, SCSISIGO, curphase); 759 } 760 if ((ahc_inb(ahc, SCSISIGI) & (CDI|MSGI)) == 0) { 761 int wait; 762 763 /* 764 * In a data phase. Faster to bitbucket 765 * the data than to individually ack each 766 * byte. This is also the only strategy 767 * that will work with AUTOACK enabled. 768 */ 769 ahc_outb(ahc, SXFRCTL1, 770 ahc_inb(ahc, SXFRCTL1) | BITBUCKET); 771 wait = 5000; 772 while (--wait != 0) { 773 if ((ahc_inb(ahc, SCSISIGI) 774 & (CDI|MSGI)) != 0) 775 break; 776 ahc_delay(100); 777 } 778 ahc_outb(ahc, SXFRCTL1, 779 ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET); 780 if (wait == 0) { 781 struct scb *scb; 782 u_int scb_index; 783 784 ahc_print_devinfo(ahc, &devinfo); 785 printf("Unable to clear parity error. " 786 "Resetting bus.\n"); 787 scb_index = ahc_inb(ahc, SCB_TAG); 788 scb = ahc_lookup_scb(ahc, scb_index); 789 if (scb != NULL) 790 ahc_set_transaction_status(scb, 791 CAM_UNCOR_PARITY); 792 ahc_reset_channel(ahc, devinfo.channel, 793 /*init reset*/TRUE); 794 } 795 } else { 796 ahc_inb(ahc, SCSIDATL); 797 } 798 } 799 break; 800 } 801 case DATA_OVERRUN: 802 { 803 /* 804 * When the sequencer detects an overrun, it 805 * places the controller in "BITBUCKET" mode 806 * and allows the target to complete its transfer. 807 * Unfortunately, none of the counters get updated 808 * when the controller is in this mode, so we have 809 * no way of knowing how large the overrun was. 810 */ 811 u_int scbindex = ahc_inb(ahc, SCB_TAG); 812 u_int lastphase = ahc_inb(ahc, LASTPHASE); 813 u_int i; 814 815 scb = ahc_lookup_scb(ahc, scbindex); 816 for (i = 0; i < num_phases; i++) { 817 if (lastphase == ahc_phase_table[i].phase) 818 break; 819 } 820 ahc_print_path(ahc, scb); 821 printf("data overrun detected %s." 822 " Tag == 0x%x.\n", 823 ahc_phase_table[i].phasemsg, 824 scb->hscb->tag); 825 ahc_print_path(ahc, scb); 826 printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n", 827 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't", 828 ahc_get_transfer_length(scb), scb->sg_count); 829 if (scb->sg_count > 0) { 830 for (i = 0; i < scb->sg_count; i++) { 831 832 printf("sg[%d] - Addr 0x%x%x : Length %d\n", 833 i, 834 (ahc_le32toh(scb->sg_list[i].len) >> 24 835 & SG_HIGH_ADDR_BITS), 836 ahc_le32toh(scb->sg_list[i].addr), 837 ahc_le32toh(scb->sg_list[i].len) 838 & AHC_SG_LEN_MASK); 839 } 840 } 841 /* 842 * Set this and it will take effect when the 843 * target does a command complete. 844 */ 845 ahc_freeze_devq(ahc, scb); 846 if ((scb->flags & SCB_SENSE) == 0) { 847 ahc_set_transaction_status(scb, CAM_DATA_RUN_ERR); 848 } else { 849 scb->flags &= ~SCB_SENSE; 850 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL); 851 } 852 ahc_freeze_scb(scb); 853 854 if ((ahc->features & AHC_ULTRA2) != 0) { 855 /* 856 * Clear the channel in case we return 857 * to data phase later. 858 */ 859 ahc_outb(ahc, SXFRCTL0, 860 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN); 861 ahc_outb(ahc, SXFRCTL0, 862 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN); 863 } 864 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 865 u_int dscommand1; 866 867 /* Ensure HHADDR is 0 for future DMA operations. */ 868 dscommand1 = ahc_inb(ahc, DSCOMMAND1); 869 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0); 870 ahc_outb(ahc, HADDR, 0); 871 ahc_outb(ahc, DSCOMMAND1, dscommand1); 872 } 873 break; 874 } 875 case MKMSG_FAILED: 876 { 877 u_int scbindex; 878 879 printf("%s:%c:%d:%d: Attempt to issue message failed\n", 880 ahc_name(ahc), devinfo.channel, devinfo.target, 881 devinfo.lun); 882 scbindex = ahc_inb(ahc, SCB_TAG); 883 scb = ahc_lookup_scb(ahc, scbindex); 884 if (scb != NULL 885 && (scb->flags & SCB_RECOVERY_SCB) != 0) 886 /* 887 * Ensure that we didn't put a second instance of this 888 * SCB into the QINFIFO. 889 */ 890 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), 891 SCB_GET_CHANNEL(ahc, scb), 892 SCB_GET_LUN(scb), scb->hscb->tag, 893 ROLE_INITIATOR, /*status*/0, 894 SEARCH_REMOVE); 895 break; 896 } 897 case NO_FREE_SCB: 898 { 899 printf("%s: No free or disconnected SCBs\n", ahc_name(ahc)); 900 ahc_dump_card_state(ahc); 901 panic("for safety"); 902 break; 903 } 904 case SCB_MISMATCH: 905 { 906 u_int scbptr; 907 908 scbptr = ahc_inb(ahc, SCBPTR); 909 printf("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n", 910 scbptr, ahc_inb(ahc, ARG_1), 911 ahc->scb_data->hscbs[scbptr].tag); 912 ahc_dump_card_state(ahc); 913 panic("for saftey"); 914 break; 915 } 916 case OUT_OF_RANGE: 917 { 918 printf("%s: BTT calculation out of range\n", ahc_name(ahc)); 919 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, " 920 "ARG_1 == 0x%x ACCUM = 0x%x\n", 921 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN), 922 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM)); 923 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, " 924 "SINDEX == 0x%x\n, A == 0x%x\n", 925 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR), 926 ahc_index_busy_tcl(ahc, 927 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID), 928 ahc_inb(ahc, SAVED_LUN))), 929 ahc_inb(ahc, SINDEX), 930 ahc_inb(ahc, ACCUM)); 931 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, " 932 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n", 933 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID), 934 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG), 935 ahc_inb(ahc, SCB_CONTROL)); 936 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n", 937 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI)); 938 ahc_dump_card_state(ahc); 939 panic("for safety"); 940 break; 941 } 942 default: 943 printf("ahc_intr: seqint, " 944 "intstat == 0x%x, scsisigi = 0x%x\n", 945 intstat, ahc_inb(ahc, SCSISIGI)); 946 break; 947 } 948 unpause: 949 /* 950 * The sequencer is paused immediately on 951 * a SEQINT, so we should restart it when 952 * we're done. 953 */ 954 ahc_unpause(ahc); 955 } 956 957 void 958 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat) 959 { 960 u_int scb_index; 961 u_int status0; 962 u_int status; 963 struct scb *scb; 964 char cur_channel; 965 char intr_channel; 966 967 if ((ahc->features & AHC_TWIN) != 0 968 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0)) 969 cur_channel = 'B'; 970 else 971 cur_channel = 'A'; 972 intr_channel = cur_channel; 973 974 if ((ahc->features & AHC_ULTRA2) != 0) 975 status0 = ahc_inb(ahc, SSTAT0) & IOERR; 976 else 977 status0 = 0; 978 status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 979 if (status == 0 && status0 == 0) { 980 if ((ahc->features & AHC_TWIN) != 0) { 981 /* Try the other channel */ 982 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 983 status = ahc_inb(ahc, SSTAT1) 984 & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR); 985 intr_channel = (cur_channel == 'A') ? 'B' : 'A'; 986 } 987 if (status == 0) { 988 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc)); 989 ahc_outb(ahc, CLRINT, CLRSCSIINT); 990 ahc_unpause(ahc); 991 return; 992 } 993 } 994 995 /* Make sure the sequencer is in a safe location. */ 996 ahc_clear_critical_section(ahc); 997 998 scb_index = ahc_inb(ahc, SCB_TAG); 999 scb = ahc_lookup_scb(ahc, scb_index); 1000 if (scb != NULL 1001 && (ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) != 0) 1002 scb = NULL; 1003 1004 if ((ahc->features & AHC_ULTRA2) != 0 1005 && (status0 & IOERR) != 0) { 1006 int now_lvd; 1007 1008 now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40; 1009 printf("%s: Transceiver State Has Changed to %s mode\n", 1010 ahc_name(ahc), now_lvd ? "LVD" : "SE"); 1011 ahc_outb(ahc, CLRSINT0, CLRIOERR); 1012 /* 1013 * When transitioning to SE mode, the reset line 1014 * glitches, triggering an arbitration bug in some 1015 * Ultra2 controllers. This bug is cleared when we 1016 * assert the reset line. Since a reset glitch has 1017 * already occurred with this transition and a 1018 * transceiver state change is handled just like 1019 * a bus reset anyway, asserting the reset line 1020 * ourselves is safe. 1021 */ 1022 ahc_reset_channel(ahc, intr_channel, 1023 /*Initiate Reset*/now_lvd == 0); 1024 } else if ((status & SCSIRSTI) != 0) { 1025 printf("%s: Someone reset channel %c\n", 1026 ahc_name(ahc), intr_channel); 1027 if (intr_channel != cur_channel) 1028 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB); 1029 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE); 1030 } else if ((status & SCSIPERR) != 0) { 1031 /* 1032 * Determine the bus phase and queue an appropriate message. 1033 * SCSIPERR is latched true as soon as a parity error 1034 * occurs. If the sequencer acked the transfer that 1035 * caused the parity error and the currently presented 1036 * transfer on the bus has correct parity, SCSIPERR will 1037 * be cleared by CLRSCSIPERR. Use this to determine if 1038 * we should look at the last phase the sequencer recorded, 1039 * or the current phase presented on the bus. 1040 */ 1041 struct ahc_devinfo devinfo; 1042 u_int mesg_out; 1043 u_int curphase; 1044 u_int errorphase; 1045 u_int lastphase; 1046 u_int scsirate; 1047 u_int i; 1048 u_int sstat2; 1049 int silent; 1050 1051 lastphase = ahc_inb(ahc, LASTPHASE); 1052 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 1053 sstat2 = ahc_inb(ahc, SSTAT2); 1054 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR); 1055 /* 1056 * For all phases save DATA, the sequencer won't 1057 * automatically ack a byte that has a parity error 1058 * in it. So the only way that the current phase 1059 * could be 'data-in' is if the parity error is for 1060 * an already acked byte in the data phase. During 1061 * synchronous data-in transfers, we may actually 1062 * ack bytes before latching the current phase in 1063 * LASTPHASE, leading to the discrepancy between 1064 * curphase and lastphase. 1065 */ 1066 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0 1067 || curphase == P_DATAIN || curphase == P_DATAIN_DT) 1068 errorphase = curphase; 1069 else 1070 errorphase = lastphase; 1071 1072 for (i = 0; i < num_phases; i++) { 1073 if (errorphase == ahc_phase_table[i].phase) 1074 break; 1075 } 1076 mesg_out = ahc_phase_table[i].mesg_out; 1077 silent = FALSE; 1078 if (scb != NULL) { 1079 if (SCB_IS_SILENT(scb)) 1080 silent = TRUE; 1081 else 1082 ahc_print_path(ahc, scb); 1083 scb->flags |= SCB_TRANSMISSION_ERROR; 1084 } else 1085 printf("%s:%c:%d: ", ahc_name(ahc), intr_channel, 1086 SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID))); 1087 scsirate = ahc_inb(ahc, SCSIRATE); 1088 if (silent == FALSE) { 1089 printf("parity error detected %s. " 1090 "SEQADDR(0x%x) SCSIRATE(0x%x)\n", 1091 ahc_phase_table[i].phasemsg, 1092 ahc_inw(ahc, SEQADDR0), 1093 scsirate); 1094 if ((ahc->features & AHC_DT) != 0) { 1095 if ((sstat2 & CRCVALERR) != 0) 1096 printf("\tCRC Value Mismatch\n"); 1097 if ((sstat2 & CRCENDERR) != 0) 1098 printf("\tNo terminal CRC packet " 1099 "recevied\n"); 1100 if ((sstat2 & CRCREQERR) != 0) 1101 printf("\tIllegal CRC packet " 1102 "request\n"); 1103 if ((sstat2 & DUAL_EDGE_ERR) != 0) 1104 printf("\tUnexpected %sDT Data Phase\n", 1105 (scsirate & SINGLE_EDGE) 1106 ? "" : "non-"); 1107 } 1108 } 1109 1110 if ((ahc->features & AHC_DT) != 0 1111 && (sstat2 & DUAL_EDGE_ERR) != 0) { 1112 /* 1113 * This error applies regardless of 1114 * data direction, so ignore the value 1115 * in the phase table. 1116 */ 1117 mesg_out = MSG_INITIATOR_DET_ERR; 1118 } 1119 1120 /* 1121 * We've set the hardware to assert ATN if we 1122 * get a parity error on "in" phases, so all we 1123 * need to do is stuff the message buffer with 1124 * the appropriate message. "In" phases have set 1125 * mesg_out to something other than MSG_NOP. 1126 */ 1127 if (mesg_out != MSG_NOOP) { 1128 if (ahc->msg_type != MSG_TYPE_NONE) 1129 ahc->send_msg_perror = TRUE; 1130 else 1131 ahc_outb(ahc, MSG_OUT, mesg_out); 1132 } 1133 /* 1134 * Force a renegotiation with this target just in 1135 * case we are out of sync for some external reason 1136 * unknown (or unreported) by the target. 1137 */ 1138 ahc_fetch_devinfo(ahc, &devinfo); 1139 ahc_force_renegotiation(ahc, &devinfo); 1140 1141 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1142 ahc_unpause(ahc); 1143 } else if ((status & SELTO) != 0) { 1144 u_int scbptr; 1145 1146 /* Stop the selection */ 1147 ahc_outb(ahc, SCSISEQ, 0); 1148 1149 /* No more pending messages */ 1150 ahc_clear_msg_state(ahc); 1151 1152 /* Clear interrupt state */ 1153 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 1154 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR); 1155 1156 /* 1157 * Although the driver does not care about the 1158 * 'Selection in Progress' status bit, the busy 1159 * LED does. SELINGO is only cleared by a sucessfull 1160 * selection, so we must manually clear it to insure 1161 * the LED turns off just incase no future successful 1162 * selections occur (e.g. no devices on the bus). 1163 */ 1164 ahc_outb(ahc, CLRSINT0, CLRSELINGO); 1165 1166 scbptr = ahc_inb(ahc, WAITING_SCBH); 1167 ahc_outb(ahc, SCBPTR, scbptr); 1168 scb_index = ahc_inb(ahc, SCB_TAG); 1169 1170 scb = ahc_lookup_scb(ahc, scb_index); 1171 if (scb == NULL) { 1172 printf("%s: ahc_intr - referenced scb not " 1173 "valid during SELTO scb(%d, %d)\n", 1174 ahc_name(ahc), scbptr, scb_index); 1175 ahc_dump_card_state(ahc); 1176 } else { 1177 struct ahc_devinfo devinfo; 1178 #ifdef AHC_DEBUG 1179 if ((ahc_debug & AHC_SHOW_SELTO) != 0) { 1180 ahc_print_path(ahc, scb); 1181 printf("Saw Selection Timeout for SCB 0x%x\n", 1182 scb_index); 1183 } 1184 #endif 1185 ahc_scb_devinfo(ahc, &devinfo, scb); 1186 ahc_set_transaction_status(scb, CAM_SEL_TIMEOUT); 1187 ahc_freeze_devq(ahc, scb); 1188 1189 /* 1190 * Cancel any pending transactions on the device 1191 * now that it seems to be missing. This will 1192 * also revert us to async/narrow transfers until 1193 * we can renegotiate with the device. 1194 */ 1195 ahc_handle_devreset(ahc, &devinfo, 1196 CAM_SEL_TIMEOUT, 1197 "Selection Timeout", 1198 /*verbose_level*/1); 1199 } 1200 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1201 ahc_restart(ahc); 1202 } else if ((status & BUSFREE) != 0 1203 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) { 1204 struct ahc_devinfo devinfo; 1205 u_int lastphase; 1206 u_int saved_scsiid; 1207 u_int saved_lun; 1208 u_int target; 1209 u_int initiator_role_id; 1210 char channel; 1211 int printerror; 1212 1213 /* 1214 * Clear our selection hardware as soon as possible. 1215 * We may have an entry in the waiting Q for this target, 1216 * that is affected by this busfree and we don't want to 1217 * go about selecting the target while we handle the event. 1218 */ 1219 ahc_outb(ahc, SCSISEQ, 1220 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP)); 1221 1222 /* 1223 * Disable busfree interrupts and clear the busfree 1224 * interrupt status. We do this here so that several 1225 * bus transactions occur prior to clearing the SCSIINT 1226 * latch. It can take a bit for the clearing to take effect. 1227 */ 1228 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE); 1229 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR); 1230 1231 /* 1232 * Look at what phase we were last in. 1233 * If its message out, chances are pretty good 1234 * that the busfree was in response to one of 1235 * our abort requests. 1236 */ 1237 lastphase = ahc_inb(ahc, LASTPHASE); 1238 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID); 1239 saved_lun = ahc_inb(ahc, SAVED_LUN); 1240 target = SCSIID_TARGET(ahc, saved_scsiid); 1241 initiator_role_id = SCSIID_OUR_ID(saved_scsiid); 1242 channel = SCSIID_CHANNEL(ahc, saved_scsiid); 1243 ahc_compile_devinfo(&devinfo, initiator_role_id, 1244 target, saved_lun, channel, ROLE_INITIATOR); 1245 printerror = 1; 1246 1247 if (lastphase == P_MESGOUT) { 1248 u_int tag; 1249 1250 tag = SCB_LIST_NULL; 1251 if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE) 1252 || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) { 1253 if (ahc->msgout_buf[ahc->msgout_index - 1] 1254 == MSG_ABORT_TAG) 1255 tag = scb->hscb->tag; 1256 ahc_print_path(ahc, scb); 1257 printf("SCB %d - Abort%s Completed.\n", 1258 scb->hscb->tag, tag == SCB_LIST_NULL ? 1259 "" : " Tag"); 1260 ahc_abort_scbs(ahc, target, channel, 1261 saved_lun, tag, 1262 ROLE_INITIATOR, 1263 CAM_REQ_ABORTED); 1264 printerror = 0; 1265 } else if (ahc_sent_msg(ahc, AHCMSG_1B, 1266 MSG_BUS_DEV_RESET, TRUE)) { 1267 #ifdef __FreeBSD__ 1268 /* 1269 * Don't mark the user's request for this BDR 1270 * as completing with CAM_BDR_SENT. CAM3 1271 * specifies CAM_REQ_CMP. 1272 */ 1273 if (scb != NULL 1274 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV 1275 && ahc_match_scb(ahc, scb, target, channel, 1276 CAM_LUN_WILDCARD, 1277 SCB_LIST_NULL, 1278 ROLE_INITIATOR)) { 1279 ahc_set_transaction_status(scb, CAM_REQ_CMP); 1280 } 1281 #endif 1282 ahc_compile_devinfo(&devinfo, 1283 initiator_role_id, 1284 target, 1285 CAM_LUN_WILDCARD, 1286 channel, 1287 ROLE_INITIATOR); 1288 ahc_handle_devreset(ahc, &devinfo, 1289 CAM_BDR_SENT, 1290 "Bus Device Reset", 1291 /*verbose_level*/0); 1292 printerror = 0; 1293 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, 1294 MSG_EXT_PPR, FALSE)) { 1295 struct ahc_initiator_tinfo *tinfo; 1296 struct ahc_tmode_tstate *tstate; 1297 1298 /* 1299 * PPR Rejected. Try non-ppr negotiation 1300 * and retry command. 1301 */ 1302 tinfo = ahc_fetch_transinfo(ahc, 1303 devinfo.channel, 1304 devinfo.our_scsiid, 1305 devinfo.target, 1306 &tstate); 1307 tinfo->curr.transport_version = 2; 1308 tinfo->goal.transport_version = 2; 1309 tinfo->goal.ppr_options = 0; 1310 ahc_qinfifo_requeue_tail(ahc, scb); 1311 printerror = 0; 1312 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, 1313 MSG_EXT_WDTR, FALSE)) { 1314 /* 1315 * Negotiation Rejected. Go-narrow and 1316 * retry command. 1317 */ 1318 ahc_set_width(ahc, &devinfo, 1319 MSG_EXT_WDTR_BUS_8_BIT, 1320 AHC_TRANS_CUR|AHC_TRANS_GOAL, 1321 /*paused*/TRUE); 1322 ahc_qinfifo_requeue_tail(ahc, scb); 1323 printerror = 0; 1324 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, 1325 MSG_EXT_SDTR, FALSE)) { 1326 /* 1327 * Negotiation Rejected. Go-async and 1328 * retry command. 1329 */ 1330 ahc_set_syncrate(ahc, &devinfo, 1331 /*syncrate*/NULL, 1332 /*period*/0, /*offset*/0, 1333 /*ppr_options*/0, 1334 AHC_TRANS_CUR|AHC_TRANS_GOAL, 1335 /*paused*/TRUE); 1336 ahc_qinfifo_requeue_tail(ahc, scb); 1337 printerror = 0; 1338 } 1339 } 1340 if (printerror != 0) { 1341 u_int i; 1342 1343 if (scb != NULL) { 1344 u_int tag; 1345 1346 if ((scb->hscb->control & TAG_ENB) != 0) 1347 tag = scb->hscb->tag; 1348 else 1349 tag = SCB_LIST_NULL; 1350 ahc_print_path(ahc, scb); 1351 ahc_abort_scbs(ahc, target, channel, 1352 SCB_GET_LUN(scb), tag, 1353 ROLE_INITIATOR, 1354 CAM_UNEXP_BUSFREE); 1355 } else { 1356 /* 1357 * We had not fully identified this connection, 1358 * so we cannot abort anything. 1359 */ 1360 printf("%s: ", ahc_name(ahc)); 1361 } 1362 for (i = 0; i < num_phases; i++) { 1363 if (lastphase == ahc_phase_table[i].phase) 1364 break; 1365 } 1366 if (lastphase != P_BUSFREE) { 1367 /* 1368 * Renegotiate with this device at the 1369 * next oportunity just in case this busfree 1370 * is due to a negotiation mismatch with the 1371 * device. 1372 */ 1373 ahc_force_renegotiation(ahc, &devinfo); 1374 } 1375 printf("Unexpected busfree %s\n" 1376 "SEQADDR == 0x%x\n", 1377 ahc_phase_table[i].phasemsg, 1378 ahc_inb(ahc, SEQADDR0) 1379 | (ahc_inb(ahc, SEQADDR1) << 8)); 1380 } 1381 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1382 ahc_restart(ahc); 1383 } else { 1384 printf("%s: Missing case in ahc_handle_scsiint. status = %x\n", 1385 ahc_name(ahc), status); 1386 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1387 } 1388 } 1389 1390 /* 1391 * Force renegotiation to occur the next time we initiate 1392 * a command to the current device. 1393 */ 1394 static void 1395 ahc_force_renegotiation(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 1396 { 1397 struct ahc_initiator_tinfo *targ_info; 1398 struct ahc_tmode_tstate *tstate; 1399 1400 targ_info = ahc_fetch_transinfo(ahc, 1401 devinfo->channel, 1402 devinfo->our_scsiid, 1403 devinfo->target, 1404 &tstate); 1405 ahc_update_neg_request(ahc, devinfo, tstate, 1406 targ_info, AHC_NEG_IF_NON_ASYNC); 1407 } 1408 1409 #define AHC_MAX_STEPS 2000 1410 void 1411 ahc_clear_critical_section(struct ahc_softc *ahc) 1412 { 1413 int stepping; 1414 int steps; 1415 u_int simode0; 1416 u_int simode1; 1417 1418 if (ahc->num_critical_sections == 0) 1419 return; 1420 1421 stepping = FALSE; 1422 steps = 0; 1423 simode0 = 0; 1424 simode1 = 0; 1425 for (;;) { 1426 struct cs *cs; 1427 u_int seqaddr; 1428 u_int i; 1429 1430 seqaddr = ahc_inb(ahc, SEQADDR0) 1431 | (ahc_inb(ahc, SEQADDR1) << 8); 1432 1433 /* 1434 * Seqaddr represents the next instruction to execute, 1435 * so we are really executing the instruction just 1436 * before it. 1437 */ 1438 if (seqaddr != 0) 1439 seqaddr -= 1; 1440 cs = ahc->critical_sections; 1441 for (i = 0; i < ahc->num_critical_sections; i++, cs++) { 1442 1443 if (cs->begin < seqaddr && cs->end >= seqaddr) 1444 break; 1445 } 1446 1447 if (i == ahc->num_critical_sections) 1448 break; 1449 1450 if (steps > AHC_MAX_STEPS) { 1451 printf("%s: Infinite loop in critical section\n", 1452 ahc_name(ahc)); 1453 ahc_dump_card_state(ahc); 1454 panic("critical section loop"); 1455 } 1456 1457 steps++; 1458 if (stepping == FALSE) { 1459 1460 /* 1461 * Disable all interrupt sources so that the 1462 * sequencer will not be stuck by a pausing 1463 * interrupt condition while we attempt to 1464 * leave a critical section. 1465 */ 1466 simode0 = ahc_inb(ahc, SIMODE0); 1467 ahc_outb(ahc, SIMODE0, 0); 1468 simode1 = ahc_inb(ahc, SIMODE1); 1469 if ((ahc->features & AHC_DT) != 0) 1470 /* 1471 * On DT class controllers, we 1472 * use the enhanced busfree logic. 1473 * Unfortunately we cannot re-enable 1474 * busfree detection within the 1475 * current connection, so we must 1476 * leave it on while single stepping. 1477 */ 1478 ahc_outb(ahc, SIMODE1, simode1 & ENBUSFREE); 1479 else 1480 ahc_outb(ahc, SIMODE1, 0); 1481 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1482 ahc_outb(ahc, SEQCTL, ahc->seqctl | STEP); 1483 stepping = TRUE; 1484 } 1485 if ((ahc->features & AHC_DT) != 0) { 1486 ahc_outb(ahc, CLRSINT1, CLRBUSFREE); 1487 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1488 } 1489 ahc_outb(ahc, HCNTRL, ahc->unpause); 1490 while (!ahc_is_paused(ahc)) 1491 ahc_delay(200); 1492 } 1493 if (stepping) { 1494 ahc_outb(ahc, SIMODE0, simode0); 1495 ahc_outb(ahc, SIMODE1, simode1); 1496 ahc_outb(ahc, SEQCTL, ahc->seqctl); 1497 } 1498 } 1499 1500 /* 1501 * Clear any pending interrupt status. 1502 */ 1503 void 1504 ahc_clear_intstat(struct ahc_softc *ahc) 1505 { 1506 /* Clear any interrupt conditions this may have caused */ 1507 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI 1508 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG| 1509 CLRREQINIT); 1510 ahc_flush_device_writes(ahc); 1511 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO); 1512 ahc_flush_device_writes(ahc); 1513 ahc_outb(ahc, CLRINT, CLRSCSIINT); 1514 ahc_flush_device_writes(ahc); 1515 } 1516 1517 /**************************** Debugging Routines ******************************/ 1518 #ifdef AHC_DEBUG 1519 uint32_t ahc_debug = AHC_DEBUG_OPTS; 1520 #endif 1521 1522 void 1523 ahc_print_scb(struct scb *scb) 1524 { 1525 int i; 1526 1527 struct hardware_scb *hscb = scb->hscb; 1528 1529 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n", 1530 (void *)scb, 1531 hscb->control, 1532 hscb->scsiid, 1533 hscb->lun, 1534 hscb->cdb_len); 1535 printf("Shared Data: "); 1536 for (i = 0; i < sizeof(hscb->shared_data.cdb); i++) 1537 printf("%#02x", hscb->shared_data.cdb[i]); 1538 printf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n", 1539 ahc_le32toh(hscb->dataptr), 1540 ahc_le32toh(hscb->datacnt), 1541 ahc_le32toh(hscb->sgptr), 1542 hscb->tag); 1543 if (scb->sg_count > 0) { 1544 for (i = 0; i < scb->sg_count; i++) { 1545 printf("sg[%d] - Addr 0x%x%x : Length %d\n", 1546 i, 1547 (ahc_le32toh(scb->sg_list[i].len) >> 24 1548 & SG_HIGH_ADDR_BITS), 1549 ahc_le32toh(scb->sg_list[i].addr), 1550 ahc_le32toh(scb->sg_list[i].len)); 1551 } 1552 } 1553 } 1554 1555 /************************* Transfer Negotiation *******************************/ 1556 /* 1557 * Allocate per target mode instance (ID we respond to as a target) 1558 * transfer negotiation data structures. 1559 */ 1560 static struct ahc_tmode_tstate * 1561 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel) 1562 { 1563 struct ahc_tmode_tstate *master_tstate; 1564 struct ahc_tmode_tstate *tstate; 1565 int i; 1566 1567 master_tstate = ahc->enabled_targets[ahc->our_id]; 1568 if (channel == 'B') { 1569 scsi_id += 8; 1570 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8]; 1571 } 1572 if (ahc->enabled_targets[scsi_id] != NULL 1573 && ahc->enabled_targets[scsi_id] != master_tstate) 1574 panic("%s: ahc_alloc_tstate - Target already allocated", 1575 ahc_name(ahc)); 1576 tstate = (struct ahc_tmode_tstate*)malloc(sizeof(*tstate), 1577 M_DEVBUF, M_NOWAIT); 1578 if (tstate == NULL) 1579 return (NULL); 1580 1581 /* 1582 * If we have allocated a master tstate, copy user settings from 1583 * the master tstate (taken from SRAM or the EEPROM) for this 1584 * channel, but reset our current and goal settings to async/narrow 1585 * until an initiator talks to us. 1586 */ 1587 if (master_tstate != NULL) { 1588 memcpy(tstate, master_tstate, sizeof(*tstate)); 1589 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns)); 1590 tstate->ultraenb = 0; 1591 for (i = 0; i < AHC_NUM_TARGETS; i++) { 1592 memset(&tstate->transinfo[i].curr, 0, 1593 sizeof(tstate->transinfo[i].curr)); 1594 memset(&tstate->transinfo[i].goal, 0, 1595 sizeof(tstate->transinfo[i].goal)); 1596 } 1597 } else 1598 memset(tstate, 0, sizeof(*tstate)); 1599 ahc->enabled_targets[scsi_id] = tstate; 1600 return (tstate); 1601 } 1602 1603 #ifdef AHC_TARGET_MODE 1604 /* 1605 * Free per target mode instance (ID we respond to as a target) 1606 * transfer negotiation data structures. 1607 */ 1608 static void 1609 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force) 1610 { 1611 struct ahc_tmode_tstate *tstate; 1612 1613 /* 1614 * Don't clean up our "master" tstate. 1615 * It has our default user settings. 1616 */ 1617 if (((channel == 'B' && scsi_id == ahc->our_id_b) 1618 || (channel == 'A' && scsi_id == ahc->our_id)) 1619 && force == FALSE) 1620 return; 1621 1622 if (channel == 'B') 1623 scsi_id += 8; 1624 tstate = ahc->enabled_targets[scsi_id]; 1625 if (tstate != NULL) 1626 free(tstate, M_DEVBUF); 1627 ahc->enabled_targets[scsi_id] = NULL; 1628 } 1629 #endif 1630 1631 /* 1632 * Called when we have an active connection to a target on the bus, 1633 * this function finds the nearest syncrate to the input period limited 1634 * by the capabilities of the bus connectivity of and sync settings for 1635 * the target. 1636 */ 1637 struct ahc_syncrate * 1638 ahc_devlimited_syncrate(struct ahc_softc *ahc, 1639 struct ahc_initiator_tinfo *tinfo, 1640 u_int *period, u_int *ppr_options, role_t role) 1641 { 1642 struct ahc_transinfo *transinfo; 1643 u_int maxsync; 1644 1645 if ((ahc->features & AHC_ULTRA2) != 0) { 1646 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0 1647 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) { 1648 maxsync = AHC_SYNCRATE_DT; 1649 } else { 1650 maxsync = AHC_SYNCRATE_ULTRA; 1651 /* Can't do DT on an SE bus */ 1652 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1653 } 1654 } else if ((ahc->features & AHC_ULTRA) != 0) { 1655 maxsync = AHC_SYNCRATE_ULTRA; 1656 } else { 1657 maxsync = AHC_SYNCRATE_FAST; 1658 } 1659 /* 1660 * Never allow a value higher than our current goal 1661 * period otherwise we may allow a target initiated 1662 * negotiation to go above the limit as set by the 1663 * user. In the case of an initiator initiated 1664 * sync negotiation, we limit based on the user 1665 * setting. This allows the system to still accept 1666 * incoming negotiations even if target initiated 1667 * negotiation is not performed. 1668 */ 1669 if (role == ROLE_TARGET) 1670 transinfo = &tinfo->user; 1671 else 1672 transinfo = &tinfo->goal; 1673 *ppr_options &= transinfo->ppr_options; 1674 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) { 1675 maxsync = max(maxsync, (u_int)AHC_SYNCRATE_ULTRA2); 1676 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1677 } 1678 if (transinfo->period == 0) { 1679 *period = 0; 1680 *ppr_options = 0; 1681 return (NULL); 1682 } 1683 *period = max(*period, (u_int)transinfo->period); 1684 return (ahc_find_syncrate(ahc, period, ppr_options, maxsync)); 1685 } 1686 1687 /* 1688 * Look up the valid period to SCSIRATE conversion in our table. 1689 * Return the period and offset that should be sent to the target 1690 * if this was the beginning of an SDTR. 1691 */ 1692 struct ahc_syncrate * 1693 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period, 1694 u_int *ppr_options, u_int maxsync) 1695 { 1696 struct ahc_syncrate *syncrate; 1697 1698 if ((ahc->features & AHC_DT) == 0) 1699 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1700 1701 /* Skip all DT only entries if DT is not available */ 1702 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0 1703 && maxsync < AHC_SYNCRATE_ULTRA2) 1704 maxsync = AHC_SYNCRATE_ULTRA2; 1705 1706 /* Now set the maxsync based on the card capabilities 1707 * DT is already done above */ 1708 if ((ahc->features & (AHC_DT | AHC_ULTRA2)) == 0 1709 && maxsync < AHC_SYNCRATE_ULTRA) 1710 maxsync = AHC_SYNCRATE_ULTRA; 1711 if ((ahc->features & (AHC_DT | AHC_ULTRA2 | AHC_ULTRA)) == 0 1712 && maxsync < AHC_SYNCRATE_FAST) 1713 maxsync = AHC_SYNCRATE_FAST; 1714 1715 for (syncrate = &ahc_syncrates[maxsync]; 1716 syncrate->rate != NULL; 1717 syncrate++) { 1718 1719 /* 1720 * The Ultra2 table doesn't go as low 1721 * as for the Fast/Ultra cards. 1722 */ 1723 if ((ahc->features & AHC_ULTRA2) != 0 1724 && (syncrate->sxfr_u2 == 0)) 1725 break; 1726 1727 if (*period <= syncrate->period) { 1728 /* 1729 * When responding to a target that requests 1730 * sync, the requested rate may fall between 1731 * two rates that we can output, but still be 1732 * a rate that we can receive. Because of this, 1733 * we want to respond to the target with 1734 * the same rate that it sent to us even 1735 * if the period we use to send data to it 1736 * is lower. Only lower the response period 1737 * if we must. 1738 */ 1739 if (syncrate == &ahc_syncrates[maxsync]) 1740 *period = syncrate->period; 1741 1742 /* 1743 * At some speeds, we only support 1744 * ST transfers. 1745 */ 1746 if ((syncrate->sxfr_u2 & ST_SXFR) != 0) 1747 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1748 break; 1749 } 1750 } 1751 1752 if ((*period == 0) 1753 || (syncrate->rate == NULL) 1754 || ((ahc->features & AHC_ULTRA2) != 0 1755 && (syncrate->sxfr_u2 == 0))) { 1756 /* Use asynchronous transfers. */ 1757 *period = 0; 1758 syncrate = NULL; 1759 *ppr_options &= ~MSG_EXT_PPR_DT_REQ; 1760 } 1761 return (syncrate); 1762 } 1763 1764 /* 1765 * Convert from an entry in our syncrate table to the SCSI equivalent 1766 * sync "period" factor. 1767 */ 1768 u_int 1769 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync) 1770 { 1771 struct ahc_syncrate *syncrate; 1772 1773 if ((ahc->features & AHC_ULTRA2) != 0) 1774 scsirate &= SXFR_ULTRA2; 1775 else 1776 scsirate &= SXFR; 1777 1778 /* now set maxsync based on card capabilities */ 1779 if ((ahc->features & AHC_DT) == 0 && maxsync < AHC_SYNCRATE_ULTRA2) 1780 maxsync = AHC_SYNCRATE_ULTRA2; 1781 if ((ahc->features & (AHC_DT | AHC_ULTRA2)) == 0 1782 && maxsync < AHC_SYNCRATE_ULTRA) 1783 maxsync = AHC_SYNCRATE_ULTRA; 1784 if ((ahc->features & (AHC_DT | AHC_ULTRA2 | AHC_ULTRA)) == 0 1785 && maxsync < AHC_SYNCRATE_FAST) 1786 maxsync = AHC_SYNCRATE_FAST; 1787 1788 1789 syncrate = &ahc_syncrates[maxsync]; 1790 while (syncrate->rate != NULL) { 1791 1792 if ((ahc->features & AHC_ULTRA2) != 0) { 1793 if (syncrate->sxfr_u2 == 0) 1794 break; 1795 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2)) 1796 return (syncrate->period); 1797 } else if (scsirate == (syncrate->sxfr & SXFR)) { 1798 return (syncrate->period); 1799 } 1800 syncrate++; 1801 } 1802 return (0); /* async */ 1803 } 1804 1805 /* 1806 * Truncate the given synchronous offset to a value the 1807 * current adapter type and syncrate are capable of. 1808 */ 1809 void 1810 ahc_validate_offset(struct ahc_softc *ahc, 1811 struct ahc_initiator_tinfo *tinfo, 1812 struct ahc_syncrate *syncrate, 1813 u_int *offset, int wide, role_t role) 1814 { 1815 u_int maxoffset; 1816 1817 /* Limit offset to what we can do */ 1818 if (syncrate == NULL) { 1819 maxoffset = 0; 1820 } else if ((ahc->features & AHC_ULTRA2) != 0) { 1821 maxoffset = MAX_OFFSET_ULTRA2; 1822 } else { 1823 if (wide) 1824 maxoffset = MAX_OFFSET_16BIT; 1825 else 1826 maxoffset = MAX_OFFSET_8BIT; 1827 } 1828 *offset = min(*offset, maxoffset); 1829 if (tinfo != NULL) { 1830 if (role == ROLE_TARGET) 1831 *offset = min(*offset, (u_int)tinfo->user.offset); 1832 else 1833 *offset = min(*offset, (u_int)tinfo->goal.offset); 1834 } 1835 } 1836 1837 /* 1838 * Truncate the given transfer width parameter to a value the 1839 * current adapter type is capable of. 1840 */ 1841 void 1842 ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo, 1843 u_int *bus_width, role_t role) 1844 { 1845 switch (*bus_width) { 1846 default: 1847 if (ahc->features & AHC_WIDE) { 1848 /* Respond Wide */ 1849 *bus_width = MSG_EXT_WDTR_BUS_16_BIT; 1850 break; 1851 } 1852 /* FALLTHROUGH */ 1853 case MSG_EXT_WDTR_BUS_8_BIT: 1854 *bus_width = MSG_EXT_WDTR_BUS_8_BIT; 1855 break; 1856 } 1857 if (tinfo != NULL) { 1858 if (role == ROLE_TARGET) 1859 *bus_width = min((u_int)tinfo->user.width, *bus_width); 1860 else 1861 *bus_width = min((u_int)tinfo->goal.width, *bus_width); 1862 } 1863 } 1864 1865 /* 1866 * Update the bitmask of targets for which the controller should 1867 * negotiate with at the next convenient oportunity. This currently 1868 * means the next time we send the initial identify messages for 1869 * a new transaction. 1870 */ 1871 int 1872 ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1873 struct ahc_tmode_tstate *tstate, 1874 struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type) 1875 { 1876 u_int auto_negotiate_orig; 1877 1878 auto_negotiate_orig = tstate->auto_negotiate; 1879 if (neg_type == AHC_NEG_ALWAYS) { 1880 /* 1881 * Force our "current" settings to be 1882 * unknown so that unless a bus reset 1883 * occurs the need to renegotiate is 1884 * recorded persistently. 1885 */ 1886 if ((ahc->features & AHC_WIDE) != 0) 1887 tinfo->curr.width = AHC_WIDTH_UNKNOWN; 1888 tinfo->curr.period = AHC_PERIOD_UNKNOWN; 1889 tinfo->curr.offset = AHC_OFFSET_UNKNOWN; 1890 } 1891 if (tinfo->curr.period != tinfo->goal.period 1892 || tinfo->curr.width != tinfo->goal.width 1893 || tinfo->curr.offset != tinfo->goal.offset 1894 || tinfo->curr.ppr_options != tinfo->goal.ppr_options 1895 || (neg_type == AHC_NEG_IF_NON_ASYNC 1896 && (tinfo->goal.offset != 0 1897 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT 1898 || tinfo->goal.ppr_options != 0))) 1899 tstate->auto_negotiate |= devinfo->target_mask; 1900 else 1901 tstate->auto_negotiate &= ~devinfo->target_mask; 1902 1903 return (auto_negotiate_orig != tstate->auto_negotiate); 1904 } 1905 1906 /* 1907 * Update the user/goal/curr tables of synchronous negotiation 1908 * parameters as well as, in the case of a current or active update, 1909 * any data structures on the host controller. In the case of an 1910 * active update, the specified target is currently talking to us on 1911 * the bus, so the transfer parameter update must take effect 1912 * immediately. 1913 */ 1914 void 1915 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 1916 struct ahc_syncrate *syncrate, u_int period, 1917 u_int offset, u_int ppr_options, u_int type, int paused) 1918 { 1919 struct ahc_initiator_tinfo *tinfo; 1920 struct ahc_tmode_tstate *tstate; 1921 u_int old_period; 1922 u_int old_offset; 1923 u_int old_ppr; 1924 int active; 1925 int update_needed; 1926 1927 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 1928 update_needed = 0; 1929 1930 if (syncrate == NULL) { 1931 period = 0; 1932 offset = 0; 1933 } 1934 1935 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 1936 devinfo->target, &tstate); 1937 1938 if ((type & AHC_TRANS_USER) != 0) { 1939 tinfo->user.period = period; 1940 tinfo->user.offset = offset; 1941 tinfo->user.ppr_options = ppr_options; 1942 } 1943 1944 if ((type & AHC_TRANS_GOAL) != 0) { 1945 tinfo->goal.period = period; 1946 tinfo->goal.offset = offset; 1947 tinfo->goal.ppr_options = ppr_options; 1948 } 1949 1950 old_period = tinfo->curr.period; 1951 old_offset = tinfo->curr.offset; 1952 old_ppr = tinfo->curr.ppr_options; 1953 1954 if ((type & AHC_TRANS_CUR) != 0 1955 && (old_period != period 1956 || old_offset != offset 1957 || old_ppr != ppr_options)) { 1958 u_int scsirate; 1959 1960 update_needed++; 1961 scsirate = tinfo->scsirate; 1962 if ((ahc->features & AHC_ULTRA2) != 0) { 1963 1964 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC); 1965 if (syncrate != NULL) { 1966 scsirate |= syncrate->sxfr_u2; 1967 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) 1968 scsirate |= ENABLE_CRC; 1969 else 1970 scsirate |= SINGLE_EDGE; 1971 } 1972 } else { 1973 1974 scsirate &= ~(SXFR|SOFS); 1975 /* 1976 * Ensure Ultra mode is set properly for 1977 * this target. 1978 */ 1979 tstate->ultraenb &= ~devinfo->target_mask; 1980 if (syncrate != NULL) { 1981 if (syncrate->sxfr & ULTRA_SXFR) { 1982 tstate->ultraenb |= 1983 devinfo->target_mask; 1984 } 1985 scsirate |= syncrate->sxfr & SXFR; 1986 scsirate |= offset & SOFS; 1987 } 1988 if (active) { 1989 u_int sxfrctl0; 1990 1991 sxfrctl0 = ahc_inb(ahc, SXFRCTL0); 1992 sxfrctl0 &= ~FAST20; 1993 if (tstate->ultraenb & devinfo->target_mask) 1994 sxfrctl0 |= FAST20; 1995 ahc_outb(ahc, SXFRCTL0, sxfrctl0); 1996 } 1997 } 1998 if (active) { 1999 ahc_outb(ahc, SCSIRATE, scsirate); 2000 if ((ahc->features & AHC_ULTRA2) != 0) 2001 ahc_outb(ahc, SCSIOFFSET, offset); 2002 } 2003 2004 tinfo->scsirate = scsirate; 2005 tinfo->curr.period = period; 2006 tinfo->curr.offset = offset; 2007 tinfo->curr.ppr_options = ppr_options; 2008 2009 ahc_send_async(ahc, devinfo->channel, devinfo->target, 2010 CAM_LUN_WILDCARD, AC_TRANSFER_NEG); 2011 if (bootverbose) { 2012 if (offset != 0) { 2013 printf("%s: target %d synchronous at %sMHz%s, " 2014 "offset = 0x%x\n", ahc_name(ahc), 2015 devinfo->target, syncrate->rate, 2016 (ppr_options & MSG_EXT_PPR_DT_REQ) 2017 ? " DT" : "", offset); 2018 } else { 2019 printf("%s: target %d using " 2020 "asynchronous transfers\n", 2021 ahc_name(ahc), devinfo->target); 2022 } 2023 } 2024 } 2025 2026 update_needed += ahc_update_neg_request(ahc, devinfo, tstate, 2027 tinfo, AHC_NEG_TO_GOAL); 2028 2029 if (update_needed) 2030 ahc_update_pending_scbs(ahc); 2031 } 2032 2033 /* 2034 * Update the user/goal/curr tables of wide negotiation 2035 * parameters as well as, in the case of a current or active update, 2036 * any data structures on the host controller. In the case of an 2037 * active update, the specified target is currently talking to us on 2038 * the bus, so the transfer parameter update must take effect 2039 * immediately. 2040 */ 2041 void 2042 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2043 u_int width, u_int type, int paused) 2044 { 2045 struct ahc_initiator_tinfo *tinfo; 2046 struct ahc_tmode_tstate *tstate; 2047 u_int oldwidth; 2048 int active; 2049 int update_needed; 2050 2051 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE; 2052 update_needed = 0; 2053 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2054 devinfo->target, &tstate); 2055 2056 if ((type & AHC_TRANS_USER) != 0) 2057 tinfo->user.width = width; 2058 2059 if ((type & AHC_TRANS_GOAL) != 0) 2060 tinfo->goal.width = width; 2061 2062 oldwidth = tinfo->curr.width; 2063 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) { 2064 u_int scsirate; 2065 2066 update_needed++; 2067 scsirate = tinfo->scsirate; 2068 scsirate &= ~WIDEXFER; 2069 if (width == MSG_EXT_WDTR_BUS_16_BIT) 2070 scsirate |= WIDEXFER; 2071 2072 tinfo->scsirate = scsirate; 2073 2074 if (active) 2075 ahc_outb(ahc, SCSIRATE, scsirate); 2076 2077 tinfo->curr.width = width; 2078 2079 ahc_send_async(ahc, devinfo->channel, devinfo->target, 2080 CAM_LUN_WILDCARD, AC_TRANSFER_NEG); 2081 if (bootverbose) { 2082 printf("%s: target %d using %dbit transfers\n", 2083 ahc_name(ahc), devinfo->target, 2084 8 * (0x01 << width)); 2085 } 2086 } 2087 2088 update_needed += ahc_update_neg_request(ahc, devinfo, tstate, 2089 tinfo, AHC_NEG_TO_GOAL); 2090 if (update_needed) 2091 ahc_update_pending_scbs(ahc); 2092 } 2093 2094 /* 2095 * Update the current state of tagged queuing for a given target. 2096 */ 2097 static void 2098 ahc_set_tags(struct ahc_softc *ahc, struct scsi_cmnd *cmd, 2099 struct ahc_devinfo *devinfo, ahc_queue_alg alg) 2100 { 2101 struct scsi_device *sdev = cmd->device; 2102 2103 ahc_platform_set_tags(ahc, sdev, devinfo, alg); 2104 ahc_send_async(ahc, devinfo->channel, devinfo->target, 2105 devinfo->lun, AC_TRANSFER_NEG); 2106 } 2107 2108 /* 2109 * When the transfer settings for a connection change, update any 2110 * in-transit SCBs to contain the new data so the hardware will 2111 * be set correctly during future (re)selections. 2112 */ 2113 static void 2114 ahc_update_pending_scbs(struct ahc_softc *ahc) 2115 { 2116 struct scb *pending_scb; 2117 int pending_scb_count; 2118 int i; 2119 int paused; 2120 u_int saved_scbptr; 2121 2122 /* 2123 * Traverse the pending SCB list and ensure that all of the 2124 * SCBs there have the proper settings. 2125 */ 2126 pending_scb_count = 0; 2127 LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) { 2128 struct ahc_devinfo devinfo; 2129 struct hardware_scb *pending_hscb; 2130 struct ahc_initiator_tinfo *tinfo; 2131 struct ahc_tmode_tstate *tstate; 2132 2133 ahc_scb_devinfo(ahc, &devinfo, pending_scb); 2134 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel, 2135 devinfo.our_scsiid, 2136 devinfo.target, &tstate); 2137 pending_hscb = pending_scb->hscb; 2138 pending_hscb->control &= ~ULTRAENB; 2139 if ((tstate->ultraenb & devinfo.target_mask) != 0) 2140 pending_hscb->control |= ULTRAENB; 2141 pending_hscb->scsirate = tinfo->scsirate; 2142 pending_hscb->scsioffset = tinfo->curr.offset; 2143 if ((tstate->auto_negotiate & devinfo.target_mask) == 0 2144 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) { 2145 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE; 2146 pending_hscb->control &= ~MK_MESSAGE; 2147 } 2148 ahc_sync_scb(ahc, pending_scb, 2149 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2150 pending_scb_count++; 2151 } 2152 2153 if (pending_scb_count == 0) 2154 return; 2155 2156 if (ahc_is_paused(ahc)) { 2157 paused = 1; 2158 } else { 2159 paused = 0; 2160 ahc_pause(ahc); 2161 } 2162 2163 saved_scbptr = ahc_inb(ahc, SCBPTR); 2164 /* Ensure that the hscbs down on the card match the new information */ 2165 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 2166 struct hardware_scb *pending_hscb; 2167 u_int control; 2168 u_int scb_tag; 2169 2170 ahc_outb(ahc, SCBPTR, i); 2171 scb_tag = ahc_inb(ahc, SCB_TAG); 2172 pending_scb = ahc_lookup_scb(ahc, scb_tag); 2173 if (pending_scb == NULL) 2174 continue; 2175 2176 pending_hscb = pending_scb->hscb; 2177 control = ahc_inb(ahc, SCB_CONTROL); 2178 control &= ~(ULTRAENB|MK_MESSAGE); 2179 control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE); 2180 ahc_outb(ahc, SCB_CONTROL, control); 2181 ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate); 2182 ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset); 2183 } 2184 ahc_outb(ahc, SCBPTR, saved_scbptr); 2185 2186 if (paused == 0) 2187 ahc_unpause(ahc); 2188 } 2189 2190 /**************************** Pathing Information *****************************/ 2191 static void 2192 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2193 { 2194 u_int saved_scsiid; 2195 role_t role; 2196 int our_id; 2197 2198 if (ahc_inb(ahc, SSTAT0) & TARGET) 2199 role = ROLE_TARGET; 2200 else 2201 role = ROLE_INITIATOR; 2202 2203 if (role == ROLE_TARGET 2204 && (ahc->features & AHC_MULTI_TID) != 0 2205 && (ahc_inb(ahc, SEQ_FLAGS) 2206 & (CMDPHASE_PENDING|TARG_CMD_PENDING|NO_DISCONNECT)) != 0) { 2207 /* We were selected, so pull our id from TARGIDIN */ 2208 our_id = ahc_inb(ahc, TARGIDIN) & OID; 2209 } else if ((ahc->features & AHC_ULTRA2) != 0) 2210 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID; 2211 else 2212 our_id = ahc_inb(ahc, SCSIID) & OID; 2213 2214 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID); 2215 ahc_compile_devinfo(devinfo, 2216 our_id, 2217 SCSIID_TARGET(ahc, saved_scsiid), 2218 ahc_inb(ahc, SAVED_LUN), 2219 SCSIID_CHANNEL(ahc, saved_scsiid), 2220 role); 2221 } 2222 2223 struct ahc_phase_table_entry* 2224 ahc_lookup_phase_entry(int phase) 2225 { 2226 struct ahc_phase_table_entry *entry; 2227 struct ahc_phase_table_entry *last_entry; 2228 2229 /* 2230 * num_phases doesn't include the default entry which 2231 * will be returned if the phase doesn't match. 2232 */ 2233 last_entry = &ahc_phase_table[num_phases]; 2234 for (entry = ahc_phase_table; entry < last_entry; entry++) { 2235 if (phase == entry->phase) 2236 break; 2237 } 2238 return (entry); 2239 } 2240 2241 void 2242 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target, 2243 u_int lun, char channel, role_t role) 2244 { 2245 devinfo->our_scsiid = our_id; 2246 devinfo->target = target; 2247 devinfo->lun = lun; 2248 devinfo->target_offset = target; 2249 devinfo->channel = channel; 2250 devinfo->role = role; 2251 if (channel == 'B') 2252 devinfo->target_offset += 8; 2253 devinfo->target_mask = (0x01 << devinfo->target_offset); 2254 } 2255 2256 void 2257 ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2258 { 2259 printf("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel, 2260 devinfo->target, devinfo->lun); 2261 } 2262 2263 static void 2264 ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2265 struct scb *scb) 2266 { 2267 role_t role; 2268 int our_id; 2269 2270 our_id = SCSIID_OUR_ID(scb->hscb->scsiid); 2271 role = ROLE_INITIATOR; 2272 if ((scb->flags & SCB_TARGET_SCB) != 0) 2273 role = ROLE_TARGET; 2274 ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb), 2275 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role); 2276 } 2277 2278 2279 /************************ Message Phase Processing ****************************/ 2280 static void 2281 ahc_assert_atn(struct ahc_softc *ahc) 2282 { 2283 u_int scsisigo; 2284 2285 scsisigo = ATNO; 2286 if ((ahc->features & AHC_DT) == 0) 2287 scsisigo |= ahc_inb(ahc, SCSISIGI); 2288 ahc_outb(ahc, SCSISIGO, scsisigo); 2289 } 2290 2291 /* 2292 * When an initiator transaction with the MK_MESSAGE flag either reconnects 2293 * or enters the initial message out phase, we are interrupted. Fill our 2294 * outgoing message buffer with the appropriate message and beging handing 2295 * the message phase(s) manually. 2296 */ 2297 static void 2298 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2299 struct scb *scb) 2300 { 2301 /* 2302 * To facilitate adding multiple messages together, 2303 * each routine should increment the index and len 2304 * variables instead of setting them explicitly. 2305 */ 2306 ahc->msgout_index = 0; 2307 ahc->msgout_len = 0; 2308 2309 if ((scb->flags & SCB_DEVICE_RESET) == 0 2310 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) { 2311 u_int identify_msg; 2312 2313 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb); 2314 if ((scb->hscb->control & DISCENB) != 0) 2315 identify_msg |= MSG_IDENTIFY_DISCFLAG; 2316 ahc->msgout_buf[ahc->msgout_index++] = identify_msg; 2317 ahc->msgout_len++; 2318 2319 if ((scb->hscb->control & TAG_ENB) != 0) { 2320 ahc->msgout_buf[ahc->msgout_index++] = 2321 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE); 2322 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag; 2323 ahc->msgout_len += 2; 2324 } 2325 } 2326 2327 if (scb->flags & SCB_DEVICE_RESET) { 2328 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET; 2329 ahc->msgout_len++; 2330 ahc_print_path(ahc, scb); 2331 printf("Bus Device Reset Message Sent\n"); 2332 /* 2333 * Clear our selection hardware in advance of 2334 * the busfree. We may have an entry in the waiting 2335 * Q for this target, and we don't want to go about 2336 * selecting while we handle the busfree and blow it 2337 * away. 2338 */ 2339 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 2340 } else if ((scb->flags & SCB_ABORT) != 0) { 2341 if ((scb->hscb->control & TAG_ENB) != 0) 2342 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG; 2343 else 2344 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT; 2345 ahc->msgout_len++; 2346 ahc_print_path(ahc, scb); 2347 printf("Abort%s Message Sent\n", 2348 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : ""); 2349 /* 2350 * Clear our selection hardware in advance of 2351 * the busfree. We may have an entry in the waiting 2352 * Q for this target, and we don't want to go about 2353 * selecting while we handle the busfree and blow it 2354 * away. 2355 */ 2356 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 2357 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) { 2358 ahc_build_transfer_msg(ahc, devinfo); 2359 } else { 2360 printf("ahc_intr: AWAITING_MSG for an SCB that " 2361 "does not have a waiting message\n"); 2362 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid, 2363 devinfo->target_mask); 2364 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x " 2365 "SCB flags = %x", scb->hscb->tag, scb->hscb->control, 2366 ahc_inb(ahc, MSG_OUT), scb->flags); 2367 } 2368 2369 /* 2370 * Clear the MK_MESSAGE flag from the SCB so we aren't 2371 * asked to send this message again. 2372 */ 2373 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE); 2374 scb->hscb->control &= ~MK_MESSAGE; 2375 ahc->msgout_index = 0; 2376 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2377 } 2378 2379 /* 2380 * Build an appropriate transfer negotiation message for the 2381 * currently active target. 2382 */ 2383 static void 2384 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 2385 { 2386 /* 2387 * We need to initiate transfer negotiations. 2388 * If our current and goal settings are identical, 2389 * we want to renegotiate due to a check condition. 2390 */ 2391 struct ahc_initiator_tinfo *tinfo; 2392 struct ahc_tmode_tstate *tstate; 2393 struct ahc_syncrate *rate; 2394 int dowide; 2395 int dosync; 2396 int doppr; 2397 u_int period; 2398 u_int ppr_options; 2399 u_int offset; 2400 2401 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 2402 devinfo->target, &tstate); 2403 /* 2404 * Filter our period based on the current connection. 2405 * If we can't perform DT transfers on this segment (not in LVD 2406 * mode for instance), then our decision to issue a PPR message 2407 * may change. 2408 */ 2409 period = tinfo->goal.period; 2410 offset = tinfo->goal.offset; 2411 ppr_options = tinfo->goal.ppr_options; 2412 /* Target initiated PPR is not allowed in the SCSI spec */ 2413 if (devinfo->role == ROLE_TARGET) 2414 ppr_options = 0; 2415 rate = ahc_devlimited_syncrate(ahc, tinfo, &period, 2416 &ppr_options, devinfo->role); 2417 dowide = tinfo->curr.width != tinfo->goal.width; 2418 dosync = tinfo->curr.offset != offset || tinfo->curr.period != period; 2419 /* 2420 * Only use PPR if we have options that need it, even if the device 2421 * claims to support it. There might be an expander in the way 2422 * that doesn't. 2423 */ 2424 doppr = ppr_options != 0; 2425 2426 if (!dowide && !dosync && !doppr) { 2427 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT; 2428 dosync = tinfo->goal.offset != 0; 2429 } 2430 2431 if (!dowide && !dosync && !doppr) { 2432 /* 2433 * Force async with a WDTR message if we have a wide bus, 2434 * or just issue an SDTR with a 0 offset. 2435 */ 2436 if ((ahc->features & AHC_WIDE) != 0) 2437 dowide = 1; 2438 else 2439 dosync = 1; 2440 2441 if (bootverbose) { 2442 ahc_print_devinfo(ahc, devinfo); 2443 printf("Ensuring async\n"); 2444 } 2445 } 2446 2447 /* Target initiated PPR is not allowed in the SCSI spec */ 2448 if (devinfo->role == ROLE_TARGET) 2449 doppr = 0; 2450 2451 /* 2452 * Both the PPR message and SDTR message require the 2453 * goal syncrate to be limited to what the target device 2454 * is capable of handling (based on whether an LVD->SE 2455 * expander is on the bus), so combine these two cases. 2456 * Regardless, guarantee that if we are using WDTR and SDTR 2457 * messages that WDTR comes first. 2458 */ 2459 if (doppr || (dosync && !dowide)) { 2460 2461 offset = tinfo->goal.offset; 2462 ahc_validate_offset(ahc, tinfo, rate, &offset, 2463 doppr ? tinfo->goal.width 2464 : tinfo->curr.width, 2465 devinfo->role); 2466 if (doppr) { 2467 ahc_construct_ppr(ahc, devinfo, period, offset, 2468 tinfo->goal.width, ppr_options); 2469 } else { 2470 ahc_construct_sdtr(ahc, devinfo, period, offset); 2471 } 2472 } else { 2473 ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width); 2474 } 2475 } 2476 2477 /* 2478 * Build a synchronous negotiation message in our message 2479 * buffer based on the input parameters. 2480 */ 2481 static void 2482 ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2483 u_int period, u_int offset) 2484 { 2485 if (offset == 0) 2486 period = AHC_ASYNC_XFER_PERIOD; 2487 ahc->msgout_index += spi_populate_sync_msg( 2488 ahc->msgout_buf + ahc->msgout_index, period, offset); 2489 ahc->msgout_len += 5; 2490 if (bootverbose) { 2491 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n", 2492 ahc_name(ahc), devinfo->channel, devinfo->target, 2493 devinfo->lun, period, offset); 2494 } 2495 } 2496 2497 /* 2498 * Build a wide negotiation message in our message 2499 * buffer based on the input parameters. 2500 */ 2501 static void 2502 ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2503 u_int bus_width) 2504 { 2505 ahc->msgout_index += spi_populate_width_msg( 2506 ahc->msgout_buf + ahc->msgout_index, bus_width); 2507 ahc->msgout_len += 4; 2508 if (bootverbose) { 2509 printf("(%s:%c:%d:%d): Sending WDTR %x\n", 2510 ahc_name(ahc), devinfo->channel, devinfo->target, 2511 devinfo->lun, bus_width); 2512 } 2513 } 2514 2515 /* 2516 * Build a parallel protocol request message in our message 2517 * buffer based on the input parameters. 2518 */ 2519 static void 2520 ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 2521 u_int period, u_int offset, u_int bus_width, 2522 u_int ppr_options) 2523 { 2524 if (offset == 0) 2525 period = AHC_ASYNC_XFER_PERIOD; 2526 ahc->msgout_index += spi_populate_ppr_msg( 2527 ahc->msgout_buf + ahc->msgout_index, period, offset, 2528 bus_width, ppr_options); 2529 ahc->msgout_len += 8; 2530 if (bootverbose) { 2531 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, " 2532 "offset %x, ppr_options %x\n", ahc_name(ahc), 2533 devinfo->channel, devinfo->target, devinfo->lun, 2534 bus_width, period, offset, ppr_options); 2535 } 2536 } 2537 2538 /* 2539 * Clear any active message state. 2540 */ 2541 static void 2542 ahc_clear_msg_state(struct ahc_softc *ahc) 2543 { 2544 ahc->msgout_len = 0; 2545 ahc->msgin_index = 0; 2546 ahc->msg_type = MSG_TYPE_NONE; 2547 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) { 2548 /* 2549 * The target didn't care to respond to our 2550 * message request, so clear ATN. 2551 */ 2552 ahc_outb(ahc, CLRSINT1, CLRATNO); 2553 } 2554 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 2555 ahc_outb(ahc, SEQ_FLAGS2, 2556 ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING); 2557 } 2558 2559 static void 2560 ahc_handle_proto_violation(struct ahc_softc *ahc) 2561 { 2562 struct ahc_devinfo devinfo; 2563 struct scb *scb; 2564 u_int scbid; 2565 u_int seq_flags; 2566 u_int curphase; 2567 u_int lastphase; 2568 int found; 2569 2570 ahc_fetch_devinfo(ahc, &devinfo); 2571 scbid = ahc_inb(ahc, SCB_TAG); 2572 scb = ahc_lookup_scb(ahc, scbid); 2573 seq_flags = ahc_inb(ahc, SEQ_FLAGS); 2574 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2575 lastphase = ahc_inb(ahc, LASTPHASE); 2576 if ((seq_flags & NOT_IDENTIFIED) != 0) { 2577 2578 /* 2579 * The reconnecting target either did not send an 2580 * identify message, or did, but we didn't find an SCB 2581 * to match. 2582 */ 2583 ahc_print_devinfo(ahc, &devinfo); 2584 printf("Target did not send an IDENTIFY message. " 2585 "LASTPHASE = 0x%x.\n", lastphase); 2586 scb = NULL; 2587 } else if (scb == NULL) { 2588 /* 2589 * We don't seem to have an SCB active for this 2590 * transaction. Print an error and reset the bus. 2591 */ 2592 ahc_print_devinfo(ahc, &devinfo); 2593 printf("No SCB found during protocol violation\n"); 2594 goto proto_violation_reset; 2595 } else { 2596 ahc_set_transaction_status(scb, CAM_SEQUENCE_FAIL); 2597 if ((seq_flags & NO_CDB_SENT) != 0) { 2598 ahc_print_path(ahc, scb); 2599 printf("No or incomplete CDB sent to device.\n"); 2600 } else if ((ahc_inb(ahc, SCB_CONTROL) & STATUS_RCVD) == 0) { 2601 /* 2602 * The target never bothered to provide status to 2603 * us prior to completing the command. Since we don't 2604 * know the disposition of this command, we must attempt 2605 * to abort it. Assert ATN and prepare to send an abort 2606 * message. 2607 */ 2608 ahc_print_path(ahc, scb); 2609 printf("Completed command without status.\n"); 2610 } else { 2611 ahc_print_path(ahc, scb); 2612 printf("Unknown protocol violation.\n"); 2613 ahc_dump_card_state(ahc); 2614 } 2615 } 2616 if ((lastphase & ~P_DATAIN_DT) == 0 2617 || lastphase == P_COMMAND) { 2618 proto_violation_reset: 2619 /* 2620 * Target either went directly to data/command 2621 * phase or didn't respond to our ATN. 2622 * The only safe thing to do is to blow 2623 * it away with a bus reset. 2624 */ 2625 found = ahc_reset_channel(ahc, 'A', TRUE); 2626 printf("%s: Issued Channel %c Bus Reset. " 2627 "%d SCBs aborted\n", ahc_name(ahc), 'A', found); 2628 } else { 2629 /* 2630 * Leave the selection hardware off in case 2631 * this abort attempt will affect yet to 2632 * be sent commands. 2633 */ 2634 ahc_outb(ahc, SCSISEQ, 2635 ahc_inb(ahc, SCSISEQ) & ~ENSELO); 2636 ahc_assert_atn(ahc); 2637 ahc_outb(ahc, MSG_OUT, HOST_MSG); 2638 if (scb == NULL) { 2639 ahc_print_devinfo(ahc, &devinfo); 2640 ahc->msgout_buf[0] = MSG_ABORT_TASK; 2641 ahc->msgout_len = 1; 2642 ahc->msgout_index = 0; 2643 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2644 } else { 2645 ahc_print_path(ahc, scb); 2646 scb->flags |= SCB_ABORT; 2647 } 2648 printf("Protocol violation %s. Attempting to abort.\n", 2649 ahc_lookup_phase_entry(curphase)->phasemsg); 2650 } 2651 } 2652 2653 /* 2654 * Manual message loop handler. 2655 */ 2656 static void 2657 ahc_handle_message_phase(struct ahc_softc *ahc) 2658 { 2659 struct ahc_devinfo devinfo; 2660 u_int bus_phase; 2661 int end_session; 2662 2663 ahc_fetch_devinfo(ahc, &devinfo); 2664 end_session = FALSE; 2665 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK; 2666 2667 reswitch: 2668 switch (ahc->msg_type) { 2669 case MSG_TYPE_INITIATOR_MSGOUT: 2670 { 2671 int lastbyte; 2672 int phasemis; 2673 int msgdone; 2674 2675 if (ahc->msgout_len == 0) 2676 panic("HOST_MSG_LOOP interrupt with no active message"); 2677 2678 #ifdef AHC_DEBUG 2679 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2680 ahc_print_devinfo(ahc, &devinfo); 2681 printf("INITIATOR_MSG_OUT"); 2682 } 2683 #endif 2684 phasemis = bus_phase != P_MESGOUT; 2685 if (phasemis) { 2686 #ifdef AHC_DEBUG 2687 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2688 printf(" PHASEMIS %s\n", 2689 ahc_lookup_phase_entry(bus_phase) 2690 ->phasemsg); 2691 } 2692 #endif 2693 if (bus_phase == P_MESGIN) { 2694 /* 2695 * Change gears and see if 2696 * this messages is of interest to 2697 * us or should be passed back to 2698 * the sequencer. 2699 */ 2700 ahc_outb(ahc, CLRSINT1, CLRATNO); 2701 ahc->send_msg_perror = FALSE; 2702 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN; 2703 ahc->msgin_index = 0; 2704 goto reswitch; 2705 } 2706 end_session = TRUE; 2707 break; 2708 } 2709 2710 if (ahc->send_msg_perror) { 2711 ahc_outb(ahc, CLRSINT1, CLRATNO); 2712 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2713 #ifdef AHC_DEBUG 2714 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2715 printf(" byte 0x%x\n", ahc->send_msg_perror); 2716 #endif 2717 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR); 2718 break; 2719 } 2720 2721 msgdone = ahc->msgout_index == ahc->msgout_len; 2722 if (msgdone) { 2723 /* 2724 * The target has requested a retry. 2725 * Re-assert ATN, reset our message index to 2726 * 0, and try again. 2727 */ 2728 ahc->msgout_index = 0; 2729 ahc_assert_atn(ahc); 2730 } 2731 2732 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1); 2733 if (lastbyte) { 2734 /* Last byte is signified by dropping ATN */ 2735 ahc_outb(ahc, CLRSINT1, CLRATNO); 2736 } 2737 2738 /* 2739 * Clear our interrupt status and present 2740 * the next byte on the bus. 2741 */ 2742 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2743 #ifdef AHC_DEBUG 2744 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2745 printf(" byte 0x%x\n", 2746 ahc->msgout_buf[ahc->msgout_index]); 2747 #endif 2748 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2749 break; 2750 } 2751 case MSG_TYPE_INITIATOR_MSGIN: 2752 { 2753 int phasemis; 2754 int message_done; 2755 2756 #ifdef AHC_DEBUG 2757 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2758 ahc_print_devinfo(ahc, &devinfo); 2759 printf("INITIATOR_MSG_IN"); 2760 } 2761 #endif 2762 phasemis = bus_phase != P_MESGIN; 2763 if (phasemis) { 2764 #ifdef AHC_DEBUG 2765 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2766 printf(" PHASEMIS %s\n", 2767 ahc_lookup_phase_entry(bus_phase) 2768 ->phasemsg); 2769 } 2770 #endif 2771 ahc->msgin_index = 0; 2772 if (bus_phase == P_MESGOUT 2773 && (ahc->send_msg_perror == TRUE 2774 || (ahc->msgout_len != 0 2775 && ahc->msgout_index == 0))) { 2776 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT; 2777 goto reswitch; 2778 } 2779 end_session = TRUE; 2780 break; 2781 } 2782 2783 /* Pull the byte in without acking it */ 2784 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL); 2785 #ifdef AHC_DEBUG 2786 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) 2787 printf(" byte 0x%x\n", 2788 ahc->msgin_buf[ahc->msgin_index]); 2789 #endif 2790 2791 message_done = ahc_parse_msg(ahc, &devinfo); 2792 2793 if (message_done) { 2794 /* 2795 * Clear our incoming message buffer in case there 2796 * is another message following this one. 2797 */ 2798 ahc->msgin_index = 0; 2799 2800 /* 2801 * If this message illicited a response, 2802 * assert ATN so the target takes us to the 2803 * message out phase. 2804 */ 2805 if (ahc->msgout_len != 0) { 2806 #ifdef AHC_DEBUG 2807 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) { 2808 ahc_print_devinfo(ahc, &devinfo); 2809 printf("Asserting ATN for response\n"); 2810 } 2811 #endif 2812 ahc_assert_atn(ahc); 2813 } 2814 } else 2815 ahc->msgin_index++; 2816 2817 if (message_done == MSGLOOP_TERMINATED) { 2818 end_session = TRUE; 2819 } else { 2820 /* Ack the byte */ 2821 ahc_outb(ahc, CLRSINT1, CLRREQINIT); 2822 ahc_inb(ahc, SCSIDATL); 2823 } 2824 break; 2825 } 2826 case MSG_TYPE_TARGET_MSGIN: 2827 { 2828 int msgdone; 2829 int msgout_request; 2830 2831 if (ahc->msgout_len == 0) 2832 panic("Target MSGIN with no active message"); 2833 2834 /* 2835 * If we interrupted a mesgout session, the initiator 2836 * will not know this until our first REQ. So, we 2837 * only honor mesgout requests after we've sent our 2838 * first byte. 2839 */ 2840 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0 2841 && ahc->msgout_index > 0) 2842 msgout_request = TRUE; 2843 else 2844 msgout_request = FALSE; 2845 2846 if (msgout_request) { 2847 2848 /* 2849 * Change gears and see if 2850 * this messages is of interest to 2851 * us or should be passed back to 2852 * the sequencer. 2853 */ 2854 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT; 2855 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO); 2856 ahc->msgin_index = 0; 2857 /* Dummy read to REQ for first byte */ 2858 ahc_inb(ahc, SCSIDATL); 2859 ahc_outb(ahc, SXFRCTL0, 2860 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2861 break; 2862 } 2863 2864 msgdone = ahc->msgout_index == ahc->msgout_len; 2865 if (msgdone) { 2866 ahc_outb(ahc, SXFRCTL0, 2867 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2868 end_session = TRUE; 2869 break; 2870 } 2871 2872 /* 2873 * Present the next byte on the bus. 2874 */ 2875 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2876 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]); 2877 break; 2878 } 2879 case MSG_TYPE_TARGET_MSGOUT: 2880 { 2881 int lastbyte; 2882 int msgdone; 2883 2884 /* 2885 * The initiator signals that this is 2886 * the last byte by dropping ATN. 2887 */ 2888 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0; 2889 2890 /* 2891 * Read the latched byte, but turn off SPIOEN first 2892 * so that we don't inadvertently cause a REQ for the 2893 * next byte. 2894 */ 2895 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN); 2896 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL); 2897 msgdone = ahc_parse_msg(ahc, &devinfo); 2898 if (msgdone == MSGLOOP_TERMINATED) { 2899 /* 2900 * The message is *really* done in that it caused 2901 * us to go to bus free. The sequencer has already 2902 * been reset at this point, so pull the ejection 2903 * handle. 2904 */ 2905 return; 2906 } 2907 2908 ahc->msgin_index++; 2909 2910 /* 2911 * XXX Read spec about initiator dropping ATN too soon 2912 * and use msgdone to detect it. 2913 */ 2914 if (msgdone == MSGLOOP_MSGCOMPLETE) { 2915 ahc->msgin_index = 0; 2916 2917 /* 2918 * If this message illicited a response, transition 2919 * to the Message in phase and send it. 2920 */ 2921 if (ahc->msgout_len != 0) { 2922 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO); 2923 ahc_outb(ahc, SXFRCTL0, 2924 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2925 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 2926 ahc->msgin_index = 0; 2927 break; 2928 } 2929 } 2930 2931 if (lastbyte) 2932 end_session = TRUE; 2933 else { 2934 /* Ask for the next byte. */ 2935 ahc_outb(ahc, SXFRCTL0, 2936 ahc_inb(ahc, SXFRCTL0) | SPIOEN); 2937 } 2938 2939 break; 2940 } 2941 default: 2942 panic("Unknown REQINIT message type"); 2943 } 2944 2945 if (end_session) { 2946 ahc_clear_msg_state(ahc); 2947 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP); 2948 } else 2949 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP); 2950 } 2951 2952 /* 2953 * See if we sent a particular extended message to the target. 2954 * If "full" is true, return true only if the target saw the full 2955 * message. If "full" is false, return true if the target saw at 2956 * least the first byte of the message. 2957 */ 2958 static int 2959 ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full) 2960 { 2961 int found; 2962 u_int index; 2963 2964 found = FALSE; 2965 index = 0; 2966 2967 while (index < ahc->msgout_len) { 2968 if (ahc->msgout_buf[index] == MSG_EXTENDED) { 2969 u_int end_index; 2970 2971 end_index = index + 1 + ahc->msgout_buf[index + 1]; 2972 if (ahc->msgout_buf[index+2] == msgval 2973 && type == AHCMSG_EXT) { 2974 2975 if (full) { 2976 if (ahc->msgout_index > end_index) 2977 found = TRUE; 2978 } else if (ahc->msgout_index > index) 2979 found = TRUE; 2980 } 2981 index = end_index; 2982 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK 2983 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) { 2984 2985 /* Skip tag type and tag id or residue param*/ 2986 index += 2; 2987 } else { 2988 /* Single byte message */ 2989 if (type == AHCMSG_1B 2990 && ahc->msgout_buf[index] == msgval 2991 && ahc->msgout_index > index) 2992 found = TRUE; 2993 index++; 2994 } 2995 2996 if (found) 2997 break; 2998 } 2999 return (found); 3000 } 3001 3002 /* 3003 * Wait for a complete incoming message, parse it, and respond accordingly. 3004 */ 3005 static int 3006 ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3007 { 3008 struct ahc_initiator_tinfo *tinfo; 3009 struct ahc_tmode_tstate *tstate; 3010 int reject; 3011 int done; 3012 int response; 3013 u_int targ_scsirate; 3014 3015 done = MSGLOOP_IN_PROG; 3016 response = FALSE; 3017 reject = FALSE; 3018 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid, 3019 devinfo->target, &tstate); 3020 targ_scsirate = tinfo->scsirate; 3021 3022 /* 3023 * Parse as much of the message as is available, 3024 * rejecting it if we don't support it. When 3025 * the entire message is available and has been 3026 * handled, return MSGLOOP_MSGCOMPLETE, indicating 3027 * that we have parsed an entire message. 3028 * 3029 * In the case of extended messages, we accept the length 3030 * byte outright and perform more checking once we know the 3031 * extended message type. 3032 */ 3033 switch (ahc->msgin_buf[0]) { 3034 case MSG_DISCONNECT: 3035 case MSG_SAVEDATAPOINTER: 3036 case MSG_CMDCOMPLETE: 3037 case MSG_RESTOREPOINTERS: 3038 case MSG_IGN_WIDE_RESIDUE: 3039 /* 3040 * End our message loop as these are messages 3041 * the sequencer handles on its own. 3042 */ 3043 done = MSGLOOP_TERMINATED; 3044 break; 3045 case MSG_MESSAGE_REJECT: 3046 response = ahc_handle_msg_reject(ahc, devinfo); 3047 /* FALLTHROUGH */ 3048 case MSG_NOOP: 3049 done = MSGLOOP_MSGCOMPLETE; 3050 break; 3051 case MSG_EXTENDED: 3052 { 3053 /* Wait for enough of the message to begin validation */ 3054 if (ahc->msgin_index < 2) 3055 break; 3056 switch (ahc->msgin_buf[2]) { 3057 case MSG_EXT_SDTR: 3058 { 3059 struct ahc_syncrate *syncrate; 3060 u_int period; 3061 u_int ppr_options; 3062 u_int offset; 3063 u_int saved_offset; 3064 3065 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) { 3066 reject = TRUE; 3067 break; 3068 } 3069 3070 /* 3071 * Wait until we have both args before validating 3072 * and acting on this message. 3073 * 3074 * Add one to MSG_EXT_SDTR_LEN to account for 3075 * the extended message preamble. 3076 */ 3077 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1)) 3078 break; 3079 3080 period = ahc->msgin_buf[3]; 3081 ppr_options = 0; 3082 saved_offset = offset = ahc->msgin_buf[4]; 3083 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period, 3084 &ppr_options, 3085 devinfo->role); 3086 ahc_validate_offset(ahc, tinfo, syncrate, &offset, 3087 targ_scsirate & WIDEXFER, 3088 devinfo->role); 3089 if (bootverbose) { 3090 printf("(%s:%c:%d:%d): Received " 3091 "SDTR period %x, offset %x\n\t" 3092 "Filtered to period %x, offset %x\n", 3093 ahc_name(ahc), devinfo->channel, 3094 devinfo->target, devinfo->lun, 3095 ahc->msgin_buf[3], saved_offset, 3096 period, offset); 3097 } 3098 ahc_set_syncrate(ahc, devinfo, 3099 syncrate, period, 3100 offset, ppr_options, 3101 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3102 /*paused*/TRUE); 3103 3104 /* 3105 * See if we initiated Sync Negotiation 3106 * and didn't have to fall down to async 3107 * transfers. 3108 */ 3109 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) { 3110 /* We started it */ 3111 if (saved_offset != offset) { 3112 /* Went too low - force async */ 3113 reject = TRUE; 3114 } 3115 } else { 3116 /* 3117 * Send our own SDTR in reply 3118 */ 3119 if (bootverbose 3120 && devinfo->role == ROLE_INITIATOR) { 3121 printf("(%s:%c:%d:%d): Target " 3122 "Initiated SDTR\n", 3123 ahc_name(ahc), devinfo->channel, 3124 devinfo->target, devinfo->lun); 3125 } 3126 ahc->msgout_index = 0; 3127 ahc->msgout_len = 0; 3128 ahc_construct_sdtr(ahc, devinfo, 3129 period, offset); 3130 ahc->msgout_index = 0; 3131 response = TRUE; 3132 } 3133 done = MSGLOOP_MSGCOMPLETE; 3134 break; 3135 } 3136 case MSG_EXT_WDTR: 3137 { 3138 u_int bus_width; 3139 u_int saved_width; 3140 u_int sending_reply; 3141 3142 sending_reply = FALSE; 3143 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) { 3144 reject = TRUE; 3145 break; 3146 } 3147 3148 /* 3149 * Wait until we have our arg before validating 3150 * and acting on this message. 3151 * 3152 * Add one to MSG_EXT_WDTR_LEN to account for 3153 * the extended message preamble. 3154 */ 3155 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1)) 3156 break; 3157 3158 bus_width = ahc->msgin_buf[3]; 3159 saved_width = bus_width; 3160 ahc_validate_width(ahc, tinfo, &bus_width, 3161 devinfo->role); 3162 if (bootverbose) { 3163 printf("(%s:%c:%d:%d): Received WDTR " 3164 "%x filtered to %x\n", 3165 ahc_name(ahc), devinfo->channel, 3166 devinfo->target, devinfo->lun, 3167 saved_width, bus_width); 3168 } 3169 3170 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) { 3171 /* 3172 * Don't send a WDTR back to the 3173 * target, since we asked first. 3174 * If the width went higher than our 3175 * request, reject it. 3176 */ 3177 if (saved_width > bus_width) { 3178 reject = TRUE; 3179 printf("(%s:%c:%d:%d): requested %dBit " 3180 "transfers. Rejecting...\n", 3181 ahc_name(ahc), devinfo->channel, 3182 devinfo->target, devinfo->lun, 3183 8 * (0x01 << bus_width)); 3184 bus_width = 0; 3185 } 3186 } else { 3187 /* 3188 * Send our own WDTR in reply 3189 */ 3190 if (bootverbose 3191 && devinfo->role == ROLE_INITIATOR) { 3192 printf("(%s:%c:%d:%d): Target " 3193 "Initiated WDTR\n", 3194 ahc_name(ahc), devinfo->channel, 3195 devinfo->target, devinfo->lun); 3196 } 3197 ahc->msgout_index = 0; 3198 ahc->msgout_len = 0; 3199 ahc_construct_wdtr(ahc, devinfo, bus_width); 3200 ahc->msgout_index = 0; 3201 response = TRUE; 3202 sending_reply = TRUE; 3203 } 3204 /* 3205 * After a wide message, we are async, but 3206 * some devices don't seem to honor this portion 3207 * of the spec. Force a renegotiation of the 3208 * sync component of our transfer agreement even 3209 * if our goal is async. By updating our width 3210 * after forcing the negotiation, we avoid 3211 * renegotiating for width. 3212 */ 3213 ahc_update_neg_request(ahc, devinfo, tstate, 3214 tinfo, AHC_NEG_ALWAYS); 3215 ahc_set_width(ahc, devinfo, bus_width, 3216 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3217 /*paused*/TRUE); 3218 if (sending_reply == FALSE && reject == FALSE) { 3219 3220 /* 3221 * We will always have an SDTR to send. 3222 */ 3223 ahc->msgout_index = 0; 3224 ahc->msgout_len = 0; 3225 ahc_build_transfer_msg(ahc, devinfo); 3226 ahc->msgout_index = 0; 3227 response = TRUE; 3228 } 3229 done = MSGLOOP_MSGCOMPLETE; 3230 break; 3231 } 3232 case MSG_EXT_PPR: 3233 { 3234 struct ahc_syncrate *syncrate; 3235 u_int period; 3236 u_int offset; 3237 u_int bus_width; 3238 u_int ppr_options; 3239 u_int saved_width; 3240 u_int saved_offset; 3241 u_int saved_ppr_options; 3242 3243 if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) { 3244 reject = TRUE; 3245 break; 3246 } 3247 3248 /* 3249 * Wait until we have all args before validating 3250 * and acting on this message. 3251 * 3252 * Add one to MSG_EXT_PPR_LEN to account for 3253 * the extended message preamble. 3254 */ 3255 if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1)) 3256 break; 3257 3258 period = ahc->msgin_buf[3]; 3259 offset = ahc->msgin_buf[5]; 3260 bus_width = ahc->msgin_buf[6]; 3261 saved_width = bus_width; 3262 ppr_options = ahc->msgin_buf[7]; 3263 /* 3264 * According to the spec, a DT only 3265 * period factor with no DT option 3266 * set implies async. 3267 */ 3268 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0 3269 && period == 9) 3270 offset = 0; 3271 saved_ppr_options = ppr_options; 3272 saved_offset = offset; 3273 3274 /* 3275 * Mask out any options we don't support 3276 * on any controller. Transfer options are 3277 * only available if we are negotiating wide. 3278 */ 3279 ppr_options &= MSG_EXT_PPR_DT_REQ; 3280 if (bus_width == 0) 3281 ppr_options = 0; 3282 3283 ahc_validate_width(ahc, tinfo, &bus_width, 3284 devinfo->role); 3285 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period, 3286 &ppr_options, 3287 devinfo->role); 3288 ahc_validate_offset(ahc, tinfo, syncrate, 3289 &offset, bus_width, 3290 devinfo->role); 3291 3292 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) { 3293 /* 3294 * If we are unable to do any of the 3295 * requested options (we went too low), 3296 * then we'll have to reject the message. 3297 */ 3298 if (saved_width > bus_width 3299 || saved_offset != offset 3300 || saved_ppr_options != ppr_options) { 3301 reject = TRUE; 3302 period = 0; 3303 offset = 0; 3304 bus_width = 0; 3305 ppr_options = 0; 3306 syncrate = NULL; 3307 } 3308 } else { 3309 if (devinfo->role != ROLE_TARGET) 3310 printf("(%s:%c:%d:%d): Target " 3311 "Initiated PPR\n", 3312 ahc_name(ahc), devinfo->channel, 3313 devinfo->target, devinfo->lun); 3314 else 3315 printf("(%s:%c:%d:%d): Initiator " 3316 "Initiated PPR\n", 3317 ahc_name(ahc), devinfo->channel, 3318 devinfo->target, devinfo->lun); 3319 ahc->msgout_index = 0; 3320 ahc->msgout_len = 0; 3321 ahc_construct_ppr(ahc, devinfo, period, offset, 3322 bus_width, ppr_options); 3323 ahc->msgout_index = 0; 3324 response = TRUE; 3325 } 3326 if (bootverbose) { 3327 printf("(%s:%c:%d:%d): Received PPR width %x, " 3328 "period %x, offset %x,options %x\n" 3329 "\tFiltered to width %x, period %x, " 3330 "offset %x, options %x\n", 3331 ahc_name(ahc), devinfo->channel, 3332 devinfo->target, devinfo->lun, 3333 saved_width, ahc->msgin_buf[3], 3334 saved_offset, saved_ppr_options, 3335 bus_width, period, offset, ppr_options); 3336 } 3337 ahc_set_width(ahc, devinfo, bus_width, 3338 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3339 /*paused*/TRUE); 3340 ahc_set_syncrate(ahc, devinfo, 3341 syncrate, period, 3342 offset, ppr_options, 3343 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3344 /*paused*/TRUE); 3345 done = MSGLOOP_MSGCOMPLETE; 3346 break; 3347 } 3348 default: 3349 /* Unknown extended message. Reject it. */ 3350 reject = TRUE; 3351 break; 3352 } 3353 break; 3354 } 3355 #ifdef AHC_TARGET_MODE 3356 case MSG_BUS_DEV_RESET: 3357 ahc_handle_devreset(ahc, devinfo, 3358 CAM_BDR_SENT, 3359 "Bus Device Reset Received", 3360 /*verbose_level*/0); 3361 ahc_restart(ahc); 3362 done = MSGLOOP_TERMINATED; 3363 break; 3364 case MSG_ABORT_TAG: 3365 case MSG_ABORT: 3366 case MSG_CLEAR_QUEUE: 3367 { 3368 int tag; 3369 3370 /* Target mode messages */ 3371 if (devinfo->role != ROLE_TARGET) { 3372 reject = TRUE; 3373 break; 3374 } 3375 tag = SCB_LIST_NULL; 3376 if (ahc->msgin_buf[0] == MSG_ABORT_TAG) 3377 tag = ahc_inb(ahc, INITIATOR_TAG); 3378 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3379 devinfo->lun, tag, ROLE_TARGET, 3380 CAM_REQ_ABORTED); 3381 3382 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3383 if (tstate != NULL) { 3384 struct ahc_tmode_lstate* lstate; 3385 3386 lstate = tstate->enabled_luns[devinfo->lun]; 3387 if (lstate != NULL) { 3388 ahc_queue_lstate_event(ahc, lstate, 3389 devinfo->our_scsiid, 3390 ahc->msgin_buf[0], 3391 /*arg*/tag); 3392 ahc_send_lstate_events(ahc, lstate); 3393 } 3394 } 3395 ahc_restart(ahc); 3396 done = MSGLOOP_TERMINATED; 3397 break; 3398 } 3399 #endif 3400 case MSG_TERM_IO_PROC: 3401 default: 3402 reject = TRUE; 3403 break; 3404 } 3405 3406 if (reject) { 3407 /* 3408 * Setup to reject the message. 3409 */ 3410 ahc->msgout_index = 0; 3411 ahc->msgout_len = 1; 3412 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT; 3413 done = MSGLOOP_MSGCOMPLETE; 3414 response = TRUE; 3415 } 3416 3417 if (done != MSGLOOP_IN_PROG && !response) 3418 /* Clear the outgoing message buffer */ 3419 ahc->msgout_len = 0; 3420 3421 return (done); 3422 } 3423 3424 /* 3425 * Process a message reject message. 3426 */ 3427 static int 3428 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3429 { 3430 /* 3431 * What we care about here is if we had an 3432 * outstanding SDTR or WDTR message for this 3433 * target. If we did, this is a signal that 3434 * the target is refusing negotiation. 3435 */ 3436 struct scb *scb; 3437 struct ahc_initiator_tinfo *tinfo; 3438 struct ahc_tmode_tstate *tstate; 3439 u_int scb_index; 3440 u_int last_msg; 3441 int response = 0; 3442 3443 scb_index = ahc_inb(ahc, SCB_TAG); 3444 scb = ahc_lookup_scb(ahc, scb_index); 3445 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, 3446 devinfo->our_scsiid, 3447 devinfo->target, &tstate); 3448 /* Might be necessary */ 3449 last_msg = ahc_inb(ahc, LAST_MSG); 3450 3451 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) { 3452 /* 3453 * Target does not support the PPR message. 3454 * Attempt to negotiate SPI-2 style. 3455 */ 3456 if (bootverbose) { 3457 printf("(%s:%c:%d:%d): PPR Rejected. " 3458 "Trying WDTR/SDTR\n", 3459 ahc_name(ahc), devinfo->channel, 3460 devinfo->target, devinfo->lun); 3461 } 3462 tinfo->goal.ppr_options = 0; 3463 tinfo->curr.transport_version = 2; 3464 tinfo->goal.transport_version = 2; 3465 ahc->msgout_index = 0; 3466 ahc->msgout_len = 0; 3467 ahc_build_transfer_msg(ahc, devinfo); 3468 ahc->msgout_index = 0; 3469 response = 1; 3470 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) { 3471 3472 /* note 8bit xfers */ 3473 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using " 3474 "8bit transfers\n", ahc_name(ahc), 3475 devinfo->channel, devinfo->target, devinfo->lun); 3476 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3477 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3478 /*paused*/TRUE); 3479 /* 3480 * No need to clear the sync rate. If the target 3481 * did not accept the command, our syncrate is 3482 * unaffected. If the target started the negotiation, 3483 * but rejected our response, we already cleared the 3484 * sync rate before sending our WDTR. 3485 */ 3486 if (tinfo->goal.offset != tinfo->curr.offset) { 3487 3488 /* Start the sync negotiation */ 3489 ahc->msgout_index = 0; 3490 ahc->msgout_len = 0; 3491 ahc_build_transfer_msg(ahc, devinfo); 3492 ahc->msgout_index = 0; 3493 response = 1; 3494 } 3495 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) { 3496 /* note asynch xfers and clear flag */ 3497 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0, 3498 /*offset*/0, /*ppr_options*/0, 3499 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL, 3500 /*paused*/TRUE); 3501 printf("(%s:%c:%d:%d): refuses synchronous negotiation. " 3502 "Using asynchronous transfers\n", 3503 ahc_name(ahc), devinfo->channel, 3504 devinfo->target, devinfo->lun); 3505 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) { 3506 int tag_type; 3507 int mask; 3508 3509 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK); 3510 3511 if (tag_type == MSG_SIMPLE_TASK) { 3512 printf("(%s:%c:%d:%d): refuses tagged commands. " 3513 "Performing non-tagged I/O\n", ahc_name(ahc), 3514 devinfo->channel, devinfo->target, devinfo->lun); 3515 ahc_set_tags(ahc, scb->io_ctx, devinfo, AHC_QUEUE_NONE); 3516 mask = ~0x23; 3517 } else { 3518 printf("(%s:%c:%d:%d): refuses %s tagged commands. " 3519 "Performing simple queue tagged I/O only\n", 3520 ahc_name(ahc), devinfo->channel, devinfo->target, 3521 devinfo->lun, tag_type == MSG_ORDERED_TASK 3522 ? "ordered" : "head of queue"); 3523 ahc_set_tags(ahc, scb->io_ctx, devinfo, AHC_QUEUE_BASIC); 3524 mask = ~0x03; 3525 } 3526 3527 /* 3528 * Resend the identify for this CCB as the target 3529 * may believe that the selection is invalid otherwise. 3530 */ 3531 ahc_outb(ahc, SCB_CONTROL, 3532 ahc_inb(ahc, SCB_CONTROL) & mask); 3533 scb->hscb->control &= mask; 3534 ahc_set_transaction_tag(scb, /*enabled*/FALSE, 3535 /*type*/MSG_SIMPLE_TASK); 3536 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG); 3537 ahc_assert_atn(ahc); 3538 3539 /* 3540 * This transaction is now at the head of 3541 * the untagged queue for this target. 3542 */ 3543 if ((ahc->flags & AHC_SCB_BTT) == 0) { 3544 struct scb_tailq *untagged_q; 3545 3546 untagged_q = 3547 &(ahc->untagged_queues[devinfo->target_offset]); 3548 TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe); 3549 scb->flags |= SCB_UNTAGGEDQ; 3550 } 3551 ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun), 3552 scb->hscb->tag); 3553 3554 /* 3555 * Requeue all tagged commands for this target 3556 * currently in our posession so they can be 3557 * converted to untagged commands. 3558 */ 3559 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb), 3560 SCB_GET_CHANNEL(ahc, scb), 3561 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL, 3562 ROLE_INITIATOR, CAM_REQUEUE_REQ, 3563 SEARCH_COMPLETE); 3564 } else { 3565 /* 3566 * Otherwise, we ignore it. 3567 */ 3568 printf("%s:%c:%d: Message reject for %x -- ignored\n", 3569 ahc_name(ahc), devinfo->channel, devinfo->target, 3570 last_msg); 3571 } 3572 return (response); 3573 } 3574 3575 /* 3576 * Process an ingnore wide residue message. 3577 */ 3578 static void 3579 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo) 3580 { 3581 u_int scb_index; 3582 struct scb *scb; 3583 3584 scb_index = ahc_inb(ahc, SCB_TAG); 3585 scb = ahc_lookup_scb(ahc, scb_index); 3586 /* 3587 * XXX Actually check data direction in the sequencer? 3588 * Perhaps add datadir to some spare bits in the hscb? 3589 */ 3590 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0 3591 || ahc_get_transfer_dir(scb) != CAM_DIR_IN) { 3592 /* 3593 * Ignore the message if we haven't 3594 * seen an appropriate data phase yet. 3595 */ 3596 } else { 3597 /* 3598 * If the residual occurred on the last 3599 * transfer and the transfer request was 3600 * expected to end on an odd count, do 3601 * nothing. Otherwise, subtract a byte 3602 * and update the residual count accordingly. 3603 */ 3604 uint32_t sgptr; 3605 3606 sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR); 3607 if ((sgptr & SG_LIST_NULL) != 0 3608 && (ahc_inb(ahc, SCB_LUN) & SCB_XFERLEN_ODD) != 0) { 3609 /* 3610 * If the residual occurred on the last 3611 * transfer and the transfer request was 3612 * expected to end on an odd count, do 3613 * nothing. 3614 */ 3615 } else { 3616 struct ahc_dma_seg *sg; 3617 uint32_t data_cnt; 3618 uint32_t data_addr; 3619 uint32_t sglen; 3620 3621 /* Pull in all of the sgptr */ 3622 sgptr = ahc_inl(ahc, SCB_RESIDUAL_SGPTR); 3623 data_cnt = ahc_inl(ahc, SCB_RESIDUAL_DATACNT); 3624 3625 if ((sgptr & SG_LIST_NULL) != 0) { 3626 /* 3627 * The residual data count is not updated 3628 * for the command run to completion case. 3629 * Explicitly zero the count. 3630 */ 3631 data_cnt &= ~AHC_SG_LEN_MASK; 3632 } 3633 3634 data_addr = ahc_inl(ahc, SHADDR); 3635 3636 data_cnt += 1; 3637 data_addr -= 1; 3638 sgptr &= SG_PTR_MASK; 3639 3640 sg = ahc_sg_bus_to_virt(scb, sgptr); 3641 3642 /* 3643 * The residual sg ptr points to the next S/G 3644 * to load so we must go back one. 3645 */ 3646 sg--; 3647 sglen = ahc_le32toh(sg->len) & AHC_SG_LEN_MASK; 3648 if (sg != scb->sg_list 3649 && sglen < (data_cnt & AHC_SG_LEN_MASK)) { 3650 3651 sg--; 3652 sglen = ahc_le32toh(sg->len); 3653 /* 3654 * Preserve High Address and SG_LIST bits 3655 * while setting the count to 1. 3656 */ 3657 data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK)); 3658 data_addr = ahc_le32toh(sg->addr) 3659 + (sglen & AHC_SG_LEN_MASK) - 1; 3660 3661 /* 3662 * Increment sg so it points to the 3663 * "next" sg. 3664 */ 3665 sg++; 3666 sgptr = ahc_sg_virt_to_bus(scb, sg); 3667 } 3668 ahc_outl(ahc, SCB_RESIDUAL_SGPTR, sgptr); 3669 ahc_outl(ahc, SCB_RESIDUAL_DATACNT, data_cnt); 3670 /* 3671 * Toggle the "oddness" of the transfer length 3672 * to handle this mid-transfer ignore wide 3673 * residue. This ensures that the oddness is 3674 * correct for subsequent data transfers. 3675 */ 3676 ahc_outb(ahc, SCB_LUN, 3677 ahc_inb(ahc, SCB_LUN) ^ SCB_XFERLEN_ODD); 3678 } 3679 } 3680 } 3681 3682 3683 /* 3684 * Reinitialize the data pointers for the active transfer 3685 * based on its current residual. 3686 */ 3687 static void 3688 ahc_reinitialize_dataptrs(struct ahc_softc *ahc) 3689 { 3690 struct scb *scb; 3691 struct ahc_dma_seg *sg; 3692 u_int scb_index; 3693 uint32_t sgptr; 3694 uint32_t resid; 3695 uint32_t dataptr; 3696 3697 scb_index = ahc_inb(ahc, SCB_TAG); 3698 scb = ahc_lookup_scb(ahc, scb_index); 3699 sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24) 3700 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16) 3701 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8) 3702 | ahc_inb(ahc, SCB_RESIDUAL_SGPTR); 3703 3704 sgptr &= SG_PTR_MASK; 3705 sg = ahc_sg_bus_to_virt(scb, sgptr); 3706 3707 /* The residual sg_ptr always points to the next sg */ 3708 sg--; 3709 3710 resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16) 3711 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8) 3712 | ahc_inb(ahc, SCB_RESIDUAL_DATACNT); 3713 3714 dataptr = ahc_le32toh(sg->addr) 3715 + (ahc_le32toh(sg->len) & AHC_SG_LEN_MASK) 3716 - resid; 3717 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) { 3718 u_int dscommand1; 3719 3720 dscommand1 = ahc_inb(ahc, DSCOMMAND1); 3721 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0); 3722 ahc_outb(ahc, HADDR, 3723 (ahc_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS); 3724 ahc_outb(ahc, DSCOMMAND1, dscommand1); 3725 } 3726 ahc_outb(ahc, HADDR + 3, dataptr >> 24); 3727 ahc_outb(ahc, HADDR + 2, dataptr >> 16); 3728 ahc_outb(ahc, HADDR + 1, dataptr >> 8); 3729 ahc_outb(ahc, HADDR, dataptr); 3730 ahc_outb(ahc, HCNT + 2, resid >> 16); 3731 ahc_outb(ahc, HCNT + 1, resid >> 8); 3732 ahc_outb(ahc, HCNT, resid); 3733 if ((ahc->features & AHC_ULTRA2) == 0) { 3734 ahc_outb(ahc, STCNT + 2, resid >> 16); 3735 ahc_outb(ahc, STCNT + 1, resid >> 8); 3736 ahc_outb(ahc, STCNT, resid); 3737 } 3738 } 3739 3740 /* 3741 * Handle the effects of issuing a bus device reset message. 3742 */ 3743 static void 3744 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3745 cam_status status, char *message, int verbose_level) 3746 { 3747 #ifdef AHC_TARGET_MODE 3748 struct ahc_tmode_tstate* tstate; 3749 u_int lun; 3750 #endif 3751 int found; 3752 3753 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel, 3754 CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role, 3755 status); 3756 3757 #ifdef AHC_TARGET_MODE 3758 /* 3759 * Send an immediate notify ccb to all target mord peripheral 3760 * drivers affected by this action. 3761 */ 3762 tstate = ahc->enabled_targets[devinfo->our_scsiid]; 3763 if (tstate != NULL) { 3764 for (lun = 0; lun < AHC_NUM_LUNS; lun++) { 3765 struct ahc_tmode_lstate* lstate; 3766 3767 lstate = tstate->enabled_luns[lun]; 3768 if (lstate == NULL) 3769 continue; 3770 3771 ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid, 3772 MSG_BUS_DEV_RESET, /*arg*/0); 3773 ahc_send_lstate_events(ahc, lstate); 3774 } 3775 } 3776 #endif 3777 3778 /* 3779 * Go back to async/narrow transfers and renegotiate. 3780 */ 3781 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT, 3782 AHC_TRANS_CUR, /*paused*/TRUE); 3783 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, 3784 /*period*/0, /*offset*/0, /*ppr_options*/0, 3785 AHC_TRANS_CUR, /*paused*/TRUE); 3786 3787 if (status != CAM_SEL_TIMEOUT) 3788 ahc_send_async(ahc, devinfo->channel, devinfo->target, 3789 CAM_LUN_WILDCARD, AC_SENT_BDR); 3790 3791 if (message != NULL 3792 && (verbose_level <= bootverbose)) 3793 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc), 3794 message, devinfo->channel, devinfo->target, found); 3795 } 3796 3797 #ifdef AHC_TARGET_MODE 3798 static void 3799 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo, 3800 struct scb *scb) 3801 { 3802 3803 /* 3804 * To facilitate adding multiple messages together, 3805 * each routine should increment the index and len 3806 * variables instead of setting them explicitly. 3807 */ 3808 ahc->msgout_index = 0; 3809 ahc->msgout_len = 0; 3810 3811 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0) 3812 ahc_build_transfer_msg(ahc, devinfo); 3813 else 3814 panic("ahc_intr: AWAITING target message with no message"); 3815 3816 ahc->msgout_index = 0; 3817 ahc->msg_type = MSG_TYPE_TARGET_MSGIN; 3818 } 3819 #endif 3820 /**************************** Initialization **********************************/ 3821 /* 3822 * Allocate a controller structure for a new device 3823 * and perform initial initializion. 3824 */ 3825 struct ahc_softc * 3826 ahc_alloc(void *platform_arg, char *name) 3827 { 3828 struct ahc_softc *ahc; 3829 int i; 3830 3831 #ifndef __FreeBSD__ 3832 ahc = malloc(sizeof(*ahc), M_DEVBUF, M_NOWAIT); 3833 if (!ahc) { 3834 printf("aic7xxx: cannot malloc softc!\n"); 3835 free(name, M_DEVBUF); 3836 return NULL; 3837 } 3838 #else 3839 ahc = device_get_softc((device_t)platform_arg); 3840 #endif 3841 memset(ahc, 0, sizeof(*ahc)); 3842 ahc->seep_config = malloc(sizeof(*ahc->seep_config), 3843 M_DEVBUF, M_NOWAIT); 3844 if (ahc->seep_config == NULL) { 3845 #ifndef __FreeBSD__ 3846 free(ahc, M_DEVBUF); 3847 #endif 3848 free(name, M_DEVBUF); 3849 return (NULL); 3850 } 3851 LIST_INIT(&ahc->pending_scbs); 3852 /* We don't know our unit number until the OSM sets it */ 3853 ahc->name = name; 3854 ahc->unit = -1; 3855 ahc->description = NULL; 3856 ahc->channel = 'A'; 3857 ahc->channel_b = 'B'; 3858 ahc->chip = AHC_NONE; 3859 ahc->features = AHC_FENONE; 3860 ahc->bugs = AHC_BUGNONE; 3861 ahc->flags = AHC_FNONE; 3862 /* 3863 * Default to all error reporting enabled with the 3864 * sequencer operating at its fastest speed. 3865 * The bus attach code may modify this. 3866 */ 3867 ahc->seqctl = FASTMODE; 3868 3869 for (i = 0; i < AHC_NUM_TARGETS; i++) 3870 TAILQ_INIT(&ahc->untagged_queues[i]); 3871 if (ahc_platform_alloc(ahc, platform_arg) != 0) { 3872 ahc_free(ahc); 3873 ahc = NULL; 3874 } 3875 return (ahc); 3876 } 3877 3878 int 3879 ahc_softc_init(struct ahc_softc *ahc) 3880 { 3881 3882 /* The IRQMS bit is only valid on VL and EISA chips */ 3883 if ((ahc->chip & AHC_PCI) == 0) 3884 ahc->unpause = ahc_inb(ahc, HCNTRL) & IRQMS; 3885 else 3886 ahc->unpause = 0; 3887 ahc->pause = ahc->unpause | PAUSE; 3888 /* XXX The shared scb data stuff should be deprecated */ 3889 if (ahc->scb_data == NULL) { 3890 ahc->scb_data = malloc(sizeof(*ahc->scb_data), 3891 M_DEVBUF, M_NOWAIT); 3892 if (ahc->scb_data == NULL) 3893 return (ENOMEM); 3894 memset(ahc->scb_data, 0, sizeof(*ahc->scb_data)); 3895 } 3896 3897 return (0); 3898 } 3899 3900 void 3901 ahc_set_unit(struct ahc_softc *ahc, int unit) 3902 { 3903 ahc->unit = unit; 3904 } 3905 3906 void 3907 ahc_set_name(struct ahc_softc *ahc, char *name) 3908 { 3909 if (ahc->name != NULL) 3910 free(ahc->name, M_DEVBUF); 3911 ahc->name = name; 3912 } 3913 3914 void 3915 ahc_free(struct ahc_softc *ahc) 3916 { 3917 int i; 3918 3919 switch (ahc->init_level) { 3920 default: 3921 case 5: 3922 ahc_shutdown(ahc); 3923 /* FALLTHROUGH */ 3924 case 4: 3925 ahc_dmamap_unload(ahc, ahc->shared_data_dmat, 3926 ahc->shared_data_dmamap); 3927 /* FALLTHROUGH */ 3928 case 3: 3929 ahc_dmamem_free(ahc, ahc->shared_data_dmat, ahc->qoutfifo, 3930 ahc->shared_data_dmamap); 3931 ahc_dmamap_destroy(ahc, ahc->shared_data_dmat, 3932 ahc->shared_data_dmamap); 3933 /* FALLTHROUGH */ 3934 case 2: 3935 ahc_dma_tag_destroy(ahc, ahc->shared_data_dmat); 3936 case 1: 3937 #ifndef __linux__ 3938 ahc_dma_tag_destroy(ahc, ahc->buffer_dmat); 3939 #endif 3940 break; 3941 case 0: 3942 break; 3943 } 3944 3945 #ifndef __linux__ 3946 ahc_dma_tag_destroy(ahc, ahc->parent_dmat); 3947 #endif 3948 ahc_platform_free(ahc); 3949 ahc_fini_scbdata(ahc); 3950 for (i = 0; i < AHC_NUM_TARGETS; i++) { 3951 struct ahc_tmode_tstate *tstate; 3952 3953 tstate = ahc->enabled_targets[i]; 3954 if (tstate != NULL) { 3955 #ifdef AHC_TARGET_MODE 3956 int j; 3957 3958 for (j = 0; j < AHC_NUM_LUNS; j++) { 3959 struct ahc_tmode_lstate *lstate; 3960 3961 lstate = tstate->enabled_luns[j]; 3962 if (lstate != NULL) { 3963 xpt_free_path(lstate->path); 3964 free(lstate, M_DEVBUF); 3965 } 3966 } 3967 #endif 3968 free(tstate, M_DEVBUF); 3969 } 3970 } 3971 #ifdef AHC_TARGET_MODE 3972 if (ahc->black_hole != NULL) { 3973 xpt_free_path(ahc->black_hole->path); 3974 free(ahc->black_hole, M_DEVBUF); 3975 } 3976 #endif 3977 if (ahc->name != NULL) 3978 free(ahc->name, M_DEVBUF); 3979 if (ahc->seep_config != NULL) 3980 free(ahc->seep_config, M_DEVBUF); 3981 #ifndef __FreeBSD__ 3982 free(ahc, M_DEVBUF); 3983 #endif 3984 return; 3985 } 3986 3987 void 3988 ahc_shutdown(void *arg) 3989 { 3990 struct ahc_softc *ahc; 3991 int i; 3992 3993 ahc = (struct ahc_softc *)arg; 3994 3995 /* This will reset most registers to 0, but not all */ 3996 ahc_reset(ahc, /*reinit*/FALSE); 3997 ahc_outb(ahc, SCSISEQ, 0); 3998 ahc_outb(ahc, SXFRCTL0, 0); 3999 ahc_outb(ahc, DSPCISTATUS, 0); 4000 4001 for (i = TARG_SCSIRATE; i < SCSICONF; i++) 4002 ahc_outb(ahc, i, 0); 4003 } 4004 4005 /* 4006 * Reset the controller and record some information about it 4007 * that is only available just after a reset. If "reinit" is 4008 * non-zero, this reset occured after initial configuration 4009 * and the caller requests that the chip be fully reinitialized 4010 * to a runable state. Chip interrupts are *not* enabled after 4011 * a reinitialization. The caller must enable interrupts via 4012 * ahc_intr_enable(). 4013 */ 4014 int 4015 ahc_reset(struct ahc_softc *ahc, int reinit) 4016 { 4017 u_int sblkctl; 4018 u_int sxfrctl1_a, sxfrctl1_b; 4019 int error; 4020 int wait; 4021 4022 /* 4023 * Preserve the value of the SXFRCTL1 register for all channels. 4024 * It contains settings that affect termination and we don't want 4025 * to disturb the integrity of the bus. 4026 */ 4027 ahc_pause(ahc); 4028 sxfrctl1_b = 0; 4029 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) { 4030 u_int sblkctl; 4031 4032 /* 4033 * Save channel B's settings in case this chip 4034 * is setup for TWIN channel operation. 4035 */ 4036 sblkctl = ahc_inb(ahc, SBLKCTL); 4037 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 4038 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1); 4039 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 4040 } 4041 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1); 4042 4043 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause); 4044 4045 /* 4046 * Ensure that the reset has finished. We delay 1000us 4047 * prior to reading the register to make sure the chip 4048 * has sufficiently completed its reset to handle register 4049 * accesses. 4050 */ 4051 wait = 1000; 4052 do { 4053 ahc_delay(1000); 4054 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK)); 4055 4056 if (wait == 0) { 4057 printf("%s: WARNING - Failed chip reset! " 4058 "Trying to initialize anyway.\n", ahc_name(ahc)); 4059 } 4060 ahc_outb(ahc, HCNTRL, ahc->pause); 4061 4062 /* Determine channel configuration */ 4063 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE); 4064 /* No Twin Channel PCI cards */ 4065 if ((ahc->chip & AHC_PCI) != 0) 4066 sblkctl &= ~SELBUSB; 4067 switch (sblkctl) { 4068 case 0: 4069 /* Single Narrow Channel */ 4070 break; 4071 case 2: 4072 /* Wide Channel */ 4073 ahc->features |= AHC_WIDE; 4074 break; 4075 case 8: 4076 /* Twin Channel */ 4077 ahc->features |= AHC_TWIN; 4078 break; 4079 default: 4080 printf(" Unsupported adapter type. Ignoring\n"); 4081 return(-1); 4082 } 4083 4084 /* 4085 * Reload sxfrctl1. 4086 * 4087 * We must always initialize STPWEN to 1 before we 4088 * restore the saved values. STPWEN is initialized 4089 * to a tri-state condition which can only be cleared 4090 * by turning it on. 4091 */ 4092 if ((ahc->features & AHC_TWIN) != 0) { 4093 u_int sblkctl; 4094 4095 sblkctl = ahc_inb(ahc, SBLKCTL); 4096 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB); 4097 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b); 4098 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB); 4099 } 4100 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a); 4101 4102 error = 0; 4103 if (reinit != 0) 4104 /* 4105 * If a recovery action has forced a chip reset, 4106 * re-initialize the chip to our liking. 4107 */ 4108 error = ahc->bus_chip_init(ahc); 4109 #ifdef AHC_DUMP_SEQ 4110 else 4111 ahc_dumpseq(ahc); 4112 #endif 4113 4114 return (error); 4115 } 4116 4117 /* 4118 * Determine the number of SCBs available on the controller 4119 */ 4120 int 4121 ahc_probe_scbs(struct ahc_softc *ahc) { 4122 int i; 4123 4124 for (i = 0; i < AHC_SCB_MAX; i++) { 4125 4126 ahc_outb(ahc, SCBPTR, i); 4127 ahc_outb(ahc, SCB_BASE, i); 4128 if (ahc_inb(ahc, SCB_BASE) != i) 4129 break; 4130 ahc_outb(ahc, SCBPTR, 0); 4131 if (ahc_inb(ahc, SCB_BASE) != 0) 4132 break; 4133 } 4134 return (i); 4135 } 4136 4137 static void 4138 ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4139 { 4140 dma_addr_t *baddr; 4141 4142 baddr = (dma_addr_t *)arg; 4143 *baddr = segs->ds_addr; 4144 } 4145 4146 static void 4147 ahc_build_free_scb_list(struct ahc_softc *ahc) 4148 { 4149 int scbsize; 4150 int i; 4151 4152 scbsize = 32; 4153 if ((ahc->flags & AHC_LSCBS_ENABLED) != 0) 4154 scbsize = 64; 4155 4156 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 4157 int j; 4158 4159 ahc_outb(ahc, SCBPTR, i); 4160 4161 /* 4162 * Touch all SCB bytes to avoid parity errors 4163 * should one of our debugging routines read 4164 * an otherwise uninitiatlized byte. 4165 */ 4166 for (j = 0; j < scbsize; j++) 4167 ahc_outb(ahc, SCB_BASE+j, 0xFF); 4168 4169 /* Clear the control byte. */ 4170 ahc_outb(ahc, SCB_CONTROL, 0); 4171 4172 /* Set the next pointer */ 4173 if ((ahc->flags & AHC_PAGESCBS) != 0) 4174 ahc_outb(ahc, SCB_NEXT, i+1); 4175 else 4176 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 4177 4178 /* Make the tag number, SCSIID, and lun invalid */ 4179 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 4180 ahc_outb(ahc, SCB_SCSIID, 0xFF); 4181 ahc_outb(ahc, SCB_LUN, 0xFF); 4182 } 4183 4184 if ((ahc->flags & AHC_PAGESCBS) != 0) { 4185 /* SCB 0 heads the free list. */ 4186 ahc_outb(ahc, FREE_SCBH, 0); 4187 } else { 4188 /* No free list. */ 4189 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL); 4190 } 4191 4192 /* Make sure that the last SCB terminates the free list */ 4193 ahc_outb(ahc, SCBPTR, i-1); 4194 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL); 4195 } 4196 4197 static int 4198 ahc_init_scbdata(struct ahc_softc *ahc) 4199 { 4200 struct scb_data *scb_data; 4201 4202 scb_data = ahc->scb_data; 4203 SLIST_INIT(&scb_data->free_scbs); 4204 SLIST_INIT(&scb_data->sg_maps); 4205 4206 /* Allocate SCB resources */ 4207 scb_data->scbarray = 4208 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX_ALLOC, 4209 M_DEVBUF, M_NOWAIT); 4210 if (scb_data->scbarray == NULL) 4211 return (ENOMEM); 4212 memset(scb_data->scbarray, 0, sizeof(struct scb) * AHC_SCB_MAX_ALLOC); 4213 4214 /* Determine the number of hardware SCBs and initialize them */ 4215 4216 scb_data->maxhscbs = ahc_probe_scbs(ahc); 4217 if (ahc->scb_data->maxhscbs == 0) { 4218 printf("%s: No SCB space found\n", ahc_name(ahc)); 4219 return (ENXIO); 4220 } 4221 4222 /* 4223 * Create our DMA tags. These tags define the kinds of device 4224 * accessible memory allocations and memory mappings we will 4225 * need to perform during normal operation. 4226 * 4227 * Unless we need to further restrict the allocation, we rely 4228 * on the restrictions of the parent dmat, hence the common 4229 * use of MAXADDR and MAXSIZE. 4230 */ 4231 4232 /* DMA tag for our hardware scb structures */ 4233 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, 4234 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4235 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 4236 /*highaddr*/BUS_SPACE_MAXADDR, 4237 /*filter*/NULL, /*filterarg*/NULL, 4238 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb), 4239 /*nsegments*/1, 4240 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 4241 /*flags*/0, &scb_data->hscb_dmat) != 0) { 4242 goto error_exit; 4243 } 4244 4245 scb_data->init_level++; 4246 4247 /* Allocation for our hscbs */ 4248 if (ahc_dmamem_alloc(ahc, scb_data->hscb_dmat, 4249 (void **)&scb_data->hscbs, 4250 BUS_DMA_NOWAIT, &scb_data->hscb_dmamap) != 0) { 4251 goto error_exit; 4252 } 4253 4254 scb_data->init_level++; 4255 4256 /* And permanently map them */ 4257 ahc_dmamap_load(ahc, scb_data->hscb_dmat, scb_data->hscb_dmamap, 4258 scb_data->hscbs, 4259 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb), 4260 ahc_dmamap_cb, &scb_data->hscb_busaddr, /*flags*/0); 4261 4262 scb_data->init_level++; 4263 4264 /* DMA tag for our sense buffers */ 4265 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, 4266 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4267 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 4268 /*highaddr*/BUS_SPACE_MAXADDR, 4269 /*filter*/NULL, /*filterarg*/NULL, 4270 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data), 4271 /*nsegments*/1, 4272 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 4273 /*flags*/0, &scb_data->sense_dmat) != 0) { 4274 goto error_exit; 4275 } 4276 4277 scb_data->init_level++; 4278 4279 /* Allocate them */ 4280 if (ahc_dmamem_alloc(ahc, scb_data->sense_dmat, 4281 (void **)&scb_data->sense, 4282 BUS_DMA_NOWAIT, &scb_data->sense_dmamap) != 0) { 4283 goto error_exit; 4284 } 4285 4286 scb_data->init_level++; 4287 4288 /* And permanently map them */ 4289 ahc_dmamap_load(ahc, scb_data->sense_dmat, scb_data->sense_dmamap, 4290 scb_data->sense, 4291 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data), 4292 ahc_dmamap_cb, &scb_data->sense_busaddr, /*flags*/0); 4293 4294 scb_data->init_level++; 4295 4296 /* DMA tag for our S/G structures. We allocate in page sized chunks */ 4297 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/8, 4298 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4299 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 4300 /*highaddr*/BUS_SPACE_MAXADDR, 4301 /*filter*/NULL, /*filterarg*/NULL, 4302 PAGE_SIZE, /*nsegments*/1, 4303 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 4304 /*flags*/0, &scb_data->sg_dmat) != 0) { 4305 goto error_exit; 4306 } 4307 4308 scb_data->init_level++; 4309 4310 /* Perform initial CCB allocation */ 4311 memset(scb_data->hscbs, 0, 4312 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb)); 4313 ahc_alloc_scbs(ahc); 4314 4315 if (scb_data->numscbs == 0) { 4316 printf("%s: ahc_init_scbdata - " 4317 "Unable to allocate initial scbs\n", 4318 ahc_name(ahc)); 4319 goto error_exit; 4320 } 4321 4322 /* 4323 * Reserve the next queued SCB. 4324 */ 4325 ahc->next_queued_scb = ahc_get_scb(ahc); 4326 4327 /* 4328 * Note that we were successfull 4329 */ 4330 return (0); 4331 4332 error_exit: 4333 4334 return (ENOMEM); 4335 } 4336 4337 static void 4338 ahc_fini_scbdata(struct ahc_softc *ahc) 4339 { 4340 struct scb_data *scb_data; 4341 4342 scb_data = ahc->scb_data; 4343 if (scb_data == NULL) 4344 return; 4345 4346 switch (scb_data->init_level) { 4347 default: 4348 case 7: 4349 { 4350 struct sg_map_node *sg_map; 4351 4352 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) { 4353 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links); 4354 ahc_dmamap_unload(ahc, scb_data->sg_dmat, 4355 sg_map->sg_dmamap); 4356 ahc_dmamem_free(ahc, scb_data->sg_dmat, 4357 sg_map->sg_vaddr, 4358 sg_map->sg_dmamap); 4359 free(sg_map, M_DEVBUF); 4360 } 4361 ahc_dma_tag_destroy(ahc, scb_data->sg_dmat); 4362 } 4363 case 6: 4364 ahc_dmamap_unload(ahc, scb_data->sense_dmat, 4365 scb_data->sense_dmamap); 4366 case 5: 4367 ahc_dmamem_free(ahc, scb_data->sense_dmat, scb_data->sense, 4368 scb_data->sense_dmamap); 4369 ahc_dmamap_destroy(ahc, scb_data->sense_dmat, 4370 scb_data->sense_dmamap); 4371 case 4: 4372 ahc_dma_tag_destroy(ahc, scb_data->sense_dmat); 4373 case 3: 4374 ahc_dmamap_unload(ahc, scb_data->hscb_dmat, 4375 scb_data->hscb_dmamap); 4376 case 2: 4377 ahc_dmamem_free(ahc, scb_data->hscb_dmat, scb_data->hscbs, 4378 scb_data->hscb_dmamap); 4379 ahc_dmamap_destroy(ahc, scb_data->hscb_dmat, 4380 scb_data->hscb_dmamap); 4381 case 1: 4382 ahc_dma_tag_destroy(ahc, scb_data->hscb_dmat); 4383 break; 4384 case 0: 4385 break; 4386 } 4387 if (scb_data->scbarray != NULL) 4388 free(scb_data->scbarray, M_DEVBUF); 4389 } 4390 4391 void 4392 ahc_alloc_scbs(struct ahc_softc *ahc) 4393 { 4394 struct scb_data *scb_data; 4395 struct scb *next_scb; 4396 struct sg_map_node *sg_map; 4397 dma_addr_t physaddr; 4398 struct ahc_dma_seg *segs; 4399 int newcount; 4400 int i; 4401 4402 scb_data = ahc->scb_data; 4403 if (scb_data->numscbs >= AHC_SCB_MAX_ALLOC) 4404 /* Can't allocate any more */ 4405 return; 4406 4407 next_scb = &scb_data->scbarray[scb_data->numscbs]; 4408 4409 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT); 4410 4411 if (sg_map == NULL) 4412 return; 4413 4414 /* Allocate S/G space for the next batch of SCBS */ 4415 if (ahc_dmamem_alloc(ahc, scb_data->sg_dmat, 4416 (void **)&sg_map->sg_vaddr, 4417 BUS_DMA_NOWAIT, &sg_map->sg_dmamap) != 0) { 4418 free(sg_map, M_DEVBUF); 4419 return; 4420 } 4421 4422 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links); 4423 4424 ahc_dmamap_load(ahc, scb_data->sg_dmat, sg_map->sg_dmamap, 4425 sg_map->sg_vaddr, PAGE_SIZE, ahc_dmamap_cb, 4426 &sg_map->sg_physaddr, /*flags*/0); 4427 4428 segs = sg_map->sg_vaddr; 4429 physaddr = sg_map->sg_physaddr; 4430 4431 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg))); 4432 newcount = min(newcount, (AHC_SCB_MAX_ALLOC - scb_data->numscbs)); 4433 for (i = 0; i < newcount; i++) { 4434 struct scb_platform_data *pdata; 4435 #ifndef __linux__ 4436 int error; 4437 #endif 4438 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata), 4439 M_DEVBUF, M_NOWAIT); 4440 if (pdata == NULL) 4441 break; 4442 next_scb->platform_data = pdata; 4443 next_scb->sg_map = sg_map; 4444 next_scb->sg_list = segs; 4445 /* 4446 * The sequencer always starts with the second entry. 4447 * The first entry is embedded in the scb. 4448 */ 4449 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg); 4450 next_scb->ahc_softc = ahc; 4451 next_scb->flags = SCB_FREE; 4452 #ifndef __linux__ 4453 error = ahc_dmamap_create(ahc, ahc->buffer_dmat, /*flags*/0, 4454 &next_scb->dmamap); 4455 if (error != 0) 4456 break; 4457 #endif 4458 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs]; 4459 next_scb->hscb->tag = ahc->scb_data->numscbs; 4460 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs, 4461 next_scb, links.sle); 4462 segs += AHC_NSEG; 4463 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg)); 4464 next_scb++; 4465 ahc->scb_data->numscbs++; 4466 } 4467 } 4468 4469 void 4470 ahc_controller_info(struct ahc_softc *ahc, char *buf) 4471 { 4472 int len; 4473 4474 len = sprintf(buf, "%s: ", ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]); 4475 buf += len; 4476 if ((ahc->features & AHC_TWIN) != 0) 4477 len = sprintf(buf, "Twin Channel, A SCSI Id=%d, " 4478 "B SCSI Id=%d, primary %c, ", 4479 ahc->our_id, ahc->our_id_b, 4480 (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A'); 4481 else { 4482 const char *speed; 4483 const char *type; 4484 4485 speed = ""; 4486 if ((ahc->features & AHC_ULTRA) != 0) { 4487 speed = "Ultra "; 4488 } else if ((ahc->features & AHC_DT) != 0) { 4489 speed = "Ultra160 "; 4490 } else if ((ahc->features & AHC_ULTRA2) != 0) { 4491 speed = "Ultra2 "; 4492 } 4493 if ((ahc->features & AHC_WIDE) != 0) { 4494 type = "Wide"; 4495 } else { 4496 type = "Single"; 4497 } 4498 len = sprintf(buf, "%s%s Channel %c, SCSI Id=%d, ", 4499 speed, type, ahc->channel, ahc->our_id); 4500 } 4501 buf += len; 4502 4503 if ((ahc->flags & AHC_PAGESCBS) != 0) 4504 sprintf(buf, "%d/%d SCBs", 4505 ahc->scb_data->maxhscbs, AHC_MAX_QUEUE); 4506 else 4507 sprintf(buf, "%d SCBs", ahc->scb_data->maxhscbs); 4508 } 4509 4510 int 4511 ahc_chip_init(struct ahc_softc *ahc) 4512 { 4513 int term; 4514 int error; 4515 u_int i; 4516 u_int scsi_conf; 4517 u_int scsiseq_template; 4518 uint32_t physaddr; 4519 4520 ahc_outb(ahc, SEQ_FLAGS, 0); 4521 ahc_outb(ahc, SEQ_FLAGS2, 0); 4522 4523 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/ 4524 if (ahc->features & AHC_TWIN) { 4525 4526 /* 4527 * Setup Channel B first. 4528 */ 4529 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB); 4530 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0; 4531 ahc_outb(ahc, SCSIID, ahc->our_id_b); 4532 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 4533 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 4534 |term|ahc->seltime_b|ENSTIMER|ACTNEGEN); 4535 if ((ahc->features & AHC_ULTRA2) != 0) 4536 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR); 4537 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 4538 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 4539 4540 /* Select Channel A */ 4541 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB); 4542 } 4543 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0; 4544 if ((ahc->features & AHC_ULTRA2) != 0) 4545 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id); 4546 else 4547 ahc_outb(ahc, SCSIID, ahc->our_id); 4548 scsi_conf = ahc_inb(ahc, SCSICONF); 4549 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL)) 4550 |term|ahc->seltime 4551 |ENSTIMER|ACTNEGEN); 4552 if ((ahc->features & AHC_ULTRA2) != 0) 4553 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR); 4554 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR); 4555 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN); 4556 4557 /* There are no untagged SCBs active yet. */ 4558 for (i = 0; i < 16; i++) { 4559 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0)); 4560 if ((ahc->flags & AHC_SCB_BTT) != 0) { 4561 int lun; 4562 4563 /* 4564 * The SCB based BTT allows an entry per 4565 * target and lun pair. 4566 */ 4567 for (lun = 1; lun < AHC_NUM_LUNS; lun++) 4568 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun)); 4569 } 4570 } 4571 4572 /* All of our queues are empty */ 4573 for (i = 0; i < 256; i++) 4574 ahc->qoutfifo[i] = SCB_LIST_NULL; 4575 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD); 4576 4577 for (i = 0; i < 256; i++) 4578 ahc->qinfifo[i] = SCB_LIST_NULL; 4579 4580 if ((ahc->features & AHC_MULTI_TID) != 0) { 4581 ahc_outb(ahc, TARGID, 0); 4582 ahc_outb(ahc, TARGID + 1, 0); 4583 } 4584 4585 /* 4586 * Tell the sequencer where it can find our arrays in memory. 4587 */ 4588 physaddr = ahc->scb_data->hscb_busaddr; 4589 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF); 4590 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF); 4591 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF); 4592 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF); 4593 4594 physaddr = ahc->shared_data_busaddr; 4595 ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF); 4596 ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF); 4597 ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF); 4598 ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF); 4599 4600 /* 4601 * Initialize the group code to command length table. 4602 * This overrides the values in TARG_SCSIRATE, so only 4603 * setup the table after we have processed that information. 4604 */ 4605 ahc_outb(ahc, CMDSIZE_TABLE, 5); 4606 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9); 4607 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9); 4608 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0); 4609 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15); 4610 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11); 4611 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0); 4612 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0); 4613 4614 if ((ahc->features & AHC_HS_MAILBOX) != 0) 4615 ahc_outb(ahc, HS_MAILBOX, 0); 4616 4617 /* Tell the sequencer of our initial queue positions */ 4618 if ((ahc->features & AHC_TARGETMODE) != 0) { 4619 ahc->tqinfifonext = 1; 4620 ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1); 4621 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext); 4622 } 4623 ahc->qinfifonext = 0; 4624 ahc->qoutfifonext = 0; 4625 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 4626 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256); 4627 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 4628 ahc_outb(ahc, SNSCB_QOFF, ahc->qinfifonext); 4629 ahc_outb(ahc, SDSCB_QOFF, 0); 4630 } else { 4631 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 4632 ahc_outb(ahc, QINPOS, ahc->qinfifonext); 4633 ahc_outb(ahc, QOUTPOS, ahc->qoutfifonext); 4634 } 4635 4636 /* We don't have any waiting selections */ 4637 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL); 4638 4639 /* Our disconnection list is empty too */ 4640 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL); 4641 4642 /* Message out buffer starts empty */ 4643 ahc_outb(ahc, MSG_OUT, MSG_NOOP); 4644 4645 /* 4646 * Setup the allowed SCSI Sequences based on operational mode. 4647 * If we are a target, we'll enalbe select in operations once 4648 * we've had a lun enabled. 4649 */ 4650 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP; 4651 if ((ahc->flags & AHC_INITIATORROLE) != 0) 4652 scsiseq_template |= ENRSELI; 4653 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template); 4654 4655 /* Initialize our list of free SCBs. */ 4656 ahc_build_free_scb_list(ahc); 4657 4658 /* 4659 * Tell the sequencer which SCB will be the next one it receives. 4660 */ 4661 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag); 4662 4663 /* 4664 * Load the Sequencer program and Enable the adapter 4665 * in "fast" mode. 4666 */ 4667 if (bootverbose) 4668 printf("%s: Downloading Sequencer Program...", 4669 ahc_name(ahc)); 4670 4671 error = ahc_loadseq(ahc); 4672 if (error != 0) 4673 return (error); 4674 4675 if ((ahc->features & AHC_ULTRA2) != 0) { 4676 int wait; 4677 4678 /* 4679 * Wait for up to 500ms for our transceivers 4680 * to settle. If the adapter does not have 4681 * a cable attached, the transceivers may 4682 * never settle, so don't complain if we 4683 * fail here. 4684 */ 4685 for (wait = 5000; 4686 (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait; 4687 wait--) 4688 ahc_delay(100); 4689 } 4690 ahc_restart(ahc); 4691 return (0); 4692 } 4693 4694 /* 4695 * Start the board, ready for normal operation 4696 */ 4697 int 4698 ahc_init(struct ahc_softc *ahc) 4699 { 4700 int max_targ; 4701 u_int i; 4702 u_int scsi_conf; 4703 u_int ultraenb; 4704 u_int discenable; 4705 u_int tagenable; 4706 size_t driver_data_size; 4707 4708 #ifdef AHC_DEBUG 4709 if ((ahc_debug & AHC_DEBUG_SEQUENCER) != 0) 4710 ahc->flags |= AHC_SEQUENCER_DEBUG; 4711 #endif 4712 4713 #ifdef AHC_PRINT_SRAM 4714 printf("Scratch Ram:"); 4715 for (i = 0x20; i < 0x5f; i++) { 4716 if (((i % 8) == 0) && (i != 0)) { 4717 printf ("\n "); 4718 } 4719 printf (" 0x%x", ahc_inb(ahc, i)); 4720 } 4721 if ((ahc->features & AHC_MORE_SRAM) != 0) { 4722 for (i = 0x70; i < 0x7f; i++) { 4723 if (((i % 8) == 0) && (i != 0)) { 4724 printf ("\n "); 4725 } 4726 printf (" 0x%x", ahc_inb(ahc, i)); 4727 } 4728 } 4729 printf ("\n"); 4730 /* 4731 * Reading uninitialized scratch ram may 4732 * generate parity errors. 4733 */ 4734 ahc_outb(ahc, CLRINT, CLRPARERR); 4735 ahc_outb(ahc, CLRINT, CLRBRKADRINT); 4736 #endif 4737 max_targ = 15; 4738 4739 /* 4740 * Assume we have a board at this stage and it has been reset. 4741 */ 4742 if ((ahc->flags & AHC_USEDEFAULTS) != 0) 4743 ahc->our_id = ahc->our_id_b = 7; 4744 4745 /* 4746 * Default to allowing initiator operations. 4747 */ 4748 ahc->flags |= AHC_INITIATORROLE; 4749 4750 /* 4751 * Only allow target mode features if this unit has them enabled. 4752 */ 4753 if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0) 4754 ahc->features &= ~AHC_TARGETMODE; 4755 4756 #ifndef __linux__ 4757 /* DMA tag for mapping buffers into device visible space. */ 4758 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, 4759 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4760 /*lowaddr*/ahc->flags & AHC_39BIT_ADDRESSING 4761 ? (dma_addr_t)0x7FFFFFFFFFULL 4762 : BUS_SPACE_MAXADDR_32BIT, 4763 /*highaddr*/BUS_SPACE_MAXADDR, 4764 /*filter*/NULL, /*filterarg*/NULL, 4765 /*maxsize*/(AHC_NSEG - 1) * PAGE_SIZE, 4766 /*nsegments*/AHC_NSEG, 4767 /*maxsegsz*/AHC_MAXTRANSFER_SIZE, 4768 /*flags*/BUS_DMA_ALLOCNOW, 4769 &ahc->buffer_dmat) != 0) { 4770 return (ENOMEM); 4771 } 4772 #endif 4773 4774 ahc->init_level++; 4775 4776 /* 4777 * DMA tag for our command fifos and other data in system memory 4778 * the card's sequencer must be able to access. For initiator 4779 * roles, we need to allocate space for the qinfifo and qoutfifo. 4780 * The qinfifo and qoutfifo are composed of 256 1 byte elements. 4781 * When providing for the target mode role, we must additionally 4782 * provide space for the incoming target command fifo and an extra 4783 * byte to deal with a dma bug in some chip versions. 4784 */ 4785 driver_data_size = 2 * 256 * sizeof(uint8_t); 4786 if ((ahc->features & AHC_TARGETMODE) != 0) 4787 driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd) 4788 + /*DMA WideOdd Bug Buffer*/1; 4789 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1, 4790 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1, 4791 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT, 4792 /*highaddr*/BUS_SPACE_MAXADDR, 4793 /*filter*/NULL, /*filterarg*/NULL, 4794 driver_data_size, 4795 /*nsegments*/1, 4796 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT, 4797 /*flags*/0, &ahc->shared_data_dmat) != 0) { 4798 return (ENOMEM); 4799 } 4800 4801 ahc->init_level++; 4802 4803 /* Allocation of driver data */ 4804 if (ahc_dmamem_alloc(ahc, ahc->shared_data_dmat, 4805 (void **)&ahc->qoutfifo, 4806 BUS_DMA_NOWAIT, &ahc->shared_data_dmamap) != 0) { 4807 return (ENOMEM); 4808 } 4809 4810 ahc->init_level++; 4811 4812 /* And permanently map it in */ 4813 ahc_dmamap_load(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap, 4814 ahc->qoutfifo, driver_data_size, ahc_dmamap_cb, 4815 &ahc->shared_data_busaddr, /*flags*/0); 4816 4817 if ((ahc->features & AHC_TARGETMODE) != 0) { 4818 ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo; 4819 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS]; 4820 ahc->dma_bug_buf = ahc->shared_data_busaddr 4821 + driver_data_size - 1; 4822 /* All target command blocks start out invalid. */ 4823 for (i = 0; i < AHC_TMODE_CMDS; i++) 4824 ahc->targetcmds[i].cmd_valid = 0; 4825 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD); 4826 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256]; 4827 } 4828 ahc->qinfifo = &ahc->qoutfifo[256]; 4829 4830 ahc->init_level++; 4831 4832 /* Allocate SCB data now that buffer_dmat is initialized */ 4833 if (ahc->scb_data->maxhscbs == 0) 4834 if (ahc_init_scbdata(ahc) != 0) 4835 return (ENOMEM); 4836 4837 /* 4838 * Allocate a tstate to house information for our 4839 * initiator presence on the bus as well as the user 4840 * data for any target mode initiator. 4841 */ 4842 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) { 4843 printf("%s: unable to allocate ahc_tmode_tstate. " 4844 "Failing attach\n", ahc_name(ahc)); 4845 return (ENOMEM); 4846 } 4847 4848 if ((ahc->features & AHC_TWIN) != 0) { 4849 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) { 4850 printf("%s: unable to allocate ahc_tmode_tstate. " 4851 "Failing attach\n", ahc_name(ahc)); 4852 return (ENOMEM); 4853 } 4854 } 4855 4856 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX_ALLOC) { 4857 ahc->flags |= AHC_PAGESCBS; 4858 } else { 4859 ahc->flags &= ~AHC_PAGESCBS; 4860 } 4861 4862 #ifdef AHC_DEBUG 4863 if (ahc_debug & AHC_SHOW_MISC) { 4864 printf("%s: hardware scb %u bytes; kernel scb %u bytes; " 4865 "ahc_dma %u bytes\n", 4866 ahc_name(ahc), 4867 (u_int)sizeof(struct hardware_scb), 4868 (u_int)sizeof(struct scb), 4869 (u_int)sizeof(struct ahc_dma_seg)); 4870 } 4871 #endif /* AHC_DEBUG */ 4872 4873 /* 4874 * Look at the information that board initialization or 4875 * the board bios has left us. 4876 */ 4877 if (ahc->features & AHC_TWIN) { 4878 scsi_conf = ahc_inb(ahc, SCSICONF + 1); 4879 if ((scsi_conf & RESET_SCSI) != 0 4880 && (ahc->flags & AHC_INITIATORROLE) != 0) 4881 ahc->flags |= AHC_RESET_BUS_B; 4882 } 4883 4884 scsi_conf = ahc_inb(ahc, SCSICONF); 4885 if ((scsi_conf & RESET_SCSI) != 0 4886 && (ahc->flags & AHC_INITIATORROLE) != 0) 4887 ahc->flags |= AHC_RESET_BUS_A; 4888 4889 ultraenb = 0; 4890 tagenable = ALL_TARGETS_MASK; 4891 4892 /* Grab the disconnection disable table and invert it for our needs */ 4893 if ((ahc->flags & AHC_USEDEFAULTS) != 0) { 4894 printf("%s: Host Adapter Bios disabled. Using default SCSI " 4895 "device parameters\n", ahc_name(ahc)); 4896 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B| 4897 AHC_TERM_ENB_A|AHC_TERM_ENB_B; 4898 discenable = ALL_TARGETS_MASK; 4899 if ((ahc->features & AHC_ULTRA) != 0) 4900 ultraenb = ALL_TARGETS_MASK; 4901 } else { 4902 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8) 4903 | ahc_inb(ahc, DISC_DSB)); 4904 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0) 4905 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8) 4906 | ahc_inb(ahc, ULTRA_ENB); 4907 } 4908 4909 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0) 4910 max_targ = 7; 4911 4912 for (i = 0; i <= max_targ; i++) { 4913 struct ahc_initiator_tinfo *tinfo; 4914 struct ahc_tmode_tstate *tstate; 4915 u_int our_id; 4916 u_int target_id; 4917 char channel; 4918 4919 channel = 'A'; 4920 our_id = ahc->our_id; 4921 target_id = i; 4922 if (i > 7 && (ahc->features & AHC_TWIN) != 0) { 4923 channel = 'B'; 4924 our_id = ahc->our_id_b; 4925 target_id = i % 8; 4926 } 4927 tinfo = ahc_fetch_transinfo(ahc, channel, our_id, 4928 target_id, &tstate); 4929 /* Default to async narrow across the board */ 4930 memset(tinfo, 0, sizeof(*tinfo)); 4931 if (ahc->flags & AHC_USEDEFAULTS) { 4932 if ((ahc->features & AHC_WIDE) != 0) 4933 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 4934 4935 /* 4936 * These will be truncated when we determine the 4937 * connection type we have with the target. 4938 */ 4939 tinfo->user.period = ahc_syncrates->period; 4940 tinfo->user.offset = MAX_OFFSET; 4941 } else { 4942 u_int scsirate; 4943 uint16_t mask; 4944 4945 /* Take the settings leftover in scratch RAM. */ 4946 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i); 4947 mask = (0x01 << i); 4948 if ((ahc->features & AHC_ULTRA2) != 0) { 4949 u_int offset; 4950 u_int maxsync; 4951 4952 if ((scsirate & SOFS) == 0x0F) { 4953 /* 4954 * Haven't negotiated yet, 4955 * so the format is different. 4956 */ 4957 scsirate = (scsirate & SXFR) >> 4 4958 | (ultraenb & mask) 4959 ? 0x08 : 0x0 4960 | (scsirate & WIDEXFER); 4961 offset = MAX_OFFSET_ULTRA2; 4962 } else 4963 offset = ahc_inb(ahc, TARG_OFFSET + i); 4964 if ((scsirate & ~WIDEXFER) == 0 && offset != 0) 4965 /* Set to the lowest sync rate, 5MHz */ 4966 scsirate |= 0x1c; 4967 maxsync = AHC_SYNCRATE_ULTRA2; 4968 if ((ahc->features & AHC_DT) != 0) 4969 maxsync = AHC_SYNCRATE_DT; 4970 tinfo->user.period = 4971 ahc_find_period(ahc, scsirate, maxsync); 4972 if (offset == 0) 4973 tinfo->user.period = 0; 4974 else 4975 tinfo->user.offset = MAX_OFFSET; 4976 if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/ 4977 && (ahc->features & AHC_DT) != 0) 4978 tinfo->user.ppr_options = 4979 MSG_EXT_PPR_DT_REQ; 4980 } else if ((scsirate & SOFS) != 0) { 4981 if ((scsirate & SXFR) == 0x40 4982 && (ultraenb & mask) != 0) { 4983 /* Treat 10MHz as a non-ultra speed */ 4984 scsirate &= ~SXFR; 4985 ultraenb &= ~mask; 4986 } 4987 tinfo->user.period = 4988 ahc_find_period(ahc, scsirate, 4989 (ultraenb & mask) 4990 ? AHC_SYNCRATE_ULTRA 4991 : AHC_SYNCRATE_FAST); 4992 if (tinfo->user.period != 0) 4993 tinfo->user.offset = MAX_OFFSET; 4994 } 4995 if (tinfo->user.period == 0) 4996 tinfo->user.offset = 0; 4997 if ((scsirate & WIDEXFER) != 0 4998 && (ahc->features & AHC_WIDE) != 0) 4999 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT; 5000 tinfo->user.protocol_version = 4; 5001 if ((ahc->features & AHC_DT) != 0) 5002 tinfo->user.transport_version = 3; 5003 else 5004 tinfo->user.transport_version = 2; 5005 tinfo->goal.protocol_version = 2; 5006 tinfo->goal.transport_version = 2; 5007 tinfo->curr.protocol_version = 2; 5008 tinfo->curr.transport_version = 2; 5009 } 5010 tstate->ultraenb = 0; 5011 } 5012 ahc->user_discenable = discenable; 5013 ahc->user_tagenable = tagenable; 5014 5015 return (ahc->bus_chip_init(ahc)); 5016 } 5017 5018 void 5019 ahc_intr_enable(struct ahc_softc *ahc, int enable) 5020 { 5021 u_int hcntrl; 5022 5023 hcntrl = ahc_inb(ahc, HCNTRL); 5024 hcntrl &= ~INTEN; 5025 ahc->pause &= ~INTEN; 5026 ahc->unpause &= ~INTEN; 5027 if (enable) { 5028 hcntrl |= INTEN; 5029 ahc->pause |= INTEN; 5030 ahc->unpause |= INTEN; 5031 } 5032 ahc_outb(ahc, HCNTRL, hcntrl); 5033 } 5034 5035 /* 5036 * Ensure that the card is paused in a location 5037 * outside of all critical sections and that all 5038 * pending work is completed prior to returning. 5039 * This routine should only be called from outside 5040 * an interrupt context. 5041 */ 5042 void 5043 ahc_pause_and_flushwork(struct ahc_softc *ahc) 5044 { 5045 int intstat; 5046 int maxloops; 5047 int paused; 5048 5049 maxloops = 1000; 5050 ahc->flags |= AHC_ALL_INTERRUPTS; 5051 paused = FALSE; 5052 do { 5053 if (paused) { 5054 ahc_unpause(ahc); 5055 /* 5056 * Give the sequencer some time to service 5057 * any active selections. 5058 */ 5059 ahc_delay(500); 5060 } 5061 ahc_intr(ahc); 5062 ahc_pause(ahc); 5063 paused = TRUE; 5064 ahc_outb(ahc, SCSISEQ, ahc_inb(ahc, SCSISEQ) & ~ENSELO); 5065 intstat = ahc_inb(ahc, INTSTAT); 5066 if ((intstat & INT_PEND) == 0) { 5067 ahc_clear_critical_section(ahc); 5068 intstat = ahc_inb(ahc, INTSTAT); 5069 } 5070 } while (--maxloops 5071 && (intstat != 0xFF || (ahc->features & AHC_REMOVABLE) == 0) 5072 && ((intstat & INT_PEND) != 0 5073 || (ahc_inb(ahc, SSTAT0) & (SELDO|SELINGO)) != 0)); 5074 if (maxloops == 0) { 5075 printf("Infinite interrupt loop, INTSTAT = %x", 5076 ahc_inb(ahc, INTSTAT)); 5077 } 5078 ahc_platform_flushwork(ahc); 5079 ahc->flags &= ~AHC_ALL_INTERRUPTS; 5080 } 5081 5082 #ifdef CONFIG_PM 5083 int 5084 ahc_suspend(struct ahc_softc *ahc) 5085 { 5086 5087 ahc_pause_and_flushwork(ahc); 5088 5089 if (LIST_FIRST(&ahc->pending_scbs) != NULL) { 5090 ahc_unpause(ahc); 5091 return (EBUSY); 5092 } 5093 5094 #ifdef AHC_TARGET_MODE 5095 /* 5096 * XXX What about ATIOs that have not yet been serviced? 5097 * Perhaps we should just refuse to be suspended if we 5098 * are acting in a target role. 5099 */ 5100 if (ahc->pending_device != NULL) { 5101 ahc_unpause(ahc); 5102 return (EBUSY); 5103 } 5104 #endif 5105 ahc_shutdown(ahc); 5106 return (0); 5107 } 5108 5109 int 5110 ahc_resume(struct ahc_softc *ahc) 5111 { 5112 5113 ahc_reset(ahc, /*reinit*/TRUE); 5114 ahc_intr_enable(ahc, TRUE); 5115 ahc_restart(ahc); 5116 return (0); 5117 } 5118 #endif 5119 /************************** Busy Target Table *********************************/ 5120 /* 5121 * Return the untagged transaction id for a given target/channel lun. 5122 * Optionally, clear the entry. 5123 */ 5124 u_int 5125 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl) 5126 { 5127 u_int scbid; 5128 u_int target_offset; 5129 5130 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5131 u_int saved_scbptr; 5132 5133 saved_scbptr = ahc_inb(ahc, SCBPTR); 5134 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5135 scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl)); 5136 ahc_outb(ahc, SCBPTR, saved_scbptr); 5137 } else { 5138 target_offset = TCL_TARGET_OFFSET(tcl); 5139 scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset); 5140 } 5141 5142 return (scbid); 5143 } 5144 5145 void 5146 ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl) 5147 { 5148 u_int target_offset; 5149 5150 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5151 u_int saved_scbptr; 5152 5153 saved_scbptr = ahc_inb(ahc, SCBPTR); 5154 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5155 ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL); 5156 ahc_outb(ahc, SCBPTR, saved_scbptr); 5157 } else { 5158 target_offset = TCL_TARGET_OFFSET(tcl); 5159 ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL); 5160 } 5161 } 5162 5163 void 5164 ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid) 5165 { 5166 u_int target_offset; 5167 5168 if ((ahc->flags & AHC_SCB_BTT) != 0) { 5169 u_int saved_scbptr; 5170 5171 saved_scbptr = ahc_inb(ahc, SCBPTR); 5172 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl)); 5173 ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid); 5174 ahc_outb(ahc, SCBPTR, saved_scbptr); 5175 } else { 5176 target_offset = TCL_TARGET_OFFSET(tcl); 5177 ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid); 5178 } 5179 } 5180 5181 /************************** SCB and SCB queue management **********************/ 5182 int 5183 ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target, 5184 char channel, int lun, u_int tag, role_t role) 5185 { 5186 int targ = SCB_GET_TARGET(ahc, scb); 5187 char chan = SCB_GET_CHANNEL(ahc, scb); 5188 int slun = SCB_GET_LUN(scb); 5189 int match; 5190 5191 match = ((chan == channel) || (channel == ALL_CHANNELS)); 5192 if (match != 0) 5193 match = ((targ == target) || (target == CAM_TARGET_WILDCARD)); 5194 if (match != 0) 5195 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD)); 5196 if (match != 0) { 5197 #ifdef AHC_TARGET_MODE 5198 int group; 5199 5200 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code); 5201 if (role == ROLE_INITIATOR) { 5202 match = (group != XPT_FC_GROUP_TMODE) 5203 && ((tag == scb->hscb->tag) 5204 || (tag == SCB_LIST_NULL)); 5205 } else if (role == ROLE_TARGET) { 5206 match = (group == XPT_FC_GROUP_TMODE) 5207 && ((tag == scb->io_ctx->csio.tag_id) 5208 || (tag == SCB_LIST_NULL)); 5209 } 5210 #else /* !AHC_TARGET_MODE */ 5211 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL)); 5212 #endif /* AHC_TARGET_MODE */ 5213 } 5214 5215 return match; 5216 } 5217 5218 void 5219 ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb) 5220 { 5221 int target; 5222 char channel; 5223 int lun; 5224 5225 target = SCB_GET_TARGET(ahc, scb); 5226 lun = SCB_GET_LUN(scb); 5227 channel = SCB_GET_CHANNEL(ahc, scb); 5228 5229 ahc_search_qinfifo(ahc, target, channel, lun, 5230 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN, 5231 CAM_REQUEUE_REQ, SEARCH_COMPLETE); 5232 5233 ahc_platform_freeze_devq(ahc, scb); 5234 } 5235 5236 void 5237 ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb) 5238 { 5239 struct scb *prev_scb; 5240 5241 prev_scb = NULL; 5242 if (ahc_qinfifo_count(ahc) != 0) { 5243 u_int prev_tag; 5244 uint8_t prev_pos; 5245 5246 prev_pos = ahc->qinfifonext - 1; 5247 prev_tag = ahc->qinfifo[prev_pos]; 5248 prev_scb = ahc_lookup_scb(ahc, prev_tag); 5249 } 5250 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5251 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5252 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 5253 } else { 5254 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 5255 } 5256 } 5257 5258 static void 5259 ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb, 5260 struct scb *scb) 5261 { 5262 if (prev_scb == NULL) { 5263 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag); 5264 } else { 5265 prev_scb->hscb->next = scb->hscb->tag; 5266 ahc_sync_scb(ahc, prev_scb, 5267 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 5268 } 5269 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag; 5270 scb->hscb->next = ahc->next_queued_scb->hscb->tag; 5271 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 5272 } 5273 5274 static int 5275 ahc_qinfifo_count(struct ahc_softc *ahc) 5276 { 5277 uint8_t qinpos; 5278 uint8_t diff; 5279 5280 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5281 qinpos = ahc_inb(ahc, SNSCB_QOFF); 5282 ahc_outb(ahc, SNSCB_QOFF, qinpos); 5283 } else 5284 qinpos = ahc_inb(ahc, QINPOS); 5285 diff = ahc->qinfifonext - qinpos; 5286 return (diff); 5287 } 5288 5289 int 5290 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel, 5291 int lun, u_int tag, role_t role, uint32_t status, 5292 ahc_search_action action) 5293 { 5294 struct scb *scb; 5295 struct scb *prev_scb; 5296 uint8_t qinstart; 5297 uint8_t qinpos; 5298 uint8_t qintail; 5299 uint8_t next; 5300 uint8_t prev; 5301 uint8_t curscbptr; 5302 int found; 5303 int have_qregs; 5304 5305 qintail = ahc->qinfifonext; 5306 have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0; 5307 if (have_qregs) { 5308 qinstart = ahc_inb(ahc, SNSCB_QOFF); 5309 ahc_outb(ahc, SNSCB_QOFF, qinstart); 5310 } else 5311 qinstart = ahc_inb(ahc, QINPOS); 5312 qinpos = qinstart; 5313 found = 0; 5314 prev_scb = NULL; 5315 5316 if (action == SEARCH_COMPLETE) { 5317 /* 5318 * Don't attempt to run any queued untagged transactions 5319 * until we are done with the abort process. 5320 */ 5321 ahc_freeze_untagged_queues(ahc); 5322 } 5323 5324 /* 5325 * Start with an empty queue. Entries that are not chosen 5326 * for removal will be re-added to the queue as we go. 5327 */ 5328 ahc->qinfifonext = qinpos; 5329 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag); 5330 5331 while (qinpos != qintail) { 5332 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]); 5333 if (scb == NULL) { 5334 printf("qinpos = %d, SCB index = %d\n", 5335 qinpos, ahc->qinfifo[qinpos]); 5336 panic("Loop 1\n"); 5337 } 5338 5339 if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) { 5340 /* 5341 * We found an scb that needs to be acted on. 5342 */ 5343 found++; 5344 switch (action) { 5345 case SEARCH_COMPLETE: 5346 { 5347 cam_status ostat; 5348 cam_status cstat; 5349 5350 ostat = ahc_get_transaction_status(scb); 5351 if (ostat == CAM_REQ_INPROG) 5352 ahc_set_transaction_status(scb, status); 5353 cstat = ahc_get_transaction_status(scb); 5354 if (cstat != CAM_REQ_CMP) 5355 ahc_freeze_scb(scb); 5356 if ((scb->flags & SCB_ACTIVE) == 0) 5357 printf("Inactive SCB in qinfifo\n"); 5358 ahc_done(ahc, scb); 5359 5360 /* FALLTHROUGH */ 5361 } 5362 case SEARCH_REMOVE: 5363 break; 5364 case SEARCH_COUNT: 5365 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5366 prev_scb = scb; 5367 break; 5368 } 5369 } else { 5370 ahc_qinfifo_requeue(ahc, prev_scb, scb); 5371 prev_scb = scb; 5372 } 5373 qinpos++; 5374 } 5375 5376 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 5377 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext); 5378 } else { 5379 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext); 5380 } 5381 5382 if (action != SEARCH_COUNT 5383 && (found != 0) 5384 && (qinstart != ahc->qinfifonext)) { 5385 /* 5386 * The sequencer may be in the process of dmaing 5387 * down the SCB at the beginning of the queue. 5388 * This could be problematic if either the first, 5389 * or the second SCB is removed from the queue 5390 * (the first SCB includes a pointer to the "next" 5391 * SCB to dma). If we have removed any entries, swap 5392 * the first element in the queue with the next HSCB 5393 * so the sequencer will notice that NEXT_QUEUED_SCB 5394 * has changed during its dma attempt and will retry 5395 * the DMA. 5396 */ 5397 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]); 5398 5399 if (scb == NULL) { 5400 printf("found = %d, qinstart = %d, qinfifionext = %d\n", 5401 found, qinstart, ahc->qinfifonext); 5402 panic("First/Second Qinfifo fixup\n"); 5403 } 5404 /* 5405 * ahc_swap_with_next_hscb forces our next pointer to 5406 * point to the reserved SCB for future commands. Save 5407 * and restore our original next pointer to maintain 5408 * queue integrity. 5409 */ 5410 next = scb->hscb->next; 5411 ahc->scb_data->scbindex[scb->hscb->tag] = NULL; 5412 ahc_swap_with_next_hscb(ahc, scb); 5413 scb->hscb->next = next; 5414 ahc->qinfifo[qinstart] = scb->hscb->tag; 5415 5416 /* Tell the card about the new head of the qinfifo. */ 5417 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag); 5418 5419 /* Fixup the tail "next" pointer. */ 5420 qintail = ahc->qinfifonext - 1; 5421 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]); 5422 scb->hscb->next = ahc->next_queued_scb->hscb->tag; 5423 } 5424 5425 /* 5426 * Search waiting for selection list. 5427 */ 5428 curscbptr = ahc_inb(ahc, SCBPTR); 5429 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */ 5430 prev = SCB_LIST_NULL; 5431 5432 while (next != SCB_LIST_NULL) { 5433 uint8_t scb_index; 5434 5435 ahc_outb(ahc, SCBPTR, next); 5436 scb_index = ahc_inb(ahc, SCB_TAG); 5437 if (scb_index >= ahc->scb_data->numscbs) { 5438 printf("Waiting List inconsistency. " 5439 "SCB index == %d, yet numscbs == %d.", 5440 scb_index, ahc->scb_data->numscbs); 5441 ahc_dump_card_state(ahc); 5442 panic("for safety"); 5443 } 5444 scb = ahc_lookup_scb(ahc, scb_index); 5445 if (scb == NULL) { 5446 printf("scb_index = %d, next = %d\n", 5447 scb_index, next); 5448 panic("Waiting List traversal\n"); 5449 } 5450 if (ahc_match_scb(ahc, scb, target, channel, 5451 lun, SCB_LIST_NULL, role)) { 5452 /* 5453 * We found an scb that needs to be acted on. 5454 */ 5455 found++; 5456 switch (action) { 5457 case SEARCH_COMPLETE: 5458 { 5459 cam_status ostat; 5460 cam_status cstat; 5461 5462 ostat = ahc_get_transaction_status(scb); 5463 if (ostat == CAM_REQ_INPROG) 5464 ahc_set_transaction_status(scb, 5465 status); 5466 cstat = ahc_get_transaction_status(scb); 5467 if (cstat != CAM_REQ_CMP) 5468 ahc_freeze_scb(scb); 5469 if ((scb->flags & SCB_ACTIVE) == 0) 5470 printf("Inactive SCB in Waiting List\n"); 5471 ahc_done(ahc, scb); 5472 /* FALLTHROUGH */ 5473 } 5474 case SEARCH_REMOVE: 5475 next = ahc_rem_wscb(ahc, next, prev); 5476 break; 5477 case SEARCH_COUNT: 5478 prev = next; 5479 next = ahc_inb(ahc, SCB_NEXT); 5480 break; 5481 } 5482 } else { 5483 5484 prev = next; 5485 next = ahc_inb(ahc, SCB_NEXT); 5486 } 5487 } 5488 ahc_outb(ahc, SCBPTR, curscbptr); 5489 5490 found += ahc_search_untagged_queues(ahc, /*ahc_io_ctx_t*/NULL, target, 5491 channel, lun, status, action); 5492 5493 if (action == SEARCH_COMPLETE) 5494 ahc_release_untagged_queues(ahc); 5495 return (found); 5496 } 5497 5498 int 5499 ahc_search_untagged_queues(struct ahc_softc *ahc, ahc_io_ctx_t ctx, 5500 int target, char channel, int lun, uint32_t status, 5501 ahc_search_action action) 5502 { 5503 struct scb *scb; 5504 int maxtarget; 5505 int found; 5506 int i; 5507 5508 if (action == SEARCH_COMPLETE) { 5509 /* 5510 * Don't attempt to run any queued untagged transactions 5511 * until we are done with the abort process. 5512 */ 5513 ahc_freeze_untagged_queues(ahc); 5514 } 5515 5516 found = 0; 5517 i = 0; 5518 if ((ahc->flags & AHC_SCB_BTT) == 0) { 5519 5520 maxtarget = 16; 5521 if (target != CAM_TARGET_WILDCARD) { 5522 5523 i = target; 5524 if (channel == 'B') 5525 i += 8; 5526 maxtarget = i + 1; 5527 } 5528 } else { 5529 maxtarget = 0; 5530 } 5531 5532 for (; i < maxtarget; i++) { 5533 struct scb_tailq *untagged_q; 5534 struct scb *next_scb; 5535 5536 untagged_q = &(ahc->untagged_queues[i]); 5537 next_scb = TAILQ_FIRST(untagged_q); 5538 while (next_scb != NULL) { 5539 5540 scb = next_scb; 5541 next_scb = TAILQ_NEXT(scb, links.tqe); 5542 5543 /* 5544 * The head of the list may be the currently 5545 * active untagged command for a device. 5546 * We're only searching for commands that 5547 * have not been started. A transaction 5548 * marked active but still in the qinfifo 5549 * is removed by the qinfifo scanning code 5550 * above. 5551 */ 5552 if ((scb->flags & SCB_ACTIVE) != 0) 5553 continue; 5554 5555 if (ahc_match_scb(ahc, scb, target, channel, lun, 5556 SCB_LIST_NULL, ROLE_INITIATOR) == 0 5557 || (ctx != NULL && ctx != scb->io_ctx)) 5558 continue; 5559 5560 /* 5561 * We found an scb that needs to be acted on. 5562 */ 5563 found++; 5564 switch (action) { 5565 case SEARCH_COMPLETE: 5566 { 5567 cam_status ostat; 5568 cam_status cstat; 5569 5570 ostat = ahc_get_transaction_status(scb); 5571 if (ostat == CAM_REQ_INPROG) 5572 ahc_set_transaction_status(scb, status); 5573 cstat = ahc_get_transaction_status(scb); 5574 if (cstat != CAM_REQ_CMP) 5575 ahc_freeze_scb(scb); 5576 if ((scb->flags & SCB_ACTIVE) == 0) 5577 printf("Inactive SCB in untaggedQ\n"); 5578 ahc_done(ahc, scb); 5579 break; 5580 } 5581 case SEARCH_REMOVE: 5582 scb->flags &= ~SCB_UNTAGGEDQ; 5583 TAILQ_REMOVE(untagged_q, scb, links.tqe); 5584 break; 5585 case SEARCH_COUNT: 5586 break; 5587 } 5588 } 5589 } 5590 5591 if (action == SEARCH_COMPLETE) 5592 ahc_release_untagged_queues(ahc); 5593 return (found); 5594 } 5595 5596 int 5597 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel, 5598 int lun, u_int tag, int stop_on_first, int remove, 5599 int save_state) 5600 { 5601 struct scb *scbp; 5602 u_int next; 5603 u_int prev; 5604 u_int count; 5605 u_int active_scb; 5606 5607 count = 0; 5608 next = ahc_inb(ahc, DISCONNECTED_SCBH); 5609 prev = SCB_LIST_NULL; 5610 5611 if (save_state) { 5612 /* restore this when we're done */ 5613 active_scb = ahc_inb(ahc, SCBPTR); 5614 } else 5615 /* Silence compiler */ 5616 active_scb = SCB_LIST_NULL; 5617 5618 while (next != SCB_LIST_NULL) { 5619 u_int scb_index; 5620 5621 ahc_outb(ahc, SCBPTR, next); 5622 scb_index = ahc_inb(ahc, SCB_TAG); 5623 if (scb_index >= ahc->scb_data->numscbs) { 5624 printf("Disconnected List inconsistency. " 5625 "SCB index == %d, yet numscbs == %d.", 5626 scb_index, ahc->scb_data->numscbs); 5627 ahc_dump_card_state(ahc); 5628 panic("for safety"); 5629 } 5630 5631 if (next == prev) { 5632 panic("Disconnected List Loop. " 5633 "cur SCBPTR == %x, prev SCBPTR == %x.", 5634 next, prev); 5635 } 5636 scbp = ahc_lookup_scb(ahc, scb_index); 5637 if (ahc_match_scb(ahc, scbp, target, channel, lun, 5638 tag, ROLE_INITIATOR)) { 5639 count++; 5640 if (remove) { 5641 next = 5642 ahc_rem_scb_from_disc_list(ahc, prev, next); 5643 } else { 5644 prev = next; 5645 next = ahc_inb(ahc, SCB_NEXT); 5646 } 5647 if (stop_on_first) 5648 break; 5649 } else { 5650 prev = next; 5651 next = ahc_inb(ahc, SCB_NEXT); 5652 } 5653 } 5654 if (save_state) 5655 ahc_outb(ahc, SCBPTR, active_scb); 5656 return (count); 5657 } 5658 5659 /* 5660 * Remove an SCB from the on chip list of disconnected transactions. 5661 * This is empty/unused if we are not performing SCB paging. 5662 */ 5663 static u_int 5664 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr) 5665 { 5666 u_int next; 5667 5668 ahc_outb(ahc, SCBPTR, scbptr); 5669 next = ahc_inb(ahc, SCB_NEXT); 5670 5671 ahc_outb(ahc, SCB_CONTROL, 0); 5672 5673 ahc_add_curscb_to_free_list(ahc); 5674 5675 if (prev != SCB_LIST_NULL) { 5676 ahc_outb(ahc, SCBPTR, prev); 5677 ahc_outb(ahc, SCB_NEXT, next); 5678 } else 5679 ahc_outb(ahc, DISCONNECTED_SCBH, next); 5680 5681 return (next); 5682 } 5683 5684 /* 5685 * Add the SCB as selected by SCBPTR onto the on chip list of 5686 * free hardware SCBs. This list is empty/unused if we are not 5687 * performing SCB paging. 5688 */ 5689 static void 5690 ahc_add_curscb_to_free_list(struct ahc_softc *ahc) 5691 { 5692 /* 5693 * Invalidate the tag so that our abort 5694 * routines don't think it's active. 5695 */ 5696 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL); 5697 5698 if ((ahc->flags & AHC_PAGESCBS) != 0) { 5699 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH)); 5700 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR)); 5701 } 5702 } 5703 5704 /* 5705 * Manipulate the waiting for selection list and return the 5706 * scb that follows the one that we remove. 5707 */ 5708 static u_int 5709 ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev) 5710 { 5711 u_int curscb, next; 5712 5713 /* 5714 * Select the SCB we want to abort and 5715 * pull the next pointer out of it. 5716 */ 5717 curscb = ahc_inb(ahc, SCBPTR); 5718 ahc_outb(ahc, SCBPTR, scbpos); 5719 next = ahc_inb(ahc, SCB_NEXT); 5720 5721 /* Clear the necessary fields */ 5722 ahc_outb(ahc, SCB_CONTROL, 0); 5723 5724 ahc_add_curscb_to_free_list(ahc); 5725 5726 /* update the waiting list */ 5727 if (prev == SCB_LIST_NULL) { 5728 /* First in the list */ 5729 ahc_outb(ahc, WAITING_SCBH, next); 5730 5731 /* 5732 * Ensure we aren't attempting to perform 5733 * selection for this entry. 5734 */ 5735 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO)); 5736 } else { 5737 /* 5738 * Select the scb that pointed to us 5739 * and update its next pointer. 5740 */ 5741 ahc_outb(ahc, SCBPTR, prev); 5742 ahc_outb(ahc, SCB_NEXT, next); 5743 } 5744 5745 /* 5746 * Point us back at the original scb position. 5747 */ 5748 ahc_outb(ahc, SCBPTR, curscb); 5749 return next; 5750 } 5751 5752 /******************************** Error Handling ******************************/ 5753 /* 5754 * Abort all SCBs that match the given description (target/channel/lun/tag), 5755 * setting their status to the passed in status if the status has not already 5756 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer 5757 * is paused before it is called. 5758 */ 5759 int 5760 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel, 5761 int lun, u_int tag, role_t role, uint32_t status) 5762 { 5763 struct scb *scbp; 5764 struct scb *scbp_next; 5765 u_int active_scb; 5766 int i, j; 5767 int maxtarget; 5768 int minlun; 5769 int maxlun; 5770 5771 int found; 5772 5773 /* 5774 * Don't attempt to run any queued untagged transactions 5775 * until we are done with the abort process. 5776 */ 5777 ahc_freeze_untagged_queues(ahc); 5778 5779 /* restore this when we're done */ 5780 active_scb = ahc_inb(ahc, SCBPTR); 5781 5782 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL, 5783 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE); 5784 5785 /* 5786 * Clean out the busy target table for any untagged commands. 5787 */ 5788 i = 0; 5789 maxtarget = 16; 5790 if (target != CAM_TARGET_WILDCARD) { 5791 i = target; 5792 if (channel == 'B') 5793 i += 8; 5794 maxtarget = i + 1; 5795 } 5796 5797 if (lun == CAM_LUN_WILDCARD) { 5798 5799 /* 5800 * Unless we are using an SCB based 5801 * busy targets table, there is only 5802 * one table entry for all luns of 5803 * a target. 5804 */ 5805 minlun = 0; 5806 maxlun = 1; 5807 if ((ahc->flags & AHC_SCB_BTT) != 0) 5808 maxlun = AHC_NUM_LUNS; 5809 } else { 5810 minlun = lun; 5811 maxlun = lun + 1; 5812 } 5813 5814 if (role != ROLE_TARGET) { 5815 for (;i < maxtarget; i++) { 5816 for (j = minlun;j < maxlun; j++) { 5817 u_int scbid; 5818 u_int tcl; 5819 5820 tcl = BUILD_TCL(i << 4, j); 5821 scbid = ahc_index_busy_tcl(ahc, tcl); 5822 scbp = ahc_lookup_scb(ahc, scbid); 5823 if (scbp == NULL 5824 || ahc_match_scb(ahc, scbp, target, channel, 5825 lun, tag, role) == 0) 5826 continue; 5827 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j)); 5828 } 5829 } 5830 5831 /* 5832 * Go through the disconnected list and remove any entries we 5833 * have queued for completion, 0'ing their control byte too. 5834 * We save the active SCB and restore it ourselves, so there 5835 * is no reason for this search to restore it too. 5836 */ 5837 ahc_search_disc_list(ahc, target, channel, lun, tag, 5838 /*stop_on_first*/FALSE, /*remove*/TRUE, 5839 /*save_state*/FALSE); 5840 } 5841 5842 /* 5843 * Go through the hardware SCB array looking for commands that 5844 * were active but not on any list. In some cases, these remnants 5845 * might not still have mappings in the scbindex array (e.g. unexpected 5846 * bus free with the same scb queued for an abort). Don't hold this 5847 * against them. 5848 */ 5849 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 5850 u_int scbid; 5851 5852 ahc_outb(ahc, SCBPTR, i); 5853 scbid = ahc_inb(ahc, SCB_TAG); 5854 scbp = ahc_lookup_scb(ahc, scbid); 5855 if ((scbp == NULL && scbid != SCB_LIST_NULL) 5856 || (scbp != NULL 5857 && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role))) 5858 ahc_add_curscb_to_free_list(ahc); 5859 } 5860 5861 /* 5862 * Go through the pending CCB list and look for 5863 * commands for this target that are still active. 5864 * These are other tagged commands that were 5865 * disconnected when the reset occurred. 5866 */ 5867 scbp_next = LIST_FIRST(&ahc->pending_scbs); 5868 while (scbp_next != NULL) { 5869 scbp = scbp_next; 5870 scbp_next = LIST_NEXT(scbp, pending_links); 5871 if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) { 5872 cam_status ostat; 5873 5874 ostat = ahc_get_transaction_status(scbp); 5875 if (ostat == CAM_REQ_INPROG) 5876 ahc_set_transaction_status(scbp, status); 5877 if (ahc_get_transaction_status(scbp) != CAM_REQ_CMP) 5878 ahc_freeze_scb(scbp); 5879 if ((scbp->flags & SCB_ACTIVE) == 0) 5880 printf("Inactive SCB on pending list\n"); 5881 ahc_done(ahc, scbp); 5882 found++; 5883 } 5884 } 5885 ahc_outb(ahc, SCBPTR, active_scb); 5886 ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status); 5887 ahc_release_untagged_queues(ahc); 5888 return found; 5889 } 5890 5891 static void 5892 ahc_reset_current_bus(struct ahc_softc *ahc) 5893 { 5894 uint8_t scsiseq; 5895 5896 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST); 5897 scsiseq = ahc_inb(ahc, SCSISEQ); 5898 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO); 5899 ahc_flush_device_writes(ahc); 5900 ahc_delay(AHC_BUSRESET_DELAY); 5901 /* Turn off the bus reset */ 5902 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO); 5903 5904 ahc_clear_intstat(ahc); 5905 5906 /* Re-enable reset interrupts */ 5907 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST); 5908 } 5909 5910 int 5911 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset) 5912 { 5913 struct ahc_devinfo devinfo; 5914 u_int initiator, target, max_scsiid; 5915 u_int sblkctl; 5916 u_int scsiseq; 5917 u_int simode1; 5918 int found; 5919 int restart_needed; 5920 char cur_channel; 5921 5922 ahc->pending_device = NULL; 5923 5924 ahc_compile_devinfo(&devinfo, 5925 CAM_TARGET_WILDCARD, 5926 CAM_TARGET_WILDCARD, 5927 CAM_LUN_WILDCARD, 5928 channel, ROLE_UNKNOWN); 5929 ahc_pause(ahc); 5930 5931 /* Make sure the sequencer is in a safe location. */ 5932 ahc_clear_critical_section(ahc); 5933 5934 /* 5935 * Run our command complete fifos to ensure that we perform 5936 * completion processing on any commands that 'completed' 5937 * before the reset occurred. 5938 */ 5939 ahc_run_qoutfifo(ahc); 5940 #ifdef AHC_TARGET_MODE 5941 /* 5942 * XXX - In Twin mode, the tqinfifo may have commands 5943 * for an unaffected channel in it. However, if 5944 * we have run out of ATIO resources to drain that 5945 * queue, we may not get them all out here. Further, 5946 * the blocked transactions for the reset channel 5947 * should just be killed off, irrespecitve of whether 5948 * we are blocked on ATIO resources. Write a routine 5949 * to compact the tqinfifo appropriately. 5950 */ 5951 if ((ahc->flags & AHC_TARGETROLE) != 0) { 5952 ahc_run_tqinfifo(ahc, /*paused*/TRUE); 5953 } 5954 #endif 5955 5956 /* 5957 * Reset the bus if we are initiating this reset 5958 */ 5959 sblkctl = ahc_inb(ahc, SBLKCTL); 5960 cur_channel = 'A'; 5961 if ((ahc->features & AHC_TWIN) != 0 5962 && ((sblkctl & SELBUSB) != 0)) 5963 cur_channel = 'B'; 5964 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 5965 if (cur_channel != channel) { 5966 /* Case 1: Command for another bus is active 5967 * Stealthily reset the other bus without 5968 * upsetting the current bus. 5969 */ 5970 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB); 5971 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST); 5972 #ifdef AHC_TARGET_MODE 5973 /* 5974 * Bus resets clear ENSELI, so we cannot 5975 * defer re-enabling bus reset interrupts 5976 * if we are in target mode. 5977 */ 5978 if ((ahc->flags & AHC_TARGETROLE) != 0) 5979 simode1 |= ENSCSIRST; 5980 #endif 5981 ahc_outb(ahc, SIMODE1, simode1); 5982 if (initiate_reset) 5983 ahc_reset_current_bus(ahc); 5984 ahc_clear_intstat(ahc); 5985 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP)); 5986 ahc_outb(ahc, SBLKCTL, sblkctl); 5987 restart_needed = FALSE; 5988 } else { 5989 /* Case 2: A command from this bus is active or we're idle */ 5990 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST); 5991 #ifdef AHC_TARGET_MODE 5992 /* 5993 * Bus resets clear ENSELI, so we cannot 5994 * defer re-enabling bus reset interrupts 5995 * if we are in target mode. 5996 */ 5997 if ((ahc->flags & AHC_TARGETROLE) != 0) 5998 simode1 |= ENSCSIRST; 5999 #endif 6000 ahc_outb(ahc, SIMODE1, simode1); 6001 if (initiate_reset) 6002 ahc_reset_current_bus(ahc); 6003 ahc_clear_intstat(ahc); 6004 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP)); 6005 restart_needed = TRUE; 6006 } 6007 6008 /* 6009 * Clean up all the state information for the 6010 * pending transactions on this bus. 6011 */ 6012 found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel, 6013 CAM_LUN_WILDCARD, SCB_LIST_NULL, 6014 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET); 6015 6016 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7; 6017 6018 #ifdef AHC_TARGET_MODE 6019 /* 6020 * Send an immediate notify ccb to all target more peripheral 6021 * drivers affected by this action. 6022 */ 6023 for (target = 0; target <= max_scsiid; target++) { 6024 struct ahc_tmode_tstate* tstate; 6025 u_int lun; 6026 6027 tstate = ahc->enabled_targets[target]; 6028 if (tstate == NULL) 6029 continue; 6030 for (lun = 0; lun < AHC_NUM_LUNS; lun++) { 6031 struct ahc_tmode_lstate* lstate; 6032 6033 lstate = tstate->enabled_luns[lun]; 6034 if (lstate == NULL) 6035 continue; 6036 6037 ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD, 6038 EVENT_TYPE_BUS_RESET, /*arg*/0); 6039 ahc_send_lstate_events(ahc, lstate); 6040 } 6041 } 6042 #endif 6043 /* Notify the XPT that a bus reset occurred */ 6044 ahc_send_async(ahc, devinfo.channel, CAM_TARGET_WILDCARD, 6045 CAM_LUN_WILDCARD, AC_BUS_RESET); 6046 6047 /* 6048 * Revert to async/narrow transfers until we renegotiate. 6049 */ 6050 for (target = 0; target <= max_scsiid; target++) { 6051 6052 if (ahc->enabled_targets[target] == NULL) 6053 continue; 6054 for (initiator = 0; initiator <= max_scsiid; initiator++) { 6055 struct ahc_devinfo devinfo; 6056 6057 ahc_compile_devinfo(&devinfo, target, initiator, 6058 CAM_LUN_WILDCARD, 6059 channel, ROLE_UNKNOWN); 6060 ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT, 6061 AHC_TRANS_CUR, /*paused*/TRUE); 6062 ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL, 6063 /*period*/0, /*offset*/0, 6064 /*ppr_options*/0, AHC_TRANS_CUR, 6065 /*paused*/TRUE); 6066 } 6067 } 6068 6069 if (restart_needed) 6070 ahc_restart(ahc); 6071 else 6072 ahc_unpause(ahc); 6073 return found; 6074 } 6075 6076 6077 /***************************** Residual Processing ****************************/ 6078 /* 6079 * Calculate the residual for a just completed SCB. 6080 */ 6081 void 6082 ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb) 6083 { 6084 struct hardware_scb *hscb; 6085 struct status_pkt *spkt; 6086 uint32_t sgptr; 6087 uint32_t resid_sgptr; 6088 uint32_t resid; 6089 6090 /* 6091 * 5 cases. 6092 * 1) No residual. 6093 * SG_RESID_VALID clear in sgptr. 6094 * 2) Transferless command 6095 * 3) Never performed any transfers. 6096 * sgptr has SG_FULL_RESID set. 6097 * 4) No residual but target did not 6098 * save data pointers after the 6099 * last transfer, so sgptr was 6100 * never updated. 6101 * 5) We have a partial residual. 6102 * Use residual_sgptr to determine 6103 * where we are. 6104 */ 6105 6106 hscb = scb->hscb; 6107 sgptr = ahc_le32toh(hscb->sgptr); 6108 if ((sgptr & SG_RESID_VALID) == 0) 6109 /* Case 1 */ 6110 return; 6111 sgptr &= ~SG_RESID_VALID; 6112 6113 if ((sgptr & SG_LIST_NULL) != 0) 6114 /* Case 2 */ 6115 return; 6116 6117 spkt = &hscb->shared_data.status; 6118 resid_sgptr = ahc_le32toh(spkt->residual_sg_ptr); 6119 if ((sgptr & SG_FULL_RESID) != 0) { 6120 /* Case 3 */ 6121 resid = ahc_get_transfer_length(scb); 6122 } else if ((resid_sgptr & SG_LIST_NULL) != 0) { 6123 /* Case 4 */ 6124 return; 6125 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) { 6126 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr); 6127 } else { 6128 struct ahc_dma_seg *sg; 6129 6130 /* 6131 * Remainder of the SG where the transfer 6132 * stopped. 6133 */ 6134 resid = ahc_le32toh(spkt->residual_datacnt) & AHC_SG_LEN_MASK; 6135 sg = ahc_sg_bus_to_virt(scb, resid_sgptr & SG_PTR_MASK); 6136 6137 /* The residual sg_ptr always points to the next sg */ 6138 sg--; 6139 6140 /* 6141 * Add up the contents of all residual 6142 * SG segments that are after the SG where 6143 * the transfer stopped. 6144 */ 6145 while ((ahc_le32toh(sg->len) & AHC_DMA_LAST_SEG) == 0) { 6146 sg++; 6147 resid += ahc_le32toh(sg->len) & AHC_SG_LEN_MASK; 6148 } 6149 } 6150 if ((scb->flags & SCB_SENSE) == 0) 6151 ahc_set_residual(scb, resid); 6152 else 6153 ahc_set_sense_residual(scb, resid); 6154 6155 #ifdef AHC_DEBUG 6156 if ((ahc_debug & AHC_SHOW_MISC) != 0) { 6157 ahc_print_path(ahc, scb); 6158 printf("Handled %sResidual of %d bytes\n", 6159 (scb->flags & SCB_SENSE) ? "Sense " : "", resid); 6160 } 6161 #endif 6162 } 6163 6164 /******************************* Target Mode **********************************/ 6165 #ifdef AHC_TARGET_MODE 6166 /* 6167 * Add a target mode event to this lun's queue 6168 */ 6169 static void 6170 ahc_queue_lstate_event(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate, 6171 u_int initiator_id, u_int event_type, u_int event_arg) 6172 { 6173 struct ahc_tmode_event *event; 6174 int pending; 6175 6176 xpt_freeze_devq(lstate->path, /*count*/1); 6177 if (lstate->event_w_idx >= lstate->event_r_idx) 6178 pending = lstate->event_w_idx - lstate->event_r_idx; 6179 else 6180 pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1 6181 - (lstate->event_r_idx - lstate->event_w_idx); 6182 6183 if (event_type == EVENT_TYPE_BUS_RESET 6184 || event_type == MSG_BUS_DEV_RESET) { 6185 /* 6186 * Any earlier events are irrelevant, so reset our buffer. 6187 * This has the effect of allowing us to deal with reset 6188 * floods (an external device holding down the reset line) 6189 * without losing the event that is really interesting. 6190 */ 6191 lstate->event_r_idx = 0; 6192 lstate->event_w_idx = 0; 6193 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE); 6194 } 6195 6196 if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) { 6197 xpt_print_path(lstate->path); 6198 printf("immediate event %x:%x lost\n", 6199 lstate->event_buffer[lstate->event_r_idx].event_type, 6200 lstate->event_buffer[lstate->event_r_idx].event_arg); 6201 lstate->event_r_idx++; 6202 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6203 lstate->event_r_idx = 0; 6204 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE); 6205 } 6206 6207 event = &lstate->event_buffer[lstate->event_w_idx]; 6208 event->initiator_id = initiator_id; 6209 event->event_type = event_type; 6210 event->event_arg = event_arg; 6211 lstate->event_w_idx++; 6212 if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6213 lstate->event_w_idx = 0; 6214 } 6215 6216 /* 6217 * Send any target mode events queued up waiting 6218 * for immediate notify resources. 6219 */ 6220 void 6221 ahc_send_lstate_events(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate) 6222 { 6223 struct ccb_hdr *ccbh; 6224 struct ccb_immed_notify *inot; 6225 6226 while (lstate->event_r_idx != lstate->event_w_idx 6227 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) { 6228 struct ahc_tmode_event *event; 6229 6230 event = &lstate->event_buffer[lstate->event_r_idx]; 6231 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle); 6232 inot = (struct ccb_immed_notify *)ccbh; 6233 switch (event->event_type) { 6234 case EVENT_TYPE_BUS_RESET: 6235 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN; 6236 break; 6237 default: 6238 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN; 6239 inot->message_args[0] = event->event_type; 6240 inot->message_args[1] = event->event_arg; 6241 break; 6242 } 6243 inot->initiator_id = event->initiator_id; 6244 inot->sense_len = 0; 6245 xpt_done((union ccb *)inot); 6246 lstate->event_r_idx++; 6247 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE) 6248 lstate->event_r_idx = 0; 6249 } 6250 } 6251 #endif 6252 6253 /******************** Sequencer Program Patching/Download *********************/ 6254 6255 #ifdef AHC_DUMP_SEQ 6256 void 6257 ahc_dumpseq(struct ahc_softc* ahc) 6258 { 6259 int i; 6260 6261 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 6262 ahc_outb(ahc, SEQADDR0, 0); 6263 ahc_outb(ahc, SEQADDR1, 0); 6264 for (i = 0; i < ahc->instruction_ram_size; i++) { 6265 uint8_t ins_bytes[4]; 6266 6267 ahc_insb(ahc, SEQRAM, ins_bytes, 4); 6268 printf("0x%08x\n", ins_bytes[0] << 24 6269 | ins_bytes[1] << 16 6270 | ins_bytes[2] << 8 6271 | ins_bytes[3]); 6272 } 6273 } 6274 #endif 6275 6276 static int 6277 ahc_loadseq(struct ahc_softc *ahc) 6278 { 6279 struct cs cs_table[num_critical_sections]; 6280 u_int begin_set[num_critical_sections]; 6281 u_int end_set[num_critical_sections]; 6282 struct patch *cur_patch; 6283 u_int cs_count; 6284 u_int cur_cs; 6285 u_int i; 6286 u_int skip_addr; 6287 u_int sg_prefetch_cnt; 6288 int downloaded; 6289 uint8_t download_consts[7]; 6290 6291 /* 6292 * Start out with 0 critical sections 6293 * that apply to this firmware load. 6294 */ 6295 cs_count = 0; 6296 cur_cs = 0; 6297 memset(begin_set, 0, sizeof(begin_set)); 6298 memset(end_set, 0, sizeof(end_set)); 6299 6300 /* Setup downloadable constant table */ 6301 download_consts[QOUTFIFO_OFFSET] = 0; 6302 if (ahc->targetcmds != NULL) 6303 download_consts[QOUTFIFO_OFFSET] += 32; 6304 download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1; 6305 download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1; 6306 download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1); 6307 sg_prefetch_cnt = ahc->pci_cachesize; 6308 if (sg_prefetch_cnt < (2 * sizeof(struct ahc_dma_seg))) 6309 sg_prefetch_cnt = 2 * sizeof(struct ahc_dma_seg); 6310 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt; 6311 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_cnt - 1); 6312 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_cnt - 1); 6313 6314 cur_patch = patches; 6315 downloaded = 0; 6316 skip_addr = 0; 6317 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM); 6318 ahc_outb(ahc, SEQADDR0, 0); 6319 ahc_outb(ahc, SEQADDR1, 0); 6320 6321 for (i = 0; i < sizeof(seqprog)/4; i++) { 6322 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) { 6323 /* 6324 * Don't download this instruction as it 6325 * is in a patch that was removed. 6326 */ 6327 continue; 6328 } 6329 6330 if (downloaded == ahc->instruction_ram_size) { 6331 /* 6332 * We're about to exceed the instruction 6333 * storage capacity for this chip. Fail 6334 * the load. 6335 */ 6336 printf("\n%s: Program too large for instruction memory " 6337 "size of %d!\n", ahc_name(ahc), 6338 ahc->instruction_ram_size); 6339 return (ENOMEM); 6340 } 6341 6342 /* 6343 * Move through the CS table until we find a CS 6344 * that might apply to this instruction. 6345 */ 6346 for (; cur_cs < num_critical_sections; cur_cs++) { 6347 if (critical_sections[cur_cs].end <= i) { 6348 if (begin_set[cs_count] == TRUE 6349 && end_set[cs_count] == FALSE) { 6350 cs_table[cs_count].end = downloaded; 6351 end_set[cs_count] = TRUE; 6352 cs_count++; 6353 } 6354 continue; 6355 } 6356 if (critical_sections[cur_cs].begin <= i 6357 && begin_set[cs_count] == FALSE) { 6358 cs_table[cs_count].begin = downloaded; 6359 begin_set[cs_count] = TRUE; 6360 } 6361 break; 6362 } 6363 ahc_download_instr(ahc, i, download_consts); 6364 downloaded++; 6365 } 6366 6367 ahc->num_critical_sections = cs_count; 6368 if (cs_count != 0) { 6369 6370 cs_count *= sizeof(struct cs); 6371 ahc->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT); 6372 if (ahc->critical_sections == NULL) 6373 panic("ahc_loadseq: Could not malloc"); 6374 memcpy(ahc->critical_sections, cs_table, cs_count); 6375 } 6376 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE); 6377 6378 if (bootverbose) { 6379 printf(" %d instructions downloaded\n", downloaded); 6380 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n", 6381 ahc_name(ahc), ahc->features, ahc->bugs, ahc->flags); 6382 } 6383 return (0); 6384 } 6385 6386 static int 6387 ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch, 6388 u_int start_instr, u_int *skip_addr) 6389 { 6390 struct patch *cur_patch; 6391 struct patch *last_patch; 6392 u_int num_patches; 6393 6394 num_patches = ARRAY_SIZE(patches); 6395 last_patch = &patches[num_patches]; 6396 cur_patch = *start_patch; 6397 6398 while (cur_patch < last_patch && start_instr == cur_patch->begin) { 6399 6400 if (cur_patch->patch_func(ahc) == 0) { 6401 6402 /* Start rejecting code */ 6403 *skip_addr = start_instr + cur_patch->skip_instr; 6404 cur_patch += cur_patch->skip_patch; 6405 } else { 6406 /* Accepted this patch. Advance to the next 6407 * one and wait for our intruction pointer to 6408 * hit this point. 6409 */ 6410 cur_patch++; 6411 } 6412 } 6413 6414 *start_patch = cur_patch; 6415 if (start_instr < *skip_addr) 6416 /* Still skipping */ 6417 return (0); 6418 6419 return (1); 6420 } 6421 6422 static void 6423 ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts) 6424 { 6425 union ins_formats instr; 6426 struct ins_format1 *fmt1_ins; 6427 struct ins_format3 *fmt3_ins; 6428 u_int opcode; 6429 6430 /* 6431 * The firmware is always compiled into a little endian format. 6432 */ 6433 instr.integer = ahc_le32toh(*(uint32_t*)&seqprog[instrptr * 4]); 6434 6435 fmt1_ins = &instr.format1; 6436 fmt3_ins = NULL; 6437 6438 /* Pull the opcode */ 6439 opcode = instr.format1.opcode; 6440 switch (opcode) { 6441 case AIC_OP_JMP: 6442 case AIC_OP_JC: 6443 case AIC_OP_JNC: 6444 case AIC_OP_CALL: 6445 case AIC_OP_JNE: 6446 case AIC_OP_JNZ: 6447 case AIC_OP_JE: 6448 case AIC_OP_JZ: 6449 { 6450 struct patch *cur_patch; 6451 int address_offset; 6452 u_int address; 6453 u_int skip_addr; 6454 u_int i; 6455 6456 fmt3_ins = &instr.format3; 6457 address_offset = 0; 6458 address = fmt3_ins->address; 6459 cur_patch = patches; 6460 skip_addr = 0; 6461 6462 for (i = 0; i < address;) { 6463 6464 ahc_check_patch(ahc, &cur_patch, i, &skip_addr); 6465 6466 if (skip_addr > i) { 6467 int end_addr; 6468 6469 end_addr = min(address, skip_addr); 6470 address_offset += end_addr - i; 6471 i = skip_addr; 6472 } else { 6473 i++; 6474 } 6475 } 6476 address -= address_offset; 6477 fmt3_ins->address = address; 6478 /* FALLTHROUGH */ 6479 } 6480 case AIC_OP_OR: 6481 case AIC_OP_AND: 6482 case AIC_OP_XOR: 6483 case AIC_OP_ADD: 6484 case AIC_OP_ADC: 6485 case AIC_OP_BMOV: 6486 if (fmt1_ins->parity != 0) { 6487 fmt1_ins->immediate = dconsts[fmt1_ins->immediate]; 6488 } 6489 fmt1_ins->parity = 0; 6490 if ((ahc->features & AHC_CMD_CHAN) == 0 6491 && opcode == AIC_OP_BMOV) { 6492 /* 6493 * Block move was added at the same time 6494 * as the command channel. Verify that 6495 * this is only a move of a single element 6496 * and convert the BMOV to a MOV 6497 * (AND with an immediate of FF). 6498 */ 6499 if (fmt1_ins->immediate != 1) 6500 panic("%s: BMOV not supported\n", 6501 ahc_name(ahc)); 6502 fmt1_ins->opcode = AIC_OP_AND; 6503 fmt1_ins->immediate = 0xff; 6504 } 6505 /* FALLTHROUGH */ 6506 case AIC_OP_ROL: 6507 if ((ahc->features & AHC_ULTRA2) != 0) { 6508 int i, count; 6509 6510 /* Calculate odd parity for the instruction */ 6511 for (i = 0, count = 0; i < 31; i++) { 6512 uint32_t mask; 6513 6514 mask = 0x01 << i; 6515 if ((instr.integer & mask) != 0) 6516 count++; 6517 } 6518 if ((count & 0x01) == 0) 6519 instr.format1.parity = 1; 6520 } else { 6521 /* Compress the instruction for older sequencers */ 6522 if (fmt3_ins != NULL) { 6523 instr.integer = 6524 fmt3_ins->immediate 6525 | (fmt3_ins->source << 8) 6526 | (fmt3_ins->address << 16) 6527 | (fmt3_ins->opcode << 25); 6528 } else { 6529 instr.integer = 6530 fmt1_ins->immediate 6531 | (fmt1_ins->source << 8) 6532 | (fmt1_ins->destination << 16) 6533 | (fmt1_ins->ret << 24) 6534 | (fmt1_ins->opcode << 25); 6535 } 6536 } 6537 /* The sequencer is a little endian cpu */ 6538 instr.integer = ahc_htole32(instr.integer); 6539 ahc_outsb(ahc, SEQRAM, instr.bytes, 4); 6540 break; 6541 default: 6542 panic("Unknown opcode encountered in seq program"); 6543 break; 6544 } 6545 } 6546 6547 int 6548 ahc_print_register(ahc_reg_parse_entry_t *table, u_int num_entries, 6549 const char *name, u_int address, u_int value, 6550 u_int *cur_column, u_int wrap_point) 6551 { 6552 int printed; 6553 u_int printed_mask; 6554 6555 if (cur_column != NULL && *cur_column >= wrap_point) { 6556 printf("\n"); 6557 *cur_column = 0; 6558 } 6559 printed = printf("%s[0x%x]", name, value); 6560 if (table == NULL) { 6561 printed += printf(" "); 6562 *cur_column += printed; 6563 return (printed); 6564 } 6565 printed_mask = 0; 6566 while (printed_mask != 0xFF) { 6567 int entry; 6568 6569 for (entry = 0; entry < num_entries; entry++) { 6570 if (((value & table[entry].mask) 6571 != table[entry].value) 6572 || ((printed_mask & table[entry].mask) 6573 == table[entry].mask)) 6574 continue; 6575 6576 printed += printf("%s%s", 6577 printed_mask == 0 ? ":(" : "|", 6578 table[entry].name); 6579 printed_mask |= table[entry].mask; 6580 6581 break; 6582 } 6583 if (entry >= num_entries) 6584 break; 6585 } 6586 if (printed_mask != 0) 6587 printed += printf(") "); 6588 else 6589 printed += printf(" "); 6590 if (cur_column != NULL) 6591 *cur_column += printed; 6592 return (printed); 6593 } 6594 6595 void 6596 ahc_dump_card_state(struct ahc_softc *ahc) 6597 { 6598 struct scb *scb; 6599 struct scb_tailq *untagged_q; 6600 u_int cur_col; 6601 int paused; 6602 int target; 6603 int maxtarget; 6604 int i; 6605 uint8_t last_phase; 6606 uint8_t qinpos; 6607 uint8_t qintail; 6608 uint8_t qoutpos; 6609 uint8_t scb_index; 6610 uint8_t saved_scbptr; 6611 6612 if (ahc_is_paused(ahc)) { 6613 paused = 1; 6614 } else { 6615 paused = 0; 6616 ahc_pause(ahc); 6617 } 6618 6619 saved_scbptr = ahc_inb(ahc, SCBPTR); 6620 last_phase = ahc_inb(ahc, LASTPHASE); 6621 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n" 6622 "%s: Dumping Card State %s, at SEQADDR 0x%x\n", 6623 ahc_name(ahc), ahc_lookup_phase_entry(last_phase)->phasemsg, 6624 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8)); 6625 if (paused) 6626 printf("Card was paused\n"); 6627 printf("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n", 6628 ahc_inb(ahc, ACCUM), ahc_inb(ahc, SINDEX), ahc_inb(ahc, DINDEX), 6629 ahc_inb(ahc, ARG_2)); 6630 printf("HCNT = 0x%x SCBPTR = 0x%x\n", ahc_inb(ahc, HCNT), 6631 ahc_inb(ahc, SCBPTR)); 6632 cur_col = 0; 6633 if ((ahc->features & AHC_DT) != 0) 6634 ahc_scsiphase_print(ahc_inb(ahc, SCSIPHASE), &cur_col, 50); 6635 ahc_scsisigi_print(ahc_inb(ahc, SCSISIGI), &cur_col, 50); 6636 ahc_error_print(ahc_inb(ahc, ERROR), &cur_col, 50); 6637 ahc_scsibusl_print(ahc_inb(ahc, SCSIBUSL), &cur_col, 50); 6638 ahc_lastphase_print(ahc_inb(ahc, LASTPHASE), &cur_col, 50); 6639 ahc_scsiseq_print(ahc_inb(ahc, SCSISEQ), &cur_col, 50); 6640 ahc_sblkctl_print(ahc_inb(ahc, SBLKCTL), &cur_col, 50); 6641 ahc_scsirate_print(ahc_inb(ahc, SCSIRATE), &cur_col, 50); 6642 ahc_seqctl_print(ahc_inb(ahc, SEQCTL), &cur_col, 50); 6643 ahc_seq_flags_print(ahc_inb(ahc, SEQ_FLAGS), &cur_col, 50); 6644 ahc_sstat0_print(ahc_inb(ahc, SSTAT0), &cur_col, 50); 6645 ahc_sstat1_print(ahc_inb(ahc, SSTAT1), &cur_col, 50); 6646 ahc_sstat2_print(ahc_inb(ahc, SSTAT2), &cur_col, 50); 6647 ahc_sstat3_print(ahc_inb(ahc, SSTAT3), &cur_col, 50); 6648 ahc_simode0_print(ahc_inb(ahc, SIMODE0), &cur_col, 50); 6649 ahc_simode1_print(ahc_inb(ahc, SIMODE1), &cur_col, 50); 6650 ahc_sxfrctl0_print(ahc_inb(ahc, SXFRCTL0), &cur_col, 50); 6651 ahc_dfcntrl_print(ahc_inb(ahc, DFCNTRL), &cur_col, 50); 6652 ahc_dfstatus_print(ahc_inb(ahc, DFSTATUS), &cur_col, 50); 6653 if (cur_col != 0) 6654 printf("\n"); 6655 printf("STACK:"); 6656 for (i = 0; i < STACK_SIZE; i++) 6657 printf(" 0x%x", ahc_inb(ahc, STACK)|(ahc_inb(ahc, STACK) << 8)); 6658 printf("\nSCB count = %d\n", ahc->scb_data->numscbs); 6659 printf("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag); 6660 printf("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB)); 6661 /* QINFIFO */ 6662 printf("QINFIFO entries: "); 6663 if ((ahc->features & AHC_QUEUE_REGS) != 0) { 6664 qinpos = ahc_inb(ahc, SNSCB_QOFF); 6665 ahc_outb(ahc, SNSCB_QOFF, qinpos); 6666 } else 6667 qinpos = ahc_inb(ahc, QINPOS); 6668 qintail = ahc->qinfifonext; 6669 while (qinpos != qintail) { 6670 printf("%d ", ahc->qinfifo[qinpos]); 6671 qinpos++; 6672 } 6673 printf("\n"); 6674 6675 printf("Waiting Queue entries: "); 6676 scb_index = ahc_inb(ahc, WAITING_SCBH); 6677 i = 0; 6678 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6679 ahc_outb(ahc, SCBPTR, scb_index); 6680 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG)); 6681 scb_index = ahc_inb(ahc, SCB_NEXT); 6682 } 6683 printf("\n"); 6684 6685 printf("Disconnected Queue entries: "); 6686 scb_index = ahc_inb(ahc, DISCONNECTED_SCBH); 6687 i = 0; 6688 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6689 ahc_outb(ahc, SCBPTR, scb_index); 6690 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG)); 6691 scb_index = ahc_inb(ahc, SCB_NEXT); 6692 } 6693 printf("\n"); 6694 6695 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD); 6696 printf("QOUTFIFO entries: "); 6697 qoutpos = ahc->qoutfifonext; 6698 i = 0; 6699 while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) { 6700 printf("%d ", ahc->qoutfifo[qoutpos]); 6701 qoutpos++; 6702 } 6703 printf("\n"); 6704 6705 printf("Sequencer Free SCB List: "); 6706 scb_index = ahc_inb(ahc, FREE_SCBH); 6707 i = 0; 6708 while (scb_index != SCB_LIST_NULL && i++ < 256) { 6709 ahc_outb(ahc, SCBPTR, scb_index); 6710 printf("%d ", scb_index); 6711 scb_index = ahc_inb(ahc, SCB_NEXT); 6712 } 6713 printf("\n"); 6714 6715 printf("Sequencer SCB Info: "); 6716 for (i = 0; i < ahc->scb_data->maxhscbs; i++) { 6717 ahc_outb(ahc, SCBPTR, i); 6718 cur_col = printf("\n%3d ", i); 6719 6720 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), &cur_col, 60); 6721 ahc_scb_scsiid_print(ahc_inb(ahc, SCB_SCSIID), &cur_col, 60); 6722 ahc_scb_lun_print(ahc_inb(ahc, SCB_LUN), &cur_col, 60); 6723 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60); 6724 } 6725 printf("\n"); 6726 6727 printf("Pending list: "); 6728 i = 0; 6729 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) { 6730 if (i++ > 256) 6731 break; 6732 cur_col = printf("\n%3d ", scb->hscb->tag); 6733 ahc_scb_control_print(scb->hscb->control, &cur_col, 60); 6734 ahc_scb_scsiid_print(scb->hscb->scsiid, &cur_col, 60); 6735 ahc_scb_lun_print(scb->hscb->lun, &cur_col, 60); 6736 if ((ahc->flags & AHC_PAGESCBS) == 0) { 6737 ahc_outb(ahc, SCBPTR, scb->hscb->tag); 6738 printf("("); 6739 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), 6740 &cur_col, 60); 6741 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60); 6742 printf(")"); 6743 } 6744 } 6745 printf("\n"); 6746 6747 printf("Kernel Free SCB list: "); 6748 i = 0; 6749 SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) { 6750 if (i++ > 256) 6751 break; 6752 printf("%d ", scb->hscb->tag); 6753 } 6754 printf("\n"); 6755 6756 maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7; 6757 for (target = 0; target <= maxtarget; target++) { 6758 untagged_q = &ahc->untagged_queues[target]; 6759 if (TAILQ_FIRST(untagged_q) == NULL) 6760 continue; 6761 printf("Untagged Q(%d): ", target); 6762 i = 0; 6763 TAILQ_FOREACH(scb, untagged_q, links.tqe) { 6764 if (i++ > 256) 6765 break; 6766 printf("%d ", scb->hscb->tag); 6767 } 6768 printf("\n"); 6769 } 6770 6771 ahc_platform_dump_card_state(ahc); 6772 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n"); 6773 ahc_outb(ahc, SCBPTR, saved_scbptr); 6774 if (paused == 0) 6775 ahc_unpause(ahc); 6776 } 6777 6778 /************************* Target Mode ****************************************/ 6779 #ifdef AHC_TARGET_MODE 6780 cam_status 6781 ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb, 6782 struct ahc_tmode_tstate **tstate, 6783 struct ahc_tmode_lstate **lstate, 6784 int notfound_failure) 6785 { 6786 6787 if ((ahc->features & AHC_TARGETMODE) == 0) 6788 return (CAM_REQ_INVALID); 6789 6790 /* 6791 * Handle the 'black hole' device that sucks up 6792 * requests to unattached luns on enabled targets. 6793 */ 6794 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD 6795 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) { 6796 *tstate = NULL; 6797 *lstate = ahc->black_hole; 6798 } else { 6799 u_int max_id; 6800 6801 max_id = (ahc->features & AHC_WIDE) ? 16 : 8; 6802 if (ccb->ccb_h.target_id >= max_id) 6803 return (CAM_TID_INVALID); 6804 6805 if (ccb->ccb_h.target_lun >= AHC_NUM_LUNS) 6806 return (CAM_LUN_INVALID); 6807 6808 *tstate = ahc->enabled_targets[ccb->ccb_h.target_id]; 6809 *lstate = NULL; 6810 if (*tstate != NULL) 6811 *lstate = 6812 (*tstate)->enabled_luns[ccb->ccb_h.target_lun]; 6813 } 6814 6815 if (notfound_failure != 0 && *lstate == NULL) 6816 return (CAM_PATH_INVALID); 6817 6818 return (CAM_REQ_CMP); 6819 } 6820 6821 void 6822 ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb) 6823 { 6824 struct ahc_tmode_tstate *tstate; 6825 struct ahc_tmode_lstate *lstate; 6826 struct ccb_en_lun *cel; 6827 cam_status status; 6828 u_long s; 6829 u_int target; 6830 u_int lun; 6831 u_int target_mask; 6832 u_int our_id; 6833 int error; 6834 char channel; 6835 6836 status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate, 6837 /*notfound_failure*/FALSE); 6838 6839 if (status != CAM_REQ_CMP) { 6840 ccb->ccb_h.status = status; 6841 return; 6842 } 6843 6844 if (cam_sim_bus(sim) == 0) 6845 our_id = ahc->our_id; 6846 else 6847 our_id = ahc->our_id_b; 6848 6849 if (ccb->ccb_h.target_id != our_id) { 6850 /* 6851 * our_id represents our initiator ID, or 6852 * the ID of the first target to have an 6853 * enabled lun in target mode. There are 6854 * two cases that may preclude enabling a 6855 * target id other than our_id. 6856 * 6857 * o our_id is for an active initiator role. 6858 * Since the hardware does not support 6859 * reselections to the initiator role at 6860 * anything other than our_id, and our_id 6861 * is used by the hardware to indicate the 6862 * ID to use for both select-out and 6863 * reselect-out operations, the only target 6864 * ID we can support in this mode is our_id. 6865 * 6866 * o The MULTARGID feature is not available and 6867 * a previous target mode ID has been enabled. 6868 */ 6869 if ((ahc->features & AHC_MULTIROLE) != 0) { 6870 6871 if ((ahc->features & AHC_MULTI_TID) != 0 6872 && (ahc->flags & AHC_INITIATORROLE) != 0) { 6873 /* 6874 * Only allow additional targets if 6875 * the initiator role is disabled. 6876 * The hardware cannot handle a re-select-in 6877 * on the initiator id during a re-select-out 6878 * on a different target id. 6879 */ 6880 status = CAM_TID_INVALID; 6881 } else if ((ahc->flags & AHC_INITIATORROLE) != 0 6882 || ahc->enabled_luns > 0) { 6883 /* 6884 * Only allow our target id to change 6885 * if the initiator role is not configured 6886 * and there are no enabled luns which 6887 * are attached to the currently registered 6888 * scsi id. 6889 */ 6890 status = CAM_TID_INVALID; 6891 } 6892 } else if ((ahc->features & AHC_MULTI_TID) == 0 6893 && ahc->enabled_luns > 0) { 6894 6895 status = CAM_TID_INVALID; 6896 } 6897 } 6898 6899 if (status != CAM_REQ_CMP) { 6900 ccb->ccb_h.status = status; 6901 return; 6902 } 6903 6904 /* 6905 * We now have an id that is valid. 6906 * If we aren't in target mode, switch modes. 6907 */ 6908 if ((ahc->flags & AHC_TARGETROLE) == 0 6909 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) { 6910 u_long s; 6911 ahc_flag saved_flags; 6912 6913 printf("Configuring Target Mode\n"); 6914 ahc_lock(ahc, &s); 6915 if (LIST_FIRST(&ahc->pending_scbs) != NULL) { 6916 ccb->ccb_h.status = CAM_BUSY; 6917 ahc_unlock(ahc, &s); 6918 return; 6919 } 6920 saved_flags = ahc->flags; 6921 ahc->flags |= AHC_TARGETROLE; 6922 if ((ahc->features & AHC_MULTIROLE) == 0) 6923 ahc->flags &= ~AHC_INITIATORROLE; 6924 ahc_pause(ahc); 6925 error = ahc_loadseq(ahc); 6926 if (error != 0) { 6927 /* 6928 * Restore original configuration and notify 6929 * the caller that we cannot support target mode. 6930 * Since the adapter started out in this 6931 * configuration, the firmware load will succeed, 6932 * so there is no point in checking ahc_loadseq's 6933 * return value. 6934 */ 6935 ahc->flags = saved_flags; 6936 (void)ahc_loadseq(ahc); 6937 ahc_restart(ahc); 6938 ahc_unlock(ahc, &s); 6939 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL; 6940 return; 6941 } 6942 ahc_restart(ahc); 6943 ahc_unlock(ahc, &s); 6944 } 6945 cel = &ccb->cel; 6946 target = ccb->ccb_h.target_id; 6947 lun = ccb->ccb_h.target_lun; 6948 channel = SIM_CHANNEL(ahc, sim); 6949 target_mask = 0x01 << target; 6950 if (channel == 'B') 6951 target_mask <<= 8; 6952 6953 if (cel->enable != 0) { 6954 u_int scsiseq; 6955 6956 /* Are we already enabled?? */ 6957 if (lstate != NULL) { 6958 xpt_print_path(ccb->ccb_h.path); 6959 printf("Lun already enabled\n"); 6960 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA; 6961 return; 6962 } 6963 6964 if (cel->grp6_len != 0 6965 || cel->grp7_len != 0) { 6966 /* 6967 * Don't (yet?) support vendor 6968 * specific commands. 6969 */ 6970 ccb->ccb_h.status = CAM_REQ_INVALID; 6971 printf("Non-zero Group Codes\n"); 6972 return; 6973 } 6974 6975 /* 6976 * Seems to be okay. 6977 * Setup our data structures. 6978 */ 6979 if (target != CAM_TARGET_WILDCARD && tstate == NULL) { 6980 tstate = ahc_alloc_tstate(ahc, target, channel); 6981 if (tstate == NULL) { 6982 xpt_print_path(ccb->ccb_h.path); 6983 printf("Couldn't allocate tstate\n"); 6984 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 6985 return; 6986 } 6987 } 6988 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT); 6989 if (lstate == NULL) { 6990 xpt_print_path(ccb->ccb_h.path); 6991 printf("Couldn't allocate lstate\n"); 6992 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 6993 return; 6994 } 6995 memset(lstate, 0, sizeof(*lstate)); 6996 status = xpt_create_path(&lstate->path, /*periph*/NULL, 6997 xpt_path_path_id(ccb->ccb_h.path), 6998 xpt_path_target_id(ccb->ccb_h.path), 6999 xpt_path_lun_id(ccb->ccb_h.path)); 7000 if (status != CAM_REQ_CMP) { 7001 free(lstate, M_DEVBUF); 7002 xpt_print_path(ccb->ccb_h.path); 7003 printf("Couldn't allocate path\n"); 7004 ccb->ccb_h.status = CAM_RESRC_UNAVAIL; 7005 return; 7006 } 7007 SLIST_INIT(&lstate->accept_tios); 7008 SLIST_INIT(&lstate->immed_notifies); 7009 ahc_lock(ahc, &s); 7010 ahc_pause(ahc); 7011 if (target != CAM_TARGET_WILDCARD) { 7012 tstate->enabled_luns[lun] = lstate; 7013 ahc->enabled_luns++; 7014 7015 if ((ahc->features & AHC_MULTI_TID) != 0) { 7016 u_int targid_mask; 7017 7018 targid_mask = ahc_inb(ahc, TARGID) 7019 | (ahc_inb(ahc, TARGID + 1) << 8); 7020 7021 targid_mask |= target_mask; 7022 ahc_outb(ahc, TARGID, targid_mask); 7023 ahc_outb(ahc, TARGID+1, (targid_mask >> 8)); 7024 7025 ahc_update_scsiid(ahc, targid_mask); 7026 } else { 7027 u_int our_id; 7028 char channel; 7029 7030 channel = SIM_CHANNEL(ahc, sim); 7031 our_id = SIM_SCSI_ID(ahc, sim); 7032 7033 /* 7034 * This can only happen if selections 7035 * are not enabled 7036 */ 7037 if (target != our_id) { 7038 u_int sblkctl; 7039 char cur_channel; 7040 int swap; 7041 7042 sblkctl = ahc_inb(ahc, SBLKCTL); 7043 cur_channel = (sblkctl & SELBUSB) 7044 ? 'B' : 'A'; 7045 if ((ahc->features & AHC_TWIN) == 0) 7046 cur_channel = 'A'; 7047 swap = cur_channel != channel; 7048 if (channel == 'A') 7049 ahc->our_id = target; 7050 else 7051 ahc->our_id_b = target; 7052 7053 if (swap) 7054 ahc_outb(ahc, SBLKCTL, 7055 sblkctl ^ SELBUSB); 7056 7057 ahc_outb(ahc, SCSIID, target); 7058 7059 if (swap) 7060 ahc_outb(ahc, SBLKCTL, sblkctl); 7061 } 7062 } 7063 } else 7064 ahc->black_hole = lstate; 7065 /* Allow select-in operations */ 7066 if (ahc->black_hole != NULL && ahc->enabled_luns > 0) { 7067 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 7068 scsiseq |= ENSELI; 7069 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq); 7070 scsiseq = ahc_inb(ahc, SCSISEQ); 7071 scsiseq |= ENSELI; 7072 ahc_outb(ahc, SCSISEQ, scsiseq); 7073 } 7074 ahc_unpause(ahc); 7075 ahc_unlock(ahc, &s); 7076 ccb->ccb_h.status = CAM_REQ_CMP; 7077 xpt_print_path(ccb->ccb_h.path); 7078 printf("Lun now enabled for target mode\n"); 7079 } else { 7080 struct scb *scb; 7081 int i, empty; 7082 7083 if (lstate == NULL) { 7084 ccb->ccb_h.status = CAM_LUN_INVALID; 7085 return; 7086 } 7087 7088 ahc_lock(ahc, &s); 7089 7090 ccb->ccb_h.status = CAM_REQ_CMP; 7091 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) { 7092 struct ccb_hdr *ccbh; 7093 7094 ccbh = &scb->io_ctx->ccb_h; 7095 if (ccbh->func_code == XPT_CONT_TARGET_IO 7096 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){ 7097 printf("CTIO pending\n"); 7098 ccb->ccb_h.status = CAM_REQ_INVALID; 7099 ahc_unlock(ahc, &s); 7100 return; 7101 } 7102 } 7103 7104 if (SLIST_FIRST(&lstate->accept_tios) != NULL) { 7105 printf("ATIOs pending\n"); 7106 ccb->ccb_h.status = CAM_REQ_INVALID; 7107 } 7108 7109 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) { 7110 printf("INOTs pending\n"); 7111 ccb->ccb_h.status = CAM_REQ_INVALID; 7112 } 7113 7114 if (ccb->ccb_h.status != CAM_REQ_CMP) { 7115 ahc_unlock(ahc, &s); 7116 return; 7117 } 7118 7119 xpt_print_path(ccb->ccb_h.path); 7120 printf("Target mode disabled\n"); 7121 xpt_free_path(lstate->path); 7122 free(lstate, M_DEVBUF); 7123 7124 ahc_pause(ahc); 7125 /* Can we clean up the target too? */ 7126 if (target != CAM_TARGET_WILDCARD) { 7127 tstate->enabled_luns[lun] = NULL; 7128 ahc->enabled_luns--; 7129 for (empty = 1, i = 0; i < 8; i++) 7130 if (tstate->enabled_luns[i] != NULL) { 7131 empty = 0; 7132 break; 7133 } 7134 7135 if (empty) { 7136 ahc_free_tstate(ahc, target, channel, 7137 /*force*/FALSE); 7138 if (ahc->features & AHC_MULTI_TID) { 7139 u_int targid_mask; 7140 7141 targid_mask = ahc_inb(ahc, TARGID) 7142 | (ahc_inb(ahc, TARGID + 1) 7143 << 8); 7144 7145 targid_mask &= ~target_mask; 7146 ahc_outb(ahc, TARGID, targid_mask); 7147 ahc_outb(ahc, TARGID+1, 7148 (targid_mask >> 8)); 7149 ahc_update_scsiid(ahc, targid_mask); 7150 } 7151 } 7152 } else { 7153 7154 ahc->black_hole = NULL; 7155 7156 /* 7157 * We can't allow selections without 7158 * our black hole device. 7159 */ 7160 empty = TRUE; 7161 } 7162 if (ahc->enabled_luns == 0) { 7163 /* Disallow select-in */ 7164 u_int scsiseq; 7165 7166 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE); 7167 scsiseq &= ~ENSELI; 7168 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq); 7169 scsiseq = ahc_inb(ahc, SCSISEQ); 7170 scsiseq &= ~ENSELI; 7171 ahc_outb(ahc, SCSISEQ, scsiseq); 7172 7173 if ((ahc->features & AHC_MULTIROLE) == 0) { 7174 printf("Configuring Initiator Mode\n"); 7175 ahc->flags &= ~AHC_TARGETROLE; 7176 ahc->flags |= AHC_INITIATORROLE; 7177 /* 7178 * Returning to a configuration that 7179 * fit previously will always succeed. 7180 */ 7181 (void)ahc_loadseq(ahc); 7182 ahc_restart(ahc); 7183 /* 7184 * Unpaused. The extra unpause 7185 * that follows is harmless. 7186 */ 7187 } 7188 } 7189 ahc_unpause(ahc); 7190 ahc_unlock(ahc, &s); 7191 } 7192 } 7193 7194 static void 7195 ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask) 7196 { 7197 u_int scsiid_mask; 7198 u_int scsiid; 7199 7200 if ((ahc->features & AHC_MULTI_TID) == 0) 7201 panic("ahc_update_scsiid called on non-multitid unit\n"); 7202 7203 /* 7204 * Since we will rely on the TARGID mask 7205 * for selection enables, ensure that OID 7206 * in SCSIID is not set to some other ID 7207 * that we don't want to allow selections on. 7208 */ 7209 if ((ahc->features & AHC_ULTRA2) != 0) 7210 scsiid = ahc_inb(ahc, SCSIID_ULTRA2); 7211 else 7212 scsiid = ahc_inb(ahc, SCSIID); 7213 scsiid_mask = 0x1 << (scsiid & OID); 7214 if ((targid_mask & scsiid_mask) == 0) { 7215 u_int our_id; 7216 7217 /* ffs counts from 1 */ 7218 our_id = ffs(targid_mask); 7219 if (our_id == 0) 7220 our_id = ahc->our_id; 7221 else 7222 our_id--; 7223 scsiid &= TID; 7224 scsiid |= our_id; 7225 } 7226 if ((ahc->features & AHC_ULTRA2) != 0) 7227 ahc_outb(ahc, SCSIID_ULTRA2, scsiid); 7228 else 7229 ahc_outb(ahc, SCSIID, scsiid); 7230 } 7231 7232 void 7233 ahc_run_tqinfifo(struct ahc_softc *ahc, int paused) 7234 { 7235 struct target_cmd *cmd; 7236 7237 /* 7238 * If the card supports auto-access pause, 7239 * we can access the card directly regardless 7240 * of whether it is paused or not. 7241 */ 7242 if ((ahc->features & AHC_AUTOPAUSE) != 0) 7243 paused = TRUE; 7244 7245 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_POSTREAD); 7246 while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) { 7247 7248 /* 7249 * Only advance through the queue if we 7250 * have the resources to process the command. 7251 */ 7252 if (ahc_handle_target_cmd(ahc, cmd) != 0) 7253 break; 7254 7255 cmd->cmd_valid = 0; 7256 ahc_dmamap_sync(ahc, ahc->shared_data_dmat, 7257 ahc->shared_data_dmamap, 7258 ahc_targetcmd_offset(ahc, ahc->tqinfifonext), 7259 sizeof(struct target_cmd), 7260 BUS_DMASYNC_PREREAD); 7261 ahc->tqinfifonext++; 7262 7263 /* 7264 * Lazily update our position in the target mode incoming 7265 * command queue as seen by the sequencer. 7266 */ 7267 if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) { 7268 if ((ahc->features & AHC_HS_MAILBOX) != 0) { 7269 u_int hs_mailbox; 7270 7271 hs_mailbox = ahc_inb(ahc, HS_MAILBOX); 7272 hs_mailbox &= ~HOST_TQINPOS; 7273 hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS; 7274 ahc_outb(ahc, HS_MAILBOX, hs_mailbox); 7275 } else { 7276 if (!paused) 7277 ahc_pause(ahc); 7278 ahc_outb(ahc, KERNEL_TQINPOS, 7279 ahc->tqinfifonext & HOST_TQINPOS); 7280 if (!paused) 7281 ahc_unpause(ahc); 7282 } 7283 } 7284 } 7285 } 7286 7287 static int 7288 ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd) 7289 { 7290 struct ahc_tmode_tstate *tstate; 7291 struct ahc_tmode_lstate *lstate; 7292 struct ccb_accept_tio *atio; 7293 uint8_t *byte; 7294 int initiator; 7295 int target; 7296 int lun; 7297 7298 initiator = SCSIID_TARGET(ahc, cmd->scsiid); 7299 target = SCSIID_OUR_ID(cmd->scsiid); 7300 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK); 7301 7302 byte = cmd->bytes; 7303 tstate = ahc->enabled_targets[target]; 7304 lstate = NULL; 7305 if (tstate != NULL) 7306 lstate = tstate->enabled_luns[lun]; 7307 7308 /* 7309 * Commands for disabled luns go to the black hole driver. 7310 */ 7311 if (lstate == NULL) 7312 lstate = ahc->black_hole; 7313 7314 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios); 7315 if (atio == NULL) { 7316 ahc->flags |= AHC_TQINFIFO_BLOCKED; 7317 /* 7318 * Wait for more ATIOs from the peripheral driver for this lun. 7319 */ 7320 if (bootverbose) 7321 printf("%s: ATIOs exhausted\n", ahc_name(ahc)); 7322 return (1); 7323 } else 7324 ahc->flags &= ~AHC_TQINFIFO_BLOCKED; 7325 #if 0 7326 printf("Incoming command from %d for %d:%d%s\n", 7327 initiator, target, lun, 7328 lstate == ahc->black_hole ? "(Black Holed)" : ""); 7329 #endif 7330 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle); 7331 7332 if (lstate == ahc->black_hole) { 7333 /* Fill in the wildcards */ 7334 atio->ccb_h.target_id = target; 7335 atio->ccb_h.target_lun = lun; 7336 } 7337 7338 /* 7339 * Package it up and send it off to 7340 * whomever has this lun enabled. 7341 */ 7342 atio->sense_len = 0; 7343 atio->init_id = initiator; 7344 if (byte[0] != 0xFF) { 7345 /* Tag was included */ 7346 atio->tag_action = *byte++; 7347 atio->tag_id = *byte++; 7348 atio->ccb_h.flags = CAM_TAG_ACTION_VALID; 7349 } else { 7350 atio->ccb_h.flags = 0; 7351 } 7352 byte++; 7353 7354 /* Okay. Now determine the cdb size based on the command code */ 7355 switch (*byte >> CMD_GROUP_CODE_SHIFT) { 7356 case 0: 7357 atio->cdb_len = 6; 7358 break; 7359 case 1: 7360 case 2: 7361 atio->cdb_len = 10; 7362 break; 7363 case 4: 7364 atio->cdb_len = 16; 7365 break; 7366 case 5: 7367 atio->cdb_len = 12; 7368 break; 7369 case 3: 7370 default: 7371 /* Only copy the opcode. */ 7372 atio->cdb_len = 1; 7373 printf("Reserved or VU command code type encountered\n"); 7374 break; 7375 } 7376 7377 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len); 7378 7379 atio->ccb_h.status |= CAM_CDB_RECVD; 7380 7381 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) { 7382 /* 7383 * We weren't allowed to disconnect. 7384 * We're hanging on the bus until a 7385 * continue target I/O comes in response 7386 * to this accept tio. 7387 */ 7388 #if 0 7389 printf("Received Immediate Command %d:%d:%d - %p\n", 7390 initiator, target, lun, ahc->pending_device); 7391 #endif 7392 ahc->pending_device = lstate; 7393 ahc_freeze_ccb((union ccb *)atio); 7394 atio->ccb_h.flags |= CAM_DIS_DISCONNECT; 7395 } 7396 xpt_done((union ccb*)atio); 7397 return (0); 7398 } 7399 7400 #endif 7401